xref: /linux/drivers/gpu/drm/ast/ast_reg.h (revision daa2be74b1b2302004945b2a5e32424e177cc7da)
1 /* SPDX-License-Identifier: MIT */
2 
3 #ifndef __AST_REG_H__
4 #define __AST_REG_H__
5 
6 #include <linux/bits.h>
7 
8 /*
9  * Modesetting
10  */
11 
12 #define AST_IO_MM_OFFSET		(0x380)
13 #define AST_IO_MM_LENGTH		(128)
14 
15 #define AST_IO_VGAARI_W			(0x40)
16 
17 #define AST_IO_VGAMR_W			(0x42)
18 #define AST_IO_VGAMR_R			(0x4c)
19 #define AST_IO_VGAMR_IOSEL		BIT(0)
20 
21 #define AST_IO_VGAER			(0x43)
22 #define AST_IO_VGAER_VGA_ENABLE		BIT(0)
23 
24 #define AST_IO_VGASRI			(0x44)
25 #define AST_IO_VGASR1_SD		BIT(5)
26 #define AST_IO_VGADRR			(0x47)
27 #define AST_IO_VGADWR			(0x48)
28 #define AST_IO_VGAPDR		        (0x49)
29 #define AST_IO_VGAGRI			(0x4E)
30 
31 #define AST_IO_VGACRI			(0x54)
32 #define AST_IO_VGACR80_PASSWORD		(0xa8)
33 #define AST_IO_VGACRA1_VGAIO_DISABLED	BIT(1)
34 #define AST_IO_VGACRA1_MMIO_ENABLED	BIT(2)
35 #define AST_IO_VGACRB6_HSYNC_OFF	BIT(0)
36 #define AST_IO_VGACRB6_VSYNC_OFF	BIT(1)
37 #define AST_IO_VGACRCB_HWC_16BPP	BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
38 #define AST_IO_VGACRCB_HWC_ENABLED	BIT(1)
39 
40 #define AST_IO_VGAIR1_R			(0x5A)
41 #define AST_IO_VGAIR1_VREFRESH		BIT(3)
42 
43 /*
44  * Display Transmitter Type
45  */
46 
47 #define TX_TYPE_MASK			GENMASK(3, 1)
48 #define NO_TX				(0 << 1)
49 #define ITE66121_VBIOS_TX		(1 << 1)
50 #define SI164_VBIOS_TX			(2 << 1)
51 #define CH7003_VBIOS_TX			(3 << 1)
52 #define DP501_VBIOS_TX			(4 << 1)
53 #define ANX9807_VBIOS_TX		(5 << 1)
54 #define TX_FW_EMBEDDED_FW_TX		(6 << 1)
55 #define ASTDP_DPMCU_TX			(7 << 1)
56 
57 #define AST_VRAM_INIT_STATUS_MASK	GENMASK(7, 6)
58 //#define AST_VRAM_INIT_BY_BMC		BIT(7)
59 //#define AST_VRAM_INIT_READY		BIT(6)
60 
61 /*
62  * AST DisplayPort
63  */
64 
65 /* Define for Soc scratched reg used on ASTDP */
66 #define AST_DP_PHY_SLEEP		BIT(4)
67 #define AST_DP_VIDEO_ENABLE		BIT(0)
68 
69 /*
70  * CRD1[b5]: DP MCU FW is executing
71  * CRDC[b0]: DP link success
72  * CRDF[b0]: DP HPD
73  * CRE5[b0]: Host reading EDID process is done
74  */
75 #define ASTDP_MCU_FW_EXECUTING		BIT(5)
76 #define ASTDP_LINK_SUCCESS		BIT(0)
77 #define ASTDP_HPD			BIT(0)
78 #define ASTDP_HOST_EDID_READ_DONE	BIT(0)
79 #define ASTDP_HOST_EDID_READ_DONE_MASK	GENMASK(0, 0)
80 
81 /*
82  * CRDF[b4]: Mirror of AST_DP_VIDEO_ENABLE
83  * Precondition:	A. ~AST_DP_PHY_SLEEP  &&
84  *			B. DP_HPD &&
85  *			C. DP_LINK_SUCCESS
86  */
87 #define ASTDP_MIRROR_VIDEO_ENABLE	BIT(4)
88 
89 #define ASTDP_EDID_READ_POINTER_MASK	GENMASK(7, 0)
90 #define ASTDP_EDID_VALID_FLAG_MASK	GENMASK(0, 0)
91 #define ASTDP_EDID_READ_DATA_MASK	GENMASK(7, 0)
92 
93 /*
94  * ASTDP setmode registers:
95  * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp)
96  * CRE1[7:0]: MISC1 (default: 0x00)
97  * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50)
98  */
99 #define ASTDP_MISC0_24bpp		BIT(5)
100 #define ASTDP_MISC1			0
101 #define ASTDP_AND_CLEAR_MASK		0x00
102 
103 #endif
104