drm/ast/ast_reg.h

/* SPDX-License-Identifier: MIT */

#ifndef __AST_REG_H__
#define __AST_REG_H__

#include <linux/bits.h>

/*
 * Modesetting
 */

#define AST_IO_MM_OFFSET		(0x380)
#define AST_IO_MM_LENGTH		(128)

#define AST_IO_VGAARI_W			(0x40)

#define AST_IO_VGAMR_W			(0x42)
#define AST_IO_VGAMR_R			(0x4c)
#define AST_IO_VGAMR_IOSEL		BIT(0)

#define AST_IO_VGAER			(0x43)
#define AST_IO_VGAER_VGA_ENABLE		BIT(0)

#define AST_IO_VGASRI			(0x44)
#define AST_IO_VGASR1_SD		BIT(5)
#define AST_IO_VGADRR			(0x47)
#define AST_IO_VGADWR			(0x48)
#define AST_IO_VGAPDR		        (0x49)
#define AST_IO_VGAGRI			(0x4E)

#define AST_IO_VGACRI				(0x54)
#define AST_IO_VGACR17_SYNC_ENABLE		BIT(7) /* called "Hardware reset" in docs */
#define AST_IO_VGACR80_PASSWORD			(0xa8)

#define AST_IO_VGACR8C_NEW_MODE_MASK		GENMASK(3, 0)
#define AST_IO_VGACR8C_NEW_MODE_EGA		(0x00)
#define AST_IO_VGACR8C_NEW_MODE_VGA		(0x01)
#define AST_IO_VGACR8C_NEW_MODE_15_BPP		(0x02)
#define AST_IO_VGACR8C_NEW_MODE_16_BPP		(0x03)
#define AST_IO_VGACR8C_NEW_MODE_32_BPP		(0x04)
#define AST_IO_VGACR8C_NEW_MODE_CGA		(0x0f)
#define AST_IO_VGACR8C_NEW_MODE_TEXT		(0x0e)
#define AST_IO_VGACR8C_CUR_MODE_MASK		GENMASK(7, 4)
#define AST_IO_VGACR8C_CUR_MODE_EGA		(0x00)
#define AST_IO_VGACR8C_CUR_MODE_VGA		(0x10)
#define AST_IO_VGACR8C_CUR_MODE_15_BPP		(0x20)
#define AST_IO_VGACR8C_CUR_MODE_16_BPP		(0x30)
#define AST_IO_VGACR8C_CUR_MODE_32_BPP		(0x40)
#define AST_IO_VGACR8C_CUR_MODE_CGA		(0xf0)
#define AST_IO_VGACR8C_CUR_MODE_TEXT		(0xe0)

#define AST_IO_VGACR91_PASSWORD			(0xa8)
#define AST_IO_VGACR99_VGAMEM_RSRV_MASK		GENMASK(1, 0)

#define AST_IO_VGACRA0_MEMORY_CHAIN4_MODE	BIT(6)
#define AST_IO_VGACRA0_LINEAR_EXT_ACCESS	BIT(5)
#define AST_IO_VGACRA0_SEGMENTED_EXT_ACCESS	BIT(4)

#define AST_IO_VGACRA1_VGAIO_DISABLED		BIT(1)
#define AST_IO_VGACRA1_MMIO_ENABLED		BIT(2)

#define AST_IO_VGACRA3_DVO_ENABLED		BIT(7)
#define AST_IO_VGACRA3_32_BPP			BIT(3)
#define AST_IO_VGACRA3_16_BPP			BIT(2)
#define AST_IO_VGACRA3_15_BPP			BIT(1)
#define AST_IO_VGACRA3_256_COLORS		BIT(0)

#define AST_IO_VGACRA8_GAMMA_CORRECTION_ENABLED	BIT(1)
#define AST_IO_VGACRAA_VGAMEM_SIZE_MASK		GENMASK(1, 0)
#define AST_IO_VGACRB6_HSYNC_OFF		BIT(0)
#define AST_IO_VGACRB6_VSYNC_OFF		BIT(1)
#define AST_IO_VGACRCB_HWC_16BPP		BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
#define AST_IO_VGACRCB_HWC_ENABLED		BIT(1)

/* mirrors SCU100[7:0] */
#define AST_IO_VGACRD0_VRAM_INIT_STATUS_MASK	GENMASK(7, 6)
#define AST_IO_VGACRD0_VRAM_INIT_BY_BMC		BIT(7)
#define AST_IO_VGACRD0_VRAM_INIT_READY		BIT(6)
#define AST_IO_VGACRD0_IKVM_WIDESCREEN		BIT(0)

#define AST_IO_VGACRD1_MCU_FW_EXECUTING		BIT(5)
/* Display Transmitter Type */
#define AST_IO_VGACRD1_TX_TYPE_MASK		GENMASK(3, 1)
#define AST_IO_VGACRD1_NO_TX			0x00
#define AST_IO_VGACRD1_TX_ITE66121_VBIOS	0x02
#define AST_IO_VGACRD1_TX_SIL164_VBIOS		0x04
#define AST_IO_VGACRD1_TX_CH7003_VBIOS		0x06
#define AST_IO_VGACRD1_TX_DP501_VBIOS		0x08
#define AST_IO_VGACRD1_TX_ANX9807_VBIOS		0x0a
#define AST_IO_VGACRD1_TX_FW_EMBEDDED_FW	0x0c /* special case of DP501 */
#define AST_IO_VGACRD1_TX_ASTDP			0x0e
#define AST_IO_VGACRD1_SUPPORTS_WUXGA		BIT(0)

/*
 * AST DisplayPort
 */
#define AST_IO_VGACRD7_EDID_VALID_FLAG	BIT(0)
#define AST_IO_VGACRDC_LINK_SUCCESS	BIT(0)
#define AST_IO_VGACRDF_HPD		BIT(0)
#define AST_IO_VGACRDF_DP_VIDEO_ENABLE	BIT(4) /* mirrors AST_IO_VGACRE3_DP_VIDEO_ENABLE */
#define AST_IO_VGACRE0_24BPP		BIT(5) /* 18 bpp, if unset  */
#define AST_IO_VGACRE3_DP_VIDEO_ENABLE	BIT(0)
#define AST_IO_VGACRE3_DP_PHY_SLEEP	BIT(4)
#define AST_IO_VGACRE5_EDID_READ_DONE	BIT(0)

#define AST_IO_VGAIR1_R			(0x5A)
#define AST_IO_VGAIR1_VREFRESH		BIT(3)

/*
 * P-Bus to AHB Bridge (0x00000000 - 0x0001ffff)
 */

#define AST_REG_P2A_BASE			(0x00000000)
#define AST_REG_P2A(__offset)			(AST_REG_P2A_BASE + (__offset))
#define AST_REG_P2A_ADDR(__addr)		AST_REG_P2A(0x10000 + ((__addr) & GENMASK(15, 0)))
#define AST_REG_P2A00				AST_REG_P2A(0xf000)
#define AST_REG_P2A00_PROTECTION_KEY		(0x01)
#define AST_REG_P2A04				AST_REG_P2A(0xf004)
#define AST_REG_P2A04_BASE_MASK			GENMASK(31, 16)

/*
 * AHB Controller (0x1e600000 - 0x1e61ffff)
 */

#define AST_REG_AHBC_BASE			(0x1e600000)
#define AST_REG_AHBC(__offset)			(AST_REG_AHBC_BASE + (__offset))
#define AST_REG_AHBC00				AST_REG_AHBC(0x00)
#define AST_REG_AHBC00_PROTECT_KEY		(0xaeed1a03)
#define AST_REG_AHBC84				AST_REG_AHBC(0x84)
#define AST_REG_AHBC88				AST_REG_AHBC(0x88)

/*
 * SDRAM Memory Controller (0x1e6e0000 - 0x1e6e0fff)
 */

#define AST_REG_MCR_BASE			(0x1e6e0000)
#define AST_REG_MCR(__offset)			(AST_REG_MCR_BASE + (__offset))
#define AST_REG_MCR00				AST_REG_MCR(0x00)
#define AST_REG_MCR00_PROTECTION_KEY		(0xfc600309)
#define AST_REG_MCR04				AST_REG_MCR(0x04)
#define AST_REG_MCR08				AST_REG_MCR(0x08)
#define AST_REG_MCR0C				AST_REG_MCR(0x0c)
#define AST_REG_MCR10				AST_REG_MCR(0x10)
#define AST_REG_MCR14				AST_REG_MCR(0x14)
#define AST_REG_MCR18				AST_REG_MCR(0x18)
#define AST_REG_MCR1C				AST_REG_MCR(0x1c)
#define AST_REG_MCR20				AST_REG_MCR(0x20)
#define AST_REG_MCR24				AST_REG_MCR(0x24)
#define AST_REG_MCR28				AST_REG_MCR(0x28)
#define AST_REG_MCR2C				AST_REG_MCR(0x2C)
#define AST_REG_MCR30				AST_REG_MCR(0x30)
#define AST_REG_MCR34				AST_REG_MCR(0x34)
#define AST_REG_MCR38				AST_REG_MCR(0x38)
#define AST_REG_MCR3C				AST_REG_MCR(0x3c)
#define AST_REG_MCR40				AST_REG_MCR(0x40)
#define AST_REG_MCR44				AST_REG_MCR(0x44)
#define AST_REG_MCR48				AST_REG_MCR(0x48)
#define AST_REG_MCR4C				AST_REG_MCR(0x4C)
#define AST_REG_MCR50				AST_REG_MCR(0x50)
#define AST_REG_MCR54				AST_REG_MCR(0x54)
#define AST_REG_MCR58				AST_REG_MCR(0x58)
#define AST_REG_MCR5C				AST_REG_MCR(0x5c)
#define AST_REG_MCR60				AST_REG_MCR(0x60)
#define AST_REG_MCR64				AST_REG_MCR(0x64)
#define AST_REG_MCR68				AST_REG_MCR(0x68)
#define AST_REG_MCR6C				AST_REG_MCR(0x6c)
#define AST_REG_MCR70				AST_REG_MCR(0x70)
#define AST_REG_MCR74				AST_REG_MCR(0x74)
#define AST_REG_MCR78				AST_REG_MCR(0x78)
#define AST_REG_MCR7C				AST_REG_MCR(0x7c)
#define AST_REG_MCR80				AST_REG_MCR(0x80)
#define AST_REG_MCR84				AST_REG_MCR(0x84)
#define AST_REG_MCR88				AST_REG_MCR(0x88)
#define AST_REG_MCR8C				AST_REG_MCR(0x8c)
#define AST_REG_MCR100				AST_REG_MCR(0x100)
#define AST_REG_MCR108				AST_REG_MCR(0x108)
#define AST_REG_MCR120				AST_REG_MCR(0x120)
#define AST_REG_MCR140				AST_REG_MCR(0x140)
#define AST_REG_MCR200				AST_REG_MCR(0x200)
#define AST_REG_MCR204				AST_REG_MCR(0x204)
#define AST_REG_MCR208				AST_REG_MCR(0x208)
#define AST_REG_MCR20C				AST_REG_MCR(0x20C)
#define AST_REG_MCR210				AST_REG_MCR(0x210)
#define AST_REG_MCR214				AST_REG_MCR(0x214)
#define AST_REG_MCR218				AST_REG_MCR(0x218)
#define AST_REG_MCR220				AST_REG_MCR(0x220)
#define AST_REG_MCR228				AST_REG_MCR(0x228)
#define AST_REG_MCR230				AST_REG_MCR(0x230)
#define AST_REG_MCR2A8				AST_REG_MCR(0x2a8)
#define AST_REG_MCR2B0				AST_REG_MCR(0x2b0)
#define AST_REG_MCR240				AST_REG_MCR(0x240)
#define AST_REG_MCR244				AST_REG_MCR(0x244)
#define AST_REG_MCR248				AST_REG_MCR(0x248)
#define AST_REG_MCR24C				AST_REG_MCR(0x24c)
#define AST_REG_MCR290				AST_REG_MCR(0x290)
#define AST_REG_MCR2C0				AST_REG_MCR(0x2c0)
#define AST_REG_MCR2C4				AST_REG_MCR(0x2c4)
#define AST_REG_MCR2C8				AST_REG_MCR(0x2c8)
#define AST_REG_MCR2CC				AST_REG_MCR(0x2cc)
#define AST_REG_MCR2E0				AST_REG_MCR(0x2e0)
#define AST_REG_MCR2E4				AST_REG_MCR(0x2e4)
#define AST_REG_MCR2E8				AST_REG_MCR(0x2e8)
#define AST_REG_MCR2EC				AST_REG_MCR(0x2ec)
#define AST_REG_MCR2F0				AST_REG_MCR(0x2f0)
#define AST_REG_MCR2F4				AST_REG_MCR(0x2f4)
#define AST_REG_MCR2F8				AST_REG_MCR(0x2f8)
#define AST_REG_MCR300				AST_REG_MCR(0x300)
#define AST_REG_MCR3D0				AST_REG_MCR(0x3d0)

/*
 * System Control Unit (0x1e6e2000 - 0x1e6e2fff)
 */

#define AST_REG_SCU_BASE			(0x1e6e2000)
#define AST_REG_SCU(__offset)			(AST_REG_SCU_BASE + (__offset))
#define AST_REG_SCU000				AST_REG_SCU(0x000)
#define AST_REG_SCU000_PROTECTION_KEY		(0x1688a8a8)
#define AST_REG_SCU008				AST_REG_SCU(0x008)
#define AST_REG_SCU00C				AST_REG_SCU(0x00c)
#define AST_REG_SCU020				AST_REG_SCU(0x020)
#define AST_REG_SCU02C				AST_REG_SCU(0x02c)
#define AST_REG_SCU040				AST_REG_SCU(0x040)
#define AST_REG_SCU070				AST_REG_SCU(0x070)
#define AST_REG_SCU07C				AST_REG_SCU(0x07c)
#define AST_REG_SCU07C_CHIP_BONDING_MASK	GENMASK(15, 8)
#define AST_REG_SCU084				AST_REG_SCU(0x084)
#define AST_REG_SCU088				AST_REG_SCU(0x088)
#define AST_REG_SCU08C				AST_REG_SCU(0x08c)
#define AST_REG_SCU090				AST_REG_SCU(0x090)
#define AST_REG_SCU094				AST_REG_SCU(0x094)
#define AST_REG_SCU0A4				AST_REG_SCU(0x0a4)
#define AST_REG_SCU0A8				AST_REG_SCU(0x0a8)
#define AST_REG_SCU100				AST_REG_SCU(0x100)
#define AST_REG_SCU104				AST_REG_SCU(0x104)
#define AST_REG_SCU160				AST_REG_SCU(0x160)

/*
 * AHB-to-P Bus Bridge (0x1e720000 - 0x1e73ffff)
 */

#define AST_REG_A2P_BASE			(0x1e720000)
#define AST_REG_A2P(__offset)			(AST_REG_A2P_BASE + (__offset))
#define AST_REG_A2P58				AST_REG_A2P(0x58)

/*
 * Watchdog timer (0x1e785000 - 0x1e785fff)
 */

#define AST_REG_WDT_BASE(__n)			(0x1e785000 + (__n) * 0x40)
#define AST_REG_WDT(__n, __offset)		(AST_REG_WDT_BASE((__n)) + (__offset))
#define AST_REG_WDT04(__n)			AST_REG_WDT((__n), 0x04)
#define AST_REG_WDT08(__n)			AST_REG_WDT((__n), 0x08)
#define AST_REG_WDT0C(__n)			AST_REG_WDT((__n), 0x0c)
#define AST_REG_WDT14(__n)			AST_REG_WDT((__n), 0x14)
#define AST_REG_WDT1C(__n)			AST_REG_WDT((__n), 0x1c)
#define AST_REG_WDT2C(__n)			AST_REG_WDT((__n), 0x2c)

/*
 * SDRAM (0x80000000 - 0xffffffff)
 */

#define AST_SDRAM_BASE				(0x80000000)
#define AST_SDRAM(__offset)			(AST_SDRAM_BASE + (__offset))

#endif