1 /* SPDX-License-Identifier: MIT */ 2 3 #ifndef __AST_REG_H__ 4 #define __AST_REG_H__ 5 6 #include <linux/bits.h> 7 8 /* 9 * Modesetting 10 */ 11 12 #define AST_IO_MM_OFFSET (0x380) 13 14 #define AST_IO_VGAARI_W (0x40) 15 #define AST_IO_VGAMR_W (0x42) 16 #define AST_IO_VGAER (0x43) 17 #define AST_IO_VGASRI (0x44) 18 #define AST_IO_VGADRR (0x47) 19 #define AST_IO_VGADWR (0x48) 20 #define AST_IO_VGAPDR (0x49) 21 #define AST_IO_VGAGRI (0x4E) 22 23 #define AST_IO_VGACRI (0x54) 24 #define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */ 25 #define AST_IO_VGACRCB_HWC_ENABLED BIT(1) 26 27 #define AST_IO_VGAIR1_R (0x5A) 28 #define AST_IO_VGAIR1_VREFRESH BIT(3) 29 30 #define AST_IO_VGAMR_R (0x4C) 31 32 /* 33 * Display Transmitter Type 34 */ 35 36 #define TX_TYPE_MASK GENMASK(3, 1) 37 #define NO_TX (0 << 1) 38 #define ITE66121_VBIOS_TX (1 << 1) 39 #define SI164_VBIOS_TX (2 << 1) 40 #define CH7003_VBIOS_TX (3 << 1) 41 #define DP501_VBIOS_TX (4 << 1) 42 #define ANX9807_VBIOS_TX (5 << 1) 43 #define TX_FW_EMBEDDED_FW_TX (6 << 1) 44 #define ASTDP_DPMCU_TX (7 << 1) 45 46 #define AST_VRAM_INIT_STATUS_MASK GENMASK(7, 6) 47 //#define AST_VRAM_INIT_BY_BMC BIT(7) 48 //#define AST_VRAM_INIT_READY BIT(6) 49 50 /* 51 * AST DisplayPort 52 */ 53 54 /* Define for Soc scratched reg used on ASTDP */ 55 #define AST_DP_PHY_SLEEP BIT(4) 56 #define AST_DP_VIDEO_ENABLE BIT(0) 57 58 /* 59 * CRD1[b5]: DP MCU FW is executing 60 * CRDC[b0]: DP link success 61 * CRDF[b0]: DP HPD 62 * CRE5[b0]: Host reading EDID process is done 63 */ 64 #define ASTDP_MCU_FW_EXECUTING BIT(5) 65 #define ASTDP_LINK_SUCCESS BIT(0) 66 #define ASTDP_HPD BIT(0) 67 #define ASTDP_HOST_EDID_READ_DONE BIT(0) 68 #define ASTDP_HOST_EDID_READ_DONE_MASK GENMASK(0, 0) 69 70 /* 71 * CRB8[b1]: Enable VSYNC off 72 * CRB8[b0]: Enable HSYNC off 73 */ 74 #define AST_DPMS_VSYNC_OFF BIT(1) 75 #define AST_DPMS_HSYNC_OFF BIT(0) 76 77 /* 78 * CRDF[b4]: Mirror of AST_DP_VIDEO_ENABLE 79 * Precondition: A. ~AST_DP_PHY_SLEEP && 80 * B. DP_HPD && 81 * C. DP_LINK_SUCCESS 82 */ 83 #define ASTDP_MIRROR_VIDEO_ENABLE BIT(4) 84 85 #define ASTDP_EDID_READ_POINTER_MASK GENMASK(7, 0) 86 #define ASTDP_EDID_VALID_FLAG_MASK GENMASK(0, 0) 87 #define ASTDP_EDID_READ_DATA_MASK GENMASK(7, 0) 88 89 /* 90 * ASTDP setmode registers: 91 * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp) 92 * CRE1[7:0]: MISC1 (default: 0x00) 93 * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50) 94 */ 95 #define ASTDP_MISC0_24bpp BIT(5) 96 #define ASTDP_MISC1 0 97 #define ASTDP_AND_CLEAR_MASK 0x00 98 99 #endif 100