1 /* 2 * Copyright 2012 Red Hat Inc. 3 * Parts based on xf86-video-ast 4 * Copyright (c) 2005 ASPEED Technology Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 * 26 */ 27 /* 28 * Authors: Dave Airlie <airlied@redhat.com> 29 */ 30 31 #include <linux/export.h> 32 #include <linux/pci.h> 33 34 #include <drm/drm_atomic.h> 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_atomic_state_helper.h> 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_crtc_helper.h> 39 #include <drm/drm_fourcc.h> 40 #include <drm/drm_gem_vram_helper.h> 41 #include <drm/drm_plane_helper.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_simple_kms_helper.h> 44 45 #include "ast_drv.h" 46 #include "ast_tables.h" 47 48 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev); 49 static void ast_i2c_destroy(struct ast_i2c_chan *i2c); 50 static int ast_cursor_move(struct drm_crtc *crtc, 51 int x, int y); 52 53 54 static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height); 55 static int ast_cursor_update(void *dst, void *src, unsigned int width, 56 unsigned int height); 57 static void ast_cursor_set_base(struct ast_private *ast, u64 address); 58 static int ast_cursor_move(struct drm_crtc *crtc, 59 int x, int y); 60 61 static inline void ast_load_palette_index(struct ast_private *ast, 62 u8 index, u8 red, u8 green, 63 u8 blue) 64 { 65 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index); 66 ast_io_read8(ast, AST_IO_SEQ_PORT); 67 ast_io_write8(ast, AST_IO_DAC_DATA, red); 68 ast_io_read8(ast, AST_IO_SEQ_PORT); 69 ast_io_write8(ast, AST_IO_DAC_DATA, green); 70 ast_io_read8(ast, AST_IO_SEQ_PORT); 71 ast_io_write8(ast, AST_IO_DAC_DATA, blue); 72 ast_io_read8(ast, AST_IO_SEQ_PORT); 73 } 74 75 static void ast_crtc_load_lut(struct ast_private *ast, struct drm_crtc *crtc) 76 { 77 u16 *r, *g, *b; 78 int i; 79 80 if (!crtc->enabled) 81 return; 82 83 r = crtc->gamma_store; 84 g = r + crtc->gamma_size; 85 b = g + crtc->gamma_size; 86 87 for (i = 0; i < 256; i++) 88 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8); 89 } 90 91 static bool ast_get_vbios_mode_info(const struct drm_format_info *format, 92 const struct drm_display_mode *mode, 93 struct drm_display_mode *adjusted_mode, 94 struct ast_vbios_mode_info *vbios_mode) 95 { 96 u32 refresh_rate_index = 0, refresh_rate; 97 const struct ast_vbios_enhtable *best = NULL; 98 u32 hborder, vborder; 99 bool check_sync; 100 101 switch (format->cpp[0] * 8) { 102 case 8: 103 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex]; 104 break; 105 case 16: 106 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex]; 107 break; 108 case 24: 109 case 32: 110 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex]; 111 break; 112 default: 113 return false; 114 } 115 116 switch (mode->crtc_hdisplay) { 117 case 640: 118 vbios_mode->enh_table = &res_640x480[refresh_rate_index]; 119 break; 120 case 800: 121 vbios_mode->enh_table = &res_800x600[refresh_rate_index]; 122 break; 123 case 1024: 124 vbios_mode->enh_table = &res_1024x768[refresh_rate_index]; 125 break; 126 case 1280: 127 if (mode->crtc_vdisplay == 800) 128 vbios_mode->enh_table = &res_1280x800[refresh_rate_index]; 129 else 130 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index]; 131 break; 132 case 1360: 133 vbios_mode->enh_table = &res_1360x768[refresh_rate_index]; 134 break; 135 case 1440: 136 vbios_mode->enh_table = &res_1440x900[refresh_rate_index]; 137 break; 138 case 1600: 139 if (mode->crtc_vdisplay == 900) 140 vbios_mode->enh_table = &res_1600x900[refresh_rate_index]; 141 else 142 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index]; 143 break; 144 case 1680: 145 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index]; 146 break; 147 case 1920: 148 if (mode->crtc_vdisplay == 1080) 149 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index]; 150 else 151 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index]; 152 break; 153 default: 154 return false; 155 } 156 157 refresh_rate = drm_mode_vrefresh(mode); 158 check_sync = vbios_mode->enh_table->flags & WideScreenMode; 159 160 while (1) { 161 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table; 162 163 while (loop->refresh_rate != 0xff) { 164 if ((check_sync) && 165 (((mode->flags & DRM_MODE_FLAG_NVSYNC) && 166 (loop->flags & PVSync)) || 167 ((mode->flags & DRM_MODE_FLAG_PVSYNC) && 168 (loop->flags & NVSync)) || 169 ((mode->flags & DRM_MODE_FLAG_NHSYNC) && 170 (loop->flags & PHSync)) || 171 ((mode->flags & DRM_MODE_FLAG_PHSYNC) && 172 (loop->flags & NHSync)))) { 173 loop++; 174 continue; 175 } 176 if (loop->refresh_rate <= refresh_rate 177 && (!best || loop->refresh_rate > best->refresh_rate)) 178 best = loop; 179 loop++; 180 } 181 if (best || !check_sync) 182 break; 183 check_sync = 0; 184 } 185 186 if (best) 187 vbios_mode->enh_table = best; 188 189 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0; 190 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0; 191 192 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht; 193 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder; 194 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder; 195 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder + 196 vbios_mode->enh_table->hfp; 197 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder + 198 vbios_mode->enh_table->hfp + 199 vbios_mode->enh_table->hsync); 200 201 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt; 202 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder; 203 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder; 204 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder + 205 vbios_mode->enh_table->vfp; 206 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder + 207 vbios_mode->enh_table->vfp + 208 vbios_mode->enh_table->vsync); 209 210 return true; 211 } 212 213 static void ast_set_vbios_color_reg(struct ast_private *ast, 214 const struct drm_format_info *format, 215 const struct ast_vbios_mode_info *vbios_mode) 216 { 217 u32 color_index; 218 219 switch (format->cpp[0]) { 220 case 1: 221 color_index = VGAModeIndex - 1; 222 break; 223 case 2: 224 color_index = HiCModeIndex; 225 break; 226 case 3: 227 case 4: 228 color_index = TrueCModeIndex; 229 default: 230 return; 231 } 232 233 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0x0f) << 4)); 234 235 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); 236 237 if (vbios_mode->enh_table->flags & NewModeInfo) { 238 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); 239 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, format->cpp[0] * 8); 240 } 241 } 242 243 static void ast_set_vbios_mode_reg(struct ast_private *ast, 244 const struct drm_display_mode *adjusted_mode, 245 const struct ast_vbios_mode_info *vbios_mode) 246 { 247 u32 refresh_rate_index, mode_id; 248 249 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index; 250 mode_id = vbios_mode->enh_table->mode_id; 251 252 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); 253 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); 254 255 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); 256 257 if (vbios_mode->enh_table->flags & NewModeInfo) { 258 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); 259 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000); 260 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay); 261 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8); 262 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay); 263 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8); 264 } 265 } 266 267 static void ast_set_std_reg(struct ast_private *ast, 268 struct drm_display_mode *mode, 269 struct ast_vbios_mode_info *vbios_mode) 270 { 271 const struct ast_vbios_stdtable *stdtable; 272 u32 i; 273 u8 jreg; 274 275 stdtable = vbios_mode->std_table; 276 277 jreg = stdtable->misc; 278 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 279 280 /* Set SEQ; except Screen Disable field */ 281 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03); 282 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x01, 0xdf, stdtable->seq[0]); 283 for (i = 1; i < 4; i++) { 284 jreg = stdtable->seq[i]; 285 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg); 286 } 287 288 /* Set CRTC; except base address and offset */ 289 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 290 for (i = 0; i < 12; i++) 291 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 292 for (i = 14; i < 19; i++) 293 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 294 for (i = 20; i < 25; i++) 295 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); 296 297 /* set AR */ 298 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 299 for (i = 0; i < 20; i++) { 300 jreg = stdtable->ar[i]; 301 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i); 302 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg); 303 } 304 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14); 305 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00); 306 307 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); 308 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20); 309 310 /* Set GR */ 311 for (i = 0; i < 9; i++) 312 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]); 313 } 314 315 static void ast_set_crtc_reg(struct ast_private *ast, 316 struct drm_display_mode *mode, 317 struct ast_vbios_mode_info *vbios_mode) 318 { 319 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0; 320 u16 temp, precache = 0; 321 322 if ((ast->chip == AST2500) && 323 (vbios_mode->enh_table->flags & AST2500PreCatchCRT)) 324 precache = 40; 325 326 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 327 328 temp = (mode->crtc_htotal >> 3) - 5; 329 if (temp & 0x100) 330 jregAC |= 0x01; /* HT D[8] */ 331 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); 332 333 temp = (mode->crtc_hdisplay >> 3) - 1; 334 if (temp & 0x100) 335 jregAC |= 0x04; /* HDE D[8] */ 336 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); 337 338 temp = (mode->crtc_hblank_start >> 3) - 1; 339 if (temp & 0x100) 340 jregAC |= 0x10; /* HBS D[8] */ 341 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); 342 343 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f; 344 if (temp & 0x20) 345 jreg05 |= 0x80; /* HBE D[5] */ 346 if (temp & 0x40) 347 jregAD |= 0x01; /* HBE D[5] */ 348 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); 349 350 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1; 351 if (temp & 0x100) 352 jregAC |= 0x40; /* HRS D[5] */ 353 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); 354 355 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f; 356 if (temp & 0x20) 357 jregAD |= 0x04; /* HRE D[5] */ 358 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); 359 360 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); 361 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD); 362 363 /* vert timings */ 364 temp = (mode->crtc_vtotal) - 2; 365 if (temp & 0x100) 366 jreg07 |= 0x01; 367 if (temp & 0x200) 368 jreg07 |= 0x20; 369 if (temp & 0x400) 370 jregAE |= 0x01; 371 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp); 372 373 temp = (mode->crtc_vsync_start) - 1; 374 if (temp & 0x100) 375 jreg07 |= 0x04; 376 if (temp & 0x200) 377 jreg07 |= 0x80; 378 if (temp & 0x400) 379 jregAE |= 0x08; 380 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp); 381 382 temp = (mode->crtc_vsync_end - 1) & 0x3f; 383 if (temp & 0x10) 384 jregAE |= 0x20; 385 if (temp & 0x20) 386 jregAE |= 0x40; 387 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf); 388 389 temp = mode->crtc_vdisplay - 1; 390 if (temp & 0x100) 391 jreg07 |= 0x02; 392 if (temp & 0x200) 393 jreg07 |= 0x40; 394 if (temp & 0x400) 395 jregAE |= 0x02; 396 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp); 397 398 temp = mode->crtc_vblank_start - 1; 399 if (temp & 0x100) 400 jreg07 |= 0x08; 401 if (temp & 0x200) 402 jreg09 |= 0x20; 403 if (temp & 0x400) 404 jregAE |= 0x04; 405 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp); 406 407 temp = mode->crtc_vblank_end - 1; 408 if (temp & 0x100) 409 jregAE |= 0x10; 410 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp); 411 412 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07); 413 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09); 414 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80)); 415 416 if (precache) 417 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80); 418 else 419 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00); 420 421 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80); 422 } 423 424 static void ast_set_offset_reg(struct ast_private *ast, 425 struct drm_framebuffer *fb) 426 { 427 u16 offset; 428 429 offset = fb->pitches[0] >> 3; 430 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff)); 431 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f); 432 } 433 434 static void ast_set_dclk_reg(struct ast_private *ast, 435 struct drm_display_mode *mode, 436 struct ast_vbios_mode_info *vbios_mode) 437 { 438 const struct ast_vbios_dclk_info *clk_info; 439 440 if (ast->chip == AST2500) 441 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index]; 442 else 443 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index]; 444 445 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1); 446 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2); 447 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f, 448 (clk_info->param3 & 0xc0) | 449 ((clk_info->param3 & 0x3) << 4)); 450 } 451 452 static void ast_set_color_reg(struct ast_private *ast, 453 const struct drm_format_info *format) 454 { 455 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0; 456 457 switch (format->cpp[0] * 8) { 458 case 8: 459 jregA0 = 0x70; 460 jregA3 = 0x01; 461 jregA8 = 0x00; 462 break; 463 case 15: 464 case 16: 465 jregA0 = 0x70; 466 jregA3 = 0x04; 467 jregA8 = 0x02; 468 break; 469 case 32: 470 jregA0 = 0x70; 471 jregA3 = 0x08; 472 jregA8 = 0x02; 473 break; 474 } 475 476 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0); 477 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3); 478 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); 479 } 480 481 static void ast_set_crtthd_reg(struct ast_private *ast) 482 { 483 /* Set Threshold */ 484 if (ast->chip == AST2300 || ast->chip == AST2400 || 485 ast->chip == AST2500) { 486 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); 487 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); 488 } else if (ast->chip == AST2100 || 489 ast->chip == AST1100 || 490 ast->chip == AST2200 || 491 ast->chip == AST2150) { 492 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f); 493 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f); 494 } else { 495 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f); 496 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f); 497 } 498 } 499 500 static void ast_set_sync_reg(struct ast_private *ast, 501 struct drm_display_mode *mode, 502 struct ast_vbios_mode_info *vbios_mode) 503 { 504 u8 jreg; 505 506 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ); 507 jreg &= ~0xC0; 508 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80; 509 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40; 510 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); 511 } 512 513 static void ast_set_start_address_crt1(struct ast_private *ast, 514 unsigned offset) 515 { 516 u32 addr; 517 518 addr = offset >> 2; 519 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff)); 520 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff)); 521 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff)); 522 523 } 524 525 /* 526 * Primary plane 527 */ 528 529 static const uint32_t ast_primary_plane_formats[] = { 530 DRM_FORMAT_XRGB8888, 531 DRM_FORMAT_RGB565, 532 DRM_FORMAT_C8, 533 }; 534 535 static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane, 536 struct drm_plane_state *state) 537 { 538 struct drm_crtc_state *crtc_state; 539 struct ast_crtc_state *ast_crtc_state; 540 int ret; 541 542 if (!state->crtc) 543 return 0; 544 545 crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); 546 547 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 548 DRM_PLANE_HELPER_NO_SCALING, 549 DRM_PLANE_HELPER_NO_SCALING, 550 false, true); 551 if (ret) 552 return ret; 553 554 if (!state->visible) 555 return 0; 556 557 ast_crtc_state = to_ast_crtc_state(crtc_state); 558 559 ast_crtc_state->format = state->fb->format; 560 561 return 0; 562 } 563 564 static void 565 ast_primary_plane_helper_atomic_update(struct drm_plane *plane, 566 struct drm_plane_state *old_state) 567 { 568 struct ast_private *ast = plane->dev->dev_private; 569 struct drm_plane_state *state = plane->state; 570 struct drm_gem_vram_object *gbo; 571 s64 gpu_addr; 572 573 gbo = drm_gem_vram_of_gem(state->fb->obj[0]); 574 gpu_addr = drm_gem_vram_offset(gbo); 575 if (WARN_ON_ONCE(gpu_addr < 0)) 576 return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */ 577 578 ast_set_offset_reg(ast, state->fb); 579 ast_set_start_address_crt1(ast, (u32)gpu_addr); 580 581 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x00); 582 } 583 584 static void 585 ast_primary_plane_helper_atomic_disable(struct drm_plane *plane, 586 struct drm_plane_state *old_state) 587 { 588 struct ast_private *ast = plane->dev->dev_private; 589 590 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20); 591 } 592 593 static const struct drm_plane_helper_funcs ast_primary_plane_helper_funcs = { 594 .prepare_fb = drm_gem_vram_plane_helper_prepare_fb, 595 .cleanup_fb = drm_gem_vram_plane_helper_cleanup_fb, 596 .atomic_check = ast_primary_plane_helper_atomic_check, 597 .atomic_update = ast_primary_plane_helper_atomic_update, 598 .atomic_disable = ast_primary_plane_helper_atomic_disable, 599 }; 600 601 static const struct drm_plane_funcs ast_primary_plane_funcs = { 602 .update_plane = drm_atomic_helper_update_plane, 603 .disable_plane = drm_atomic_helper_disable_plane, 604 .destroy = drm_plane_cleanup, 605 .reset = drm_atomic_helper_plane_reset, 606 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 607 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 608 }; 609 610 /* 611 * Cursor plane 612 */ 613 614 static const uint32_t ast_cursor_plane_formats[] = { 615 DRM_FORMAT_ARGB8888, 616 }; 617 618 static int 619 ast_cursor_plane_helper_prepare_fb(struct drm_plane *plane, 620 struct drm_plane_state *new_state) 621 { 622 struct drm_framebuffer *fb = new_state->fb; 623 struct drm_crtc *crtc = new_state->crtc; 624 struct drm_gem_vram_object *gbo; 625 struct ast_private *ast; 626 int ret; 627 void *src, *dst; 628 629 if (!crtc || !fb) 630 return 0; 631 632 if (WARN_ON_ONCE(fb->width > AST_MAX_HWC_WIDTH) || 633 WARN_ON_ONCE(fb->height > AST_MAX_HWC_HEIGHT)) 634 return -EINVAL; /* BUG: didn't test in atomic_check() */ 635 636 ast = crtc->dev->dev_private; 637 638 gbo = drm_gem_vram_of_gem(fb->obj[0]); 639 src = drm_gem_vram_vmap(gbo); 640 if (IS_ERR(src)) { 641 ret = PTR_ERR(src); 642 goto err_drm_gem_vram_unpin; 643 } 644 645 dst = drm_gem_vram_vmap(ast->cursor.gbo[ast->cursor.next_index]); 646 if (IS_ERR(dst)) { 647 ret = PTR_ERR(dst); 648 goto err_drm_gem_vram_vunmap_src; 649 } 650 651 ret = ast_cursor_update(dst, src, fb->width, fb->height); 652 if (ret) 653 goto err_drm_gem_vram_vunmap_dst; 654 655 /* Always unmap buffers here. Destination buffers are 656 * perma-pinned while the driver is active. We're only 657 * changing ref-counters here. 658 */ 659 drm_gem_vram_vunmap(ast->cursor.gbo[ast->cursor.next_index], dst); 660 drm_gem_vram_vunmap(gbo, src); 661 662 return 0; 663 664 err_drm_gem_vram_vunmap_dst: 665 drm_gem_vram_vunmap(ast->cursor.gbo[ast->cursor.next_index], dst); 666 err_drm_gem_vram_vunmap_src: 667 drm_gem_vram_vunmap(gbo, src); 668 err_drm_gem_vram_unpin: 669 drm_gem_vram_unpin(gbo); 670 return ret; 671 } 672 673 static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane, 674 struct drm_plane_state *state) 675 { 676 struct drm_framebuffer *fb = state->fb; 677 struct drm_crtc_state *crtc_state; 678 int ret; 679 680 if (!state->crtc) 681 return 0; 682 683 crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); 684 685 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 686 DRM_PLANE_HELPER_NO_SCALING, 687 DRM_PLANE_HELPER_NO_SCALING, 688 true, true); 689 if (ret) 690 return ret; 691 692 if (!state->visible) 693 return 0; 694 695 if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT) 696 return -EINVAL; 697 698 return 0; 699 } 700 701 static void 702 ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, 703 struct drm_plane_state *old_state) 704 { 705 struct drm_plane_state *state = plane->state; 706 struct drm_crtc *crtc = state->crtc; 707 struct drm_framebuffer *fb = state->fb; 708 struct ast_private *ast = plane->dev->dev_private; 709 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 710 struct drm_gem_vram_object *gbo; 711 s64 off; 712 u8 jreg; 713 714 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - fb->width; 715 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - fb->height; 716 717 if (state->fb != old_state->fb) { 718 /* A new cursor image was installed. */ 719 gbo = ast->cursor.gbo[ast->cursor.next_index]; 720 off = drm_gem_vram_offset(gbo); 721 if (WARN_ON_ONCE(off < 0)) 722 return; /* Bug: we didn't pin cursor HW BO to VRAM. */ 723 ast_cursor_set_base(ast, off); 724 725 ++ast->cursor.next_index; 726 ast->cursor.next_index %= ARRAY_SIZE(ast->cursor.gbo); 727 } 728 729 ast_cursor_move(crtc, state->crtc_x, state->crtc_y); 730 731 jreg = 0x2; 732 /* enable ARGB cursor */ 733 jreg |= 1; 734 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg); 735 } 736 737 static void 738 ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane, 739 struct drm_plane_state *old_state) 740 { 741 struct ast_private *ast = plane->dev->dev_private; 742 743 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00); 744 } 745 746 static const struct drm_plane_helper_funcs ast_cursor_plane_helper_funcs = { 747 .prepare_fb = ast_cursor_plane_helper_prepare_fb, 748 .cleanup_fb = NULL, /* not required for cursor plane */ 749 .atomic_check = ast_cursor_plane_helper_atomic_check, 750 .atomic_update = ast_cursor_plane_helper_atomic_update, 751 .atomic_disable = ast_cursor_plane_helper_atomic_disable, 752 }; 753 754 static const struct drm_plane_funcs ast_cursor_plane_funcs = { 755 .update_plane = drm_atomic_helper_update_plane, 756 .disable_plane = drm_atomic_helper_disable_plane, 757 .destroy = drm_plane_cleanup, 758 .reset = drm_atomic_helper_plane_reset, 759 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 760 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 761 }; 762 763 /* 764 * CRTC 765 */ 766 767 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode) 768 { 769 struct ast_private *ast = crtc->dev->dev_private; 770 771 if (ast->chip == AST1180) 772 return; 773 774 /* TODO: Maybe control display signal generation with 775 * Sync Enable (bit CR17.7). 776 */ 777 switch (mode) { 778 case DRM_MODE_DPMS_ON: 779 case DRM_MODE_DPMS_STANDBY: 780 case DRM_MODE_DPMS_SUSPEND: 781 if (ast->tx_chip_type == AST_TX_DP501) 782 ast_set_dp501_video_output(crtc->dev, 1); 783 ast_crtc_load_lut(ast, crtc); 784 break; 785 case DRM_MODE_DPMS_OFF: 786 if (ast->tx_chip_type == AST_TX_DP501) 787 ast_set_dp501_video_output(crtc->dev, 0); 788 break; 789 } 790 } 791 792 static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc, 793 struct drm_crtc_state *state) 794 { 795 struct ast_private *ast = crtc->dev->dev_private; 796 struct ast_crtc_state *ast_state; 797 const struct drm_format_info *format; 798 bool succ; 799 800 if (ast->chip == AST1180) { 801 DRM_ERROR("AST 1180 modesetting not supported\n"); 802 return -EINVAL; 803 } 804 805 if (!state->enable) 806 return 0; /* no mode checks if CRTC is being disabled */ 807 808 ast_state = to_ast_crtc_state(state); 809 810 format = ast_state->format; 811 if (!format) 812 return 0; 813 814 succ = ast_get_vbios_mode_info(format, &state->mode, 815 &state->adjusted_mode, 816 &ast_state->vbios_mode_info); 817 if (!succ) 818 return -EINVAL; 819 820 return 0; 821 } 822 823 static void ast_crtc_helper_atomic_begin(struct drm_crtc *crtc, 824 struct drm_crtc_state *old_crtc_state) 825 { 826 struct ast_private *ast = crtc->dev->dev_private; 827 828 ast_open_key(ast); 829 } 830 831 static void ast_crtc_helper_atomic_flush(struct drm_crtc *crtc, 832 struct drm_crtc_state *old_crtc_state) 833 { 834 struct drm_device *dev = crtc->dev; 835 struct ast_private *ast = dev->dev_private; 836 struct ast_crtc_state *ast_state; 837 const struct drm_format_info *format; 838 struct ast_vbios_mode_info *vbios_mode_info; 839 struct drm_display_mode *adjusted_mode; 840 841 ast_state = to_ast_crtc_state(crtc->state); 842 843 format = ast_state->format; 844 if (!format) 845 return; 846 847 vbios_mode_info = &ast_state->vbios_mode_info; 848 849 ast_set_color_reg(ast, format); 850 ast_set_vbios_color_reg(ast, format, vbios_mode_info); 851 852 if (!crtc->state->mode_changed) 853 return; 854 855 adjusted_mode = &crtc->state->adjusted_mode; 856 857 ast_set_vbios_mode_reg(ast, adjusted_mode, vbios_mode_info); 858 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); 859 ast_set_std_reg(ast, adjusted_mode, vbios_mode_info); 860 ast_set_crtc_reg(ast, adjusted_mode, vbios_mode_info); 861 ast_set_dclk_reg(ast, adjusted_mode, vbios_mode_info); 862 ast_set_crtthd_reg(ast); 863 ast_set_sync_reg(ast, adjusted_mode, vbios_mode_info); 864 } 865 866 static void 867 ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, 868 struct drm_crtc_state *old_crtc_state) 869 { 870 ast_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 871 } 872 873 static void 874 ast_crtc_helper_atomic_disable(struct drm_crtc *crtc, 875 struct drm_crtc_state *old_crtc_state) 876 { 877 ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 878 } 879 880 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = { 881 .atomic_check = ast_crtc_helper_atomic_check, 882 .atomic_begin = ast_crtc_helper_atomic_begin, 883 .atomic_flush = ast_crtc_helper_atomic_flush, 884 .atomic_enable = ast_crtc_helper_atomic_enable, 885 .atomic_disable = ast_crtc_helper_atomic_disable, 886 }; 887 888 static void ast_crtc_reset(struct drm_crtc *crtc) 889 { 890 struct ast_crtc_state *ast_state = 891 kzalloc(sizeof(*ast_state), GFP_KERNEL); 892 893 if (crtc->state) 894 crtc->funcs->atomic_destroy_state(crtc, crtc->state); 895 896 __drm_atomic_helper_crtc_reset(crtc, &ast_state->base); 897 } 898 899 static void ast_crtc_destroy(struct drm_crtc *crtc) 900 { 901 drm_crtc_cleanup(crtc); 902 kfree(crtc); 903 } 904 905 static struct drm_crtc_state * 906 ast_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 907 { 908 struct ast_crtc_state *new_ast_state, *ast_state; 909 910 if (WARN_ON(!crtc->state)) 911 return NULL; 912 913 new_ast_state = kmalloc(sizeof(*new_ast_state), GFP_KERNEL); 914 if (!new_ast_state) 915 return NULL; 916 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_ast_state->base); 917 918 ast_state = to_ast_crtc_state(crtc->state); 919 920 new_ast_state->format = ast_state->format; 921 memcpy(&new_ast_state->vbios_mode_info, &ast_state->vbios_mode_info, 922 sizeof(new_ast_state->vbios_mode_info)); 923 924 return &new_ast_state->base; 925 } 926 927 static void ast_crtc_atomic_destroy_state(struct drm_crtc *crtc, 928 struct drm_crtc_state *state) 929 { 930 struct ast_crtc_state *ast_state = to_ast_crtc_state(state); 931 932 __drm_atomic_helper_crtc_destroy_state(&ast_state->base); 933 kfree(ast_state); 934 } 935 936 static const struct drm_crtc_funcs ast_crtc_funcs = { 937 .reset = ast_crtc_reset, 938 .gamma_set = drm_atomic_helper_legacy_gamma_set, 939 .destroy = ast_crtc_destroy, 940 .set_config = drm_atomic_helper_set_config, 941 .page_flip = drm_atomic_helper_page_flip, 942 .atomic_duplicate_state = ast_crtc_atomic_duplicate_state, 943 .atomic_destroy_state = ast_crtc_atomic_destroy_state, 944 }; 945 946 static int ast_crtc_init(struct drm_device *dev) 947 { 948 struct ast_private *ast = dev->dev_private; 949 struct ast_crtc *crtc; 950 int ret; 951 952 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL); 953 if (!crtc) 954 return -ENOMEM; 955 956 ret = drm_crtc_init_with_planes(dev, &crtc->base, &ast->primary_plane, 957 &ast->cursor_plane, &ast_crtc_funcs, 958 NULL); 959 if (ret) 960 goto err_kfree; 961 962 drm_mode_crtc_set_gamma_size(&crtc->base, 256); 963 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs); 964 return 0; 965 966 err_kfree: 967 kfree(crtc); 968 return ret; 969 } 970 971 /* 972 * Encoder 973 */ 974 975 static int ast_encoder_init(struct drm_device *dev) 976 { 977 struct ast_private *ast = dev->dev_private; 978 struct drm_encoder *encoder = &ast->encoder; 979 int ret; 980 981 ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC); 982 if (ret) 983 return ret; 984 985 encoder->possible_crtcs = 1; 986 987 return 0; 988 } 989 990 /* 991 * Connector 992 */ 993 994 static int ast_get_modes(struct drm_connector *connector) 995 { 996 struct ast_connector *ast_connector = to_ast_connector(connector); 997 struct ast_private *ast = connector->dev->dev_private; 998 struct edid *edid; 999 int ret; 1000 bool flags = false; 1001 if (ast->tx_chip_type == AST_TX_DP501) { 1002 ast->dp501_maxclk = 0xff; 1003 edid = kmalloc(128, GFP_KERNEL); 1004 if (!edid) 1005 return -ENOMEM; 1006 1007 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid); 1008 if (flags) 1009 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev); 1010 else 1011 kfree(edid); 1012 } 1013 if (!flags) 1014 edid = drm_get_edid(connector, &ast_connector->i2c->adapter); 1015 if (edid) { 1016 drm_connector_update_edid_property(&ast_connector->base, edid); 1017 ret = drm_add_edid_modes(connector, edid); 1018 kfree(edid); 1019 return ret; 1020 } else 1021 drm_connector_update_edid_property(&ast_connector->base, NULL); 1022 return 0; 1023 } 1024 1025 static enum drm_mode_status ast_mode_valid(struct drm_connector *connector, 1026 struct drm_display_mode *mode) 1027 { 1028 struct ast_private *ast = connector->dev->dev_private; 1029 int flags = MODE_NOMODE; 1030 uint32_t jtemp; 1031 1032 if (ast->support_wide_screen) { 1033 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050)) 1034 return MODE_OK; 1035 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800)) 1036 return MODE_OK; 1037 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900)) 1038 return MODE_OK; 1039 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768)) 1040 return MODE_OK; 1041 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900)) 1042 return MODE_OK; 1043 1044 if ((ast->chip == AST2100) || (ast->chip == AST2200) || 1045 (ast->chip == AST2300) || (ast->chip == AST2400) || 1046 (ast->chip == AST2500) || (ast->chip == AST1180)) { 1047 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080)) 1048 return MODE_OK; 1049 1050 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) { 1051 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 1052 if (jtemp & 0x01) 1053 return MODE_NOMODE; 1054 else 1055 return MODE_OK; 1056 } 1057 } 1058 } 1059 switch (mode->hdisplay) { 1060 case 640: 1061 if (mode->vdisplay == 480) flags = MODE_OK; 1062 break; 1063 case 800: 1064 if (mode->vdisplay == 600) flags = MODE_OK; 1065 break; 1066 case 1024: 1067 if (mode->vdisplay == 768) flags = MODE_OK; 1068 break; 1069 case 1280: 1070 if (mode->vdisplay == 1024) flags = MODE_OK; 1071 break; 1072 case 1600: 1073 if (mode->vdisplay == 1200) flags = MODE_OK; 1074 break; 1075 default: 1076 return flags; 1077 } 1078 1079 return flags; 1080 } 1081 1082 static void ast_connector_destroy(struct drm_connector *connector) 1083 { 1084 struct ast_connector *ast_connector = to_ast_connector(connector); 1085 ast_i2c_destroy(ast_connector->i2c); 1086 drm_connector_cleanup(connector); 1087 kfree(connector); 1088 } 1089 1090 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = { 1091 .get_modes = ast_get_modes, 1092 .mode_valid = ast_mode_valid, 1093 }; 1094 1095 static const struct drm_connector_funcs ast_connector_funcs = { 1096 .reset = drm_atomic_helper_connector_reset, 1097 .fill_modes = drm_helper_probe_single_connector_modes, 1098 .destroy = ast_connector_destroy, 1099 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1100 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1101 }; 1102 1103 static int ast_connector_init(struct drm_device *dev) 1104 { 1105 struct ast_connector *ast_connector; 1106 struct drm_connector *connector; 1107 struct drm_encoder *encoder; 1108 1109 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL); 1110 if (!ast_connector) 1111 return -ENOMEM; 1112 1113 connector = &ast_connector->base; 1114 ast_connector->i2c = ast_i2c_create(dev); 1115 if (!ast_connector->i2c) 1116 DRM_ERROR("failed to add ddc bus for connector\n"); 1117 1118 drm_connector_init_with_ddc(dev, connector, 1119 &ast_connector_funcs, 1120 DRM_MODE_CONNECTOR_VGA, 1121 &ast_connector->i2c->adapter); 1122 1123 drm_connector_helper_add(connector, &ast_connector_helper_funcs); 1124 1125 connector->interlace_allowed = 0; 1126 connector->doublescan_allowed = 0; 1127 1128 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1129 1130 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head); 1131 drm_connector_attach_encoder(connector, encoder); 1132 1133 return 0; 1134 } 1135 1136 /* allocate cursor cache and pin at start of VRAM */ 1137 static int ast_cursor_init(struct drm_device *dev) 1138 { 1139 struct ast_private *ast = dev->dev_private; 1140 size_t size, i; 1141 struct drm_gem_vram_object *gbo; 1142 int ret; 1143 1144 size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE); 1145 1146 for (i = 0; i < ARRAY_SIZE(ast->cursor.gbo); ++i) { 1147 gbo = drm_gem_vram_create(dev, size, 0); 1148 if (IS_ERR(gbo)) { 1149 ret = PTR_ERR(gbo); 1150 goto err_drm_gem_vram_put; 1151 } 1152 ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM | 1153 DRM_GEM_VRAM_PL_FLAG_TOPDOWN); 1154 if (ret) { 1155 drm_gem_vram_put(gbo); 1156 goto err_drm_gem_vram_put; 1157 } 1158 1159 ast->cursor.gbo[i] = gbo; 1160 } 1161 1162 return 0; 1163 1164 err_drm_gem_vram_put: 1165 while (i) { 1166 --i; 1167 gbo = ast->cursor.gbo[i]; 1168 drm_gem_vram_unpin(gbo); 1169 drm_gem_vram_put(gbo); 1170 ast->cursor.gbo[i] = NULL; 1171 } 1172 return ret; 1173 } 1174 1175 static void ast_cursor_fini(struct drm_device *dev) 1176 { 1177 struct ast_private *ast = dev->dev_private; 1178 size_t i; 1179 struct drm_gem_vram_object *gbo; 1180 1181 for (i = 0; i < ARRAY_SIZE(ast->cursor.gbo); ++i) { 1182 gbo = ast->cursor.gbo[i]; 1183 drm_gem_vram_unpin(gbo); 1184 drm_gem_vram_put(gbo); 1185 } 1186 } 1187 1188 int ast_mode_init(struct drm_device *dev) 1189 { 1190 struct ast_private *ast = dev->dev_private; 1191 int ret; 1192 1193 memset(&ast->primary_plane, 0, sizeof(ast->primary_plane)); 1194 ret = drm_universal_plane_init(dev, &ast->primary_plane, 0x01, 1195 &ast_primary_plane_funcs, 1196 ast_primary_plane_formats, 1197 ARRAY_SIZE(ast_primary_plane_formats), 1198 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 1199 if (ret) { 1200 DRM_ERROR("ast: drm_universal_plane_init() failed: %d\n", ret); 1201 return ret; 1202 } 1203 drm_plane_helper_add(&ast->primary_plane, 1204 &ast_primary_plane_helper_funcs); 1205 1206 ret = drm_universal_plane_init(dev, &ast->cursor_plane, 0x01, 1207 &ast_cursor_plane_funcs, 1208 ast_cursor_plane_formats, 1209 ARRAY_SIZE(ast_cursor_plane_formats), 1210 NULL, DRM_PLANE_TYPE_CURSOR, NULL); 1211 if (ret) { 1212 DRM_ERROR("drm_universal_plane_failed(): %d\n", ret); 1213 return ret; 1214 } 1215 drm_plane_helper_add(&ast->cursor_plane, 1216 &ast_cursor_plane_helper_funcs); 1217 1218 ast_cursor_init(dev); 1219 ast_crtc_init(dev); 1220 ast_encoder_init(dev); 1221 ast_connector_init(dev); 1222 1223 return 0; 1224 } 1225 1226 void ast_mode_fini(struct drm_device *dev) 1227 { 1228 ast_cursor_fini(dev); 1229 } 1230 1231 static int get_clock(void *i2c_priv) 1232 { 1233 struct ast_i2c_chan *i2c = i2c_priv; 1234 struct ast_private *ast = i2c->dev->dev_private; 1235 uint32_t val, val2, count, pass; 1236 1237 count = 0; 1238 pass = 0; 1239 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 1240 do { 1241 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 1242 if (val == val2) { 1243 pass++; 1244 } else { 1245 pass = 0; 1246 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; 1247 } 1248 } while ((pass < 5) && (count++ < 0x10000)); 1249 1250 return val & 1 ? 1 : 0; 1251 } 1252 1253 static int get_data(void *i2c_priv) 1254 { 1255 struct ast_i2c_chan *i2c = i2c_priv; 1256 struct ast_private *ast = i2c->dev->dev_private; 1257 uint32_t val, val2, count, pass; 1258 1259 count = 0; 1260 pass = 0; 1261 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1262 do { 1263 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1264 if (val == val2) { 1265 pass++; 1266 } else { 1267 pass = 0; 1268 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; 1269 } 1270 } while ((pass < 5) && (count++ < 0x10000)); 1271 1272 return val & 1 ? 1 : 0; 1273 } 1274 1275 static void set_clock(void *i2c_priv, int clock) 1276 { 1277 struct ast_i2c_chan *i2c = i2c_priv; 1278 struct ast_private *ast = i2c->dev->dev_private; 1279 int i; 1280 u8 ujcrb7, jtemp; 1281 1282 for (i = 0; i < 0x10000; i++) { 1283 ujcrb7 = ((clock & 0x01) ? 0 : 1); 1284 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7); 1285 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01); 1286 if (ujcrb7 == jtemp) 1287 break; 1288 } 1289 } 1290 1291 static void set_data(void *i2c_priv, int data) 1292 { 1293 struct ast_i2c_chan *i2c = i2c_priv; 1294 struct ast_private *ast = i2c->dev->dev_private; 1295 int i; 1296 u8 ujcrb7, jtemp; 1297 1298 for (i = 0; i < 0x10000; i++) { 1299 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2; 1300 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7); 1301 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04); 1302 if (ujcrb7 == jtemp) 1303 break; 1304 } 1305 } 1306 1307 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev) 1308 { 1309 struct ast_i2c_chan *i2c; 1310 int ret; 1311 1312 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL); 1313 if (!i2c) 1314 return NULL; 1315 1316 i2c->adapter.owner = THIS_MODULE; 1317 i2c->adapter.class = I2C_CLASS_DDC; 1318 i2c->adapter.dev.parent = &dev->pdev->dev; 1319 i2c->dev = dev; 1320 i2c_set_adapdata(&i2c->adapter, i2c); 1321 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1322 "AST i2c bit bus"); 1323 i2c->adapter.algo_data = &i2c->bit; 1324 1325 i2c->bit.udelay = 20; 1326 i2c->bit.timeout = 2; 1327 i2c->bit.data = i2c; 1328 i2c->bit.setsda = set_data; 1329 i2c->bit.setscl = set_clock; 1330 i2c->bit.getsda = get_data; 1331 i2c->bit.getscl = get_clock; 1332 ret = i2c_bit_add_bus(&i2c->adapter); 1333 if (ret) { 1334 DRM_ERROR("Failed to register bit i2c\n"); 1335 goto out_free; 1336 } 1337 1338 return i2c; 1339 out_free: 1340 kfree(i2c); 1341 return NULL; 1342 } 1343 1344 static void ast_i2c_destroy(struct ast_i2c_chan *i2c) 1345 { 1346 if (!i2c) 1347 return; 1348 i2c_del_adapter(&i2c->adapter); 1349 kfree(i2c); 1350 } 1351 1352 static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height) 1353 { 1354 union { 1355 u32 ul; 1356 u8 b[4]; 1357 } srcdata32[2], data32; 1358 union { 1359 u16 us; 1360 u8 b[2]; 1361 } data16; 1362 u32 csum = 0; 1363 s32 alpha_dst_delta, last_alpha_dst_delta; 1364 u8 *srcxor, *dstxor; 1365 int i, j; 1366 u32 per_pixel_copy, two_pixel_copy; 1367 1368 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1; 1369 last_alpha_dst_delta = alpha_dst_delta - (width << 1); 1370 1371 srcxor = src; 1372 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta; 1373 per_pixel_copy = width & 1; 1374 two_pixel_copy = width >> 1; 1375 1376 for (j = 0; j < height; j++) { 1377 for (i = 0; i < two_pixel_copy; i++) { 1378 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1379 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0; 1380 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1381 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1382 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4); 1383 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4); 1384 1385 writel(data32.ul, dstxor); 1386 csum += data32.ul; 1387 1388 dstxor += 4; 1389 srcxor += 8; 1390 1391 } 1392 1393 for (i = 0; i < per_pixel_copy; i++) { 1394 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0; 1395 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4); 1396 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4); 1397 writew(data16.us, dstxor); 1398 csum += (u32)data16.us; 1399 1400 dstxor += 2; 1401 srcxor += 4; 1402 } 1403 dstxor += last_alpha_dst_delta; 1404 } 1405 return csum; 1406 } 1407 1408 static int ast_cursor_update(void *dst, void *src, unsigned int width, 1409 unsigned int height) 1410 { 1411 u32 csum; 1412 1413 /* do data transfer to cursor cache */ 1414 csum = copy_cursor_image(src, dst, width, height); 1415 1416 /* write checksum + signature */ 1417 dst += AST_HWC_SIZE; 1418 writel(csum, dst); 1419 writel(width, dst + AST_HWC_SIGNATURE_SizeX); 1420 writel(height, dst + AST_HWC_SIGNATURE_SizeY); 1421 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX); 1422 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY); 1423 1424 return 0; 1425 } 1426 1427 static void ast_cursor_set_base(struct ast_private *ast, u64 address) 1428 { 1429 u8 addr0 = (address >> 3) & 0xff; 1430 u8 addr1 = (address >> 11) & 0xff; 1431 u8 addr2 = (address >> 19) & 0xff; 1432 1433 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0); 1434 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1); 1435 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2); 1436 } 1437 1438 static int ast_cursor_move(struct drm_crtc *crtc, 1439 int x, int y) 1440 { 1441 struct ast_crtc *ast_crtc = to_ast_crtc(crtc); 1442 struct ast_private *ast = crtc->dev->dev_private; 1443 struct drm_gem_vram_object *gbo; 1444 int x_offset, y_offset; 1445 u8 *dst, *sig; 1446 u8 jreg; 1447 1448 gbo = ast->cursor.gbo[ast->cursor.next_index]; 1449 dst = drm_gem_vram_vmap(gbo); 1450 if (IS_ERR(dst)) 1451 return PTR_ERR(dst); 1452 1453 sig = dst + AST_HWC_SIZE; 1454 writel(x, sig + AST_HWC_SIGNATURE_X); 1455 writel(y, sig + AST_HWC_SIGNATURE_Y); 1456 1457 x_offset = ast_crtc->offset_x; 1458 y_offset = ast_crtc->offset_y; 1459 if (x < 0) { 1460 x_offset = (-x) + ast_crtc->offset_x; 1461 x = 0; 1462 } 1463 1464 if (y < 0) { 1465 y_offset = (-y) + ast_crtc->offset_y; 1466 y = 0; 1467 } 1468 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset); 1469 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset); 1470 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff)); 1471 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f)); 1472 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff)); 1473 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07)); 1474 1475 /* dummy write to fire HWC */ 1476 jreg = 0x02 | 1477 0x01; /* enable ARGB4444 cursor */ 1478 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg); 1479 1480 drm_gem_vram_vunmap(gbo, dst); 1481 1482 return 0; 1483 } 1484