1 /* 2 * Copyright 2012 Red Hat Inc. 3 * Parts based on xf86-video-ast 4 * Copyright (c) 2005 ASPEED Technology Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 * 26 */ 27 /* 28 * Authors: Dave Airlie <airlied@redhat.com> 29 */ 30 31 #include <linux/delay.h> 32 #include <linux/pci.h> 33 34 #include <drm/drm_atomic.h> 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_color_mgmt.h> 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_damage_helper.h> 39 #include <drm/drm_format_helper.h> 40 #include <drm/drm_fourcc.h> 41 #include <drm/drm_gem_atomic_helper.h> 42 #include <drm/drm_gem_framebuffer_helper.h> 43 #include <drm/drm_gem_shmem_helper.h> 44 #include <drm/drm_managed.h> 45 #include <drm/drm_panic.h> 46 #include <drm/drm_print.h> 47 #include <drm/drm_probe_helper.h> 48 49 #include "ast_drv.h" 50 #include "ast_tables.h" 51 #include "ast_vbios.h" 52 53 #define AST_LUT_SIZE 256 54 55 #define AST_PRIMARY_PLANE_MAX_OFFSET (BIT(16) - 1) 56 57 static unsigned long ast_fb_vram_offset(void) 58 { 59 return 0; // with shmem, the primary plane is always at offset 0 60 } 61 62 static unsigned long ast_fb_vram_size(struct ast_device *ast) 63 { 64 struct drm_device *dev = &ast->base; 65 unsigned long offset = ast_fb_vram_offset(); // starts at offset 66 long cursor_offset = ast_cursor_vram_offset(ast); // ends at cursor offset 67 68 if (cursor_offset < 0) 69 cursor_offset = ast->vram_size; // no cursor; it's all ours 70 if (drm_WARN_ON_ONCE(dev, offset > cursor_offset)) 71 return 0; // cannot legally happen; signal error 72 return cursor_offset - offset; 73 } 74 75 static void ast_set_gamma_lut(struct drm_crtc *crtc, unsigned int index, 76 u16 red, u16 green, u16 blue) 77 { 78 struct drm_device *dev = crtc->dev; 79 struct ast_device *ast = to_ast_device(dev); 80 u8 i8 = index & 0xff; 81 u8 r8 = red >> 8; 82 u8 g8 = green >> 8; 83 u8 b8 = blue >> 8; 84 85 if (drm_WARN_ON_ONCE(dev, index != i8)) 86 return; /* driver bug */ 87 88 ast_io_write8(ast, AST_IO_VGADWR, i8); 89 ast_io_read8(ast, AST_IO_VGASRI); 90 ast_io_write8(ast, AST_IO_VGAPDR, r8); 91 ast_io_read8(ast, AST_IO_VGASRI); 92 ast_io_write8(ast, AST_IO_VGAPDR, g8); 93 ast_io_read8(ast, AST_IO_VGASRI); 94 ast_io_write8(ast, AST_IO_VGAPDR, b8); 95 ast_io_read8(ast, AST_IO_VGASRI); 96 } 97 98 static void ast_crtc_fill_gamma(struct ast_device *ast, 99 const struct drm_format_info *format) 100 { 101 struct drm_crtc *crtc = &ast->crtc; 102 103 switch (format->format) { 104 case DRM_FORMAT_C8: 105 /* gamma table is used as color palette */ 106 drm_crtc_fill_palette_8(crtc, ast_set_gamma_lut); 107 break; 108 case DRM_FORMAT_XRGB1555: 109 case DRM_FORMAT_RGB565: 110 /* also uses 24-bit gamma correction on high-color modes */ 111 fallthrough; 112 case DRM_FORMAT_XRGB8888: 113 drm_crtc_fill_gamma_888(crtc, ast_set_gamma_lut); 114 break; 115 default: 116 drm_warn_once(&ast->base, "Unsupported format %p4cc for gamma correction\n", 117 &format->format); 118 break; 119 } 120 } 121 122 static void ast_crtc_load_gamma(struct ast_device *ast, 123 const struct drm_format_info *format, 124 struct drm_color_lut *lut) 125 { 126 struct drm_crtc *crtc = &ast->crtc; 127 128 switch (format->format) { 129 case DRM_FORMAT_C8: 130 /* gamma table is used as color palette */ 131 drm_crtc_load_palette_8(crtc, lut, ast_set_gamma_lut); 132 break; 133 case DRM_FORMAT_XRGB1555: 134 case DRM_FORMAT_RGB565: 135 /* also uses 24-bit gamma correction on high-color modes */ 136 fallthrough; 137 case DRM_FORMAT_XRGB8888: 138 drm_crtc_load_gamma_888(crtc, lut, ast_set_gamma_lut); 139 break; 140 default: 141 drm_warn_once(&ast->base, "Unsupported format %p4cc for gamma correction\n", 142 &format->format); 143 break; 144 } 145 } 146 147 static void ast_set_vbios_color_reg(struct ast_device *ast, 148 const struct drm_format_info *format, 149 const struct ast_vbios_enhtable *vmode) 150 { 151 u8 vgacr8c = 0x00; 152 u8 vgacr92 = 0x00; 153 154 switch (format->format) { 155 case DRM_FORMAT_C8: 156 vgacr8c |= AST_IO_VGACR8C_CUR_MODE_VGA; 157 vgacr92 = 8; 158 break; 159 case DRM_FORMAT_XRGB1555: 160 vgacr8c |= AST_IO_VGACR8C_CUR_MODE_15_BPP; 161 vgacr92 = 15; 162 break; 163 case DRM_FORMAT_RGB565: 164 vgacr8c |= AST_IO_VGACR8C_CUR_MODE_16_BPP; 165 vgacr92 = 16; 166 break; 167 case DRM_FORMAT_XRGB8888: 168 vgacr8c |= AST_IO_VGACR8C_CUR_MODE_32_BPP; 169 vgacr92 = 32; 170 break; 171 } 172 173 ast_set_index_reg(ast, AST_IO_VGACRI, 0x8c, vgacr8c); 174 175 ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0x00); 176 177 if (vmode->flags & NewModeInfo) { 178 ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, AST_IO_VGACR91_PASSWORD); 179 ast_set_index_reg(ast, AST_IO_VGACRI, 0x92, vgacr92); 180 } 181 } 182 183 static void ast_set_vbios_mode_reg(struct ast_device *ast, 184 const struct drm_display_mode *adjusted_mode, 185 const struct ast_vbios_enhtable *vmode) 186 { 187 u32 refresh_rate_index, mode_id; 188 189 refresh_rate_index = vmode->refresh_rate_index; 190 mode_id = vmode->mode_id; 191 192 ast_set_index_reg(ast, AST_IO_VGACRI, 0x8d, refresh_rate_index & 0xff); 193 ast_set_index_reg(ast, AST_IO_VGACRI, 0x8e, mode_id & 0xff); 194 195 ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0x00); 196 197 if (vmode->flags & NewModeInfo) { 198 ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, AST_IO_VGACR91_PASSWORD); 199 ast_set_index_reg(ast, AST_IO_VGACRI, 0x93, adjusted_mode->clock / 1000); 200 ast_set_index_reg(ast, AST_IO_VGACRI, 0x94, adjusted_mode->crtc_hdisplay); 201 ast_set_index_reg(ast, AST_IO_VGACRI, 0x95, adjusted_mode->crtc_hdisplay >> 8); 202 ast_set_index_reg(ast, AST_IO_VGACRI, 0x96, adjusted_mode->crtc_vdisplay); 203 ast_set_index_reg(ast, AST_IO_VGACRI, 0x97, adjusted_mode->crtc_vdisplay >> 8); 204 } 205 } 206 207 static void ast_set_std_reg(struct ast_device *ast, 208 struct drm_display_mode *mode, 209 const struct ast_vbios_stdtable *stdtable) 210 { 211 u32 i; 212 u8 jreg; 213 214 jreg = stdtable->misc; 215 ast_io_write8(ast, AST_IO_VGAMR_W, jreg); 216 217 /* Set SEQ; except Screen Disable field */ 218 ast_set_index_reg(ast, AST_IO_VGASRI, 0x00, 0x03); 219 ast_set_index_reg_mask(ast, AST_IO_VGASRI, 0x01, 0x20, stdtable->seq[0]); 220 for (i = 1; i < 4; i++) { 221 jreg = stdtable->seq[i]; 222 ast_set_index_reg(ast, AST_IO_VGASRI, (i + 1), jreg); 223 } 224 225 /* Set CRTC; except base address and offset */ 226 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x11, 0x7f, 0x00); 227 for (i = 0; i < 12; i++) 228 ast_set_index_reg(ast, AST_IO_VGACRI, i, stdtable->crtc[i]); 229 for (i = 14; i < 19; i++) 230 ast_set_index_reg(ast, AST_IO_VGACRI, i, stdtable->crtc[i]); 231 for (i = 20; i < 25; i++) 232 ast_set_index_reg(ast, AST_IO_VGACRI, i, stdtable->crtc[i]); 233 234 /* set AR */ 235 jreg = ast_io_read8(ast, AST_IO_VGAIR1_R); 236 for (i = 0; i < 20; i++) { 237 jreg = stdtable->ar[i]; 238 ast_io_write8(ast, AST_IO_VGAARI_W, (u8)i); 239 ast_io_write8(ast, AST_IO_VGAARI_W, jreg); 240 } 241 ast_io_write8(ast, AST_IO_VGAARI_W, 0x14); 242 ast_io_write8(ast, AST_IO_VGAARI_W, 0x00); 243 244 jreg = ast_io_read8(ast, AST_IO_VGAIR1_R); 245 ast_io_write8(ast, AST_IO_VGAARI_W, 0x20); 246 247 /* Set GR */ 248 for (i = 0; i < 9; i++) 249 ast_set_index_reg(ast, AST_IO_VGAGRI, i, stdtable->gr[i]); 250 } 251 252 static void ast_set_crtc_reg(struct ast_device *ast, struct drm_display_mode *mode, 253 const struct ast_vbios_enhtable *vmode) 254 { 255 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0; 256 u16 temp; 257 unsigned char crtc_hsync_precatch = 0; 258 259 if (ast->quirks->crtc_hsync_precatch_needed && (vmode->flags & AST2500PreCatchCRT)) 260 crtc_hsync_precatch = 40; 261 262 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x11, 0x7f, 0x00); 263 264 temp = (mode->crtc_htotal >> 3) - 5; 265 if (temp & 0x100) 266 jregAC |= 0x01; /* HT D[8] */ 267 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x00, 0x00, temp); 268 269 temp = (mode->crtc_hdisplay >> 3) - 1; 270 if (temp & 0x100) 271 jregAC |= 0x04; /* HDE D[8] */ 272 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x01, 0x00, temp); 273 274 temp = (mode->crtc_hblank_start >> 3) - 1; 275 if (temp & 0x100) 276 jregAC |= 0x10; /* HBS D[8] */ 277 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x02, 0x00, temp); 278 279 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f; 280 if (temp & 0x20) 281 jreg05 |= 0x80; /* HBE D[5] */ 282 if (temp & 0x40) 283 jregAD |= 0x01; /* HBE D[5] */ 284 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x03, 0xE0, (temp & 0x1f)); 285 286 temp = ((mode->crtc_hsync_start - crtc_hsync_precatch) >> 3) - 1; 287 if (temp & 0x100) 288 jregAC |= 0x40; /* HRS D[5] */ 289 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x04, 0x00, temp); 290 291 temp = (((mode->crtc_hsync_end - crtc_hsync_precatch) >> 3) - 1) & 0x3f; 292 if (temp & 0x20) 293 jregAD |= 0x04; /* HRE D[5] */ 294 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); 295 296 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xAC, 0x00, jregAC); 297 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xAD, 0x00, jregAD); 298 299 if (ast->quirks->crtc_hsync_add4_needed && mode->crtc_vdisplay == 1080) 300 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xFC, 0xFD, 0x02); 301 else 302 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xFC, 0xFD, 0x00); 303 304 /* vert timings */ 305 temp = (mode->crtc_vtotal) - 2; 306 if (temp & 0x100) 307 jreg07 |= 0x01; 308 if (temp & 0x200) 309 jreg07 |= 0x20; 310 if (temp & 0x400) 311 jregAE |= 0x01; 312 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x06, 0x00, temp); 313 314 temp = (mode->crtc_vsync_start) - 1; 315 if (temp & 0x100) 316 jreg07 |= 0x04; 317 if (temp & 0x200) 318 jreg07 |= 0x80; 319 if (temp & 0x400) 320 jregAE |= 0x08; 321 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x10, 0x00, temp); 322 323 temp = (mode->crtc_vsync_end - 1) & 0x3f; 324 if (temp & 0x10) 325 jregAE |= 0x20; 326 if (temp & 0x20) 327 jregAE |= 0x40; 328 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x11, 0x70, temp & 0xf); 329 330 temp = mode->crtc_vdisplay - 1; 331 if (temp & 0x100) 332 jreg07 |= 0x02; 333 if (temp & 0x200) 334 jreg07 |= 0x40; 335 if (temp & 0x400) 336 jregAE |= 0x02; 337 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x12, 0x00, temp); 338 339 temp = mode->crtc_vblank_start - 1; 340 if (temp & 0x100) 341 jreg07 |= 0x08; 342 if (temp & 0x200) 343 jreg09 |= 0x20; 344 if (temp & 0x400) 345 jregAE |= 0x04; 346 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x15, 0x00, temp); 347 348 temp = mode->crtc_vblank_end - 1; 349 if (temp & 0x100) 350 jregAE |= 0x10; 351 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x16, 0x00, temp); 352 353 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x07, 0x00, jreg07); 354 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x09, 0xdf, jreg09); 355 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xAE, 0x00, (jregAE | 0x80)); 356 357 if (crtc_hsync_precatch) 358 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0x3f, 0x80); 359 else 360 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0x3f, 0x00); 361 362 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x11, 0x7f, 0x80); 363 } 364 365 static void ast_set_offset_reg(struct ast_device *ast, 366 struct drm_framebuffer *fb) 367 { 368 u16 offset; 369 370 offset = fb->pitches[0] >> 3; 371 ast_set_index_reg(ast, AST_IO_VGACRI, 0x13, (offset & 0xff)); 372 ast_set_index_reg(ast, AST_IO_VGACRI, 0xb0, (offset >> 8) & 0x3f); 373 } 374 375 static void ast_set_dclk_reg(struct ast_device *ast, 376 struct drm_display_mode *mode, 377 const struct ast_vbios_enhtable *vmode) 378 { 379 const struct ast_vbios_dclk_info *clk_info = &ast->dclk_table[vmode->dclk_index]; 380 381 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xc0, 0x00, clk_info->param1); 382 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xc1, 0x00, clk_info->param2); 383 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xbb, 0x0f, 384 (clk_info->param3 & 0xc0) | 385 ((clk_info->param3 & 0x3) << 4)); 386 } 387 388 static void ast_set_color_reg(struct ast_device *ast, 389 const struct drm_format_info *format) 390 { 391 u8 vgacra0 = 0x00; 392 u8 vgacra3 = 0x00; 393 u8 vgacra8 = 0x00; 394 395 vgacra0 |= AST_IO_VGACRA0_MEMORY_CHAIN4_MODE | 396 AST_IO_VGACRA0_LINEAR_EXT_ACCESS | 397 AST_IO_VGACRA0_SEGMENTED_EXT_ACCESS; 398 399 switch (format->format) { 400 case DRM_FORMAT_C8: 401 vgacra3 |= AST_IO_VGACRA3_256_COLORS; 402 vgacra8 &= ~AST_IO_VGACRA8_GAMMA_CORRECTION_ENABLED; 403 break; 404 case DRM_FORMAT_XRGB1555: 405 vgacra3 |= AST_IO_VGACRA3_15_BPP; 406 vgacra8 |= AST_IO_VGACRA8_GAMMA_CORRECTION_ENABLED; 407 break; 408 case DRM_FORMAT_RGB565: 409 vgacra3 |= AST_IO_VGACRA3_16_BPP; 410 vgacra8 |= AST_IO_VGACRA8_GAMMA_CORRECTION_ENABLED; 411 break; 412 case DRM_FORMAT_XRGB8888: 413 vgacra3 |= AST_IO_VGACRA3_32_BPP; 414 vgacra8 |= AST_IO_VGACRA8_GAMMA_CORRECTION_ENABLED; 415 break; 416 } 417 418 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa0, 0x8f, vgacra0); 419 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xf0, vgacra3); 420 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa8, 0xfd, vgacra8); 421 } 422 423 static void ast_set_crtthd_reg(struct ast_device *ast) 424 { 425 u8 vgacra6 = ast->quirks->crtc_mem_req_threshold_low; 426 u8 vgacra7 = ast->quirks->crtc_mem_req_threshold_high; 427 428 ast_set_index_reg(ast, AST_IO_VGACRI, 0xa7, vgacra7); 429 ast_set_index_reg(ast, AST_IO_VGACRI, 0xa6, vgacra6); 430 } 431 432 static void ast_set_sync_reg(struct ast_device *ast, 433 struct drm_display_mode *mode, 434 const struct ast_vbios_enhtable *vmode) 435 { 436 u8 jreg; 437 438 jreg = ast_io_read8(ast, AST_IO_VGAMR_R); 439 jreg &= ~0xC0; 440 if (vmode->flags & NVSync) 441 jreg |= 0x80; 442 if (vmode->flags & NHSync) 443 jreg |= 0x40; 444 ast_io_write8(ast, AST_IO_VGAMR_W, jreg); 445 } 446 447 static void ast_set_start_address_crt1(struct ast_device *ast, 448 unsigned int offset) 449 { 450 u32 addr; 451 452 addr = offset >> 2; 453 ast_set_index_reg(ast, AST_IO_VGACRI, 0x0d, (u8)(addr & 0xff)); 454 ast_set_index_reg(ast, AST_IO_VGACRI, 0x0c, (u8)((addr >> 8) & 0xff)); 455 ast_set_index_reg(ast, AST_IO_VGACRI, 0xaf, (u8)((addr >> 16) & 0xff)); 456 457 } 458 459 static void ast_wait_for_vretrace(struct ast_device *ast) 460 { 461 unsigned long timeout = jiffies + HZ; 462 u8 vgair1; 463 464 do { 465 vgair1 = ast_io_read8(ast, AST_IO_VGAIR1_R); 466 } while (!(vgair1 & AST_IO_VGAIR1_VREFRESH) && time_before(jiffies, timeout)); 467 } 468 469 /* 470 * Planes 471 */ 472 473 int ast_plane_init(struct drm_device *dev, struct ast_plane *ast_plane, 474 u64 offset, unsigned long size, 475 uint32_t possible_crtcs, 476 const struct drm_plane_funcs *funcs, 477 const uint32_t *formats, unsigned int format_count, 478 const uint64_t *format_modifiers, 479 enum drm_plane_type type) 480 { 481 struct drm_plane *plane = &ast_plane->base; 482 483 ast_plane->offset = offset; 484 ast_plane->size = size; 485 486 return drm_universal_plane_init(dev, plane, possible_crtcs, funcs, 487 formats, format_count, format_modifiers, 488 type, NULL); 489 } 490 491 void __iomem *ast_plane_vaddr(struct ast_plane *ast_plane) 492 { 493 struct ast_device *ast = to_ast_device(ast_plane->base.dev); 494 495 return ast->vram + ast_plane->offset; 496 } 497 498 /* 499 * Primary plane 500 */ 501 502 static const uint32_t ast_primary_plane_formats[] = { 503 DRM_FORMAT_XRGB8888, 504 DRM_FORMAT_RGB565, 505 DRM_FORMAT_XRGB1555, 506 DRM_FORMAT_C8, 507 }; 508 509 static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane, 510 struct drm_atomic_commit *state) 511 { 512 struct drm_device *dev = plane->dev; 513 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); 514 struct drm_crtc_state *new_crtc_state = NULL; 515 struct ast_crtc_state *new_ast_crtc_state; 516 int ret; 517 518 if (new_plane_state->crtc) 519 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 520 521 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, 522 DRM_PLANE_NO_SCALING, 523 DRM_PLANE_NO_SCALING, 524 false, true); 525 if (ret) { 526 return ret; 527 } else if (!new_plane_state->visible) { 528 if (drm_WARN_ON(dev, new_plane_state->crtc)) /* cannot legally happen */ 529 return -EINVAL; 530 else 531 return 0; 532 } 533 534 new_ast_crtc_state = to_ast_crtc_state(new_crtc_state); 535 536 new_ast_crtc_state->format = new_plane_state->fb->format; 537 538 return 0; 539 } 540 541 static void ast_handle_damage(struct ast_plane *ast_plane, struct iosys_map *src, 542 struct drm_framebuffer *fb, 543 const struct drm_rect *clip, 544 struct drm_format_conv_state *fmtcnv_state) 545 { 546 struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(ast_plane_vaddr(ast_plane)); 547 548 iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, clip)); 549 550 #if defined(__BIG_ENDIAN) 551 drm_fb_swab(&dst, fb->pitches, src, fb, clip, !src[0].is_iomem, fmtcnv_state); 552 #else 553 drm_fb_memcpy(&dst, fb->pitches, src, fb, clip); 554 #endif 555 } 556 557 static void ast_primary_plane_helper_atomic_update(struct drm_plane *plane, 558 struct drm_atomic_commit *state) 559 { 560 struct drm_device *dev = plane->dev; 561 struct ast_device *ast = to_ast_device(dev); 562 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 563 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 564 struct drm_framebuffer *fb = plane_state->fb; 565 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 566 struct drm_framebuffer *old_fb = old_plane_state->fb; 567 struct ast_plane *ast_plane = to_ast_plane(plane); 568 struct drm_crtc *crtc = plane_state->crtc; 569 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 570 struct drm_rect damage; 571 struct drm_atomic_helper_damage_iter iter; 572 573 if (!old_fb || (fb->format != old_fb->format) || crtc_state->mode_changed) { 574 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state); 575 576 ast_set_color_reg(ast, fb->format); 577 ast_set_vbios_color_reg(ast, fb->format, ast_crtc_state->vmode); 578 } 579 580 /* if the buffer comes from another device */ 581 if (drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE) == 0) { 582 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 583 drm_atomic_for_each_plane_damage(&iter, &damage) { 584 ast_handle_damage(ast_plane, shadow_plane_state->data, fb, &damage, 585 &shadow_plane_state->fmtcnv_state); 586 } 587 588 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 589 } 590 591 /* 592 * Some BMCs stop scanning out the video signal after the driver 593 * reprogrammed the offset. This stalls display output for several 594 * seconds and makes the display unusable. Therefore only update 595 * the offset if it changes. 596 */ 597 if (!old_fb || old_fb->pitches[0] != fb->pitches[0]) 598 ast_set_offset_reg(ast, fb); 599 } 600 601 static void ast_primary_plane_helper_atomic_enable(struct drm_plane *plane, 602 struct drm_atomic_commit *state) 603 { 604 struct ast_device *ast = to_ast_device(plane->dev); 605 struct ast_plane *ast_plane = to_ast_plane(plane); 606 607 /* 608 * Some BMCs stop scanning out the video signal after the driver 609 * reprogrammed the scanout address. This stalls display 610 * output for several seconds and makes the display unusable. 611 * Therefore only reprogram the address after enabling the plane. 612 */ 613 ast_set_start_address_crt1(ast, (u32)ast_plane->offset); 614 } 615 616 static void ast_primary_plane_helper_atomic_disable(struct drm_plane *plane, 617 struct drm_atomic_commit *state) 618 { 619 /* 620 * Keep this empty function to avoid calling 621 * atomic_update when disabling the plane. 622 */ 623 } 624 625 static int ast_primary_plane_helper_get_scanout_buffer(struct drm_plane *plane, 626 struct drm_scanout_buffer *sb) 627 { 628 struct ast_plane *ast_plane = to_ast_plane(plane); 629 630 if (plane->state && plane->state->fb) { 631 sb->format = plane->state->fb->format; 632 sb->width = plane->state->fb->width; 633 sb->height = plane->state->fb->height; 634 sb->pitch[0] = plane->state->fb->pitches[0]; 635 iosys_map_set_vaddr_iomem(&sb->map[0], ast_plane_vaddr(ast_plane)); 636 return 0; 637 } 638 return -ENODEV; 639 } 640 641 static const struct drm_plane_helper_funcs ast_primary_plane_helper_funcs = { 642 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 643 .atomic_check = ast_primary_plane_helper_atomic_check, 644 .atomic_update = ast_primary_plane_helper_atomic_update, 645 .atomic_enable = ast_primary_plane_helper_atomic_enable, 646 .atomic_disable = ast_primary_plane_helper_atomic_disable, 647 .get_scanout_buffer = ast_primary_plane_helper_get_scanout_buffer, 648 }; 649 650 static const struct drm_plane_funcs ast_primary_plane_funcs = { 651 .update_plane = drm_atomic_helper_update_plane, 652 .disable_plane = drm_atomic_helper_disable_plane, 653 .destroy = drm_plane_cleanup, 654 DRM_GEM_SHADOW_PLANE_FUNCS, 655 }; 656 657 static int ast_primary_plane_init(struct ast_device *ast) 658 { 659 struct drm_device *dev = &ast->base; 660 struct ast_plane *ast_primary_plane = &ast->primary_plane; 661 struct drm_plane *primary_plane = &ast_primary_plane->base; 662 u64 offset = ast_fb_vram_offset(); 663 unsigned long size = ast_fb_vram_size(ast); 664 int ret; 665 666 ret = ast_plane_init(dev, ast_primary_plane, offset, size, 667 0x01, &ast_primary_plane_funcs, 668 ast_primary_plane_formats, ARRAY_SIZE(ast_primary_plane_formats), 669 NULL, DRM_PLANE_TYPE_PRIMARY); 670 if (ret) { 671 drm_err(dev, "ast_plane_init() failed: %d\n", ret); 672 return ret; 673 } 674 drm_plane_helper_add(primary_plane, &ast_primary_plane_helper_funcs); 675 drm_plane_enable_fb_damage_clips(primary_plane); 676 677 return 0; 678 } 679 680 /* 681 * CRTC 682 */ 683 684 static enum drm_mode_status 685 ast_crtc_helper_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) 686 { 687 struct ast_device *ast = to_ast_device(crtc->dev); 688 const struct ast_vbios_enhtable *vmode; 689 690 vmode = ast_vbios_find_mode(ast, mode); 691 if (!vmode) 692 return MODE_NOMODE; 693 694 return MODE_OK; 695 } 696 697 static void ast_crtc_helper_mode_set_nofb(struct drm_crtc *crtc) 698 { 699 struct drm_device *dev = crtc->dev; 700 struct ast_device *ast = to_ast_device(dev); 701 struct drm_crtc_state *crtc_state = crtc->state; 702 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state); 703 const struct ast_vbios_stdtable *std_table = ast_crtc_state->std_table; 704 const struct ast_vbios_enhtable *vmode = ast_crtc_state->vmode; 705 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 706 707 /* 708 * Ensure that no scanout takes place before reprogramming mode 709 * and format registers. 710 * 711 * TODO: Get vblank interrupts working and remove this line. 712 */ 713 ast_wait_for_vretrace(ast); 714 715 ast_set_vbios_mode_reg(ast, adjusted_mode, vmode); 716 ast_set_index_reg(ast, AST_IO_VGACRI, 0xa1, 0x06); 717 ast_set_std_reg(ast, adjusted_mode, std_table); 718 ast_set_crtc_reg(ast, adjusted_mode, vmode); 719 ast_set_dclk_reg(ast, adjusted_mode, vmode); 720 ast_set_crtthd_reg(ast); 721 ast_set_sync_reg(ast, adjusted_mode, vmode); 722 } 723 724 static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc, 725 struct drm_atomic_commit *state) 726 { 727 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 728 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 729 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); 730 struct ast_crtc_state *old_ast_crtc_state = to_ast_crtc_state(old_crtc_state); 731 struct drm_device *dev = crtc->dev; 732 struct ast_device *ast = to_ast_device(dev); 733 struct ast_crtc_state *ast_state; 734 const struct drm_format_info *format; 735 const struct ast_vbios_enhtable *vmode; 736 unsigned int hborder = 0; 737 unsigned int vborder = 0; 738 int ret; 739 740 if (!crtc_state->enable) 741 return 0; 742 743 ret = drm_atomic_helper_check_crtc_primary_plane(crtc_state); 744 if (ret) 745 return ret; 746 747 ast_state = to_ast_crtc_state(crtc_state); 748 749 format = ast_state->format; 750 if (drm_WARN_ON_ONCE(dev, !format)) 751 return -EINVAL; /* BUG: We didn't set format in primary check(). */ 752 753 /* 754 * The gamma LUT has to be reloaded after changing the primary 755 * plane's color format. 756 */ 757 if (old_ast_crtc_state->format != format) 758 crtc_state->color_mgmt_changed = true; 759 760 if (crtc_state->color_mgmt_changed && crtc_state->gamma_lut) { 761 if (crtc_state->gamma_lut->length != 762 AST_LUT_SIZE * sizeof(struct drm_color_lut)) { 763 drm_err(dev, "Wrong size for gamma_lut %zu\n", 764 crtc_state->gamma_lut->length); 765 return -EINVAL; 766 } 767 } 768 769 /* 770 * Set register tables. 771 * 772 * TODO: These tables mix all kinds of fields and should 773 * probably be resolved into various helper functions. 774 */ 775 switch (format->format) { 776 case DRM_FORMAT_C8: 777 ast_state->std_table = &vbios_stdtable[VGAModeIndex]; 778 break; 779 case DRM_FORMAT_XRGB1555: 780 case DRM_FORMAT_RGB565: 781 ast_state->std_table = &vbios_stdtable[HiCModeIndex]; 782 break; 783 case DRM_FORMAT_XRGB8888: 784 ast_state->std_table = &vbios_stdtable[TrueCModeIndex]; 785 break; 786 default: 787 return -EINVAL; 788 } 789 790 /* 791 * Find the VBIOS mode and adjust the DRM display mode accordingly 792 * if a full modeset is required. Otherwise keep the existing values. 793 */ 794 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 795 vmode = ast_vbios_find_mode(ast, &crtc_state->mode); 796 if (!vmode) 797 return -EINVAL; 798 ast_state->vmode = vmode; 799 800 if (vmode->flags & HBorder) 801 hborder = 8; 802 if (vmode->flags & VBorder) 803 vborder = 8; 804 805 adjusted_mode->crtc_hdisplay = vmode->hde; 806 adjusted_mode->crtc_hblank_start = vmode->hde + hborder; 807 adjusted_mode->crtc_hblank_end = vmode->ht - hborder; 808 adjusted_mode->crtc_hsync_start = vmode->hde + hborder + vmode->hfp; 809 adjusted_mode->crtc_hsync_end = vmode->hde + hborder + vmode->hfp + vmode->hsync; 810 adjusted_mode->crtc_htotal = vmode->ht; 811 812 adjusted_mode->crtc_vdisplay = vmode->vde; 813 adjusted_mode->crtc_vblank_start = vmode->vde + vborder; 814 adjusted_mode->crtc_vblank_end = vmode->vt - vborder; 815 adjusted_mode->crtc_vsync_start = vmode->vde + vborder + vmode->vfp; 816 adjusted_mode->crtc_vsync_end = vmode->vde + vborder + vmode->vfp + vmode->vsync; 817 adjusted_mode->crtc_vtotal = vmode->vt; 818 } 819 820 return 0; 821 } 822 823 static void 824 ast_crtc_helper_atomic_flush(struct drm_crtc *crtc, 825 struct drm_atomic_commit *state) 826 { 827 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 828 crtc); 829 struct drm_device *dev = crtc->dev; 830 struct ast_device *ast = to_ast_device(dev); 831 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state); 832 833 /* 834 * The gamma LUT has to be reloaded after changing the primary 835 * plane's color format. 836 */ 837 if (crtc_state->enable && crtc_state->color_mgmt_changed) { 838 if (crtc_state->gamma_lut) 839 ast_crtc_load_gamma(ast, 840 ast_crtc_state->format, 841 crtc_state->gamma_lut->data); 842 else 843 ast_crtc_fill_gamma(ast, ast_crtc_state->format); 844 } 845 } 846 847 static void ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_commit *state) 848 { 849 struct ast_device *ast = to_ast_device(crtc->dev); 850 u8 vgacr17 = 0x00; 851 u8 vgacrb6 = 0xff; 852 853 vgacr17 |= AST_IO_VGACR17_SYNC_ENABLE; 854 vgacrb6 &= ~(AST_IO_VGACRB6_VSYNC_OFF | AST_IO_VGACRB6_HSYNC_OFF); 855 856 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x17, 0x7f, vgacr17); 857 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xfc, vgacrb6); 858 } 859 860 static void ast_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_commit *state) 861 { 862 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); 863 struct ast_device *ast = to_ast_device(crtc->dev); 864 u8 vgacr17 = 0xff; 865 866 vgacr17 &= ~AST_IO_VGACR17_SYNC_ENABLE; 867 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x17, 0x7f, vgacr17); 868 869 /* 870 * HW cursors require the underlying primary plane and CRTC to 871 * display a valid mode and image. This is not the case during 872 * full modeset operations. So we temporarily disable any active 873 * plane, including the HW cursor. Each plane's atomic_update() 874 * helper will re-enable it if necessary. 875 * 876 * We only do this during *full* modesets. It does not affect 877 * simple pageflips on the planes. 878 */ 879 drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false); 880 } 881 882 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = { 883 .mode_valid = ast_crtc_helper_mode_valid, 884 .mode_set_nofb = ast_crtc_helper_mode_set_nofb, 885 .atomic_check = ast_crtc_helper_atomic_check, 886 .atomic_flush = ast_crtc_helper_atomic_flush, 887 .atomic_enable = ast_crtc_helper_atomic_enable, 888 .atomic_disable = ast_crtc_helper_atomic_disable, 889 }; 890 891 static void ast_crtc_reset(struct drm_crtc *crtc) 892 { 893 struct ast_crtc_state *ast_state = kzalloc_obj(*ast_state); 894 895 if (crtc->state) 896 crtc->funcs->atomic_destroy_state(crtc, crtc->state); 897 898 if (ast_state) 899 __drm_atomic_helper_crtc_reset(crtc, &ast_state->base); 900 else 901 __drm_atomic_helper_crtc_reset(crtc, NULL); 902 } 903 904 static struct drm_crtc_state * 905 ast_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 906 { 907 struct ast_crtc_state *new_ast_state, *ast_state; 908 struct drm_device *dev = crtc->dev; 909 910 if (drm_WARN_ON(dev, !crtc->state)) 911 return NULL; 912 913 new_ast_state = kmalloc_obj(*new_ast_state); 914 if (!new_ast_state) 915 return NULL; 916 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_ast_state->base); 917 918 ast_state = to_ast_crtc_state(crtc->state); 919 920 new_ast_state->format = ast_state->format; 921 new_ast_state->std_table = ast_state->std_table; 922 new_ast_state->vmode = ast_state->vmode; 923 924 return &new_ast_state->base; 925 } 926 927 static void ast_crtc_atomic_destroy_state(struct drm_crtc *crtc, 928 struct drm_crtc_state *state) 929 { 930 struct ast_crtc_state *ast_state = to_ast_crtc_state(state); 931 932 __drm_atomic_helper_crtc_destroy_state(&ast_state->base); 933 kfree(ast_state); 934 } 935 936 static const struct drm_crtc_funcs ast_crtc_funcs = { 937 .reset = ast_crtc_reset, 938 .destroy = drm_crtc_cleanup, 939 .set_config = drm_atomic_helper_set_config, 940 .page_flip = drm_atomic_helper_page_flip, 941 .atomic_duplicate_state = ast_crtc_atomic_duplicate_state, 942 .atomic_destroy_state = ast_crtc_atomic_destroy_state, 943 }; 944 945 static int ast_crtc_init(struct ast_device *ast) 946 { 947 struct drm_device *dev = &ast->base; 948 struct drm_crtc *crtc = &ast->crtc; 949 int ret; 950 951 ret = drm_crtc_init_with_planes(dev, crtc, &ast->primary_plane.base, 952 &ast->cursor_plane.base.base, &ast_crtc_funcs, 953 NULL); 954 if (ret) 955 return ret; 956 957 drm_mode_crtc_set_gamma_size(crtc, AST_LUT_SIZE); 958 drm_crtc_enable_color_mgmt(crtc, 0, false, AST_LUT_SIZE); 959 960 drm_crtc_helper_add(crtc, &ast_crtc_helper_funcs); 961 962 return 0; 963 } 964 965 /* 966 * Mode config 967 */ 968 969 static void ast_mode_config_helper_atomic_commit_tail(struct drm_atomic_commit *state) 970 { 971 struct ast_device *ast = to_ast_device(state->dev); 972 973 /* 974 * Concurrent operations could possibly trigger a call to 975 * drm_connector_helper_funcs.get_modes by reading the display 976 * modes. Protect access to registers by acquiring the modeset 977 * lock. 978 */ 979 mutex_lock(&ast->modeset_lock); 980 drm_atomic_helper_commit_tail(state); 981 mutex_unlock(&ast->modeset_lock); 982 } 983 984 static const struct drm_mode_config_helper_funcs ast_mode_config_helper_funcs = { 985 .atomic_commit_tail = ast_mode_config_helper_atomic_commit_tail, 986 }; 987 988 static enum drm_mode_status ast_mode_config_mode_valid(struct drm_device *dev, 989 const struct drm_display_mode *mode) 990 { 991 const struct drm_format_info *info = drm_format_info(DRM_FORMAT_XRGB8888); 992 struct ast_device *ast = to_ast_device(dev); 993 unsigned long max_fb_size = ast_fb_vram_size(ast); 994 u64 pitch; 995 996 if (drm_WARN_ON_ONCE(dev, !info)) 997 return MODE_ERROR; /* driver bug */ 998 999 pitch = drm_format_info_min_pitch(info, 0, mode->hdisplay); 1000 if (!pitch) 1001 return MODE_BAD_WIDTH; 1002 if (pitch > AST_PRIMARY_PLANE_MAX_OFFSET) 1003 return MODE_BAD_WIDTH; /* maximum programmable pitch */ 1004 if (pitch > max_fb_size / mode->vdisplay) 1005 return MODE_MEM; 1006 1007 return MODE_OK; 1008 } 1009 1010 static const struct drm_mode_config_funcs ast_mode_config_funcs = { 1011 .fb_create = drm_gem_fb_create_with_dirty, 1012 .mode_valid = ast_mode_config_mode_valid, 1013 .atomic_check = drm_atomic_helper_check, 1014 .atomic_commit = drm_atomic_helper_commit, 1015 }; 1016 1017 int ast_mode_config_init(struct ast_device *ast) 1018 { 1019 struct drm_device *dev = &ast->base; 1020 int ret; 1021 1022 ret = drmm_mutex_init(dev, &ast->modeset_lock); 1023 if (ret) 1024 return ret; 1025 1026 ret = drmm_mode_config_init(dev); 1027 if (ret) 1028 return ret; 1029 1030 dev->mode_config.funcs = &ast_mode_config_funcs; 1031 dev->mode_config.min_width = 0; 1032 dev->mode_config.min_height = 0; 1033 dev->mode_config.preferred_depth = 24; 1034 1035 if (ast->support_fullhd) { 1036 dev->mode_config.max_width = 1920; 1037 dev->mode_config.max_height = 2048; 1038 } else { 1039 dev->mode_config.max_width = 1600; 1040 dev->mode_config.max_height = 1200; 1041 } 1042 1043 dev->mode_config.helper_private = &ast_mode_config_helper_funcs; 1044 1045 ret = ast_primary_plane_init(ast); 1046 if (ret) 1047 return ret; 1048 1049 ret = ast_cursor_plane_init(ast); 1050 if (ret) 1051 return ret; 1052 1053 ret = ast_crtc_init(ast); 1054 if (ret) 1055 return ret; 1056 1057 switch (ast->tx_chip) { 1058 case AST_TX_NONE: 1059 ret = ast_vga_output_init(ast); 1060 break; 1061 case AST_TX_SIL164: 1062 ret = ast_sil164_output_init(ast); 1063 break; 1064 case AST_TX_DP501: 1065 ret = ast_dp501_output_init(ast); 1066 break; 1067 case AST_TX_ASTDP: 1068 ret = ast_astdp_output_init(ast); 1069 break; 1070 } 1071 if (ret) 1072 return ret; 1073 1074 drm_mode_config_reset(dev); 1075 drmm_kms_helper_poll_init(dev); 1076 1077 return 0; 1078 } 1079