xref: /linux/drivers/gpu/drm/ast/ast_main.c (revision a36e9f5cfe9eb3a1dce8769c7058251c42705357)
1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the
6  * "Software"), to deal in the Software without restriction, including
7  * without limitation the rights to use, copy, modify, merge, publish,
8  * distribute, sub license, and/or sell copies of the Software, and to
9  * permit persons to whom the Software is furnished to do so, subject to
10  * the following conditions:
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18  * USE OR OTHER DEALINGS IN THE SOFTWARE.
19  *
20  * The above copyright notice and this permission notice (including the
21  * next paragraph) shall be included in all copies or substantial portions
22  * of the Software.
23  *
24  */
25 /*
26  * Authors: Dave Airlie <airlied@redhat.com>
27  */
28 
29 #include <linux/of.h>
30 #include <linux/pci.h>
31 
32 #include <drm/drm_atomic_helper.h>
33 #include <drm/drm_drv.h>
34 #include <drm/drm_gem.h>
35 #include <drm/drm_managed.h>
36 
37 #include "ast_drv.h"
38 
39 static void ast_detect_widescreen(struct ast_device *ast)
40 {
41 	u8 jreg;
42 
43 	/* Check if we support wide screen */
44 	switch (AST_GEN(ast)) {
45 	case 1:
46 		ast->support_wide_screen = false;
47 		break;
48 	default:
49 		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
50 		if (!(jreg & 0x80))
51 			ast->support_wide_screen = true;
52 		else if (jreg & 0x01)
53 			ast->support_wide_screen = true;
54 		else {
55 			ast->support_wide_screen = false;
56 			if (ast->chip == AST1300)
57 				ast->support_wide_screen = true;
58 			if (ast->chip == AST1400)
59 				ast->support_wide_screen = true;
60 			if (ast->chip == AST2510)
61 				ast->support_wide_screen = true;
62 			if (IS_AST_GEN7(ast))
63 				ast->support_wide_screen = true;
64 		}
65 		break;
66 	}
67 }
68 
69 static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
70 {
71 	struct drm_device *dev = &ast->base;
72 	u8 jreg;
73 
74 	/* Check 3rd Tx option (digital output afaik) */
75 	ast->tx_chip_types |= AST_TX_NONE_BIT;
76 
77 	/*
78 	 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
79 	 * enabled, in that case, assume we have a SIL164 TMDS transmitter
80 	 *
81 	 * Don't make that assumption if we the chip wasn't enabled and
82 	 * is at power-on reset, otherwise we'll incorrectly "detect" a
83 	 * SIL164 when there is none.
84 	 */
85 	if (!need_post) {
86 		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
87 		if (jreg & 0x80)
88 			ast->tx_chip_types = AST_TX_SIL164_BIT;
89 	}
90 
91 	if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) {
92 		/*
93 		 * On AST GEN4+, look the configuration set by the SoC in
94 		 * the SOC scratch register #1 bits 11:8 (interestingly marked
95 		 * as "reserved" in the spec)
96 		 */
97 		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 0xff);
98 		switch (jreg) {
99 		case 0x04:
100 			ast->tx_chip_types = AST_TX_SIL164_BIT;
101 			break;
102 		case 0x08:
103 			ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL);
104 			if (ast->dp501_fw_addr) {
105 				/* backup firmware */
106 				if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
107 					drmm_kfree(dev, ast->dp501_fw_addr);
108 					ast->dp501_fw_addr = NULL;
109 				}
110 			}
111 			fallthrough;
112 		case 0x0c:
113 			ast->tx_chip_types = AST_TX_DP501_BIT;
114 		}
115 	} else if (IS_AST_GEN7(ast)) {
116 		if (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD1, TX_TYPE_MASK) ==
117 		    ASTDP_DPMCU_TX) {
118 			ast->tx_chip_types = AST_TX_ASTDP_BIT;
119 			ast_dp_launch(&ast->base);
120 		}
121 	}
122 
123 	/* Print stuff for diagnostic purposes */
124 	if (ast->tx_chip_types & AST_TX_NONE_BIT)
125 		drm_info(dev, "Using analog VGA\n");
126 	if (ast->tx_chip_types & AST_TX_SIL164_BIT)
127 		drm_info(dev, "Using Sil164 TMDS transmitter\n");
128 	if (ast->tx_chip_types & AST_TX_DP501_BIT)
129 		drm_info(dev, "Using DP501 DisplayPort transmitter\n");
130 	if (ast->tx_chip_types & AST_TX_ASTDP_BIT)
131 		drm_info(dev, "Using ASPEED DisplayPort transmitter\n");
132 }
133 
134 static int ast_get_dram_info(struct drm_device *dev)
135 {
136 	struct device_node *np = dev->dev->of_node;
137 	struct ast_device *ast = to_ast_device(dev);
138 	uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
139 	uint32_t denum, num, div, ref_pll, dsel;
140 
141 	switch (ast->config_mode) {
142 	case ast_use_dt:
143 		/*
144 		 * If some properties are missing, use reasonable
145 		 * defaults for GEN5
146 		 */
147 		if (of_property_read_u32(np, "aspeed,mcr-configuration",
148 					 &mcr_cfg))
149 			mcr_cfg = 0x00000577;
150 		if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
151 					 &mcr_scu_mpll))
152 			mcr_scu_mpll = 0x000050C0;
153 		if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
154 					 &mcr_scu_strap))
155 			mcr_scu_strap = 0;
156 		break;
157 	case ast_use_p2a:
158 		ast_write32(ast, 0xf004, 0x1e6e0000);
159 		ast_write32(ast, 0xf000, 0x1);
160 		mcr_cfg = ast_read32(ast, 0x10004);
161 		mcr_scu_mpll = ast_read32(ast, 0x10120);
162 		mcr_scu_strap = ast_read32(ast, 0x10170);
163 		break;
164 	case ast_use_defaults:
165 	default:
166 		ast->dram_bus_width = 16;
167 		ast->dram_type = AST_DRAM_1Gx16;
168 		if (IS_AST_GEN6(ast))
169 			ast->mclk = 800;
170 		else
171 			ast->mclk = 396;
172 		return 0;
173 	}
174 
175 	if (mcr_cfg & 0x40)
176 		ast->dram_bus_width = 16;
177 	else
178 		ast->dram_bus_width = 32;
179 
180 	if (IS_AST_GEN6(ast)) {
181 		switch (mcr_cfg & 0x03) {
182 		case 0:
183 			ast->dram_type = AST_DRAM_1Gx16;
184 			break;
185 		default:
186 		case 1:
187 			ast->dram_type = AST_DRAM_2Gx16;
188 			break;
189 		case 2:
190 			ast->dram_type = AST_DRAM_4Gx16;
191 			break;
192 		case 3:
193 			ast->dram_type = AST_DRAM_8Gx16;
194 			break;
195 		}
196 	} else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast)) {
197 		switch (mcr_cfg & 0x03) {
198 		case 0:
199 			ast->dram_type = AST_DRAM_512Mx16;
200 			break;
201 		default:
202 		case 1:
203 			ast->dram_type = AST_DRAM_1Gx16;
204 			break;
205 		case 2:
206 			ast->dram_type = AST_DRAM_2Gx16;
207 			break;
208 		case 3:
209 			ast->dram_type = AST_DRAM_4Gx16;
210 			break;
211 		}
212 	} else {
213 		switch (mcr_cfg & 0x0c) {
214 		case 0:
215 		case 4:
216 			ast->dram_type = AST_DRAM_512Mx16;
217 			break;
218 		case 8:
219 			if (mcr_cfg & 0x40)
220 				ast->dram_type = AST_DRAM_1Gx16;
221 			else
222 				ast->dram_type = AST_DRAM_512Mx32;
223 			break;
224 		case 0xc:
225 			ast->dram_type = AST_DRAM_1Gx32;
226 			break;
227 		}
228 	}
229 
230 	if (mcr_scu_strap & 0x2000)
231 		ref_pll = 14318;
232 	else
233 		ref_pll = 12000;
234 
235 	denum = mcr_scu_mpll & 0x1f;
236 	num = (mcr_scu_mpll & 0x3fe0) >> 5;
237 	dsel = (mcr_scu_mpll & 0xc000) >> 14;
238 	switch (dsel) {
239 	case 3:
240 		div = 0x4;
241 		break;
242 	case 2:
243 	case 1:
244 		div = 0x2;
245 		break;
246 	default:
247 		div = 0x1;
248 		break;
249 	}
250 	ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
251 	return 0;
252 }
253 
254 struct drm_device *ast_device_create(struct pci_dev *pdev,
255 				     const struct drm_driver *drv,
256 				     enum ast_chip chip,
257 				     enum ast_config_mode config_mode,
258 				     void __iomem *regs,
259 				     void __iomem *ioregs,
260 				     bool need_post)
261 {
262 	struct drm_device *dev;
263 	struct ast_device *ast;
264 	int ret;
265 
266 	ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_device, base);
267 	if (IS_ERR(ast))
268 		return ERR_CAST(ast);
269 	dev = &ast->base;
270 
271 	ast->chip = chip;
272 	ast->config_mode = config_mode;
273 	ast->regs = regs;
274 	ast->ioregs = ioregs;
275 
276 	ast_detect_widescreen(ast);
277 	ast_detect_tx_chip(ast, need_post);
278 
279 	ret = ast_get_dram_info(dev);
280 	if (ret)
281 		return ERR_PTR(ret);
282 
283 	drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n",
284 		 ast->mclk, ast->dram_type, ast->dram_bus_width);
285 
286 	if (need_post)
287 		ast_post_gpu(dev);
288 
289 	ret = ast_mm_init(ast);
290 	if (ret)
291 		return ERR_PTR(ret);
292 
293 	/* map reserved buffer */
294 	ast->dp501_fw_buf = NULL;
295 	if (ast->vram_size < pci_resource_len(pdev, 0)) {
296 		ast->dp501_fw_buf = pci_iomap_range(pdev, 0, ast->vram_size, 0);
297 		if (!ast->dp501_fw_buf)
298 			drm_info(dev, "failed to map reserved buffer!\n");
299 	}
300 
301 	ret = ast_mode_config_init(ast);
302 	if (ret)
303 		return ERR_PTR(ret);
304 
305 	return dev;
306 }
307