xref: /linux/drivers/gpu/drm/ast/ast_drv.h (revision f5bd9d528ebac41a31919aa41f1a99eccb8917c8)
1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the
6  * "Software"), to deal in the Software without restriction, including
7  * without limitation the rights to use, copy, modify, merge, publish,
8  * distribute, sub license, and/or sell copies of the Software, and to
9  * permit persons to whom the Software is furnished to do so, subject to
10  * the following conditions:
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18  * USE OR OTHER DEALINGS IN THE SOFTWARE.
19  *
20  * The above copyright notice and this permission notice (including the
21  * next paragraph) shall be included in all copies or substantial portions
22  * of the Software.
23  *
24  */
25 /*
26  * Authors: Dave Airlie <airlied@redhat.com>
27  */
28 #ifndef __AST_DRV_H__
29 #define __AST_DRV_H__
30 
31 #include <linux/io.h>
32 #include <linux/types.h>
33 
34 #include <drm/drm_connector.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_mode.h>
38 #include <drm/drm_framebuffer.h>
39 
40 #include "ast_reg.h"
41 
42 struct ast_vbios_enhtable;
43 
44 #define DRIVER_AUTHOR		"Dave Airlie"
45 
46 #define DRIVER_NAME		"ast"
47 #define DRIVER_DESC		"AST"
48 
49 #define DRIVER_MAJOR		0
50 #define DRIVER_MINOR		1
51 #define DRIVER_PATCHLEVEL	0
52 
53 #define PCI_CHIP_AST2000 0x2000
54 #define PCI_CHIP_AST2100 0x2010
55 
56 #define __AST_CHIP(__gen, __index)	((__gen) << 16 | (__index))
57 
58 enum ast_chip {
59 	/* 1st gen */
60 	AST1000 = __AST_CHIP(1, 0), // unused
61 	AST2000 = __AST_CHIP(1, 1),
62 	/* 2nd gen */
63 	AST1100 = __AST_CHIP(2, 0),
64 	AST2100 = __AST_CHIP(2, 1),
65 	AST2050 = __AST_CHIP(2, 2), // unused
66 	/* 3rd gen */
67 	AST2200 = __AST_CHIP(3, 0),
68 	AST2150 = __AST_CHIP(3, 1),
69 	/* 4th gen */
70 	AST2300 = __AST_CHIP(4, 0),
71 	AST1300 = __AST_CHIP(4, 1),
72 	AST1050 = __AST_CHIP(4, 2), // unused
73 	/* 5th gen */
74 	AST2400 = __AST_CHIP(5, 0),
75 	AST1400 = __AST_CHIP(5, 1),
76 	AST1250 = __AST_CHIP(5, 2), // unused
77 	/* 6th gen */
78 	AST2500 = __AST_CHIP(6, 0),
79 	AST2510 = __AST_CHIP(6, 1),
80 	AST2520 = __AST_CHIP(6, 2), // unused
81 	/* 7th gen */
82 	AST2600 = __AST_CHIP(7, 0),
83 	AST2620 = __AST_CHIP(7, 1), // unused
84 };
85 
86 #define __AST_CHIP_GEN(__chip)	(((unsigned long)(__chip)) >> 16)
87 
88 enum ast_tx_chip {
89 	AST_TX_NONE,
90 	AST_TX_SIL164,
91 	AST_TX_DP501,
92 	AST_TX_ASTDP,
93 };
94 
95 enum ast_config_mode {
96 	ast_use_p2a,
97 	ast_use_dt,
98 	ast_use_defaults
99 };
100 
101 #define AST_DRAM_512Mx16 0
102 #define AST_DRAM_1Gx16   1
103 #define AST_DRAM_512Mx32 2
104 #define AST_DRAM_1Gx32   3
105 #define AST_DRAM_2Gx16   6
106 #define AST_DRAM_4Gx16   7
107 #define AST_DRAM_8Gx16   8
108 
109 /*
110  * Hardware cursor
111  */
112 
113 #define AST_MAX_HWC_WIDTH	64
114 #define AST_MAX_HWC_HEIGHT	64
115 #define AST_HWC_PITCH		(AST_MAX_HWC_WIDTH * SZ_2)
116 #define AST_HWC_SIZE		(AST_MAX_HWC_HEIGHT * AST_HWC_PITCH)
117 
118 /*
119  * Planes
120  */
121 
122 struct ast_plane {
123 	struct drm_plane base;
124 
125 	void __iomem *vaddr;
126 	u64 offset;
127 	unsigned long size;
128 };
129 
130 static inline struct ast_plane *to_ast_plane(struct drm_plane *plane)
131 {
132 	return container_of(plane, struct ast_plane, base);
133 }
134 
135 struct ast_cursor_plane {
136 	struct ast_plane base;
137 
138 	u8 argb4444[AST_HWC_SIZE];
139 };
140 
141 static inline struct ast_cursor_plane *to_ast_cursor_plane(struct drm_plane *plane)
142 {
143 	return container_of(to_ast_plane(plane), struct ast_cursor_plane, base);
144 }
145 
146 /*
147  * Connector
148  */
149 
150 struct ast_connector {
151 	struct drm_connector base;
152 
153 	enum drm_connector_status physical_status;
154 };
155 
156 static inline struct ast_connector *
157 to_ast_connector(struct drm_connector *connector)
158 {
159 	return container_of(connector, struct ast_connector, base);
160 }
161 
162 /*
163  * Device
164  */
165 
166 struct ast_device {
167 	struct drm_device base;
168 
169 	void __iomem *regs;
170 	void __iomem *ioregs;
171 	void __iomem *dp501_fw_buf;
172 
173 	enum ast_config_mode config_mode;
174 	enum ast_chip chip;
175 
176 	uint32_t dram_bus_width;
177 	uint32_t dram_type;
178 	uint32_t mclk;
179 
180 	void __iomem	*vram;
181 	unsigned long	vram_base;
182 	unsigned long	vram_size;
183 
184 	struct mutex modeset_lock; /* Protects access to modeset I/O registers in ioregs */
185 
186 	enum ast_tx_chip tx_chip;
187 
188 	struct ast_plane primary_plane;
189 	struct ast_cursor_plane cursor_plane;
190 	struct drm_crtc crtc;
191 	union {
192 		struct {
193 			struct drm_encoder encoder;
194 			struct ast_connector connector;
195 		} vga;
196 		struct {
197 			struct drm_encoder encoder;
198 			struct ast_connector connector;
199 		} sil164;
200 		struct {
201 			struct drm_encoder encoder;
202 			struct ast_connector connector;
203 		} dp501;
204 		struct {
205 			struct drm_encoder encoder;
206 			struct ast_connector connector;
207 		} astdp;
208 	} output;
209 
210 	bool support_wsxga_p; /* 1680x1050 */
211 	bool support_fullhd; /* 1920x1080 */
212 	bool support_wuxga; /* 1920x1200 */
213 
214 	u8 *dp501_fw_addr;
215 	const struct firmware *dp501_fw;	/* dp501 fw */
216 };
217 
218 static inline struct ast_device *to_ast_device(struct drm_device *dev)
219 {
220 	return container_of(dev, struct ast_device, base);
221 }
222 
223 struct drm_device *ast_device_create(struct pci_dev *pdev,
224 				     const struct drm_driver *drv,
225 				     enum ast_chip chip,
226 				     enum ast_config_mode config_mode,
227 				     void __iomem *regs,
228 				     void __iomem *ioregs,
229 				     bool need_post);
230 
231 static inline unsigned long __ast_gen(struct ast_device *ast)
232 {
233 	return __AST_CHIP_GEN(ast->chip);
234 }
235 #define AST_GEN(__ast)	__ast_gen(__ast)
236 
237 static inline bool __ast_gen_is_eq(struct ast_device *ast, unsigned long gen)
238 {
239 	return __ast_gen(ast) == gen;
240 }
241 #define IS_AST_GEN1(__ast)	__ast_gen_is_eq(__ast, 1)
242 #define IS_AST_GEN2(__ast)	__ast_gen_is_eq(__ast, 2)
243 #define IS_AST_GEN3(__ast)	__ast_gen_is_eq(__ast, 3)
244 #define IS_AST_GEN4(__ast)	__ast_gen_is_eq(__ast, 4)
245 #define IS_AST_GEN5(__ast)	__ast_gen_is_eq(__ast, 5)
246 #define IS_AST_GEN6(__ast)	__ast_gen_is_eq(__ast, 6)
247 #define IS_AST_GEN7(__ast)	__ast_gen_is_eq(__ast, 7)
248 
249 static inline u8 __ast_read8(const void __iomem *addr, u32 reg)
250 {
251 	return ioread8(addr + reg);
252 }
253 
254 static inline u32 __ast_read32(const void __iomem *addr, u32 reg)
255 {
256 	return ioread32(addr + reg);
257 }
258 
259 static inline void __ast_write8(void __iomem *addr, u32 reg, u8 val)
260 {
261 	iowrite8(val, addr + reg);
262 }
263 
264 static inline void __ast_write32(void __iomem *addr, u32 reg, u32 val)
265 {
266 	iowrite32(val, addr + reg);
267 }
268 
269 static inline u8 __ast_read8_i(void __iomem *addr, u32 reg, u8 index)
270 {
271 	__ast_write8(addr, reg, index);
272 	return __ast_read8(addr, reg + 1);
273 }
274 
275 static inline u8 __ast_read8_i_masked(void __iomem *addr, u32 reg, u8 index, u8 read_mask)
276 {
277 	u8 val = __ast_read8_i(addr, reg, index);
278 
279 	return val & read_mask;
280 }
281 
282 static inline void __ast_write8_i(void __iomem *addr, u32 reg, u8 index, u8 val)
283 {
284 	__ast_write8(addr, reg, index);
285 	__ast_write8(addr, reg + 1, val);
286 }
287 
288 static inline void __ast_write8_i_masked(void __iomem *addr, u32 reg, u8 index, u8 read_mask,
289 					 u8 val)
290 {
291 	u8 tmp = __ast_read8_i_masked(addr, reg, index, read_mask);
292 
293 	tmp |= val;
294 	__ast_write8_i(addr, reg, index, tmp);
295 }
296 
297 static inline u32 ast_read32(struct ast_device *ast, u32 reg)
298 {
299 	return __ast_read32(ast->regs, reg);
300 }
301 
302 static inline void ast_write32(struct ast_device *ast, u32 reg, u32 val)
303 {
304 	__ast_write32(ast->regs, reg, val);
305 }
306 
307 static inline u8 ast_io_read8(struct ast_device *ast, u32 reg)
308 {
309 	return __ast_read8(ast->ioregs, reg);
310 }
311 
312 static inline void ast_io_write8(struct ast_device *ast, u32 reg, u8 val)
313 {
314 	__ast_write8(ast->ioregs, reg, val);
315 }
316 
317 static inline u8 ast_get_index_reg(struct ast_device *ast, u32 base, u8 index)
318 {
319 	return __ast_read8_i(ast->ioregs, base, index);
320 }
321 
322 static inline u8 ast_get_index_reg_mask(struct ast_device *ast, u32 base, u8 index,
323 					u8 preserve_mask)
324 {
325 	return __ast_read8_i_masked(ast->ioregs, base, index, preserve_mask);
326 }
327 
328 static inline void ast_set_index_reg(struct ast_device *ast, u32 base, u8 index, u8 val)
329 {
330 	__ast_write8_i(ast->ioregs, base, index, val);
331 }
332 
333 static inline void ast_set_index_reg_mask(struct ast_device *ast, u32 base, u8 index,
334 					  u8 preserve_mask, u8 val)
335 {
336 	__ast_write8_i_masked(ast->ioregs, base, index, preserve_mask, val);
337 }
338 
339 struct ast_vbios_stdtable {
340 	u8 misc;
341 	u8 seq[4];
342 	u8 crtc[25];
343 	u8 ar[20];
344 	u8 gr[9];
345 };
346 
347 struct ast_vbios_dclk_info {
348 	u8 param1;
349 	u8 param2;
350 	u8 param3;
351 };
352 
353 struct ast_crtc_state {
354 	struct drm_crtc_state base;
355 
356 	/* Last known format of primary plane */
357 	const struct drm_format_info *format;
358 
359 	const struct ast_vbios_stdtable *std_table;
360 	const struct ast_vbios_enhtable *vmode;
361 };
362 
363 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)
364 
365 #define AST_MM_ALIGN_SHIFT 4
366 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
367 
368 #define AST_DP501_FW_VERSION_MASK	GENMASK(7, 4)
369 #define AST_DP501_FW_VERSION_1		BIT(4)
370 #define AST_DP501_PNP_CONNECTED		BIT(1)
371 
372 #define AST_DP501_DEFAULT_DCLK	65
373 
374 #define AST_DP501_GBL_VERSION	0xf000
375 #define AST_DP501_PNPMONITOR	0xf010
376 #define AST_DP501_LINKRATE	0xf014
377 #define AST_DP501_EDID_DATA	0xf020
378 
379 /*
380  * ASTDP resoultion table:
381  * EX:	ASTDP_A_B_C:
382  *		A: Resolution
383  *		B: Refresh Rate
384  *		C: Misc information, such as CVT, Reduce Blanked
385  */
386 #define ASTDP_640x480_60		0x00
387 #define ASTDP_640x480_72		0x01
388 #define ASTDP_640x480_75		0x02
389 #define ASTDP_640x480_85		0x03
390 #define ASTDP_800x600_56		0x04
391 #define ASTDP_800x600_60		0x05
392 #define ASTDP_800x600_72		0x06
393 #define ASTDP_800x600_75		0x07
394 #define ASTDP_800x600_85		0x08
395 #define ASTDP_1024x768_60		0x09
396 #define ASTDP_1024x768_70		0x0A
397 #define ASTDP_1024x768_75		0x0B
398 #define ASTDP_1024x768_85		0x0C
399 #define ASTDP_1280x1024_60		0x0D
400 #define ASTDP_1280x1024_75		0x0E
401 #define ASTDP_1280x1024_85		0x0F
402 #define ASTDP_1600x1200_60		0x10
403 #define ASTDP_320x240_60		0x11
404 #define ASTDP_400x300_60		0x12
405 #define ASTDP_512x384_60		0x13
406 #define ASTDP_1920x1200_60		0x14
407 #define ASTDP_1920x1080_60		0x15
408 #define ASTDP_1280x800_60		0x16
409 #define ASTDP_1280x800_60_RB	0x17
410 #define ASTDP_1440x900_60		0x18
411 #define ASTDP_1440x900_60_RB	0x19
412 #define ASTDP_1680x1050_60		0x1A
413 #define ASTDP_1680x1050_60_RB	0x1B
414 #define ASTDP_1600x900_60		0x1C
415 #define ASTDP_1600x900_60_RB	0x1D
416 #define ASTDP_1366x768_60		0x1E
417 #define ASTDP_1152x864_75		0x1F
418 
419 int ast_mm_init(struct ast_device *ast);
420 
421 /* ast post */
422 int ast_post_gpu(struct ast_device *ast);
423 u32 ast_mindwm(struct ast_device *ast, u32 r);
424 void ast_moutdwm(struct ast_device *ast, u32 r, u32 v);
425 void ast_patch_ahb_2500(void __iomem *regs);
426 
427 int ast_vga_output_init(struct ast_device *ast);
428 int ast_sil164_output_init(struct ast_device *ast);
429 
430 /* ast_cursor.c */
431 long ast_cursor_vram_offset(struct ast_device *ast);
432 int ast_cursor_plane_init(struct ast_device *ast);
433 
434 /* ast dp501 */
435 bool ast_backup_fw(struct ast_device *ast, u8 *addr, u32 size);
436 void ast_init_3rdtx(struct ast_device *ast);
437 int ast_dp501_output_init(struct ast_device *ast);
438 
439 /* aspeed DP */
440 int ast_dp_launch(struct ast_device *ast);
441 int ast_astdp_output_init(struct ast_device *ast);
442 
443 /* ast_mode.c */
444 int ast_mode_config_init(struct ast_device *ast);
445 int ast_plane_init(struct drm_device *dev, struct ast_plane *ast_plane,
446 		   void __iomem *vaddr, u64 offset, unsigned long size,
447 		   uint32_t possible_crtcs,
448 		   const struct drm_plane_funcs *funcs,
449 		   const uint32_t *formats, unsigned int format_count,
450 		   const uint64_t *format_modifiers,
451 		   enum drm_plane_type type);
452 
453 #endif
454