1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 #ifndef __AST_DRV_H__ 29 #define __AST_DRV_H__ 30 31 #include <linux/io.h> 32 #include <linux/types.h> 33 34 #include <drm/drm_connector.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_encoder.h> 37 #include <drm/drm_mode.h> 38 #include <drm/drm_framebuffer.h> 39 40 #include "ast_reg.h" 41 42 #define DRIVER_AUTHOR "Dave Airlie" 43 44 #define DRIVER_NAME "ast" 45 #define DRIVER_DESC "AST" 46 47 #define DRIVER_MAJOR 0 48 #define DRIVER_MINOR 1 49 #define DRIVER_PATCHLEVEL 0 50 51 #define PCI_CHIP_AST2000 0x2000 52 #define PCI_CHIP_AST2100 0x2010 53 54 #define __AST_CHIP(__gen, __index) ((__gen) << 16 | (__index)) 55 56 enum ast_chip { 57 /* 1st gen */ 58 AST1000 = __AST_CHIP(1, 0), // unused 59 AST2000 = __AST_CHIP(1, 1), 60 /* 2nd gen */ 61 AST1100 = __AST_CHIP(2, 0), 62 AST2100 = __AST_CHIP(2, 1), 63 AST2050 = __AST_CHIP(2, 2), // unused 64 /* 3rd gen */ 65 AST2200 = __AST_CHIP(3, 0), 66 AST2150 = __AST_CHIP(3, 1), 67 /* 4th gen */ 68 AST2300 = __AST_CHIP(4, 0), 69 AST1300 = __AST_CHIP(4, 1), 70 AST1050 = __AST_CHIP(4, 2), // unused 71 /* 5th gen */ 72 AST2400 = __AST_CHIP(5, 0), 73 AST1400 = __AST_CHIP(5, 1), 74 AST1250 = __AST_CHIP(5, 2), // unused 75 /* 6th gen */ 76 AST2500 = __AST_CHIP(6, 0), 77 AST2510 = __AST_CHIP(6, 1), 78 AST2520 = __AST_CHIP(6, 2), // unused 79 /* 7th gen */ 80 AST2600 = __AST_CHIP(7, 0), 81 AST2620 = __AST_CHIP(7, 1), // unused 82 }; 83 84 #define __AST_CHIP_GEN(__chip) (((unsigned long)(__chip)) >> 16) 85 86 enum ast_tx_chip { 87 AST_TX_NONE, 88 AST_TX_SIL164, 89 AST_TX_DP501, 90 AST_TX_ASTDP, 91 }; 92 93 enum ast_config_mode { 94 ast_use_p2a, 95 ast_use_dt, 96 ast_use_defaults 97 }; 98 99 #define AST_DRAM_512Mx16 0 100 #define AST_DRAM_1Gx16 1 101 #define AST_DRAM_512Mx32 2 102 #define AST_DRAM_1Gx32 3 103 #define AST_DRAM_2Gx16 6 104 #define AST_DRAM_4Gx16 7 105 #define AST_DRAM_8Gx16 8 106 107 /* 108 * Hardware cursor 109 */ 110 111 #define AST_MAX_HWC_WIDTH 64 112 #define AST_MAX_HWC_HEIGHT 64 113 114 #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2) 115 #define AST_HWC_SIGNATURE_SIZE 32 116 117 /* define for signature structure */ 118 #define AST_HWC_SIGNATURE_CHECKSUM 0x00 119 #define AST_HWC_SIGNATURE_SizeX 0x04 120 #define AST_HWC_SIGNATURE_SizeY 0x08 121 #define AST_HWC_SIGNATURE_X 0x0C 122 #define AST_HWC_SIGNATURE_Y 0x10 123 #define AST_HWC_SIGNATURE_HOTSPOTX 0x14 124 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18 125 126 /* 127 * Planes 128 */ 129 130 struct ast_plane { 131 struct drm_plane base; 132 133 void __iomem *vaddr; 134 u64 offset; 135 unsigned long size; 136 }; 137 138 static inline struct ast_plane *to_ast_plane(struct drm_plane *plane) 139 { 140 return container_of(plane, struct ast_plane, base); 141 } 142 143 /* 144 * Connector 145 */ 146 147 struct ast_connector { 148 struct drm_connector base; 149 150 enum drm_connector_status physical_status; 151 }; 152 153 static inline struct ast_connector * 154 to_ast_connector(struct drm_connector *connector) 155 { 156 return container_of(connector, struct ast_connector, base); 157 } 158 159 /* 160 * Device 161 */ 162 163 struct ast_device { 164 struct drm_device base; 165 166 void __iomem *regs; 167 void __iomem *ioregs; 168 void __iomem *dp501_fw_buf; 169 170 enum ast_config_mode config_mode; 171 enum ast_chip chip; 172 173 uint32_t dram_bus_width; 174 uint32_t dram_type; 175 uint32_t mclk; 176 177 void __iomem *vram; 178 unsigned long vram_base; 179 unsigned long vram_size; 180 unsigned long vram_fb_available; 181 182 struct mutex modeset_lock; /* Protects access to modeset I/O registers in ioregs */ 183 184 enum ast_tx_chip tx_chip; 185 186 struct ast_plane primary_plane; 187 struct ast_plane cursor_plane; 188 struct drm_crtc crtc; 189 union { 190 struct { 191 struct drm_encoder encoder; 192 struct ast_connector connector; 193 } vga; 194 struct { 195 struct drm_encoder encoder; 196 struct ast_connector connector; 197 } sil164; 198 struct { 199 struct drm_encoder encoder; 200 struct ast_connector connector; 201 } dp501; 202 struct { 203 struct drm_encoder encoder; 204 struct ast_connector connector; 205 } astdp; 206 } output; 207 208 bool support_wide_screen; 209 210 u8 *dp501_fw_addr; 211 const struct firmware *dp501_fw; /* dp501 fw */ 212 }; 213 214 static inline struct ast_device *to_ast_device(struct drm_device *dev) 215 { 216 return container_of(dev, struct ast_device, base); 217 } 218 219 struct drm_device *ast_device_create(struct pci_dev *pdev, 220 const struct drm_driver *drv, 221 enum ast_chip chip, 222 enum ast_config_mode config_mode, 223 void __iomem *regs, 224 void __iomem *ioregs, 225 bool need_post); 226 227 static inline unsigned long __ast_gen(struct ast_device *ast) 228 { 229 return __AST_CHIP_GEN(ast->chip); 230 } 231 #define AST_GEN(__ast) __ast_gen(__ast) 232 233 static inline bool __ast_gen_is_eq(struct ast_device *ast, unsigned long gen) 234 { 235 return __ast_gen(ast) == gen; 236 } 237 #define IS_AST_GEN1(__ast) __ast_gen_is_eq(__ast, 1) 238 #define IS_AST_GEN2(__ast) __ast_gen_is_eq(__ast, 2) 239 #define IS_AST_GEN3(__ast) __ast_gen_is_eq(__ast, 3) 240 #define IS_AST_GEN4(__ast) __ast_gen_is_eq(__ast, 4) 241 #define IS_AST_GEN5(__ast) __ast_gen_is_eq(__ast, 5) 242 #define IS_AST_GEN6(__ast) __ast_gen_is_eq(__ast, 6) 243 #define IS_AST_GEN7(__ast) __ast_gen_is_eq(__ast, 7) 244 245 static inline u8 __ast_read8(const void __iomem *addr, u32 reg) 246 { 247 return ioread8(addr + reg); 248 } 249 250 static inline u32 __ast_read32(const void __iomem *addr, u32 reg) 251 { 252 return ioread32(addr + reg); 253 } 254 255 static inline void __ast_write8(void __iomem *addr, u32 reg, u8 val) 256 { 257 iowrite8(val, addr + reg); 258 } 259 260 static inline void __ast_write32(void __iomem *addr, u32 reg, u32 val) 261 { 262 iowrite32(val, addr + reg); 263 } 264 265 static inline u8 __ast_read8_i(void __iomem *addr, u32 reg, u8 index) 266 { 267 __ast_write8(addr, reg, index); 268 return __ast_read8(addr, reg + 1); 269 } 270 271 static inline u8 __ast_read8_i_masked(void __iomem *addr, u32 reg, u8 index, u8 read_mask) 272 { 273 u8 val = __ast_read8_i(addr, reg, index); 274 275 return val & read_mask; 276 } 277 278 static inline void __ast_write8_i(void __iomem *addr, u32 reg, u8 index, u8 val) 279 { 280 __ast_write8(addr, reg, index); 281 __ast_write8(addr, reg + 1, val); 282 } 283 284 static inline void __ast_write8_i_masked(void __iomem *addr, u32 reg, u8 index, u8 read_mask, 285 u8 val) 286 { 287 u8 tmp = __ast_read8_i_masked(addr, reg, index, read_mask); 288 289 tmp |= val; 290 __ast_write8_i(addr, reg, index, tmp); 291 } 292 293 static inline u32 ast_read32(struct ast_device *ast, u32 reg) 294 { 295 return __ast_read32(ast->regs, reg); 296 } 297 298 static inline void ast_write32(struct ast_device *ast, u32 reg, u32 val) 299 { 300 __ast_write32(ast->regs, reg, val); 301 } 302 303 static inline u8 ast_io_read8(struct ast_device *ast, u32 reg) 304 { 305 return __ast_read8(ast->ioregs, reg); 306 } 307 308 static inline void ast_io_write8(struct ast_device *ast, u32 reg, u8 val) 309 { 310 __ast_write8(ast->ioregs, reg, val); 311 } 312 313 static inline u8 ast_get_index_reg(struct ast_device *ast, u32 base, u8 index) 314 { 315 return __ast_read8_i(ast->ioregs, base, index); 316 } 317 318 static inline u8 ast_get_index_reg_mask(struct ast_device *ast, u32 base, u8 index, 319 u8 preserve_mask) 320 { 321 return __ast_read8_i_masked(ast->ioregs, base, index, preserve_mask); 322 } 323 324 static inline void ast_set_index_reg(struct ast_device *ast, u32 base, u8 index, u8 val) 325 { 326 __ast_write8_i(ast->ioregs, base, index, val); 327 } 328 329 static inline void ast_set_index_reg_mask(struct ast_device *ast, u32 base, u8 index, 330 u8 preserve_mask, u8 val) 331 { 332 __ast_write8_i_masked(ast->ioregs, base, index, preserve_mask, val); 333 } 334 335 #define AST_VIDMEM_SIZE_8M 0x00800000 336 #define AST_VIDMEM_SIZE_16M 0x01000000 337 #define AST_VIDMEM_SIZE_32M 0x02000000 338 #define AST_VIDMEM_SIZE_64M 0x04000000 339 #define AST_VIDMEM_SIZE_128M 0x08000000 340 341 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M 342 343 struct ast_vbios_stdtable { 344 u8 misc; 345 u8 seq[4]; 346 u8 crtc[25]; 347 u8 ar[20]; 348 u8 gr[9]; 349 }; 350 351 struct ast_vbios_enhtable { 352 u32 ht; 353 u32 hde; 354 u32 hfp; 355 u32 hsync; 356 u32 vt; 357 u32 vde; 358 u32 vfp; 359 u32 vsync; 360 u32 dclk_index; 361 u32 flags; 362 u32 refresh_rate; 363 u32 refresh_rate_index; 364 u32 mode_id; 365 }; 366 367 struct ast_vbios_dclk_info { 368 u8 param1; 369 u8 param2; 370 u8 param3; 371 }; 372 373 struct ast_vbios_mode_info { 374 const struct ast_vbios_stdtable *std_table; 375 const struct ast_vbios_enhtable *enh_table; 376 }; 377 378 struct ast_crtc_state { 379 struct drm_crtc_state base; 380 381 /* Last known format of primary plane */ 382 const struct drm_format_info *format; 383 384 struct ast_vbios_mode_info vbios_mode_info; 385 }; 386 387 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base) 388 389 int ast_mode_config_init(struct ast_device *ast); 390 391 #define AST_MM_ALIGN_SHIFT 4 392 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1) 393 394 #define AST_DP501_FW_VERSION_MASK GENMASK(7, 4) 395 #define AST_DP501_FW_VERSION_1 BIT(4) 396 #define AST_DP501_PNP_CONNECTED BIT(1) 397 398 #define AST_DP501_DEFAULT_DCLK 65 399 400 #define AST_DP501_GBL_VERSION 0xf000 401 #define AST_DP501_PNPMONITOR 0xf010 402 #define AST_DP501_LINKRATE 0xf014 403 #define AST_DP501_EDID_DATA 0xf020 404 405 /* 406 * ASTDP resoultion table: 407 * EX: ASTDP_A_B_C: 408 * A: Resolution 409 * B: Refresh Rate 410 * C: Misc information, such as CVT, Reduce Blanked 411 */ 412 #define ASTDP_640x480_60 0x00 413 #define ASTDP_640x480_72 0x01 414 #define ASTDP_640x480_75 0x02 415 #define ASTDP_640x480_85 0x03 416 #define ASTDP_800x600_56 0x04 417 #define ASTDP_800x600_60 0x05 418 #define ASTDP_800x600_72 0x06 419 #define ASTDP_800x600_75 0x07 420 #define ASTDP_800x600_85 0x08 421 #define ASTDP_1024x768_60 0x09 422 #define ASTDP_1024x768_70 0x0A 423 #define ASTDP_1024x768_75 0x0B 424 #define ASTDP_1024x768_85 0x0C 425 #define ASTDP_1280x1024_60 0x0D 426 #define ASTDP_1280x1024_75 0x0E 427 #define ASTDP_1280x1024_85 0x0F 428 #define ASTDP_1600x1200_60 0x10 429 #define ASTDP_320x240_60 0x11 430 #define ASTDP_400x300_60 0x12 431 #define ASTDP_512x384_60 0x13 432 #define ASTDP_1920x1200_60 0x14 433 #define ASTDP_1920x1080_60 0x15 434 #define ASTDP_1280x800_60 0x16 435 #define ASTDP_1280x800_60_RB 0x17 436 #define ASTDP_1440x900_60 0x18 437 #define ASTDP_1440x900_60_RB 0x19 438 #define ASTDP_1680x1050_60 0x1A 439 #define ASTDP_1680x1050_60_RB 0x1B 440 #define ASTDP_1600x900_60 0x1C 441 #define ASTDP_1600x900_60_RB 0x1D 442 #define ASTDP_1366x768_60 0x1E 443 #define ASTDP_1152x864_75 0x1F 444 445 int ast_mm_init(struct ast_device *ast); 446 447 /* ast post */ 448 void ast_post_gpu(struct ast_device *ast); 449 u32 ast_mindwm(struct ast_device *ast, u32 r); 450 void ast_moutdwm(struct ast_device *ast, u32 r, u32 v); 451 void ast_patch_ahb_2500(void __iomem *regs); 452 453 int ast_vga_output_init(struct ast_device *ast); 454 int ast_sil164_output_init(struct ast_device *ast); 455 456 /* ast dp501 */ 457 bool ast_backup_fw(struct ast_device *ast, u8 *addr, u32 size); 458 void ast_init_3rdtx(struct ast_device *ast); 459 int ast_dp501_output_init(struct ast_device *ast); 460 461 /* aspeed DP */ 462 int ast_dp_launch(struct ast_device *ast); 463 int ast_astdp_output_init(struct ast_device *ast); 464 465 #endif 466