1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 #ifndef __AST_DRV_H__ 29 #define __AST_DRV_H__ 30 31 #include <drm/drm_encoder.h> 32 #include <drm/drm_fb_helper.h> 33 34 #include <drm/drm_gem.h> 35 #include <drm/drm_gem_vram_helper.h> 36 37 #include <drm/drm_vram_mm_helper.h> 38 39 #include <linux/i2c.h> 40 #include <linux/i2c-algo-bit.h> 41 42 #define DRIVER_AUTHOR "Dave Airlie" 43 44 #define DRIVER_NAME "ast" 45 #define DRIVER_DESC "AST" 46 #define DRIVER_DATE "20120228" 47 48 #define DRIVER_MAJOR 0 49 #define DRIVER_MINOR 1 50 #define DRIVER_PATCHLEVEL 0 51 52 #define PCI_CHIP_AST2000 0x2000 53 #define PCI_CHIP_AST2100 0x2010 54 #define PCI_CHIP_AST1180 0x1180 55 56 57 enum ast_chip { 58 AST2000, 59 AST2100, 60 AST1100, 61 AST2200, 62 AST2150, 63 AST2300, 64 AST2400, 65 AST2500, 66 AST1180, 67 }; 68 69 enum ast_tx_chip { 70 AST_TX_NONE, 71 AST_TX_SIL164, 72 AST_TX_ITE66121, 73 AST_TX_DP501, 74 }; 75 76 #define AST_DRAM_512Mx16 0 77 #define AST_DRAM_1Gx16 1 78 #define AST_DRAM_512Mx32 2 79 #define AST_DRAM_1Gx32 3 80 #define AST_DRAM_2Gx16 6 81 #define AST_DRAM_4Gx16 7 82 #define AST_DRAM_8Gx16 8 83 84 struct ast_fbdev; 85 86 struct ast_private { 87 struct drm_device *dev; 88 89 void __iomem *regs; 90 void __iomem *ioregs; 91 92 enum ast_chip chip; 93 bool vga2_clone; 94 uint32_t dram_bus_width; 95 uint32_t dram_type; 96 uint32_t mclk; 97 uint32_t vram_size; 98 99 struct ast_fbdev *fbdev; 100 101 int fb_mtrr; 102 103 struct drm_gem_object *cursor_cache; 104 int next_cursor; 105 bool support_wide_screen; 106 enum { 107 ast_use_p2a, 108 ast_use_dt, 109 ast_use_defaults 110 } config_mode; 111 112 enum ast_tx_chip tx_chip_type; 113 u8 dp501_maxclk; 114 u8 *dp501_fw_addr; 115 const struct firmware *dp501_fw; /* dp501 fw */ 116 }; 117 118 int ast_driver_load(struct drm_device *dev, unsigned long flags); 119 void ast_driver_unload(struct drm_device *dev); 120 121 struct ast_gem_object; 122 123 #define AST_IO_AR_PORT_WRITE (0x40) 124 #define AST_IO_MISC_PORT_WRITE (0x42) 125 #define AST_IO_VGA_ENABLE_PORT (0x43) 126 #define AST_IO_SEQ_PORT (0x44) 127 #define AST_IO_DAC_INDEX_READ (0x47) 128 #define AST_IO_DAC_INDEX_WRITE (0x48) 129 #define AST_IO_DAC_DATA (0x49) 130 #define AST_IO_GR_PORT (0x4E) 131 #define AST_IO_CRTC_PORT (0x54) 132 #define AST_IO_INPUT_STATUS1_READ (0x5A) 133 #define AST_IO_MISC_PORT_READ (0x4C) 134 135 #define AST_IO_MM_OFFSET (0x380) 136 137 #define __ast_read(x) \ 138 static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \ 139 u##x val = 0;\ 140 val = ioread##x(ast->regs + reg); \ 141 return val;\ 142 } 143 144 __ast_read(8); 145 __ast_read(16); 146 __ast_read(32) 147 148 #define __ast_io_read(x) \ 149 static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \ 150 u##x val = 0;\ 151 val = ioread##x(ast->ioregs + reg); \ 152 return val;\ 153 } 154 155 __ast_io_read(8); 156 __ast_io_read(16); 157 __ast_io_read(32); 158 159 #define __ast_write(x) \ 160 static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\ 161 iowrite##x(val, ast->regs + reg);\ 162 } 163 164 __ast_write(8); 165 __ast_write(16); 166 __ast_write(32); 167 168 #define __ast_io_write(x) \ 169 static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\ 170 iowrite##x(val, ast->ioregs + reg);\ 171 } 172 173 __ast_io_write(8); 174 __ast_io_write(16); 175 #undef __ast_io_write 176 177 static inline void ast_set_index_reg(struct ast_private *ast, 178 uint32_t base, uint8_t index, 179 uint8_t val) 180 { 181 ast_io_write16(ast, base, ((u16)val << 8) | index); 182 } 183 184 void ast_set_index_reg_mask(struct ast_private *ast, 185 uint32_t base, uint8_t index, 186 uint8_t mask, uint8_t val); 187 uint8_t ast_get_index_reg(struct ast_private *ast, 188 uint32_t base, uint8_t index); 189 uint8_t ast_get_index_reg_mask(struct ast_private *ast, 190 uint32_t base, uint8_t index, uint8_t mask); 191 192 static inline void ast_open_key(struct ast_private *ast) 193 { 194 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8); 195 } 196 197 #define AST_VIDMEM_SIZE_8M 0x00800000 198 #define AST_VIDMEM_SIZE_16M 0x01000000 199 #define AST_VIDMEM_SIZE_32M 0x02000000 200 #define AST_VIDMEM_SIZE_64M 0x04000000 201 #define AST_VIDMEM_SIZE_128M 0x08000000 202 203 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M 204 205 #define AST_MAX_HWC_WIDTH 64 206 #define AST_MAX_HWC_HEIGHT 64 207 208 #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH*AST_MAX_HWC_HEIGHT*2) 209 #define AST_HWC_SIGNATURE_SIZE 32 210 211 #define AST_DEFAULT_HWC_NUM 2 212 /* define for signature structure */ 213 #define AST_HWC_SIGNATURE_CHECKSUM 0x00 214 #define AST_HWC_SIGNATURE_SizeX 0x04 215 #define AST_HWC_SIGNATURE_SizeY 0x08 216 #define AST_HWC_SIGNATURE_X 0x0C 217 #define AST_HWC_SIGNATURE_Y 0x10 218 #define AST_HWC_SIGNATURE_HOTSPOTX 0x14 219 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18 220 221 222 struct ast_i2c_chan { 223 struct i2c_adapter adapter; 224 struct drm_device *dev; 225 struct i2c_algo_bit_data bit; 226 }; 227 228 struct ast_connector { 229 struct drm_connector base; 230 struct ast_i2c_chan *i2c; 231 }; 232 233 struct ast_crtc { 234 struct drm_crtc base; 235 u8 offset_x, offset_y; 236 }; 237 238 struct ast_encoder { 239 struct drm_encoder base; 240 }; 241 242 struct ast_framebuffer { 243 struct drm_framebuffer base; 244 struct drm_gem_object *obj; 245 }; 246 247 struct ast_fbdev { 248 struct drm_fb_helper helper; /* must be first */ 249 struct ast_framebuffer afb; 250 void *sysram; 251 int size; 252 int x1, y1, x2, y2; /* dirty rect */ 253 spinlock_t dirty_lock; 254 }; 255 256 #define to_ast_crtc(x) container_of(x, struct ast_crtc, base) 257 #define to_ast_connector(x) container_of(x, struct ast_connector, base) 258 #define to_ast_encoder(x) container_of(x, struct ast_encoder, base) 259 #define to_ast_framebuffer(x) container_of(x, struct ast_framebuffer, base) 260 261 struct ast_vbios_stdtable { 262 u8 misc; 263 u8 seq[4]; 264 u8 crtc[25]; 265 u8 ar[20]; 266 u8 gr[9]; 267 }; 268 269 struct ast_vbios_enhtable { 270 u32 ht; 271 u32 hde; 272 u32 hfp; 273 u32 hsync; 274 u32 vt; 275 u32 vde; 276 u32 vfp; 277 u32 vsync; 278 u32 dclk_index; 279 u32 flags; 280 u32 refresh_rate; 281 u32 refresh_rate_index; 282 u32 mode_id; 283 }; 284 285 struct ast_vbios_dclk_info { 286 u8 param1; 287 u8 param2; 288 u8 param3; 289 }; 290 291 struct ast_vbios_mode_info { 292 const struct ast_vbios_stdtable *std_table; 293 const struct ast_vbios_enhtable *enh_table; 294 }; 295 296 extern int ast_mode_init(struct drm_device *dev); 297 extern void ast_mode_fini(struct drm_device *dev); 298 299 int ast_framebuffer_init(struct drm_device *dev, 300 struct ast_framebuffer *ast_fb, 301 const struct drm_mode_fb_cmd2 *mode_cmd, 302 struct drm_gem_object *obj); 303 304 int ast_fbdev_init(struct drm_device *dev); 305 void ast_fbdev_fini(struct drm_device *dev); 306 void ast_fbdev_set_suspend(struct drm_device *dev, int state); 307 void ast_fbdev_set_base(struct ast_private *ast, unsigned long gpu_addr); 308 309 #define AST_MM_ALIGN_SHIFT 4 310 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1) 311 312 int ast_mm_init(struct ast_private *ast); 313 void ast_mm_fini(struct ast_private *ast); 314 315 int ast_gem_create(struct drm_device *dev, 316 u32 size, bool iskernel, 317 struct drm_gem_object **obj); 318 319 /* ast post */ 320 void ast_enable_vga(struct drm_device *dev); 321 void ast_enable_mmio(struct drm_device *dev); 322 bool ast_is_vga_enabled(struct drm_device *dev); 323 void ast_post_gpu(struct drm_device *dev); 324 u32 ast_mindwm(struct ast_private *ast, u32 r); 325 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); 326 /* ast dp501 */ 327 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); 328 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); 329 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); 330 u8 ast_get_dp501_max_clk(struct drm_device *dev); 331 void ast_init_3rdtx(struct drm_device *dev); 332 void ast_release_firmware(struct drm_device *dev); 333 #endif 334