1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25 /*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28 #ifndef __AST_DRV_H__
29 #define __AST_DRV_H__
30
31 #include <linux/io.h>
32 #include <linux/types.h>
33
34 #include <drm/drm_connector.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_mode.h>
38 #include <drm/drm_framebuffer.h>
39
40 #include "ast_reg.h"
41
42 struct ast_vbios_enhtable;
43
44 #define DRIVER_AUTHOR "Dave Airlie"
45
46 #define DRIVER_NAME "ast"
47 #define DRIVER_DESC "AST"
48
49 #define DRIVER_MAJOR 0
50 #define DRIVER_MINOR 1
51 #define DRIVER_PATCHLEVEL 0
52
53 #define PCI_CHIP_AST2000 0x2000
54 #define PCI_CHIP_AST2100 0x2010
55
56 #define __AST_CHIP(__gen, __index) ((__gen) << 16 | (__index))
57
58 enum ast_chip {
59 /* 1st gen */
60 AST1000 = __AST_CHIP(1, 0), // unused
61 AST2000 = __AST_CHIP(1, 1),
62 /* 2nd gen */
63 AST1100 = __AST_CHIP(2, 0),
64 AST2100 = __AST_CHIP(2, 1),
65 AST2050 = __AST_CHIP(2, 2), // unused
66 /* 3rd gen */
67 AST2200 = __AST_CHIP(3, 0),
68 AST2150 = __AST_CHIP(3, 1),
69 /* 4th gen */
70 AST2300 = __AST_CHIP(4, 0),
71 AST1300 = __AST_CHIP(4, 1),
72 AST1050 = __AST_CHIP(4, 2), // unused
73 /* 5th gen */
74 AST2400 = __AST_CHIP(5, 0),
75 AST1400 = __AST_CHIP(5, 1),
76 AST1250 = __AST_CHIP(5, 2), // unused
77 /* 6th gen */
78 AST2500 = __AST_CHIP(6, 0),
79 AST2510 = __AST_CHIP(6, 1),
80 AST2520 = __AST_CHIP(6, 2), // unused
81 /* 7th gen */
82 AST2600 = __AST_CHIP(7, 0),
83 AST2620 = __AST_CHIP(7, 1), // unused
84 };
85
86 #define __AST_CHIP_GEN(__chip) (((unsigned long)(__chip)) >> 16)
87
88 enum ast_tx_chip {
89 AST_TX_NONE,
90 AST_TX_SIL164,
91 AST_TX_DP501,
92 AST_TX_ASTDP,
93 };
94
95 enum ast_config_mode {
96 ast_use_p2a,
97 ast_use_dt,
98 ast_use_defaults
99 };
100
101 enum ast_dram_layout {
102 AST_DRAM_512Mx16 = 0,
103 AST_DRAM_1Gx16 = 1,
104 AST_DRAM_512Mx32 = 2,
105 AST_DRAM_1Gx32 = 3,
106 AST_DRAM_2Gx16 = 6,
107 AST_DRAM_4Gx16 = 7,
108 AST_DRAM_8Gx16 = 8,
109 };
110
111 /*
112 * Hardware cursor
113 */
114
115 #define AST_MAX_HWC_WIDTH 64
116 #define AST_MAX_HWC_HEIGHT 64
117 #define AST_HWC_PITCH (AST_MAX_HWC_WIDTH * SZ_2)
118 #define AST_HWC_SIZE (AST_MAX_HWC_HEIGHT * AST_HWC_PITCH)
119
120 /*
121 * Planes
122 */
123
124 struct ast_plane {
125 struct drm_plane base;
126
127 u64 offset;
128 unsigned long size;
129 };
130
to_ast_plane(struct drm_plane * plane)131 static inline struct ast_plane *to_ast_plane(struct drm_plane *plane)
132 {
133 return container_of(plane, struct ast_plane, base);
134 }
135
136 struct ast_cursor_plane {
137 struct ast_plane base;
138
139 u8 argb4444[AST_HWC_SIZE];
140 };
141
to_ast_cursor_plane(struct drm_plane * plane)142 static inline struct ast_cursor_plane *to_ast_cursor_plane(struct drm_plane *plane)
143 {
144 return container_of(to_ast_plane(plane), struct ast_cursor_plane, base);
145 }
146
147 /*
148 * Connector
149 */
150
151 struct ast_connector {
152 struct drm_connector base;
153
154 enum drm_connector_status physical_status;
155 };
156
157 static inline struct ast_connector *
to_ast_connector(struct drm_connector * connector)158 to_ast_connector(struct drm_connector *connector)
159 {
160 return container_of(connector, struct ast_connector, base);
161 }
162
163 /*
164 * Device
165 */
166
167 struct ast_device {
168 struct drm_device base;
169
170 void __iomem *regs;
171 void __iomem *ioregs;
172 void __iomem *dp501_fw_buf;
173
174 enum ast_config_mode config_mode;
175 enum ast_chip chip;
176
177 void __iomem *vram;
178 unsigned long vram_base;
179 unsigned long vram_size;
180
181 struct mutex modeset_lock; /* Protects access to modeset I/O registers in ioregs */
182
183 enum ast_tx_chip tx_chip;
184
185 struct ast_plane primary_plane;
186 struct ast_cursor_plane cursor_plane;
187 struct drm_crtc crtc;
188 union {
189 struct {
190 struct drm_encoder encoder;
191 struct ast_connector connector;
192 } vga;
193 struct {
194 struct drm_encoder encoder;
195 struct ast_connector connector;
196 } sil164;
197 struct {
198 struct drm_encoder encoder;
199 struct ast_connector connector;
200 } dp501;
201 struct {
202 struct drm_encoder encoder;
203 struct ast_connector connector;
204 } astdp;
205 } output;
206
207 bool support_wsxga_p; /* 1680x1050 */
208 bool support_fullhd; /* 1920x1080 */
209 bool support_wuxga; /* 1920x1200 */
210
211 u8 *dp501_fw_addr;
212 const struct firmware *dp501_fw; /* dp501 fw */
213 };
214
to_ast_device(struct drm_device * dev)215 static inline struct ast_device *to_ast_device(struct drm_device *dev)
216 {
217 return container_of(dev, struct ast_device, base);
218 }
219
220 struct drm_device *ast_device_create(struct pci_dev *pdev,
221 const struct drm_driver *drv,
222 enum ast_chip chip,
223 enum ast_config_mode config_mode,
224 void __iomem *regs,
225 void __iomem *ioregs,
226 bool need_post);
227
__ast_gen(struct ast_device * ast)228 static inline unsigned long __ast_gen(struct ast_device *ast)
229 {
230 return __AST_CHIP_GEN(ast->chip);
231 }
232 #define AST_GEN(__ast) __ast_gen(__ast)
233
__ast_gen_is_eq(struct ast_device * ast,unsigned long gen)234 static inline bool __ast_gen_is_eq(struct ast_device *ast, unsigned long gen)
235 {
236 return __ast_gen(ast) == gen;
237 }
238 #define IS_AST_GEN1(__ast) __ast_gen_is_eq(__ast, 1)
239 #define IS_AST_GEN2(__ast) __ast_gen_is_eq(__ast, 2)
240 #define IS_AST_GEN3(__ast) __ast_gen_is_eq(__ast, 3)
241 #define IS_AST_GEN4(__ast) __ast_gen_is_eq(__ast, 4)
242 #define IS_AST_GEN5(__ast) __ast_gen_is_eq(__ast, 5)
243 #define IS_AST_GEN6(__ast) __ast_gen_is_eq(__ast, 6)
244 #define IS_AST_GEN7(__ast) __ast_gen_is_eq(__ast, 7)
245
__ast_read8(const void __iomem * addr,u32 reg)246 static inline u8 __ast_read8(const void __iomem *addr, u32 reg)
247 {
248 return ioread8(addr + reg);
249 }
250
__ast_read32(const void __iomem * addr,u32 reg)251 static inline u32 __ast_read32(const void __iomem *addr, u32 reg)
252 {
253 return ioread32(addr + reg);
254 }
255
__ast_write8(void __iomem * addr,u32 reg,u8 val)256 static inline void __ast_write8(void __iomem *addr, u32 reg, u8 val)
257 {
258 iowrite8(val, addr + reg);
259 }
260
__ast_write32(void __iomem * addr,u32 reg,u32 val)261 static inline void __ast_write32(void __iomem *addr, u32 reg, u32 val)
262 {
263 iowrite32(val, addr + reg);
264 }
265
__ast_read8_i(void __iomem * addr,u32 reg,u8 index)266 static inline u8 __ast_read8_i(void __iomem *addr, u32 reg, u8 index)
267 {
268 __ast_write8(addr, reg, index);
269 return __ast_read8(addr, reg + 1);
270 }
271
__ast_read8_i_masked(void __iomem * addr,u32 reg,u8 index,u8 read_mask)272 static inline u8 __ast_read8_i_masked(void __iomem *addr, u32 reg, u8 index, u8 read_mask)
273 {
274 u8 val = __ast_read8_i(addr, reg, index);
275
276 return val & read_mask;
277 }
278
__ast_write8_i(void __iomem * addr,u32 reg,u8 index,u8 val)279 static inline void __ast_write8_i(void __iomem *addr, u32 reg, u8 index, u8 val)
280 {
281 __ast_write8(addr, reg, index);
282 __ast_write8(addr, reg + 1, val);
283 }
284
__ast_write8_i_masked(void __iomem * addr,u32 reg,u8 index,u8 preserve_mask,u8 val)285 static inline void __ast_write8_i_masked(void __iomem *addr, u32 reg, u8 index, u8 preserve_mask,
286 u8 val)
287 {
288 u8 tmp = __ast_read8_i_masked(addr, reg, index, preserve_mask);
289
290 val &= ~preserve_mask;
291 __ast_write8_i(addr, reg, index, tmp | val);
292 }
293
ast_read32(struct ast_device * ast,u32 reg)294 static inline u32 ast_read32(struct ast_device *ast, u32 reg)
295 {
296 return __ast_read32(ast->regs, reg);
297 }
298
ast_write32(struct ast_device * ast,u32 reg,u32 val)299 static inline void ast_write32(struct ast_device *ast, u32 reg, u32 val)
300 {
301 __ast_write32(ast->regs, reg, val);
302 }
303
ast_io_read8(struct ast_device * ast,u32 reg)304 static inline u8 ast_io_read8(struct ast_device *ast, u32 reg)
305 {
306 return __ast_read8(ast->ioregs, reg);
307 }
308
ast_io_write8(struct ast_device * ast,u32 reg,u8 val)309 static inline void ast_io_write8(struct ast_device *ast, u32 reg, u8 val)
310 {
311 __ast_write8(ast->ioregs, reg, val);
312 }
313
ast_get_index_reg(struct ast_device * ast,u32 base,u8 index)314 static inline u8 ast_get_index_reg(struct ast_device *ast, u32 base, u8 index)
315 {
316 return __ast_read8_i(ast->ioregs, base, index);
317 }
318
ast_get_index_reg_mask(struct ast_device * ast,u32 base,u8 index,u8 preserve_mask)319 static inline u8 ast_get_index_reg_mask(struct ast_device *ast, u32 base, u8 index,
320 u8 preserve_mask)
321 {
322 return __ast_read8_i_masked(ast->ioregs, base, index, preserve_mask);
323 }
324
ast_set_index_reg(struct ast_device * ast,u32 base,u8 index,u8 val)325 static inline void ast_set_index_reg(struct ast_device *ast, u32 base, u8 index, u8 val)
326 {
327 __ast_write8_i(ast->ioregs, base, index, val);
328 }
329
ast_set_index_reg_mask(struct ast_device * ast,u32 base,u8 index,u8 preserve_mask,u8 val)330 static inline void ast_set_index_reg_mask(struct ast_device *ast, u32 base, u8 index,
331 u8 preserve_mask, u8 val)
332 {
333 __ast_write8_i_masked(ast->ioregs, base, index, preserve_mask, val);
334 }
335
336 struct ast_vbios_stdtable {
337 u8 misc;
338 u8 seq[4];
339 u8 crtc[25];
340 u8 ar[20];
341 u8 gr[9];
342 };
343
344 struct ast_vbios_dclk_info {
345 u8 param1;
346 u8 param2;
347 u8 param3;
348 };
349
350 struct ast_crtc_state {
351 struct drm_crtc_state base;
352
353 /* Last known format of primary plane */
354 const struct drm_format_info *format;
355
356 const struct ast_vbios_stdtable *std_table;
357 const struct ast_vbios_enhtable *vmode;
358 };
359
360 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)
361
362 #define AST_MM_ALIGN_SHIFT 4
363 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
364
365 #define AST_DP501_FW_VERSION_MASK GENMASK(7, 4)
366 #define AST_DP501_FW_VERSION_1 BIT(4)
367 #define AST_DP501_PNP_CONNECTED BIT(1)
368
369 #define AST_DP501_DEFAULT_DCLK 65
370
371 #define AST_DP501_GBL_VERSION 0xf000
372 #define AST_DP501_PNPMONITOR 0xf010
373 #define AST_DP501_LINKRATE 0xf014
374 #define AST_DP501_EDID_DATA 0xf020
375
376 /*
377 * ASTDP resoultion table:
378 * EX: ASTDP_A_B_C:
379 * A: Resolution
380 * B: Refresh Rate
381 * C: Misc information, such as CVT, Reduce Blanked
382 */
383 #define ASTDP_640x480_60 0x00
384 #define ASTDP_640x480_72 0x01
385 #define ASTDP_640x480_75 0x02
386 #define ASTDP_640x480_85 0x03
387 #define ASTDP_800x600_56 0x04
388 #define ASTDP_800x600_60 0x05
389 #define ASTDP_800x600_72 0x06
390 #define ASTDP_800x600_75 0x07
391 #define ASTDP_800x600_85 0x08
392 #define ASTDP_1024x768_60 0x09
393 #define ASTDP_1024x768_70 0x0A
394 #define ASTDP_1024x768_75 0x0B
395 #define ASTDP_1024x768_85 0x0C
396 #define ASTDP_1280x1024_60 0x0D
397 #define ASTDP_1280x1024_75 0x0E
398 #define ASTDP_1280x1024_85 0x0F
399 #define ASTDP_1600x1200_60 0x10
400 #define ASTDP_320x240_60 0x11
401 #define ASTDP_400x300_60 0x12
402 #define ASTDP_512x384_60 0x13
403 #define ASTDP_1920x1200_60 0x14
404 #define ASTDP_1920x1080_60 0x15
405 #define ASTDP_1280x800_60 0x16
406 #define ASTDP_1280x800_60_RB 0x17
407 #define ASTDP_1440x900_60 0x18
408 #define ASTDP_1440x900_60_RB 0x19
409 #define ASTDP_1680x1050_60 0x1A
410 #define ASTDP_1680x1050_60_RB 0x1B
411 #define ASTDP_1600x900_60 0x1C
412 #define ASTDP_1600x900_60_RB 0x1D
413 #define ASTDP_1366x768_60 0x1E
414 #define ASTDP_1152x864_75 0x1F
415
416 int ast_mm_init(struct ast_device *ast);
417
418 /* ast_2000.c */
419 int ast_2000_post(struct ast_device *ast);
420
421 /* ast_2100.c */
422 int ast_2100_post(struct ast_device *ast);
423
424 /* ast_2300.c */
425 int ast_2300_post(struct ast_device *ast);
426
427 /* ast_2500.c */
428 void ast_2500_patch_ahb(void __iomem *regs);
429 int ast_2500_post(struct ast_device *ast);
430
431 /* ast_2600.c */
432 int ast_2600_post(struct ast_device *ast);
433
434 /* ast post */
435 int ast_post_gpu(struct ast_device *ast);
436 u32 ast_mindwm(struct ast_device *ast, u32 r);
437 void ast_moutdwm(struct ast_device *ast, u32 r, u32 v);
438
439 int ast_vga_output_init(struct ast_device *ast);
440 int ast_sil164_output_init(struct ast_device *ast);
441
442 /* ast_cursor.c */
443 long ast_cursor_vram_offset(struct ast_device *ast);
444 int ast_cursor_plane_init(struct ast_device *ast);
445
446 /* ast dp501 */
447 bool ast_backup_fw(struct ast_device *ast, u8 *addr, u32 size);
448 void ast_init_3rdtx(struct ast_device *ast);
449 int ast_dp501_output_init(struct ast_device *ast);
450
451 /* aspeed DP */
452 int ast_dp_launch(struct ast_device *ast);
453 int ast_astdp_output_init(struct ast_device *ast);
454
455 /* ast_mode.c */
456 int ast_mode_config_init(struct ast_device *ast);
457 int ast_plane_init(struct drm_device *dev, struct ast_plane *ast_plane,
458 u64 offset, unsigned long size,
459 uint32_t possible_crtcs,
460 const struct drm_plane_funcs *funcs,
461 const uint32_t *formats, unsigned int format_count,
462 const uint64_t *format_modifiers,
463 enum drm_plane_type type);
464 void __iomem *ast_plane_vaddr(struct ast_plane *ast);
465
466 #endif
467