1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 29 #include <linux/aperture.h> 30 #include <linux/module.h> 31 #include <linux/of.h> 32 #include <linux/pci.h> 33 34 #include <drm/clients/drm_client_setup.h> 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_drv.h> 37 #include <drm/drm_fbdev_shmem.h> 38 #include <drm/drm_gem_shmem_helper.h> 39 #include <drm/drm_module.h> 40 #include <drm/drm_print.h> 41 #include <drm/drm_probe_helper.h> 42 43 #include "ast_drv.h" 44 45 static int ast_modeset = -1; 46 47 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 48 module_param_named(modeset, ast_modeset, int, 0400); 49 50 /* 51 * Register access 52 */ 53 54 /* Select R/W segment */ 55 static void __ast_selseg(void __iomem *regs, u32 r) 56 { 57 u32 p2a04, p2a04_base; 58 59 p2a04 = r & AST_REG_P2A04_BASE_MASK; 60 __ast_write32(regs, AST_REG_P2A04, p2a04); 61 __ast_write32(regs, AST_REG_P2A00, AST_REG_P2A00_PROTECTION_KEY); 62 63 do { 64 cpu_relax(); 65 p2a04_base = __ast_read32(regs, AST_REG_P2A04); 66 p2a04_base &= AST_REG_P2A04_BASE_MASK; 67 } while (p2a04_base != p2a04); 68 } 69 70 /* Read within segment */ 71 static u32 __ast_rdseg32(void __iomem *regs, u32 r) 72 { 73 return __ast_read32(regs, AST_REG_P2A_ADDR(r)); 74 } 75 76 /* Write within segment */ 77 static void __ast_wrseg32(void __iomem *regs, u32 r, u32 v) 78 { 79 __ast_write32(regs, AST_REG_P2A_ADDR(r), v); 80 } 81 82 u32 __ast_mindwm(void __iomem *regs, u32 r) 83 { 84 __ast_selseg(regs, r); 85 86 return __ast_rdseg32(regs, r); 87 } 88 89 void __ast_moutdwm(void __iomem *regs, u32 r, u32 v) 90 { 91 __ast_selseg(regs, r); 92 __ast_wrseg32(regs, r, v); 93 } 94 95 u32 ast_mindwm(struct ast_device *ast, u32 r) 96 { 97 return __ast_mindwm(ast->regs, r); 98 } 99 100 void ast_moutdwm(struct ast_device *ast, u32 r, u32 v) 101 { 102 __ast_moutdwm(ast->regs, r, v); 103 } 104 105 void ast_moutdwm_poll(struct ast_device *ast, u32 r, u32 v, u32 res) 106 { 107 void __iomem *regs = ast->regs; 108 109 __ast_selseg(regs, r); 110 __ast_wrseg32(regs, r, v); 111 112 do { 113 cpu_relax(); 114 } while (__ast_rdseg32(regs, r) != res); 115 } 116 117 /* 118 * AST device 119 */ 120 121 void ast_device_init(struct ast_device *ast, 122 enum ast_chip chip, 123 enum ast_config_mode config_mode, 124 void __iomem *regs, 125 void __iomem *ioregs, 126 const struct ast_device_quirks *quirks) 127 { 128 ast->quirks = quirks; 129 ast->chip = chip; 130 ast->config_mode = config_mode; 131 ast->regs = regs; 132 ast->ioregs = ioregs; 133 } 134 135 void __ast_device_set_tx_chip(struct ast_device *ast, enum ast_tx_chip tx_chip) 136 { 137 static const char * const info_str[] = { 138 "analog VGA", 139 "Sil164 TMDS transmitter", 140 "DP501 DisplayPort transmitter", 141 "ASPEED DisplayPort transmitter", 142 }; 143 144 drm_info(&ast->base, "Using %s\n", info_str[tx_chip]); 145 146 ast->tx_chip = tx_chip; 147 } 148 149 /* 150 * DRM driver 151 */ 152 153 DEFINE_DRM_GEM_FOPS(ast_fops); 154 155 static const struct drm_driver ast_driver = { 156 .driver_features = DRIVER_ATOMIC | 157 DRIVER_GEM | 158 DRIVER_MODESET, 159 160 .fops = &ast_fops, 161 .name = DRIVER_NAME, 162 .desc = DRIVER_DESC, 163 .major = DRIVER_MAJOR, 164 .minor = DRIVER_MINOR, 165 .patchlevel = DRIVER_PATCHLEVEL, 166 167 DRM_GEM_SHMEM_DRIVER_OPS, 168 DRM_FBDEV_SHMEM_DRIVER_OPS, 169 }; 170 171 /* 172 * PCI driver 173 */ 174 175 #define PCI_VENDOR_ASPEED 0x1a03 176 177 #define AST_VGA_DEVICE(id, info) { \ 178 .class = PCI_BASE_CLASS_DISPLAY << 16, \ 179 .class_mask = 0xff0000, \ 180 .vendor = PCI_VENDOR_ASPEED, \ 181 .device = id, \ 182 .subvendor = PCI_ANY_ID, \ 183 .subdevice = PCI_ANY_ID, \ 184 .driver_data = (unsigned long) info } 185 186 static const struct pci_device_id ast_pciidlist[] = { 187 AST_VGA_DEVICE(PCI_CHIP_AST2000, NULL), 188 AST_VGA_DEVICE(PCI_CHIP_AST2100, NULL), 189 {0, 0, 0}, 190 }; 191 192 MODULE_DEVICE_TABLE(pci, ast_pciidlist); 193 194 static bool ast_is_vga_enabled(void __iomem *ioregs) 195 { 196 u8 vgaer = __ast_read8(ioregs, AST_IO_VGAER); 197 198 return vgaer & AST_IO_VGAER_VGA_ENABLE; 199 } 200 201 static void ast_enable_vga(void __iomem *ioregs) 202 { 203 __ast_write8(ioregs, AST_IO_VGAER, AST_IO_VGAER_VGA_ENABLE); 204 __ast_write8(ioregs, AST_IO_VGAMR_W, AST_IO_VGAMR_IOSEL); 205 } 206 207 /* 208 * Run this function as part of the HW device cleanup; not 209 * when the DRM device gets released. 210 */ 211 static void ast_enable_mmio_release(void *data) 212 { 213 void __iomem *ioregs = (void __force __iomem *)data; 214 215 /* enable standard VGA decode */ 216 __ast_write8_i(ioregs, AST_IO_VGACRI, 0xa1, AST_IO_VGACRA1_MMIO_ENABLED); 217 } 218 219 static int ast_enable_mmio(struct device *dev, void __iomem *ioregs) 220 { 221 void *data = (void __force *)ioregs; 222 223 __ast_write8_i(ioregs, AST_IO_VGACRI, 0xa1, 224 AST_IO_VGACRA1_MMIO_ENABLED | 225 AST_IO_VGACRA1_VGAIO_DISABLED); 226 227 return devm_add_action_or_reset(dev, ast_enable_mmio_release, data); 228 } 229 230 static void ast_open_key(void __iomem *ioregs) 231 { 232 __ast_write8_i(ioregs, AST_IO_VGACRI, 0x80, AST_IO_VGACR80_PASSWORD); 233 } 234 235 static int ast_detect_chip(struct pci_dev *pdev, 236 void __iomem *regs, void __iomem *ioregs, 237 enum ast_chip *chip_out, 238 enum ast_config_mode *config_mode_out) 239 { 240 struct device *dev = &pdev->dev; 241 struct device_node *np = dev->of_node; 242 enum ast_config_mode config_mode = ast_use_defaults; 243 uint32_t scu_rev = 0xffffffff; 244 enum ast_chip chip; 245 u32 data, p2a04, scu07c; 246 u8 vgacrd0, vgacrd1; 247 248 /* 249 * Find configuration mode and read SCU revision 250 */ 251 252 /* Check if we have device-tree properties */ 253 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", &data)) { 254 /* We do, disable P2A access */ 255 config_mode = ast_use_dt; 256 scu_rev = data; 257 } else if (pdev->device == PCI_CHIP_AST2000) { // Not all families have a P2A bridge 258 /* 259 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge 260 * is disabled. We force using P2A if VGA only mode bit 261 * is set D[7] 262 */ 263 vgacrd0 = __ast_read8_i(ioregs, AST_IO_VGACRI, 0xd0); 264 vgacrd1 = __ast_read8_i(ioregs, AST_IO_VGACRI, 0xd1); 265 if (!(vgacrd0 & 0x80) || !(vgacrd1 & 0x10)) { 266 267 /* 268 * We have a P2A bridge and it is enabled. 269 */ 270 271 /* Patch AST2500/AST2510 */ 272 if ((pdev->revision & 0xf0) == 0x40) { 273 if (!(vgacrd0 & AST_IO_VGACRD0_VRAM_INIT_STATUS_MASK)) 274 ast_2500_patch_ahb(regs); 275 } 276 277 /* Double check that it's actually working */ 278 p2a04 = __ast_read32(regs, AST_REG_P2A04); 279 if (p2a04 != 0xffffffff && p2a04 != 0x00000000) { 280 config_mode = ast_use_p2a; 281 282 /* Read SCU7C (silicon revision register) */ 283 scu07c = __ast_mindwm(regs, AST_REG_SCU07C); 284 scu_rev = scu07c & AST_REG_SCU07C_CHIP_BONDING_MASK; 285 } 286 } 287 } 288 289 switch (config_mode) { 290 case ast_use_defaults: 291 dev_info(dev, "Using default configuration\n"); 292 break; 293 case ast_use_dt: 294 dev_info(dev, "Using device-tree for configuration\n"); 295 break; 296 case ast_use_p2a: 297 dev_info(dev, "Using P2A bridge for configuration\n"); 298 break; 299 } 300 301 /* 302 * Identify chipset 303 */ 304 305 if (pdev->revision >= 0x50) { 306 chip = AST2600; 307 dev_info(dev, "AST 2600 detected\n"); 308 } else if (pdev->revision >= 0x40) { 309 switch (scu_rev & 0x300) { 310 case 0x0100: 311 chip = AST2510; 312 dev_info(dev, "AST 2510 detected\n"); 313 break; 314 default: 315 chip = AST2500; 316 dev_info(dev, "AST 2500 detected\n"); 317 break; 318 } 319 } else if (pdev->revision >= 0x30) { 320 switch (scu_rev & 0x300) { 321 case 0x0100: 322 chip = AST1400; 323 dev_info(dev, "AST 1400 detected\n"); 324 break; 325 default: 326 chip = AST2400; 327 dev_info(dev, "AST 2400 detected\n"); 328 break; 329 } 330 } else if (pdev->revision >= 0x20) { 331 switch (scu_rev & 0x300) { 332 case 0x0000: 333 chip = AST1300; 334 dev_info(dev, "AST 1300 detected\n"); 335 break; 336 default: 337 chip = AST2300; 338 dev_info(dev, "AST 2300 detected\n"); 339 break; 340 } 341 } else if (pdev->revision >= 0x10) { 342 switch (scu_rev & 0x0300) { 343 case 0x0200: 344 chip = AST1100; 345 dev_info(dev, "AST 1100 detected\n"); 346 break; 347 case 0x0100: 348 chip = AST2200; 349 dev_info(dev, "AST 2200 detected\n"); 350 break; 351 case 0x0000: 352 chip = AST2150; 353 dev_info(dev, "AST 2150 detected\n"); 354 break; 355 default: 356 chip = AST2100; 357 dev_info(dev, "AST 2100 detected\n"); 358 break; 359 } 360 } else { 361 chip = AST2000; 362 dev_info(dev, "AST 2000 detected\n"); 363 } 364 365 *chip_out = chip; 366 *config_mode_out = config_mode; 367 368 return __AST_CHIP_GEN(chip); 369 } 370 371 static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 372 { 373 struct device *dev = &pdev->dev; 374 int ret; 375 void __iomem *regs; 376 void __iomem *ioregs; 377 enum ast_config_mode config_mode; 378 enum ast_chip chip; 379 unsigned int chip_gen; 380 struct drm_device *drm; 381 bool need_post = false; 382 383 ret = aperture_remove_conflicting_pci_devices(pdev, ast_driver.name); 384 if (ret) 385 return ret; 386 387 ret = pcim_enable_device(pdev); 388 if (ret) 389 return ret; 390 391 regs = pcim_iomap_region(pdev, 1, "ast"); 392 if (IS_ERR(regs)) 393 return PTR_ERR(regs); 394 395 if (pdev->revision >= 0x40) { 396 /* 397 * On AST2500 and later models, MMIO is enabled by 398 * default. Adopt it to be compatible with ARM. 399 */ 400 resource_size_t len = pci_resource_len(pdev, 1); 401 402 if (len < AST_IO_MM_OFFSET) 403 return -EIO; 404 if ((len - AST_IO_MM_OFFSET) < AST_IO_MM_LENGTH) 405 return -EIO; 406 ioregs = regs + AST_IO_MM_OFFSET; 407 } else if (pci_resource_flags(pdev, 2) & IORESOURCE_IO) { 408 /* 409 * Map I/O registers if we have a PCI BAR for I/O. 410 */ 411 resource_size_t len = pci_resource_len(pdev, 2); 412 413 if (len < AST_IO_MM_LENGTH) 414 return -EIO; 415 ioregs = pcim_iomap_region(pdev, 2, "ast"); 416 if (IS_ERR(ioregs)) 417 return PTR_ERR(ioregs); 418 } else { 419 /* 420 * Anything else is best effort. 421 */ 422 resource_size_t len = pci_resource_len(pdev, 1); 423 424 if (len < AST_IO_MM_OFFSET) 425 return -EIO; 426 if ((len - AST_IO_MM_OFFSET) < AST_IO_MM_LENGTH) 427 return -EIO; 428 ioregs = regs + AST_IO_MM_OFFSET; 429 430 dev_info(dev, "Platform has no I/O space, using MMIO\n"); 431 } 432 433 if (!ast_is_vga_enabled(ioregs)) { 434 dev_info(dev, "VGA not enabled on entry, requesting chip POST\n"); 435 need_post = true; 436 } 437 438 /* 439 * If VGA isn't enabled, we need to enable now or subsequent 440 * access to the scratch registers will fail. 441 */ 442 if (need_post) 443 ast_enable_vga(ioregs); 444 /* Enable extended register access */ 445 ast_open_key(ioregs); 446 447 ret = ast_enable_mmio(dev, ioregs); 448 if (ret) 449 return ret; 450 451 ret = ast_detect_chip(pdev, regs, ioregs, &chip, &config_mode); 452 if (ret < 0) 453 return ret; 454 chip_gen = ret; 455 456 switch (chip_gen) { 457 case 1: 458 drm = ast_2000_device_create(pdev, &ast_driver, chip, config_mode, 459 regs, ioregs, need_post); 460 break; 461 case 2: 462 drm = ast_2100_device_create(pdev, &ast_driver, chip, config_mode, 463 regs, ioregs, need_post); 464 break; 465 case 3: 466 drm = ast_2200_device_create(pdev, &ast_driver, chip, config_mode, 467 regs, ioregs, need_post); 468 break; 469 case 4: 470 drm = ast_2300_device_create(pdev, &ast_driver, chip, config_mode, 471 regs, ioregs, need_post); 472 break; 473 case 5: 474 drm = ast_2400_device_create(pdev, &ast_driver, chip, config_mode, 475 regs, ioregs, need_post); 476 break; 477 case 6: 478 drm = ast_2500_device_create(pdev, &ast_driver, chip, config_mode, 479 regs, ioregs, need_post); 480 break; 481 case 7: 482 drm = ast_2600_device_create(pdev, &ast_driver, chip, config_mode, 483 regs, ioregs, need_post); 484 break; 485 default: 486 dev_err(&pdev->dev, "Gen%d not supported\n", chip_gen); 487 return -ENODEV; 488 } 489 if (IS_ERR(drm)) 490 return PTR_ERR(drm); 491 pci_set_drvdata(pdev, drm); 492 493 ret = drm_dev_register(drm, ent->driver_data); 494 if (ret) 495 return ret; 496 497 drm_client_setup(drm, NULL); 498 499 return 0; 500 } 501 502 static void ast_pci_remove(struct pci_dev *pdev) 503 { 504 struct drm_device *dev = pci_get_drvdata(pdev); 505 506 drm_dev_unregister(dev); 507 drm_atomic_helper_shutdown(dev); 508 } 509 510 static void ast_pci_shutdown(struct pci_dev *pdev) 511 { 512 drm_atomic_helper_shutdown(pci_get_drvdata(pdev)); 513 } 514 515 static int ast_drm_freeze(struct drm_device *dev) 516 { 517 int error; 518 519 error = drm_mode_config_helper_suspend(dev); 520 if (error) 521 return error; 522 pci_save_state(to_pci_dev(dev->dev)); 523 return 0; 524 } 525 526 static int ast_drm_thaw(struct drm_device *dev) 527 { 528 struct ast_device *ast = to_ast_device(dev); 529 int ret; 530 531 ast_enable_vga(ast->ioregs); 532 ast_open_key(ast->ioregs); 533 ast_enable_mmio(dev->dev, ast->ioregs); 534 535 ret = ast_post_gpu(ast); 536 if (ret) 537 return ret; 538 539 return drm_mode_config_helper_resume(dev); 540 } 541 542 static int ast_drm_resume(struct drm_device *dev) 543 { 544 if (pci_enable_device(to_pci_dev(dev->dev))) 545 return -EIO; 546 547 return ast_drm_thaw(dev); 548 } 549 550 static int ast_pm_suspend(struct device *dev) 551 { 552 struct pci_dev *pdev = to_pci_dev(dev); 553 struct drm_device *ddev = pci_get_drvdata(pdev); 554 int error; 555 556 error = ast_drm_freeze(ddev); 557 if (error) 558 return error; 559 560 pci_disable_device(pdev); 561 pci_set_power_state(pdev, PCI_D3hot); 562 return 0; 563 } 564 565 static int ast_pm_resume(struct device *dev) 566 { 567 struct pci_dev *pdev = to_pci_dev(dev); 568 struct drm_device *ddev = pci_get_drvdata(pdev); 569 return ast_drm_resume(ddev); 570 } 571 572 static int ast_pm_freeze(struct device *dev) 573 { 574 struct pci_dev *pdev = to_pci_dev(dev); 575 struct drm_device *ddev = pci_get_drvdata(pdev); 576 return ast_drm_freeze(ddev); 577 } 578 579 static int ast_pm_thaw(struct device *dev) 580 { 581 struct pci_dev *pdev = to_pci_dev(dev); 582 struct drm_device *ddev = pci_get_drvdata(pdev); 583 return ast_drm_thaw(ddev); 584 } 585 586 static int ast_pm_poweroff(struct device *dev) 587 { 588 struct pci_dev *pdev = to_pci_dev(dev); 589 struct drm_device *ddev = pci_get_drvdata(pdev); 590 591 return ast_drm_freeze(ddev); 592 } 593 594 static const struct dev_pm_ops ast_pm_ops = { 595 .suspend = ast_pm_suspend, 596 .resume = ast_pm_resume, 597 .freeze = ast_pm_freeze, 598 .thaw = ast_pm_thaw, 599 .poweroff = ast_pm_poweroff, 600 .restore = ast_pm_resume, 601 }; 602 603 static struct pci_driver ast_pci_driver = { 604 .name = DRIVER_NAME, 605 .id_table = ast_pciidlist, 606 .probe = ast_pci_probe, 607 .remove = ast_pci_remove, 608 .shutdown = ast_pci_shutdown, 609 .driver.pm = &ast_pm_ops, 610 }; 611 612 drm_module_pci_driver_if_modeset(ast_pci_driver, ast_modeset); 613 614 MODULE_AUTHOR(DRIVER_AUTHOR); 615 MODULE_DESCRIPTION(DRIVER_DESC); 616 MODULE_LICENSE("GPL and additional rights"); 617