1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/delay.h> 4 #include <linux/firmware.h> 5 #include <linux/module.h> 6 7 #include <drm/drm_atomic_state_helper.h> 8 #include <drm/drm_edid.h> 9 #include <drm/drm_modeset_helper_vtables.h> 10 #include <drm/drm_probe_helper.h> 11 12 #include "ast_drv.h" 13 14 MODULE_FIRMWARE("ast_dp501_fw.bin"); 15 16 static void ast_release_firmware(void *data) 17 { 18 struct ast_device *ast = data; 19 20 release_firmware(ast->dp501_fw); 21 ast->dp501_fw = NULL; 22 } 23 24 static int ast_load_dp501_microcode(struct ast_device *ast) 25 { 26 struct drm_device *dev = &ast->base; 27 int ret; 28 29 ret = request_firmware(&ast->dp501_fw, "ast_dp501_fw.bin", dev->dev); 30 if (ret) 31 return ret; 32 33 return devm_add_action_or_reset(dev->dev, ast_release_firmware, ast); 34 } 35 36 static void send_ack(struct ast_device *ast) 37 { 38 u8 sendack; 39 sendack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0xff); 40 sendack |= 0x80; 41 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0x00, sendack); 42 } 43 44 static void send_nack(struct ast_device *ast) 45 { 46 u8 sendack; 47 sendack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0xff); 48 sendack &= ~0x80; 49 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0x00, sendack); 50 } 51 52 static bool wait_ack(struct ast_device *ast) 53 { 54 u8 waitack; 55 u32 retry = 0; 56 do { 57 waitack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff); 58 waitack &= 0x80; 59 udelay(100); 60 } while ((!waitack) && (retry++ < 1000)); 61 62 if (retry < 1000) 63 return true; 64 else 65 return false; 66 } 67 68 static bool wait_nack(struct ast_device *ast) 69 { 70 u8 waitack; 71 u32 retry = 0; 72 do { 73 waitack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff); 74 waitack &= 0x80; 75 udelay(100); 76 } while ((waitack) && (retry++ < 1000)); 77 78 if (retry < 1000) 79 return true; 80 else 81 return false; 82 } 83 84 static void set_cmd_trigger(struct ast_device *ast) 85 { 86 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, ~0x40, 0x40); 87 } 88 89 static void clear_cmd_trigger(struct ast_device *ast) 90 { 91 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, ~0x40, 0x00); 92 } 93 94 #if 0 95 static bool wait_fw_ready(struct ast_device *ast) 96 { 97 u8 waitready; 98 u32 retry = 0; 99 do { 100 waitready = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff); 101 waitready &= 0x40; 102 udelay(100); 103 } while ((!waitready) && (retry++ < 1000)); 104 105 if (retry < 1000) 106 return true; 107 else 108 return false; 109 } 110 #endif 111 112 static bool ast_write_cmd(struct ast_device *ast, u8 data) 113 { 114 int retry = 0; 115 116 if (wait_nack(ast)) { 117 send_nack(ast); 118 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9a, 0x00, data); 119 send_ack(ast); 120 set_cmd_trigger(ast); 121 do { 122 if (wait_ack(ast)) { 123 clear_cmd_trigger(ast); 124 send_nack(ast); 125 return true; 126 } 127 } while (retry++ < 100); 128 } 129 clear_cmd_trigger(ast); 130 send_nack(ast); 131 return false; 132 } 133 134 static bool ast_write_data(struct ast_device *ast, u8 data) 135 { 136 if (wait_nack(ast)) { 137 send_nack(ast); 138 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9a, 0x00, data); 139 send_ack(ast); 140 if (wait_ack(ast)) { 141 send_nack(ast); 142 return true; 143 } 144 } 145 send_nack(ast); 146 return false; 147 } 148 149 #if 0 150 static bool ast_read_data(struct drm_device *dev, u8 *data) 151 { 152 struct ast_device *ast = to_ast_device(dev); 153 u8 tmp; 154 155 *data = 0; 156 157 if (wait_ack(ast) == false) 158 return false; 159 tmp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd3, 0xff); 160 *data = tmp; 161 if (wait_nack(ast) == false) { 162 send_nack(ast); 163 return false; 164 } 165 send_nack(ast); 166 return true; 167 } 168 169 static void clear_cmd(struct ast_device *ast) 170 { 171 send_nack(ast); 172 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9a, 0x00, 0x00); 173 } 174 #endif 175 176 static void ast_set_dp501_video_output(struct ast_device *ast, u8 mode) 177 { 178 ast_write_cmd(ast, 0x40); 179 ast_write_data(ast, mode); 180 181 msleep(10); 182 } 183 184 static u32 get_fw_base(struct ast_device *ast) 185 { 186 return ast_mindwm(ast, AST_REG_SCU104) & 0x7fffffff; 187 } 188 189 bool ast_backup_fw(struct ast_device *ast, u8 *addr, u32 size) 190 { 191 u32 i, data; 192 u32 boot_address; 193 194 if (ast->config_mode != ast_use_p2a) 195 return false; 196 197 data = ast_mindwm(ast, AST_REG_SCU100) & 0x01; 198 if (data) { 199 boot_address = get_fw_base(ast); 200 for (i = 0; i < size; i += 4) 201 *(u32 *)(addr + i) = ast_mindwm(ast, boot_address + i); 202 return true; 203 } 204 return false; 205 } 206 207 static bool ast_launch_m68k(struct ast_device *ast) 208 { 209 u32 i, data, len = 0; 210 u32 boot_address; 211 u8 *fw_addr = NULL; 212 u8 jreg; 213 214 if (ast->config_mode != ast_use_p2a) 215 return false; 216 217 data = ast_mindwm(ast, AST_REG_SCU100) & 0x01; 218 if (!data) { 219 220 if (ast->dp501_fw_addr) { 221 fw_addr = ast->dp501_fw_addr; 222 len = 32*1024; 223 } else { 224 if (!ast->dp501_fw && 225 ast_load_dp501_microcode(ast) < 0) 226 return false; 227 228 fw_addr = (u8 *)ast->dp501_fw->data; 229 len = ast->dp501_fw->size; 230 } 231 /* Get BootAddress */ 232 ast_moutdwm(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY); 233 data = ast_mindwm(ast, AST_REG_MCR04); 234 switch (data & 0x03) { 235 case 0: 236 boot_address = 0x44000000; 237 break; 238 default: 239 case 1: 240 boot_address = 0x48000000; 241 break; 242 case 2: 243 boot_address = 0x50000000; 244 break; 245 case 3: 246 boot_address = 0x60000000; 247 break; 248 } 249 boot_address -= 0x200000; /* -2MB */ 250 251 /* copy image to buffer */ 252 for (i = 0; i < len; i += 4) { 253 data = *(u32 *)(fw_addr + i); 254 ast_moutdwm(ast, boot_address + i, data); 255 } 256 257 /* Init SCU */ 258 ast_moutdwm(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY); 259 260 /* Launch FW */ 261 ast_moutdwm(ast, AST_REG_SCU104, 0x80000000 + boot_address); 262 ast_moutdwm(ast, AST_REG_SCU100, 1); 263 264 /* Update Scratch */ 265 data = ast_mindwm(ast, AST_REG_SCU040) & 0xfffff1ff; 266 data |= 0x800; /* D[11:9] = 100b: UEFI handling */ 267 ast_moutdwm(ast, AST_REG_SCU040, data); 268 269 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */ 270 jreg |= 0x02; 271 ast_set_index_reg(ast, AST_IO_VGACRI, 0x99, jreg); 272 } 273 return true; 274 } 275 276 static bool ast_dp501_is_connected(struct ast_device *ast) 277 { 278 u32 boot_address, offset, data; 279 280 if (ast->config_mode == ast_use_p2a) { 281 boot_address = get_fw_base(ast); 282 283 /* validate FW version */ 284 offset = AST_DP501_GBL_VERSION; 285 data = ast_mindwm(ast, boot_address + offset); 286 if ((data & AST_DP501_FW_VERSION_MASK) != AST_DP501_FW_VERSION_1) 287 return false; 288 289 /* validate PnP Monitor */ 290 offset = AST_DP501_PNPMONITOR; 291 data = ast_mindwm(ast, boot_address + offset); 292 if (!(data & AST_DP501_PNP_CONNECTED)) 293 return false; 294 } else { 295 if (!ast->dp501_fw_buf) 296 return false; 297 298 /* dummy read */ 299 offset = 0x0000; 300 data = readl(ast->dp501_fw_buf + offset); 301 302 /* validate FW version */ 303 offset = AST_DP501_GBL_VERSION; 304 data = readl(ast->dp501_fw_buf + offset); 305 if ((data & AST_DP501_FW_VERSION_MASK) != AST_DP501_FW_VERSION_1) 306 return false; 307 308 /* validate PnP Monitor */ 309 offset = AST_DP501_PNPMONITOR; 310 data = readl(ast->dp501_fw_buf + offset); 311 if (!(data & AST_DP501_PNP_CONNECTED)) 312 return false; 313 } 314 return true; 315 } 316 317 static int ast_dp512_read_edid_block(void *data, u8 *buf, unsigned int block, size_t len) 318 { 319 struct ast_device *ast = data; 320 size_t rdlen = round_up(len, 4); 321 u32 i, boot_address, offset, ediddata; 322 323 if (block > (512 / EDID_LENGTH)) 324 return -EIO; 325 326 offset = AST_DP501_EDID_DATA + block * EDID_LENGTH; 327 328 if (ast->config_mode == ast_use_p2a) { 329 boot_address = get_fw_base(ast); 330 331 for (i = 0; i < rdlen; i += 4) { 332 ediddata = ast_mindwm(ast, boot_address + offset + i); 333 memcpy(buf, &ediddata, min((len - i), 4)); 334 buf += 4; 335 } 336 } else { 337 for (i = 0; i < rdlen; i += 4) { 338 ediddata = readl(ast->dp501_fw_buf + offset + i); 339 memcpy(buf, &ediddata, min((len - i), 4)); 340 buf += 4; 341 } 342 } 343 344 return true; 345 } 346 347 static bool ast_init_dvo(struct ast_device *ast) 348 { 349 u8 jreg; 350 u32 scu02c; 351 352 ast_moutdwm(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY); 353 354 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); 355 if (!(jreg & 0x80)) { 356 u32 scu008; 357 358 /* Init SCU DVO Settings */ 359 360 scu008 = ast_mindwm(ast, AST_REG_SCU008); 361 scu008 &= 0xfffff8ff; 362 scu008 |= 0x00000500; /* delay phase */ 363 ast_moutdwm(ast, AST_REG_SCU008, scu008); 364 365 if (IS_AST_GEN4(ast)) { 366 u32 scu084, scu088, scu090; 367 368 scu084 = ast_mindwm(ast, AST_REG_SCU084); 369 scu084 |= 0xfffe0000; /* multi-pins for DVO single-edge */ 370 ast_moutdwm(ast, AST_REG_SCU084, scu084); 371 372 scu088 = ast_mindwm(ast, AST_REG_SCU088); 373 scu088 |= 0x000fffff; /* multi-pins for DVO single-edge */ 374 ast_moutdwm(ast, AST_REG_SCU088, scu088); 375 376 scu090 = ast_mindwm(ast, AST_REG_SCU090); 377 scu090 &= 0xffffffcf; 378 scu090 |= 0x00000020; /* multi-pins for DVO single-edge */ 379 ast_moutdwm(ast, AST_REG_SCU090, scu090); 380 } else { /* AST GEN5+ */ 381 u32 scu088, scu08c, scu0a4, scu0a8, scu094; 382 383 scu088 = ast_mindwm(ast, AST_REG_SCU088); 384 scu088 |= 0x30000000; /* multi-pins for DVO single-edge */ 385 ast_moutdwm(ast, AST_REG_SCU088, scu088); 386 387 scu08c = ast_mindwm(ast, AST_REG_SCU08C); 388 scu08c |= 0x000000cf; /* multi-pins for DVO single-edge */ 389 ast_moutdwm(ast, AST_REG_SCU08C, scu08c); 390 391 scu0a4 = ast_mindwm(ast, AST_REG_SCU0A4); 392 scu0a4 |= 0xffff0000; /* multi-pins for DVO single-edge */ 393 ast_moutdwm(ast, AST_REG_SCU0A4, scu0a4); 394 395 scu0a8 = ast_mindwm(ast, AST_REG_SCU0A8); 396 scu0a8 |= 0x0000000f; /* multi-pins for DVO single-edge */ 397 ast_moutdwm(ast, AST_REG_SCU0A8, scu0a8); 398 399 scu094 = ast_mindwm(ast, AST_REG_SCU094); 400 scu094 |= 0x00000002; /* multi-pins for DVO single-edge */ 401 ast_moutdwm(ast, AST_REG_SCU094, scu094); 402 } 403 } 404 405 /* Force to DVO */ 406 scu02c = ast_mindwm(ast, AST_REG_SCU02C); 407 scu02c &= 0xfffbffff; 408 ast_moutdwm(ast, AST_REG_SCU02C, scu02c); 409 410 /* Init VGA DVO Settings */ 411 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80); 412 return true; 413 } 414 415 416 static void ast_init_analog(struct ast_device *ast) 417 { 418 u32 scu02c; 419 420 /* 421 * Set DAC source to VGA mode in SCU2C via the P2A 422 * bridge. 423 */ 424 425 /* Unlock the SCU with the magic password */ 426 ast_moutdwm_poll(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY, 0x01); 427 428 /* Clear bits [17:16] of SCU2C */ 429 scu02c = ast_mindwm(ast, AST_REG_SCU02C); 430 scu02c &= 0xfffcffff; 431 ast_moutdwm(ast, AST_REG_SCU02C, scu02c); 432 433 /* Disable DVO */ 434 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x00); 435 } 436 437 void ast_init_3rdtx(struct ast_device *ast) 438 { 439 u8 vgacrd1; 440 441 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast)) { 442 vgacrd1 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 443 AST_IO_VGACRD1_TX_TYPE_MASK); 444 switch (vgacrd1) { 445 case AST_IO_VGACRD1_TX_SIL164_VBIOS: 446 ast_init_dvo(ast); 447 break; 448 case AST_IO_VGACRD1_TX_DP501_VBIOS: 449 ast_launch_m68k(ast); 450 break; 451 case AST_IO_VGACRD1_TX_FW_EMBEDDED_FW: 452 ast_init_dvo(ast); 453 break; 454 default: 455 if (ast->tx_chip == AST_TX_SIL164) 456 ast_init_dvo(ast); 457 else 458 ast_init_analog(ast); 459 } 460 } 461 } 462 463 /* 464 * Encoder 465 */ 466 467 static const struct drm_encoder_funcs ast_dp501_encoder_funcs = { 468 .destroy = drm_encoder_cleanup, 469 }; 470 471 static void ast_dp501_encoder_helper_atomic_enable(struct drm_encoder *encoder, 472 struct drm_atomic_commit *state) 473 { 474 struct ast_device *ast = to_ast_device(encoder->dev); 475 476 ast_set_dp501_video_output(ast, 1); 477 } 478 479 static void ast_dp501_encoder_helper_atomic_disable(struct drm_encoder *encoder, 480 struct drm_atomic_commit *state) 481 { 482 struct ast_device *ast = to_ast_device(encoder->dev); 483 484 ast_set_dp501_video_output(ast, 0); 485 } 486 487 static const struct drm_encoder_helper_funcs ast_dp501_encoder_helper_funcs = { 488 .atomic_enable = ast_dp501_encoder_helper_atomic_enable, 489 .atomic_disable = ast_dp501_encoder_helper_atomic_disable, 490 }; 491 492 /* 493 * Connector 494 */ 495 496 static int ast_dp501_connector_helper_get_modes(struct drm_connector *connector) 497 { 498 struct ast_connector *ast_connector = to_ast_connector(connector); 499 int count; 500 501 if (ast_connector->physical_status == connector_status_connected) { 502 struct ast_device *ast = to_ast_device(connector->dev); 503 const struct drm_edid *drm_edid; 504 505 drm_edid = drm_edid_read_custom(connector, ast_dp512_read_edid_block, ast); 506 drm_edid_connector_update(connector, drm_edid); 507 count = drm_edid_connector_add_modes(connector); 508 drm_edid_free(drm_edid); 509 } else { 510 drm_edid_connector_update(connector, NULL); 511 512 /* 513 * There's no EDID data without a connected monitor. Set BMC- 514 * compatible modes in this case. The XGA default resolution 515 * should work well for all BMCs. 516 */ 517 count = drm_add_modes_noedid(connector, 4096, 4096); 518 if (count) 519 drm_set_preferred_mode(connector, 1024, 768); 520 } 521 522 return count; 523 } 524 525 static int ast_dp501_connector_helper_detect_ctx(struct drm_connector *connector, 526 struct drm_modeset_acquire_ctx *ctx, 527 bool force) 528 { 529 struct ast_connector *ast_connector = to_ast_connector(connector); 530 struct ast_device *ast = to_ast_device(connector->dev); 531 enum drm_connector_status status = connector_status_disconnected; 532 533 if (ast_dp501_is_connected(ast)) 534 status = connector_status_connected; 535 536 if (status != ast_connector->physical_status) 537 ++connector->epoch_counter; 538 ast_connector->physical_status = status; 539 540 return connector_status_connected; 541 } 542 543 static const struct drm_connector_helper_funcs ast_dp501_connector_helper_funcs = { 544 .get_modes = ast_dp501_connector_helper_get_modes, 545 .detect_ctx = ast_dp501_connector_helper_detect_ctx, 546 }; 547 548 static const struct drm_connector_funcs ast_dp501_connector_funcs = { 549 .reset = drm_atomic_helper_connector_reset, 550 .fill_modes = drm_helper_probe_single_connector_modes, 551 .destroy = drm_connector_cleanup, 552 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 553 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 554 }; 555 556 /* 557 * Output 558 */ 559 560 int ast_dp501_output_init(struct ast_device *ast) 561 { 562 struct drm_device *dev = &ast->base; 563 struct drm_crtc *crtc = &ast->crtc; 564 struct drm_encoder *encoder; 565 struct ast_connector *ast_connector; 566 struct drm_connector *connector; 567 int ret; 568 569 /* encoder */ 570 571 encoder = &ast->output.dp501.encoder; 572 ret = drm_encoder_init(dev, encoder, &ast_dp501_encoder_funcs, 573 DRM_MODE_ENCODER_TMDS, NULL); 574 if (ret) 575 return ret; 576 drm_encoder_helper_add(encoder, &ast_dp501_encoder_helper_funcs); 577 578 encoder->possible_crtcs = drm_crtc_mask(crtc); 579 580 /* connector */ 581 582 ast_connector = &ast->output.dp501.connector; 583 connector = &ast_connector->base; 584 ret = drm_connector_init(dev, connector, &ast_dp501_connector_funcs, 585 DRM_MODE_CONNECTOR_DisplayPort); 586 if (ret) 587 return ret; 588 drm_connector_helper_add(connector, &ast_dp501_connector_helper_funcs); 589 590 connector->interlace_allowed = 0; 591 connector->doublescan_allowed = 0; 592 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 593 594 ast_connector->physical_status = connector->status; 595 596 ret = drm_connector_attach_encoder(connector, encoder); 597 if (ret) 598 return ret; 599 600 return 0; 601 } 602