1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2021, ASPEED Technology Inc. 3 // Authors: KuoHsiang Chou <kuohsiang_chou@aspeedtech.com> 4 5 #include <linux/firmware.h> 6 #include <linux/delay.h> 7 #include <drm/drm_print.h> 8 #include "ast_drv.h" 9 10 bool ast_astdp_is_connected(struct ast_device *ast) 11 { 12 if (!ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD1, ASTDP_MCU_FW_EXECUTING)) 13 return false; 14 if (!ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDF, ASTDP_HPD)) 15 return false; 16 if (!ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDC, ASTDP_LINK_SUCCESS)) 17 return false; 18 return true; 19 } 20 21 int ast_astdp_read_edid(struct drm_device *dev, u8 *ediddata) 22 { 23 struct ast_device *ast = to_ast_device(dev); 24 u8 i = 0, j = 0; 25 26 /* 27 * CRD1[b5]: DP MCU FW is executing 28 * CRDC[b0]: DP link success 29 * CRDF[b0]: DP HPD 30 * CRE5[b0]: Host reading EDID process is done 31 */ 32 if (!(ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD1, ASTDP_MCU_FW_EXECUTING) && 33 ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDC, ASTDP_LINK_SUCCESS) && 34 ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDF, ASTDP_HPD) && 35 ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xE5, 36 ASTDP_HOST_EDID_READ_DONE_MASK))) { 37 goto err_astdp_edid_not_ready; 38 } 39 40 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE5, (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK, 41 0x00); 42 43 for (i = 0; i < 32; i++) { 44 /* 45 * CRE4[7:0]: Read-Pointer for EDID (Unit: 4bytes); valid range: 0~64 46 */ 47 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE4, 48 ASTDP_AND_CLEAR_MASK, (u8)i); 49 j = 0; 50 51 /* 52 * CRD7[b0]: valid flag for EDID 53 * CRD6[b0]: mirror read pointer for EDID 54 */ 55 while ((ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD7, 56 ASTDP_EDID_VALID_FLAG_MASK) != 0x01) || 57 (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD6, 58 ASTDP_EDID_READ_POINTER_MASK) != i)) { 59 /* 60 * Delay are getting longer with each retry. 61 * 1. The Delays are often 2 loops when users request "Display Settings" 62 * of right-click of mouse. 63 * 2. The Delays are often longer a lot when system resume from S3/S4. 64 */ 65 mdelay(j+1); 66 67 if (!(ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD1, 68 ASTDP_MCU_FW_EXECUTING) && 69 ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDC, 70 ASTDP_LINK_SUCCESS) && 71 ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDF, ASTDP_HPD))) { 72 goto err_astdp_jump_out_loop_of_edid; 73 } 74 75 j++; 76 if (j > 200) 77 goto err_astdp_jump_out_loop_of_edid; 78 } 79 80 *(ediddata) = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 81 0xD8, ASTDP_EDID_READ_DATA_MASK); 82 *(ediddata + 1) = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD9, 83 ASTDP_EDID_READ_DATA_MASK); 84 *(ediddata + 2) = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDA, 85 ASTDP_EDID_READ_DATA_MASK); 86 *(ediddata + 3) = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDB, 87 ASTDP_EDID_READ_DATA_MASK); 88 89 if (i == 31) { 90 /* 91 * For 128-bytes EDID_1.3, 92 * 1. Add the value of Bytes-126 to Bytes-127. 93 * The Bytes-127 is Checksum. Sum of all 128bytes should 94 * equal 0 (mod 256). 95 * 2. Modify Bytes-126 to be 0. 96 * The Bytes-126 indicates the Number of extensions to 97 * follow. 0 represents noextensions. 98 */ 99 *(ediddata + 3) = *(ediddata + 3) + *(ediddata + 2); 100 *(ediddata + 2) = 0; 101 } 102 103 ediddata += 4; 104 } 105 106 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE5, (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK, 107 ASTDP_HOST_EDID_READ_DONE); 108 109 return 0; 110 111 err_astdp_jump_out_loop_of_edid: 112 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE5, 113 (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK, 114 ASTDP_HOST_EDID_READ_DONE); 115 return (~(j+256) + 1); 116 117 err_astdp_edid_not_ready: 118 if (!(ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD1, ASTDP_MCU_FW_EXECUTING))) 119 return (~0xD1 + 1); 120 if (!(ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDC, ASTDP_LINK_SUCCESS))) 121 return (~0xDC + 1); 122 if (!(ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDF, ASTDP_HPD))) 123 return (~0xDF + 1); 124 if (!(ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xE5, ASTDP_HOST_EDID_READ_DONE_MASK))) 125 return (~0xE5 + 1); 126 127 return 0; 128 } 129 130 /* 131 * Launch Aspeed DP 132 */ 133 void ast_dp_launch(struct drm_device *dev) 134 { 135 u32 i = 0; 136 u8 bDPExecute = 1; 137 struct ast_device *ast = to_ast_device(dev); 138 139 // Wait one second then timeout. 140 while (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD1, ASTDP_MCU_FW_EXECUTING) != 141 ASTDP_MCU_FW_EXECUTING) { 142 i++; 143 // wait 100 ms 144 msleep(100); 145 146 if (i >= 10) { 147 // DP would not be ready. 148 bDPExecute = 0; 149 break; 150 } 151 } 152 153 if (!bDPExecute) 154 drm_err(dev, "Wait DPMCU executing timeout\n"); 155 156 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE5, 157 (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK, 158 ASTDP_HOST_EDID_READ_DONE); 159 } 160 161 bool ast_dp_power_is_on(struct ast_device *ast) 162 { 163 u8 vgacre3; 164 165 vgacre3 = ast_get_index_reg(ast, AST_IO_VGACRI, 0xe3); 166 167 return !(vgacre3 & AST_DP_PHY_SLEEP); 168 } 169 170 void ast_dp_power_on_off(struct drm_device *dev, bool on) 171 { 172 struct ast_device *ast = to_ast_device(dev); 173 // Read and Turn off DP PHY sleep 174 u8 bE3 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xE3, AST_DP_VIDEO_ENABLE); 175 176 // Turn on DP PHY sleep 177 if (!on) 178 bE3 |= AST_DP_PHY_SLEEP; 179 180 // DP Power on/off 181 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE3, (u8) ~AST_DP_PHY_SLEEP, bE3); 182 } 183 184 185 186 void ast_dp_set_on_off(struct drm_device *dev, bool on) 187 { 188 struct ast_device *ast = to_ast_device(dev); 189 u8 video_on_off = on; 190 u32 i = 0; 191 192 // Video On/Off 193 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE3, (u8) ~AST_DP_VIDEO_ENABLE, on); 194 195 // If DP plug in and link successful then check video on / off status 196 if (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDC, ASTDP_LINK_SUCCESS) && 197 ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDF, ASTDP_HPD)) { 198 video_on_off <<= 4; 199 while (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDF, 200 ASTDP_MIRROR_VIDEO_ENABLE) != video_on_off) { 201 // wait 1 ms 202 mdelay(1); 203 if (++i > 200) 204 break; 205 } 206 } 207 } 208 209 void ast_dp_set_mode(struct drm_crtc *crtc, struct ast_vbios_mode_info *vbios_mode) 210 { 211 struct ast_device *ast = to_ast_device(crtc->dev); 212 213 u32 ulRefreshRateIndex; 214 u8 ModeIdx; 215 216 ulRefreshRateIndex = vbios_mode->enh_table->refresh_rate_index - 1; 217 218 switch (crtc->mode.crtc_hdisplay) { 219 case 320: 220 ModeIdx = ASTDP_320x240_60; 221 break; 222 case 400: 223 ModeIdx = ASTDP_400x300_60; 224 break; 225 case 512: 226 ModeIdx = ASTDP_512x384_60; 227 break; 228 case 640: 229 ModeIdx = (ASTDP_640x480_60 + (u8) ulRefreshRateIndex); 230 break; 231 case 800: 232 ModeIdx = (ASTDP_800x600_56 + (u8) ulRefreshRateIndex); 233 break; 234 case 1024: 235 ModeIdx = (ASTDP_1024x768_60 + (u8) ulRefreshRateIndex); 236 break; 237 case 1152: 238 ModeIdx = ASTDP_1152x864_75; 239 break; 240 case 1280: 241 if (crtc->mode.crtc_vdisplay == 800) 242 ModeIdx = (ASTDP_1280x800_60_RB - (u8) ulRefreshRateIndex); 243 else // 1024 244 ModeIdx = (ASTDP_1280x1024_60 + (u8) ulRefreshRateIndex); 245 break; 246 case 1360: 247 case 1366: 248 ModeIdx = ASTDP_1366x768_60; 249 break; 250 case 1440: 251 ModeIdx = (ASTDP_1440x900_60_RB - (u8) ulRefreshRateIndex); 252 break; 253 case 1600: 254 if (crtc->mode.crtc_vdisplay == 900) 255 ModeIdx = (ASTDP_1600x900_60_RB - (u8) ulRefreshRateIndex); 256 else //1200 257 ModeIdx = ASTDP_1600x1200_60; 258 break; 259 case 1680: 260 ModeIdx = (ASTDP_1680x1050_60_RB - (u8) ulRefreshRateIndex); 261 break; 262 case 1920: 263 if (crtc->mode.crtc_vdisplay == 1080) 264 ModeIdx = ASTDP_1920x1080_60; 265 else //1200 266 ModeIdx = ASTDP_1920x1200_60; 267 break; 268 default: 269 return; 270 } 271 272 /* 273 * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp) 274 * CRE1[7:0]: MISC1 (default: 0x00) 275 * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50) 276 */ 277 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE0, ASTDP_AND_CLEAR_MASK, 278 ASTDP_MISC0_24bpp); 279 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE1, ASTDP_AND_CLEAR_MASK, ASTDP_MISC1); 280 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE2, ASTDP_AND_CLEAR_MASK, ModeIdx); 281 } 282