1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2012 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/pci.h> 31 32 #include <drm/drm_drv.h> 33 34 #include "ast_drv.h" 35 #include "ast_post.h" 36 37 /* 38 * POST 39 */ 40 41 void ast_2000_set_def_ext_reg(struct ast_device *ast) 42 { 43 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff }; 44 u8 i, index, reg; 45 const u8 *ext_reg_info; 46 47 /* reset scratch */ 48 for (i = 0x81; i <= 0x9f; i++) 49 ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00); 50 51 ext_reg_info = extreginfo; 52 index = 0xa0; 53 while (*ext_reg_info != 0xff) { 54 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info); 55 index++; 56 ext_reg_info++; 57 } 58 59 /* disable standard IO/MEM decode if secondary */ 60 /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */ 61 62 /* Set Ext. Default */ 63 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01); 64 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00); 65 66 /* Enable RAMDAC for A1 */ 67 reg = 0x04; 68 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg); 69 } 70 71 static const struct ast_dramstruct ast2000_dram_table_data[] = { 72 AST_DRAMSTRUCT_REG(AST_REG_MCR108, 0x00000000), 73 AST_DRAMSTRUCT_REG(AST_REG_MCR120, 0x00004a21), 74 AST_DRAMSTRUCT_UDELAY(67u), 75 AST_DRAMSTRUCT_REG(AST_REG_MCR00, 0xffffffff), /* FIXME: This locks the MCR registers. */ 76 AST_DRAMSTRUCT_REG(AST_REG_MCR04, 0x00000089), /* DRAM type */ 77 AST_DRAMSTRUCT_REG(AST_REG_MCR08, 0x22331353), 78 AST_DRAMSTRUCT_REG(AST_REG_MCR0C, 0x0d07000b), 79 AST_DRAMSTRUCT_REG(AST_REG_MCR10, 0x11113333), 80 AST_DRAMSTRUCT_REG(AST_REG_MCR20, 0x00110350), 81 AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x1e0828f0), 82 AST_DRAMSTRUCT_REG(AST_REG_MCR24, 0x00000001), 83 AST_DRAMSTRUCT_REG(AST_REG_MCR1C, 0x00000000), 84 AST_DRAMSTRUCT_REG(AST_REG_MCR14, 0x00000003), 85 AST_DRAMSTRUCT_UDELAY(67u), 86 AST_DRAMSTRUCT_REG(AST_REG_MCR18, 0x00000131), 87 AST_DRAMSTRUCT_REG(AST_REG_MCR14, 0x00000001), 88 AST_DRAMSTRUCT_UDELAY(67u), 89 AST_DRAMSTRUCT_REG(AST_REG_MCR18, 0x00000031), 90 AST_DRAMSTRUCT_REG(AST_REG_MCR14, 0x00000001), 91 AST_DRAMSTRUCT_UDELAY(67u), 92 AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x1e0828f1), 93 AST_DRAMSTRUCT_REG(AST_REG_MCR24, 0x00000003), 94 AST_DRAMSTRUCT_REG(AST_REG_MCR2C, 0x1f0f28fb), 95 AST_DRAMSTRUCT_REG(AST_REG_MCR30, 0xfffffe01), 96 AST_DRAMSTRUCT_INVALID, 97 }; 98 99 static void ast_post_chip_2000(struct ast_device *ast) 100 { 101 u8 j; 102 u32 i; 103 104 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); 105 106 if ((j & 0x80) == 0) { /* VGA only */ 107 const struct ast_dramstruct *dram_reg_info = ast2000_dram_table_data; 108 u32 mcr140; 109 110 ast_moutdwm_poll(ast, AST_REG_MCR100, 0xa8, 0xa8); 111 112 while (!AST_DRAMSTRUCT_IS(dram_reg_info, INVALID)) { 113 if (AST_DRAMSTRUCT_IS(dram_reg_info, UDELAY)) { 114 for (i = 0; i < 15; i++) 115 udelay(dram_reg_info->data); 116 } else { 117 ast_moutdwm(ast, dram_reg_info->index, dram_reg_info->data); 118 } 119 dram_reg_info++; 120 } 121 122 mcr140 = ast_mindwm(ast, AST_REG_MCR140); 123 mcr140 |= 0x00000040; 124 ast_moutdwm(ast, AST_REG_MCR140, mcr140); 125 } 126 127 /* wait ready */ 128 do { 129 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); 130 } while ((j & 0x40) == 0); 131 } 132 133 int ast_2000_post(struct ast_device *ast) 134 { 135 ast_2000_set_def_ext_reg(ast); 136 137 if (ast->config_mode == ast_use_p2a) { 138 ast_post_chip_2000(ast); 139 } else { 140 if (ast->tx_chip == AST_TX_SIL164) { 141 /* Enable DVO */ 142 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80); 143 } 144 } 145 146 return 0; 147 } 148 149 /* 150 * Mode setting 151 */ 152 153 const struct ast_vbios_dclk_info ast_2000_dclk_table[] = { 154 {0x2c, 0xe7, 0x03}, /* 00: VCLK25_175 */ 155 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ 156 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ 157 {0x76, 0x63, 0x01}, /* 03: VCLK36 */ 158 {0xee, 0x67, 0x01}, /* 04: VCLK40 */ 159 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ 160 {0xc6, 0x64, 0x01}, /* 06: VCLK50 */ 161 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ 162 {0x80, 0x64, 0x00}, /* 08: VCLK65 */ 163 {0x7b, 0x63, 0x00}, /* 09: VCLK75 */ 164 {0x67, 0x62, 0x00}, /* 0a: VCLK78_75 */ 165 {0x7c, 0x62, 0x00}, /* 0b: VCLK94_5 */ 166 {0x8e, 0x62, 0x00}, /* 0c: VCLK108 */ 167 {0x85, 0x24, 0x00}, /* 0d: VCLK135 */ 168 {0x67, 0x22, 0x00}, /* 0e: VCLK157_5 */ 169 {0x6a, 0x22, 0x00}, /* 0f: VCLK162 */ 170 {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ 171 {0x68, 0x6f, 0x80}, /* 11: VCLK83.5 */ 172 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ 173 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ 174 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ 175 {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ 176 {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ 177 {0x77, 0x58, 0x80}, /* 17: VCLK119 */ 178 {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ 179 {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */ 180 {0x3b, 0x2c, 0x81}, /* 1a: VCLK118_25 */ 181 }; 182 183 /* 184 * Device initialization 185 */ 186 187 void ast_2000_detect_tx_chip(struct ast_device *ast, bool need_post) 188 { 189 enum ast_tx_chip tx_chip = AST_TX_NONE; 190 u8 vgacra3; 191 192 /* 193 * VGACRA3 Enhanced Color Mode Register, check if DVO is already 194 * enabled, in that case, assume we have a SIL164 TMDS transmitter 195 * 196 * Don't make that assumption if we the chip wasn't enabled and 197 * is at power-on reset, otherwise we'll incorrectly "detect" a 198 * SIL164 when there is none. 199 */ 200 if (!need_post) { 201 vgacra3 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff); 202 if (vgacra3 & AST_IO_VGACRA3_DVO_ENABLED) 203 tx_chip = AST_TX_SIL164; 204 } 205 206 __ast_device_set_tx_chip(ast, tx_chip); 207 } 208 209 static const struct ast_device_quirks ast_2000_device_quirks = { 210 .crtc_mem_req_threshold_low = 31, 211 .crtc_mem_req_threshold_high = 47, 212 }; 213 214 struct drm_device *ast_2000_device_create(struct pci_dev *pdev, 215 const struct drm_driver *drv, 216 enum ast_chip chip, 217 enum ast_config_mode config_mode, 218 void __iomem *regs, 219 void __iomem *ioregs, 220 bool need_post) 221 { 222 struct drm_device *dev; 223 struct ast_device *ast; 224 int ret; 225 226 ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_device, base); 227 if (IS_ERR(ast)) 228 return ERR_CAST(ast); 229 dev = &ast->base; 230 231 ast_device_init(ast, chip, config_mode, regs, ioregs, &ast_2000_device_quirks); 232 233 ast->dclk_table = ast_2000_dclk_table; 234 235 ast_2000_detect_tx_chip(ast, need_post); 236 237 if (need_post) { 238 ret = ast_post_gpu(ast); 239 if (ret) 240 return ERR_PTR(ret); 241 } 242 243 ret = ast_mm_init(ast); 244 if (ret) 245 return ERR_PTR(ret); 246 247 ret = ast_mode_config_init(ast); 248 if (ret) 249 return ERR_PTR(ret); 250 251 return dev; 252 } 253