1 /* 2 * Copyright (C) 2012 Russell King 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Armada 510 (aka Dove) variant support 9 */ 10 #include <linux/clk.h> 11 #include <linux/io.h> 12 #include <drm/drm_probe_helper.h> 13 #include "armada_crtc.h" 14 #include "armada_drm.h" 15 #include "armada_hw.h" 16 17 static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev) 18 { 19 struct clk *clk; 20 21 clk = devm_clk_get(dev, "ext_ref_clk1"); 22 if (IS_ERR(clk)) 23 return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER : PTR_ERR(clk); 24 25 dcrtc->extclk[0] = clk; 26 27 /* 28 * Lower the watermark so to eliminate jitter at higher bandwidths. 29 * Disable SRAM read wait state to avoid system hang with external 30 * clock. 31 */ 32 armada_updatel(CFG_DMA_WM(0x20), CFG_SRAM_WAIT | CFG_DMA_WM_MASK, 33 dcrtc->base + LCD_CFG_RDREG4F); 34 35 /* Initialise SPU register */ 36 writel_relaxed(ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND, 37 dcrtc->base + LCD_SPU_ADV_REG); 38 39 return 0; 40 } 41 42 /* 43 * Armada510 specific SCLK register selection. 44 * This gets called with sclk = NULL to test whether the mode is 45 * supportable, and again with sclk != NULL to set the clocks up for 46 * that. The former can return an error, but the latter is expected 47 * not to. 48 * 49 * We currently are pretty rudimentary here, always selecting 50 * EXT_REF_CLK_1 for LCD0 and erroring LCD1. This needs improvement! 51 */ 52 static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc, 53 const struct drm_display_mode *mode, uint32_t *sclk) 54 { 55 struct clk *clk = dcrtc->extclk[0]; 56 int ret; 57 58 if (dcrtc->num == 1) 59 return -EINVAL; 60 61 if (IS_ERR(clk)) 62 return PTR_ERR(clk); 63 64 if (dcrtc->clk != clk) { 65 ret = clk_prepare_enable(clk); 66 if (ret) 67 return ret; 68 dcrtc->clk = clk; 69 } 70 71 if (sclk) { 72 uint32_t rate, ref, div; 73 74 rate = mode->clock * 1000; 75 ref = clk_round_rate(clk, rate); 76 div = DIV_ROUND_UP(ref, rate); 77 if (div < 1) 78 div = 1; 79 80 clk_set_rate(clk, ref); 81 *sclk = div | SCLK_510_EXTCLK1; 82 } 83 84 return 0; 85 } 86 87 static void armada510_crtc_disable(struct armada_crtc *dcrtc) 88 { 89 if (!IS_ERR(dcrtc->clk)) { 90 clk_disable_unprepare(dcrtc->clk); 91 dcrtc->clk = ERR_PTR(-EINVAL); 92 } 93 } 94 95 static void armada510_crtc_enable(struct armada_crtc *dcrtc, 96 const struct drm_display_mode *mode) 97 { 98 if (IS_ERR(dcrtc->clk)) { 99 dcrtc->clk = dcrtc->extclk[0]; 100 WARN_ON(clk_prepare_enable(dcrtc->clk)); 101 } 102 } 103 104 const struct armada_variant armada510_ops = { 105 .has_spu_adv_reg = true, 106 .init = armada510_crtc_init, 107 .compute_clock = armada510_crtc_compute_clock, 108 .disable = armada510_crtc_disable, 109 .enable = armada510_crtc_enable, 110 }; 111