196f60e37SRussell King /* 296f60e37SRussell King * Copyright (C) 2012 Russell King 396f60e37SRussell King * 496f60e37SRussell King * This program is free software; you can redistribute it and/or modify 596f60e37SRussell King * it under the terms of the GNU General Public License version 2 as 696f60e37SRussell King * published by the Free Software Foundation. 796f60e37SRussell King * 896f60e37SRussell King * Armada 510 (aka Dove) variant support 996f60e37SRussell King */ 1096f60e37SRussell King #include <linux/clk.h> 1196f60e37SRussell King #include <linux/io.h> 12fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 1396f60e37SRussell King #include "armada_crtc.h" 1496f60e37SRussell King #include "armada_drm.h" 1596f60e37SRussell King #include "armada_hw.h" 1696f60e37SRussell King 173ecea269SRussell King static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev) 1896f60e37SRussell King { 193ecea269SRussell King struct clk *clk; 2096f60e37SRussell King 21fe424872SRussell King clk = devm_clk_get(dev, "ext_ref_clk1"); 223ecea269SRussell King if (IS_ERR(clk)) 233ecea269SRussell King return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER : PTR_ERR(clk); 2496f60e37SRussell King 253ecea269SRussell King dcrtc->extclk[0] = clk; 2696f60e37SRussell King 27*5a6cbce8SRussell King /* 28*5a6cbce8SRussell King * Lower the watermark so to eliminate jitter at higher bandwidths. 29*5a6cbce8SRussell King * Disable SRAM read wait state to avoid system hang with external 30*5a6cbce8SRussell King * clock. 31*5a6cbce8SRussell King */ 32*5a6cbce8SRussell King armada_updatel(CFG_DMA_WM(0x20), CFG_SRAM_WAIT | CFG_DMA_WM_MASK, 33*5a6cbce8SRussell King dcrtc->base + LCD_CFG_RDREG4F); 343ecea269SRussell King 354e4b3563SRussell King /* Initialise SPU register */ 364e4b3563SRussell King writel_relaxed(ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND, 374e4b3563SRussell King dcrtc->base + LCD_SPU_ADV_REG); 384e4b3563SRussell King 3996f60e37SRussell King return 0; 4096f60e37SRussell King } 4196f60e37SRussell King 4296f60e37SRussell King /* 4396f60e37SRussell King * Armada510 specific SCLK register selection. 4496f60e37SRussell King * This gets called with sclk = NULL to test whether the mode is 4596f60e37SRussell King * supportable, and again with sclk != NULL to set the clocks up for 4696f60e37SRussell King * that. The former can return an error, but the latter is expected 4796f60e37SRussell King * not to. 4896f60e37SRussell King * 4996f60e37SRussell King * We currently are pretty rudimentary here, always selecting 5096f60e37SRussell King * EXT_REF_CLK_1 for LCD0 and erroring LCD1. This needs improvement! 5196f60e37SRussell King */ 5296f60e37SRussell King static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc, 5396f60e37SRussell King const struct drm_display_mode *mode, uint32_t *sclk) 5496f60e37SRussell King { 553ecea269SRussell King struct clk *clk = dcrtc->extclk[0]; 5696f60e37SRussell King int ret; 5796f60e37SRussell King 5896f60e37SRussell King if (dcrtc->num == 1) 5996f60e37SRussell King return -EINVAL; 6096f60e37SRussell King 6196f60e37SRussell King if (IS_ERR(clk)) 6296f60e37SRussell King return PTR_ERR(clk); 6396f60e37SRussell King 6496f60e37SRussell King if (dcrtc->clk != clk) { 6596f60e37SRussell King ret = clk_prepare_enable(clk); 6696f60e37SRussell King if (ret) 6796f60e37SRussell King return ret; 6896f60e37SRussell King dcrtc->clk = clk; 6996f60e37SRussell King } 7096f60e37SRussell King 7196f60e37SRussell King if (sclk) { 7296f60e37SRussell King uint32_t rate, ref, div; 7396f60e37SRussell King 7496f60e37SRussell King rate = mode->clock * 1000; 7596f60e37SRussell King ref = clk_round_rate(clk, rate); 7696f60e37SRussell King div = DIV_ROUND_UP(ref, rate); 7796f60e37SRussell King if (div < 1) 7896f60e37SRussell King div = 1; 7996f60e37SRussell King 8096f60e37SRussell King clk_set_rate(clk, ref); 8196f60e37SRussell King *sclk = div | SCLK_510_EXTCLK1; 8296f60e37SRussell King } 8396f60e37SRussell King 8496f60e37SRussell King return 0; 8596f60e37SRussell King } 8696f60e37SRussell King 87a0fbb35eSRussell King static void armada510_crtc_disable(struct armada_crtc *dcrtc) 88a0fbb35eSRussell King { 89a0fbb35eSRussell King if (!IS_ERR(dcrtc->clk)) { 90a0fbb35eSRussell King clk_disable_unprepare(dcrtc->clk); 91a0fbb35eSRussell King dcrtc->clk = ERR_PTR(-EINVAL); 92a0fbb35eSRussell King } 93a0fbb35eSRussell King } 94a0fbb35eSRussell King 95a0fbb35eSRussell King static void armada510_crtc_enable(struct armada_crtc *dcrtc, 96a0fbb35eSRussell King const struct drm_display_mode *mode) 97a0fbb35eSRussell King { 98a0fbb35eSRussell King if (IS_ERR(dcrtc->clk)) { 99a0fbb35eSRussell King dcrtc->clk = dcrtc->extclk[0]; 100a0fbb35eSRussell King WARN_ON(clk_prepare_enable(dcrtc->clk)); 101a0fbb35eSRussell King } 102a0fbb35eSRussell King } 103a0fbb35eSRussell King 10496f60e37SRussell King const struct armada_variant armada510_ops = { 10596f60e37SRussell King .has_spu_adv_reg = true, 10642e62ba7SRussell King .init = armada510_crtc_init, 10742e62ba7SRussell King .compute_clock = armada510_crtc_compute_clock, 108a0fbb35eSRussell King .disable = armada510_crtc_disable, 109a0fbb35eSRussell King .enable = armada510_crtc_enable, 11096f60e37SRussell King }; 111