xref: /linux/drivers/gpu/drm/arm/malidp_mw.c (revision db5d28c0bfe566908719bec8e25443aabecbb802)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
4  * Author: Brian Starkey <brian.starkey@arm.com>
5  *
6  * ARM Mali DP Writeback connector implementation
7  */
8 
9 #include <drm/drm_atomic.h>
10 #include <drm/drm_atomic_helper.h>
11 #include <drm/drm_crtc.h>
12 #include <drm/drm_edid.h>
13 #include <drm/drm_fb_dma_helper.h>
14 #include <drm/drm_fourcc.h>
15 #include <drm/drm_framebuffer.h>
16 #include <drm/drm_gem_dma_helper.h>
17 #include <drm/drm_probe_helper.h>
18 #include <drm/drm_writeback.h>
19 
20 #include "malidp_drv.h"
21 #include "malidp_hw.h"
22 #include "malidp_mw.h"
23 
24 #define to_mw_state(_state) (struct malidp_mw_connector_state *)(_state)
25 
26 struct malidp_mw_connector_state {
27 	struct drm_connector_state base;
28 	dma_addr_t addrs[2];
29 	s32 pitches[2];
30 	u8 format;
31 	u8 n_planes;
32 	bool rgb2yuv_initialized;
33 	const s16 *rgb2yuv_coeffs;
34 };
35 
malidp_mw_connector_get_modes(struct drm_connector * connector)36 static int malidp_mw_connector_get_modes(struct drm_connector *connector)
37 {
38 	struct drm_device *dev = connector->dev;
39 
40 	return drm_add_modes_noedid(connector, dev->mode_config.max_width,
41 				    dev->mode_config.max_height);
42 }
43 
44 static enum drm_mode_status
malidp_mw_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)45 malidp_mw_connector_mode_valid(struct drm_connector *connector,
46 			       struct drm_display_mode *mode)
47 {
48 	struct drm_device *dev = connector->dev;
49 	struct drm_mode_config *mode_config = &dev->mode_config;
50 	int w = mode->hdisplay, h = mode->vdisplay;
51 
52 	if ((w < mode_config->min_width) || (w > mode_config->max_width))
53 		return MODE_BAD_HVALUE;
54 
55 	if ((h < mode_config->min_height) || (h > mode_config->max_height))
56 		return MODE_BAD_VVALUE;
57 
58 	return MODE_OK;
59 }
60 
61 static const struct drm_connector_helper_funcs malidp_mw_connector_helper_funcs = {
62 	.get_modes = malidp_mw_connector_get_modes,
63 	.mode_valid = malidp_mw_connector_mode_valid,
64 };
65 
malidp_mw_connector_reset(struct drm_connector * connector)66 static void malidp_mw_connector_reset(struct drm_connector *connector)
67 {
68 	struct malidp_mw_connector_state *mw_state =
69 		kzalloc(sizeof(*mw_state), GFP_KERNEL);
70 
71 	if (connector->state)
72 		__drm_atomic_helper_connector_destroy_state(connector->state);
73 
74 	kfree(connector->state);
75 	connector->state = NULL;
76 
77 	if (mw_state)
78 		__drm_atomic_helper_connector_reset(connector, &mw_state->base);
79 }
80 
81 static enum drm_connector_status
malidp_mw_connector_detect(struct drm_connector * connector,bool force)82 malidp_mw_connector_detect(struct drm_connector *connector, bool force)
83 {
84 	return connector_status_connected;
85 }
86 
malidp_mw_connector_destroy(struct drm_connector * connector)87 static void malidp_mw_connector_destroy(struct drm_connector *connector)
88 {
89 	drm_connector_cleanup(connector);
90 }
91 
92 static struct drm_connector_state *
malidp_mw_connector_duplicate_state(struct drm_connector * connector)93 malidp_mw_connector_duplicate_state(struct drm_connector *connector)
94 {
95 	struct malidp_mw_connector_state *mw_state, *mw_current_state;
96 
97 	if (WARN_ON(!connector->state))
98 		return NULL;
99 
100 	mw_state = kzalloc(sizeof(*mw_state), GFP_KERNEL);
101 	if (!mw_state)
102 		return NULL;
103 
104 	mw_current_state = to_mw_state(connector->state);
105 	mw_state->rgb2yuv_coeffs = mw_current_state->rgb2yuv_coeffs;
106 	mw_state->rgb2yuv_initialized = mw_current_state->rgb2yuv_initialized;
107 
108 	__drm_atomic_helper_connector_duplicate_state(connector, &mw_state->base);
109 
110 	return &mw_state->base;
111 }
112 
113 static const struct drm_connector_funcs malidp_mw_connector_funcs = {
114 	.reset = malidp_mw_connector_reset,
115 	.detect = malidp_mw_connector_detect,
116 	.fill_modes = drm_helper_probe_single_connector_modes,
117 	.destroy = malidp_mw_connector_destroy,
118 	.atomic_duplicate_state = malidp_mw_connector_duplicate_state,
119 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
120 };
121 
122 static const s16 rgb2yuv_coeffs_bt709_limited[MALIDP_COLORADJ_NUM_COEFFS] = {
123 	47,  157,   16,
124 	-26,  -87,  112,
125 	112, -102,  -10,
126 	16,  128,  128
127 };
128 
129 static int
malidp_mw_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)130 malidp_mw_encoder_atomic_check(struct drm_encoder *encoder,
131 			       struct drm_crtc_state *crtc_state,
132 			       struct drm_connector_state *conn_state)
133 {
134 	struct malidp_mw_connector_state *mw_state = to_mw_state(conn_state);
135 	struct malidp_drm *malidp = drm_to_malidp(encoder->dev);
136 	struct drm_framebuffer *fb;
137 	int i, n_planes;
138 
139 	if (!conn_state->writeback_job)
140 		return 0;
141 
142 	fb = conn_state->writeback_job->fb;
143 	if ((fb->width != crtc_state->mode.hdisplay) ||
144 	    (fb->height != crtc_state->mode.vdisplay)) {
145 		DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n",
146 				fb->width, fb->height);
147 		return -EINVAL;
148 	}
149 
150 	if (fb->modifier) {
151 		DRM_DEBUG_KMS("Writeback framebuffer does not support modifiers\n");
152 		return -EINVAL;
153 	}
154 
155 	mw_state->format =
156 		malidp_hw_get_format_id(&malidp->dev->hw->map, SE_MEMWRITE,
157 					fb->format->format, !!fb->modifier);
158 	if (mw_state->format == MALIDP_INVALID_FORMAT_ID) {
159 		DRM_DEBUG_KMS("Invalid pixel format %p4cc\n",
160 			      &fb->format->format);
161 		return -EINVAL;
162 	}
163 
164 	n_planes = fb->format->num_planes;
165 	for (i = 0; i < n_planes; i++) {
166 		struct drm_gem_dma_object *obj = drm_fb_dma_get_gem_obj(fb, i);
167 		/* memory write buffers are never rotated */
168 		u8 alignment = malidp_hw_get_pitch_align(malidp->dev, 0);
169 
170 		if (fb->pitches[i] & (alignment - 1)) {
171 			DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n",
172 				      fb->pitches[i], i);
173 			return -EINVAL;
174 		}
175 		mw_state->pitches[i] = fb->pitches[i];
176 		mw_state->addrs[i] = obj->dma_addr + fb->offsets[i];
177 	}
178 	mw_state->n_planes = n_planes;
179 
180 	if (fb->format->is_yuv)
181 		mw_state->rgb2yuv_coeffs = rgb2yuv_coeffs_bt709_limited;
182 
183 	return 0;
184 }
185 
186 static const struct drm_encoder_helper_funcs malidp_mw_encoder_helper_funcs = {
187 	.atomic_check = malidp_mw_encoder_atomic_check,
188 };
189 
get_writeback_formats(struct malidp_drm * malidp,int * n_formats)190 static u32 *get_writeback_formats(struct malidp_drm *malidp, int *n_formats)
191 {
192 	const struct malidp_hw_regmap *map = &malidp->dev->hw->map;
193 	u32 *formats;
194 	int n, i;
195 
196 	formats = kcalloc(map->n_pixel_formats, sizeof(*formats),
197 			  GFP_KERNEL);
198 	if (!formats)
199 		return NULL;
200 
201 	for (n = 0, i = 0;  i < map->n_pixel_formats; i++) {
202 		if (map->pixel_formats[i].layer & SE_MEMWRITE)
203 			formats[n++] = map->pixel_formats[i].format;
204 	}
205 
206 	*n_formats = n;
207 
208 	return formats;
209 }
210 
malidp_mw_connector_init(struct drm_device * drm)211 int malidp_mw_connector_init(struct drm_device *drm)
212 {
213 	struct malidp_drm *malidp = drm_to_malidp(drm);
214 	u32 *formats;
215 	int ret, n_formats;
216 
217 	if (!malidp->dev->hw->enable_memwrite)
218 		return 0;
219 
220 	drm_connector_helper_add(&malidp->mw_connector.base,
221 				 &malidp_mw_connector_helper_funcs);
222 
223 	formats = get_writeback_formats(malidp, &n_formats);
224 	if (!formats)
225 		return -ENOMEM;
226 
227 	ret = drm_writeback_connector_init(drm, &malidp->mw_connector,
228 					   &malidp_mw_connector_funcs,
229 					   &malidp_mw_encoder_helper_funcs,
230 					   formats, n_formats,
231 					   1 << drm_crtc_index(&malidp->crtc));
232 	kfree(formats);
233 	if (ret)
234 		return ret;
235 
236 	return 0;
237 }
238 
malidp_mw_atomic_commit(struct drm_device * drm,struct drm_atomic_state * old_state)239 void malidp_mw_atomic_commit(struct drm_device *drm,
240 			     struct drm_atomic_state *old_state)
241 {
242 	struct malidp_drm *malidp = drm_to_malidp(drm);
243 	struct drm_writeback_connector *mw_conn = &malidp->mw_connector;
244 	struct drm_connector_state *conn_state = mw_conn->base.state;
245 	struct malidp_hw_device *hwdev = malidp->dev;
246 	struct malidp_mw_connector_state *mw_state;
247 
248 	if (!conn_state)
249 		return;
250 
251 	mw_state = to_mw_state(conn_state);
252 
253 	if (conn_state->writeback_job) {
254 		struct drm_framebuffer *fb = conn_state->writeback_job->fb;
255 
256 		DRM_DEV_DEBUG_DRIVER(drm->dev,
257 				     "Enable memwrite %ux%u:%d %pad fmt: %u\n",
258 				     fb->width, fb->height,
259 				     mw_state->pitches[0],
260 				     &mw_state->addrs[0],
261 				     mw_state->format);
262 
263 		drm_writeback_queue_job(mw_conn, conn_state);
264 		hwdev->hw->enable_memwrite(hwdev, mw_state->addrs,
265 					   mw_state->pitches, mw_state->n_planes,
266 					   fb->width, fb->height, mw_state->format,
267 					   !mw_state->rgb2yuv_initialized ?
268 					   mw_state->rgb2yuv_coeffs : NULL);
269 		mw_state->rgb2yuv_initialized = !!mw_state->rgb2yuv_coeffs;
270 	} else {
271 		DRM_DEV_DEBUG_DRIVER(drm->dev, "Disable memwrite\n");
272 		hwdev->hw->disable_memwrite(hwdev);
273 	}
274 }
275