1 /* 2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This program is free software and is provided to you under the terms of the 6 * GNU General Public License version 2 as published by the Free Software 7 * Foundation, and any use by you of this program is subject to the terms 8 * of such GNU licence. 9 * 10 * ARM Mali DP500/DP550/DP650 hardware manipulation routines. This is where 11 * the difference between various versions of the hardware is being dealt with 12 * in an attempt to provide to the rest of the driver code a unified view 13 */ 14 15 #include <linux/types.h> 16 #include <linux/io.h> 17 #include <drm/drmP.h> 18 #include <video/videomode.h> 19 #include <video/display_timing.h> 20 21 #include "malidp_drv.h" 22 #include "malidp_hw.h" 23 24 static const struct malidp_input_format malidp500_de_formats[] = { 25 /* fourcc, layers supporting the format, internal id */ 26 { DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 0 }, 27 { DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 1 }, 28 { DRM_FORMAT_ARGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 2 }, 29 { DRM_FORMAT_ABGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 3 }, 30 { DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 4 }, 31 { DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 5 }, 32 { DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 6 }, 33 { DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 7 }, 34 { DRM_FORMAT_RGBA5551, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 8 }, 35 { DRM_FORMAT_ABGR1555, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 9 }, 36 { DRM_FORMAT_RGB565, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 10 }, 37 { DRM_FORMAT_BGR565, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 11 }, 38 { DRM_FORMAT_UYVY, DE_VIDEO1, 12 }, 39 { DRM_FORMAT_YUYV, DE_VIDEO1, 13 }, 40 { DRM_FORMAT_NV12, DE_VIDEO1, 14 }, 41 { DRM_FORMAT_YUV420, DE_VIDEO1, 15 }, 42 }; 43 44 #define MALIDP_ID(__group, __format) \ 45 ((((__group) & 0x7) << 3) | ((__format) & 0x7)) 46 47 #define MALIDP_COMMON_FORMATS \ 48 /* fourcc, layers supporting the format, internal id */ \ 49 { DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 0) }, \ 50 { DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 1) }, \ 51 { DRM_FORMAT_RGBA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 2) }, \ 52 { DRM_FORMAT_BGRA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 3) }, \ 53 { DRM_FORMAT_ARGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 0) }, \ 54 { DRM_FORMAT_ABGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 1) }, \ 55 { DRM_FORMAT_RGBA8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 2) }, \ 56 { DRM_FORMAT_BGRA8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 3) }, \ 57 { DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 0) }, \ 58 { DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 1) }, \ 59 { DRM_FORMAT_RGBX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 2) }, \ 60 { DRM_FORMAT_BGRX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 3) }, \ 61 { DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(3, 0) }, \ 62 { DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(3, 1) }, \ 63 { DRM_FORMAT_RGBA5551, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 0) }, \ 64 { DRM_FORMAT_ABGR1555, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 1) }, \ 65 { DRM_FORMAT_RGB565, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 2) }, \ 66 { DRM_FORMAT_BGR565, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 3) }, \ 67 { DRM_FORMAT_YUYV, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 2) }, \ 68 { DRM_FORMAT_UYVY, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 3) }, \ 69 { DRM_FORMAT_NV12, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 6) }, \ 70 { DRM_FORMAT_YUV420, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 7) } 71 72 static const struct malidp_input_format malidp550_de_formats[] = { 73 MALIDP_COMMON_FORMATS, 74 }; 75 76 static const struct malidp_layer malidp500_layers[] = { 77 { DE_VIDEO1, MALIDP500_DE_LV_BASE, MALIDP500_DE_LV_PTR_BASE }, 78 { DE_GRAPHICS1, MALIDP500_DE_LG1_BASE, MALIDP500_DE_LG1_PTR_BASE }, 79 { DE_GRAPHICS2, MALIDP500_DE_LG2_BASE, MALIDP500_DE_LG2_PTR_BASE }, 80 }; 81 82 static const struct malidp_layer malidp550_layers[] = { 83 { DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE }, 84 { DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE }, 85 { DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE }, 86 { DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE }, 87 }; 88 89 #define MALIDP_DE_DEFAULT_PREFETCH_START 5 90 91 static int malidp500_query_hw(struct malidp_hw_device *hwdev) 92 { 93 u32 conf = malidp_hw_read(hwdev, MALIDP500_CONFIG_ID); 94 /* bit 4 of the CONFIG_ID register holds the line size multiplier */ 95 u8 ln_size_mult = conf & 0x10 ? 2 : 1; 96 97 hwdev->min_line_size = 2; 98 hwdev->max_line_size = SZ_2K * ln_size_mult; 99 hwdev->rotation_memory[0] = SZ_1K * 64 * ln_size_mult; 100 hwdev->rotation_memory[1] = 0; /* no second rotation memory bank */ 101 102 return 0; 103 } 104 105 static void malidp500_enter_config_mode(struct malidp_hw_device *hwdev) 106 { 107 u32 status, count = 100; 108 109 malidp_hw_setbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL); 110 while (count) { 111 status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS); 112 if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ) 113 break; 114 /* 115 * entering config mode can take as long as the rendering 116 * of a full frame, hence the long sleep here 117 */ 118 usleep_range(1000, 10000); 119 count--; 120 } 121 WARN(count == 0, "timeout while entering config mode"); 122 } 123 124 static void malidp500_leave_config_mode(struct malidp_hw_device *hwdev) 125 { 126 u32 status, count = 100; 127 128 malidp_hw_clearbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL); 129 while (count) { 130 status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS); 131 if ((status & MALIDP500_DC_CONFIG_REQ) == 0) 132 break; 133 usleep_range(100, 1000); 134 count--; 135 } 136 WARN(count == 0, "timeout while leaving config mode"); 137 } 138 139 static bool malidp500_in_config_mode(struct malidp_hw_device *hwdev) 140 { 141 u32 status; 142 143 status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS); 144 if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ) 145 return true; 146 147 return false; 148 } 149 150 static void malidp500_set_config_valid(struct malidp_hw_device *hwdev) 151 { 152 malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID); 153 } 154 155 static void malidp500_modeset(struct malidp_hw_device *hwdev, struct videomode *mode) 156 { 157 u32 val = 0; 158 159 malidp_hw_clearbits(hwdev, MALIDP500_DC_CLEAR_MASK, MALIDP500_DC_CONTROL); 160 if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH) 161 val |= MALIDP500_HSYNCPOL; 162 if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH) 163 val |= MALIDP500_VSYNCPOL; 164 val |= MALIDP_DE_DEFAULT_PREFETCH_START; 165 malidp_hw_setbits(hwdev, val, MALIDP500_DC_CONTROL); 166 167 /* 168 * Mali-DP500 encodes the background color like this: 169 * - red @ MALIDP500_BGND_COLOR[12:0] 170 * - green @ MALIDP500_BGND_COLOR[27:16] 171 * - blue @ (MALIDP500_BGND_COLOR + 4)[12:0] 172 */ 173 val = ((MALIDP_BGND_COLOR_G & 0xfff) << 16) | 174 (MALIDP_BGND_COLOR_R & 0xfff); 175 malidp_hw_write(hwdev, val, MALIDP500_BGND_COLOR); 176 malidp_hw_write(hwdev, MALIDP_BGND_COLOR_B, MALIDP500_BGND_COLOR + 4); 177 178 val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) | 179 MALIDP_DE_H_BACKPORCH(mode->hback_porch); 180 malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_H_TIMINGS); 181 182 val = MALIDP500_DE_V_FRONTPORCH(mode->vfront_porch) | 183 MALIDP_DE_V_BACKPORCH(mode->vback_porch); 184 malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_V_TIMINGS); 185 186 val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) | 187 MALIDP_DE_V_SYNCWIDTH(mode->vsync_len); 188 malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH); 189 190 val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive); 191 malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE); 192 193 if (mode->flags & DISPLAY_FLAGS_INTERLACED) 194 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC); 195 else 196 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC); 197 } 198 199 static int malidp500_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt) 200 { 201 /* RGB888 or BGR888 can't be rotated */ 202 if ((fmt == DRM_FORMAT_RGB888) || (fmt == DRM_FORMAT_BGR888)) 203 return -EINVAL; 204 205 /* 206 * Each layer needs enough rotation memory to fit 8 lines 207 * worth of pixel data. Required size is then: 208 * size = rotated_width * (bpp / 8) * 8; 209 */ 210 return w * drm_format_plane_cpp(fmt, 0) * 8; 211 } 212 213 static int malidp550_query_hw(struct malidp_hw_device *hwdev) 214 { 215 u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID); 216 u8 ln_size = (conf >> 4) & 0x3, rsize; 217 218 hwdev->min_line_size = 2; 219 220 switch (ln_size) { 221 case 0: 222 hwdev->max_line_size = SZ_2K; 223 /* two banks of 64KB for rotation memory */ 224 rsize = 64; 225 break; 226 case 1: 227 hwdev->max_line_size = SZ_4K; 228 /* two banks of 128KB for rotation memory */ 229 rsize = 128; 230 break; 231 case 2: 232 hwdev->max_line_size = 1280; 233 /* two banks of 40KB for rotation memory */ 234 rsize = 40; 235 break; 236 case 3: 237 /* reserved value */ 238 hwdev->max_line_size = 0; 239 return -EINVAL; 240 } 241 242 hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K; 243 return 0; 244 } 245 246 static void malidp550_enter_config_mode(struct malidp_hw_device *hwdev) 247 { 248 u32 status, count = 100; 249 250 malidp_hw_setbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL); 251 while (count) { 252 status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS); 253 if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ) 254 break; 255 /* 256 * entering config mode can take as long as the rendering 257 * of a full frame, hence the long sleep here 258 */ 259 usleep_range(1000, 10000); 260 count--; 261 } 262 WARN(count == 0, "timeout while entering config mode"); 263 } 264 265 static void malidp550_leave_config_mode(struct malidp_hw_device *hwdev) 266 { 267 u32 status, count = 100; 268 269 malidp_hw_clearbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL); 270 while (count) { 271 status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS); 272 if ((status & MALIDP550_DC_CONFIG_REQ) == 0) 273 break; 274 usleep_range(100, 1000); 275 count--; 276 } 277 WARN(count == 0, "timeout while leaving config mode"); 278 } 279 280 static bool malidp550_in_config_mode(struct malidp_hw_device *hwdev) 281 { 282 u32 status; 283 284 status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS); 285 if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ) 286 return true; 287 288 return false; 289 } 290 291 static void malidp550_set_config_valid(struct malidp_hw_device *hwdev) 292 { 293 malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID); 294 } 295 296 static void malidp550_modeset(struct malidp_hw_device *hwdev, struct videomode *mode) 297 { 298 u32 val = MALIDP_DE_DEFAULT_PREFETCH_START; 299 300 malidp_hw_write(hwdev, val, MALIDP550_DE_CONTROL); 301 /* 302 * Mali-DP550 and Mali-DP650 encode the background color like this: 303 * - red @ MALIDP550_DE_BGND_COLOR[23:16] 304 * - green @ MALIDP550_DE_BGND_COLOR[15:8] 305 * - blue @ MALIDP550_DE_BGND_COLOR[7:0] 306 * 307 * We need to truncate the least significant 4 bits from the default 308 * MALIDP_BGND_COLOR_x values 309 */ 310 val = (((MALIDP_BGND_COLOR_R >> 4) & 0xff) << 16) | 311 (((MALIDP_BGND_COLOR_G >> 4) & 0xff) << 8) | 312 ((MALIDP_BGND_COLOR_B >> 4) & 0xff); 313 malidp_hw_write(hwdev, val, MALIDP550_DE_BGND_COLOR); 314 315 val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) | 316 MALIDP_DE_H_BACKPORCH(mode->hback_porch); 317 malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_H_TIMINGS); 318 319 val = MALIDP550_DE_V_FRONTPORCH(mode->vfront_porch) | 320 MALIDP_DE_V_BACKPORCH(mode->vback_porch); 321 malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_V_TIMINGS); 322 323 val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) | 324 MALIDP_DE_V_SYNCWIDTH(mode->vsync_len); 325 if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH) 326 val |= MALIDP550_HSYNCPOL; 327 if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH) 328 val |= MALIDP550_VSYNCPOL; 329 malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH); 330 331 val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive); 332 malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE); 333 334 if (mode->flags & DISPLAY_FLAGS_INTERLACED) 335 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC); 336 else 337 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC); 338 } 339 340 static int malidp550_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt) 341 { 342 u32 bytes_per_col; 343 344 /* raw RGB888 or BGR888 can't be rotated */ 345 if ((fmt == DRM_FORMAT_RGB888) || (fmt == DRM_FORMAT_BGR888)) 346 return -EINVAL; 347 348 switch (fmt) { 349 /* 8 lines at 4 bytes per pixel */ 350 case DRM_FORMAT_ARGB2101010: 351 case DRM_FORMAT_ABGR2101010: 352 case DRM_FORMAT_RGBA1010102: 353 case DRM_FORMAT_BGRA1010102: 354 case DRM_FORMAT_ARGB8888: 355 case DRM_FORMAT_ABGR8888: 356 case DRM_FORMAT_RGBA8888: 357 case DRM_FORMAT_BGRA8888: 358 case DRM_FORMAT_XRGB8888: 359 case DRM_FORMAT_XBGR8888: 360 case DRM_FORMAT_RGBX8888: 361 case DRM_FORMAT_BGRX8888: 362 case DRM_FORMAT_RGB888: 363 case DRM_FORMAT_BGR888: 364 /* 16 lines at 2 bytes per pixel */ 365 case DRM_FORMAT_RGBA5551: 366 case DRM_FORMAT_ABGR1555: 367 case DRM_FORMAT_RGB565: 368 case DRM_FORMAT_BGR565: 369 case DRM_FORMAT_UYVY: 370 case DRM_FORMAT_YUYV: 371 bytes_per_col = 32; 372 break; 373 /* 16 lines at 1.5 bytes per pixel */ 374 case DRM_FORMAT_NV12: 375 case DRM_FORMAT_YUV420: 376 bytes_per_col = 24; 377 break; 378 default: 379 return -EINVAL; 380 } 381 382 return w * bytes_per_col; 383 } 384 385 static int malidp650_query_hw(struct malidp_hw_device *hwdev) 386 { 387 u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID); 388 u8 ln_size = (conf >> 4) & 0x3, rsize; 389 390 hwdev->min_line_size = 4; 391 392 switch (ln_size) { 393 case 0: 394 case 2: 395 /* reserved values */ 396 hwdev->max_line_size = 0; 397 return -EINVAL; 398 case 1: 399 hwdev->max_line_size = SZ_4K; 400 /* two banks of 128KB for rotation memory */ 401 rsize = 128; 402 break; 403 case 3: 404 hwdev->max_line_size = 2560; 405 /* two banks of 80KB for rotation memory */ 406 rsize = 80; 407 } 408 409 hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K; 410 return 0; 411 } 412 413 const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = { 414 [MALIDP_500] = { 415 .map = { 416 .se_base = MALIDP500_SE_BASE, 417 .dc_base = MALIDP500_DC_BASE, 418 .out_depth_base = MALIDP500_OUTPUT_DEPTH, 419 .features = 0, /* no CLEARIRQ register */ 420 .n_layers = ARRAY_SIZE(malidp500_layers), 421 .layers = malidp500_layers, 422 .de_irq_map = { 423 .irq_mask = MALIDP_DE_IRQ_UNDERRUN | 424 MALIDP500_DE_IRQ_AXI_ERR | 425 MALIDP500_DE_IRQ_VSYNC | 426 MALIDP500_DE_IRQ_GLOBAL, 427 .vsync_irq = MALIDP500_DE_IRQ_VSYNC, 428 }, 429 .se_irq_map = { 430 .irq_mask = MALIDP500_SE_IRQ_CONF_MODE, 431 .vsync_irq = 0, 432 }, 433 .dc_irq_map = { 434 .irq_mask = MALIDP500_DE_IRQ_CONF_VALID, 435 .vsync_irq = MALIDP500_DE_IRQ_CONF_VALID, 436 }, 437 .input_formats = malidp500_de_formats, 438 .n_input_formats = ARRAY_SIZE(malidp500_de_formats), 439 }, 440 .query_hw = malidp500_query_hw, 441 .enter_config_mode = malidp500_enter_config_mode, 442 .leave_config_mode = malidp500_leave_config_mode, 443 .in_config_mode = malidp500_in_config_mode, 444 .set_config_valid = malidp500_set_config_valid, 445 .modeset = malidp500_modeset, 446 .rotmem_required = malidp500_rotmem_required, 447 }, 448 [MALIDP_550] = { 449 .map = { 450 .se_base = MALIDP550_SE_BASE, 451 .dc_base = MALIDP550_DC_BASE, 452 .out_depth_base = MALIDP550_DE_OUTPUT_DEPTH, 453 .features = MALIDP_REGMAP_HAS_CLEARIRQ, 454 .n_layers = ARRAY_SIZE(malidp550_layers), 455 .layers = malidp550_layers, 456 .de_irq_map = { 457 .irq_mask = MALIDP_DE_IRQ_UNDERRUN | 458 MALIDP550_DE_IRQ_VSYNC, 459 .vsync_irq = MALIDP550_DE_IRQ_VSYNC, 460 }, 461 .se_irq_map = { 462 .irq_mask = MALIDP550_SE_IRQ_EOW | 463 MALIDP550_SE_IRQ_AXI_ERR, 464 }, 465 .dc_irq_map = { 466 .irq_mask = MALIDP550_DC_IRQ_CONF_VALID, 467 .vsync_irq = MALIDP550_DC_IRQ_CONF_VALID, 468 }, 469 .input_formats = malidp550_de_formats, 470 .n_input_formats = ARRAY_SIZE(malidp550_de_formats), 471 }, 472 .query_hw = malidp550_query_hw, 473 .enter_config_mode = malidp550_enter_config_mode, 474 .leave_config_mode = malidp550_leave_config_mode, 475 .in_config_mode = malidp550_in_config_mode, 476 .set_config_valid = malidp550_set_config_valid, 477 .modeset = malidp550_modeset, 478 .rotmem_required = malidp550_rotmem_required, 479 }, 480 [MALIDP_650] = { 481 .map = { 482 .se_base = MALIDP550_SE_BASE, 483 .dc_base = MALIDP550_DC_BASE, 484 .out_depth_base = MALIDP550_DE_OUTPUT_DEPTH, 485 .features = MALIDP_REGMAP_HAS_CLEARIRQ, 486 .n_layers = ARRAY_SIZE(malidp550_layers), 487 .layers = malidp550_layers, 488 .de_irq_map = { 489 .irq_mask = MALIDP_DE_IRQ_UNDERRUN | 490 MALIDP650_DE_IRQ_DRIFT | 491 MALIDP550_DE_IRQ_VSYNC, 492 .vsync_irq = MALIDP550_DE_IRQ_VSYNC, 493 }, 494 .se_irq_map = { 495 .irq_mask = MALIDP550_SE_IRQ_EOW | 496 MALIDP550_SE_IRQ_AXI_ERR, 497 }, 498 .dc_irq_map = { 499 .irq_mask = MALIDP550_DC_IRQ_CONF_VALID, 500 .vsync_irq = MALIDP550_DC_IRQ_CONF_VALID, 501 }, 502 .input_formats = malidp550_de_formats, 503 .n_input_formats = ARRAY_SIZE(malidp550_de_formats), 504 }, 505 .query_hw = malidp650_query_hw, 506 .enter_config_mode = malidp550_enter_config_mode, 507 .leave_config_mode = malidp550_leave_config_mode, 508 .in_config_mode = malidp550_in_config_mode, 509 .set_config_valid = malidp550_set_config_valid, 510 .modeset = malidp550_modeset, 511 .rotmem_required = malidp550_rotmem_required, 512 }, 513 }; 514 515 u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map, 516 u8 layer_id, u32 format) 517 { 518 unsigned int i; 519 520 for (i = 0; i < map->n_input_formats; i++) { 521 if (((map->input_formats[i].layer & layer_id) == layer_id) && 522 (map->input_formats[i].format == format)) 523 return map->input_formats[i].id; 524 } 525 526 return MALIDP_INVALID_FORMAT_ID; 527 } 528 529 static void malidp_hw_clear_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq) 530 { 531 u32 base = malidp_get_block_base(hwdev, block); 532 533 if (hwdev->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) 534 malidp_hw_write(hwdev, irq, base + MALIDP_REG_CLEARIRQ); 535 else 536 malidp_hw_write(hwdev, irq, base + MALIDP_REG_STATUS); 537 } 538 539 static irqreturn_t malidp_de_irq(int irq, void *arg) 540 { 541 struct drm_device *drm = arg; 542 struct malidp_drm *malidp = drm->dev_private; 543 struct malidp_hw_device *hwdev; 544 const struct malidp_irq_map *de; 545 u32 status, mask, dc_status; 546 irqreturn_t ret = IRQ_NONE; 547 548 if (!drm->dev_private) 549 return IRQ_HANDLED; 550 551 hwdev = malidp->dev; 552 de = &hwdev->map.de_irq_map; 553 554 /* first handle the config valid IRQ */ 555 dc_status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS); 556 if (dc_status & hwdev->map.dc_irq_map.vsync_irq) { 557 /* we have a page flip event */ 558 atomic_set(&malidp->config_valid, 1); 559 malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status); 560 ret = IRQ_WAKE_THREAD; 561 } 562 563 status = malidp_hw_read(hwdev, MALIDP_REG_STATUS); 564 if (!(status & de->irq_mask)) 565 return ret; 566 567 mask = malidp_hw_read(hwdev, MALIDP_REG_MASKIRQ); 568 status &= mask; 569 if (status & de->vsync_irq) 570 drm_crtc_handle_vblank(&malidp->crtc); 571 572 malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, status); 573 574 return (ret == IRQ_NONE) ? IRQ_HANDLED : ret; 575 } 576 577 static irqreturn_t malidp_de_irq_thread_handler(int irq, void *arg) 578 { 579 struct drm_device *drm = arg; 580 struct malidp_drm *malidp = drm->dev_private; 581 582 wake_up(&malidp->wq); 583 584 return IRQ_HANDLED; 585 } 586 587 int malidp_de_irq_init(struct drm_device *drm, int irq) 588 { 589 struct malidp_drm *malidp = drm->dev_private; 590 struct malidp_hw_device *hwdev = malidp->dev; 591 int ret; 592 593 /* ensure interrupts are disabled */ 594 malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff); 595 malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff); 596 malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff); 597 malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff); 598 599 ret = devm_request_threaded_irq(drm->dev, irq, malidp_de_irq, 600 malidp_de_irq_thread_handler, 601 IRQF_SHARED, "malidp-de", drm); 602 if (ret < 0) { 603 DRM_ERROR("failed to install DE IRQ handler\n"); 604 return ret; 605 } 606 607 /* first enable the DC block IRQs */ 608 malidp_hw_enable_irq(hwdev, MALIDP_DC_BLOCK, 609 hwdev->map.dc_irq_map.irq_mask); 610 611 /* now enable the DE block IRQs */ 612 malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK, 613 hwdev->map.de_irq_map.irq_mask); 614 615 return 0; 616 } 617 618 void malidp_de_irq_fini(struct drm_device *drm) 619 { 620 struct malidp_drm *malidp = drm->dev_private; 621 struct malidp_hw_device *hwdev = malidp->dev; 622 623 malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 624 hwdev->map.de_irq_map.irq_mask); 625 malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, 626 hwdev->map.dc_irq_map.irq_mask); 627 } 628 629 static irqreturn_t malidp_se_irq(int irq, void *arg) 630 { 631 struct drm_device *drm = arg; 632 struct malidp_drm *malidp = drm->dev_private; 633 struct malidp_hw_device *hwdev = malidp->dev; 634 u32 status, mask; 635 636 status = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_STATUS); 637 if (!(status & hwdev->map.se_irq_map.irq_mask)) 638 return IRQ_NONE; 639 640 mask = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_MASKIRQ); 641 status = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_STATUS); 642 status &= mask; 643 /* ToDo: status decoding and firing up of VSYNC and page flip events */ 644 645 malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, status); 646 647 return IRQ_HANDLED; 648 } 649 650 static irqreturn_t malidp_se_irq_thread_handler(int irq, void *arg) 651 { 652 return IRQ_HANDLED; 653 } 654 655 int malidp_se_irq_init(struct drm_device *drm, int irq) 656 { 657 struct malidp_drm *malidp = drm->dev_private; 658 struct malidp_hw_device *hwdev = malidp->dev; 659 int ret; 660 661 /* ensure interrupts are disabled */ 662 malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff); 663 malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff); 664 665 ret = devm_request_threaded_irq(drm->dev, irq, malidp_se_irq, 666 malidp_se_irq_thread_handler, 667 IRQF_SHARED, "malidp-se", drm); 668 if (ret < 0) { 669 DRM_ERROR("failed to install SE IRQ handler\n"); 670 return ret; 671 } 672 673 malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK, 674 hwdev->map.se_irq_map.irq_mask); 675 676 return 0; 677 } 678 679 void malidp_se_irq_fini(struct drm_device *drm) 680 { 681 struct malidp_drm *malidp = drm->dev_private; 682 struct malidp_hw_device *hwdev = malidp->dev; 683 684 malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 685 hwdev->map.se_irq_map.irq_mask); 686 } 687