xref: /linux/drivers/gpu/drm/arm/malidp_hw.c (revision 071bf69a0220253a44acb8b2a27f7a262b9a46bf)
1 /*
2  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
3  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
4  *
5  * This program is free software and is provided to you under the terms of the
6  * GNU General Public License version 2 as published by the Free Software
7  * Foundation, and any use by you of this program is subject to the terms
8  * of such GNU licence.
9  *
10  * ARM Mali DP500/DP550/DP650 hardware manipulation routines. This is where
11  * the difference between various versions of the hardware is being dealt with
12  * in an attempt to provide to the rest of the driver code a unified view
13  */
14 
15 #include <linux/types.h>
16 #include <linux/io.h>
17 #include <drm/drmP.h>
18 #include <video/videomode.h>
19 #include <video/display_timing.h>
20 
21 #include "malidp_drv.h"
22 #include "malidp_hw.h"
23 
24 static const struct malidp_input_format malidp500_de_formats[] = {
25 	/*    fourcc,   layers supporting the format,     internal id  */
26 	{ DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  0 },
27 	{ DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  1 },
28 	{ DRM_FORMAT_ARGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  2 },
29 	{ DRM_FORMAT_ABGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  3 },
30 	{ DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  4 },
31 	{ DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  5 },
32 	{ DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  6 },
33 	{ DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  7 },
34 	{ DRM_FORMAT_RGBA5551, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  8 },
35 	{ DRM_FORMAT_ABGR1555, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  9 },
36 	{ DRM_FORMAT_RGB565, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 10 },
37 	{ DRM_FORMAT_BGR565, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 11 },
38 	{ DRM_FORMAT_UYVY, DE_VIDEO1, 12 },
39 	{ DRM_FORMAT_YUYV, DE_VIDEO1, 13 },
40 	{ DRM_FORMAT_NV12, DE_VIDEO1, 14 },
41 	{ DRM_FORMAT_YUV420, DE_VIDEO1, 15 },
42 };
43 
44 #define MALIDP_ID(__group, __format) \
45 	((((__group) & 0x7) << 3) | ((__format) & 0x7))
46 
47 #define MALIDP_COMMON_FORMATS \
48 	/*    fourcc,   layers supporting the format,      internal id   */ \
49 	{ DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 0) }, \
50 	{ DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 1) }, \
51 	{ DRM_FORMAT_RGBA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 2) }, \
52 	{ DRM_FORMAT_BGRA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 3) }, \
53 	{ DRM_FORMAT_ARGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 0) }, \
54 	{ DRM_FORMAT_ABGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 1) }, \
55 	{ DRM_FORMAT_RGBA8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 2) }, \
56 	{ DRM_FORMAT_BGRA8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 3) }, \
57 	{ DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 0) }, \
58 	{ DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 1) }, \
59 	{ DRM_FORMAT_RGBX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 2) }, \
60 	{ DRM_FORMAT_BGRX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 3) }, \
61 	{ DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(3, 0) }, \
62 	{ DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(3, 1) }, \
63 	{ DRM_FORMAT_RGBA5551, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 0) }, \
64 	{ DRM_FORMAT_ABGR1555, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 1) }, \
65 	{ DRM_FORMAT_RGB565, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 2) }, \
66 	{ DRM_FORMAT_BGR565, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 3) }, \
67 	{ DRM_FORMAT_YUYV, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 2) },	\
68 	{ DRM_FORMAT_UYVY, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 3) },	\
69 	{ DRM_FORMAT_NV12, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 6) },	\
70 	{ DRM_FORMAT_YUV420, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 7) }
71 
72 static const struct malidp_input_format malidp550_de_formats[] = {
73 	MALIDP_COMMON_FORMATS,
74 };
75 
76 static const struct malidp_layer malidp500_layers[] = {
77 	{ DE_VIDEO1, MALIDP500_DE_LV_BASE, MALIDP500_DE_LV_PTR_BASE },
78 	{ DE_GRAPHICS1, MALIDP500_DE_LG1_BASE, MALIDP500_DE_LG1_PTR_BASE },
79 	{ DE_GRAPHICS2, MALIDP500_DE_LG2_BASE, MALIDP500_DE_LG2_PTR_BASE },
80 };
81 
82 static const struct malidp_layer malidp550_layers[] = {
83 	{ DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE },
84 	{ DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE },
85 	{ DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE },
86 	{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE },
87 };
88 
89 #define MALIDP_DE_DEFAULT_PREFETCH_START	5
90 
91 static int malidp500_query_hw(struct malidp_hw_device *hwdev)
92 {
93 	u32 conf = malidp_hw_read(hwdev, MALIDP500_CONFIG_ID);
94 	/* bit 4 of the CONFIG_ID register holds the line size multiplier */
95 	u8 ln_size_mult = conf & 0x10 ? 2 : 1;
96 
97 	hwdev->min_line_size = 2;
98 	hwdev->max_line_size = SZ_2K * ln_size_mult;
99 	hwdev->rotation_memory[0] = SZ_1K * 64 * ln_size_mult;
100 	hwdev->rotation_memory[1] = 0; /* no second rotation memory bank */
101 
102 	return 0;
103 }
104 
105 static void malidp500_enter_config_mode(struct malidp_hw_device *hwdev)
106 {
107 	u32 status, count = 100;
108 
109 	malidp_hw_setbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
110 	while (count) {
111 		status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
112 		if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ)
113 			break;
114 		/*
115 		 * entering config mode can take as long as the rendering
116 		 * of a full frame, hence the long sleep here
117 		 */
118 		usleep_range(1000, 10000);
119 		count--;
120 	}
121 	WARN(count == 0, "timeout while entering config mode");
122 }
123 
124 static void malidp500_leave_config_mode(struct malidp_hw_device *hwdev)
125 {
126 	u32 status, count = 100;
127 
128 	malidp_hw_clearbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
129 	while (count) {
130 		status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
131 		if ((status & MALIDP500_DC_CONFIG_REQ) == 0)
132 			break;
133 		usleep_range(100, 1000);
134 		count--;
135 	}
136 	WARN(count == 0, "timeout while leaving config mode");
137 }
138 
139 static bool malidp500_in_config_mode(struct malidp_hw_device *hwdev)
140 {
141 	u32 status;
142 
143 	status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
144 	if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ)
145 		return true;
146 
147 	return false;
148 }
149 
150 static void malidp500_set_config_valid(struct malidp_hw_device *hwdev)
151 {
152 	malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID);
153 }
154 
155 static void malidp500_modeset(struct malidp_hw_device *hwdev, struct videomode *mode)
156 {
157 	u32 val = 0;
158 
159 	malidp_hw_clearbits(hwdev, MALIDP500_DC_CLEAR_MASK, MALIDP500_DC_CONTROL);
160 	if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
161 		val |= MALIDP500_HSYNCPOL;
162 	if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
163 		val |= MALIDP500_VSYNCPOL;
164 	val |= MALIDP_DE_DEFAULT_PREFETCH_START;
165 	malidp_hw_setbits(hwdev, val, MALIDP500_DC_CONTROL);
166 
167 	/*
168 	 * Mali-DP500 encodes the background color like this:
169 	 *    - red   @ MALIDP500_BGND_COLOR[12:0]
170 	 *    - green @ MALIDP500_BGND_COLOR[27:16]
171 	 *    - blue  @ (MALIDP500_BGND_COLOR + 4)[12:0]
172 	 */
173 	val = ((MALIDP_BGND_COLOR_G & 0xfff) << 16) |
174 	      (MALIDP_BGND_COLOR_R & 0xfff);
175 	malidp_hw_write(hwdev, val, MALIDP500_BGND_COLOR);
176 	malidp_hw_write(hwdev, MALIDP_BGND_COLOR_B, MALIDP500_BGND_COLOR + 4);
177 
178 	val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) |
179 		MALIDP_DE_H_BACKPORCH(mode->hback_porch);
180 	malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_H_TIMINGS);
181 
182 	val = MALIDP500_DE_V_FRONTPORCH(mode->vfront_porch) |
183 		MALIDP_DE_V_BACKPORCH(mode->vback_porch);
184 	malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_V_TIMINGS);
185 
186 	val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) |
187 		MALIDP_DE_V_SYNCWIDTH(mode->vsync_len);
188 	malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH);
189 
190 	val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive);
191 	malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE);
192 
193 	if (mode->flags & DISPLAY_FLAGS_INTERLACED)
194 		malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
195 	else
196 		malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
197 }
198 
199 static int malidp500_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt)
200 {
201 	unsigned int depth;
202 	int bpp;
203 
204 	/* RGB888 or BGR888 can't be rotated */
205 	if ((fmt == DRM_FORMAT_RGB888) || (fmt == DRM_FORMAT_BGR888))
206 		return -EINVAL;
207 
208 	/*
209 	 * Each layer needs enough rotation memory to fit 8 lines
210 	 * worth of pixel data. Required size is then:
211 	 *    size = rotated_width * (bpp / 8) * 8;
212 	 */
213 	drm_fb_get_bpp_depth(fmt, &depth, &bpp);
214 
215 	return w * bpp;
216 }
217 
218 static int malidp550_query_hw(struct malidp_hw_device *hwdev)
219 {
220 	u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID);
221 	u8 ln_size = (conf >> 4) & 0x3, rsize;
222 
223 	hwdev->min_line_size = 2;
224 
225 	switch (ln_size) {
226 	case 0:
227 		hwdev->max_line_size = SZ_2K;
228 		/* two banks of 64KB for rotation memory */
229 		rsize = 64;
230 		break;
231 	case 1:
232 		hwdev->max_line_size = SZ_4K;
233 		/* two banks of 128KB for rotation memory */
234 		rsize = 128;
235 		break;
236 	case 2:
237 		hwdev->max_line_size = 1280;
238 		/* two banks of 40KB for rotation memory */
239 		rsize = 40;
240 		break;
241 	case 3:
242 		/* reserved value */
243 		hwdev->max_line_size = 0;
244 		return -EINVAL;
245 	}
246 
247 	hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K;
248 	return 0;
249 }
250 
251 static void malidp550_enter_config_mode(struct malidp_hw_device *hwdev)
252 {
253 	u32 status, count = 100;
254 
255 	malidp_hw_setbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
256 	while (count) {
257 		status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
258 		if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ)
259 			break;
260 		/*
261 		 * entering config mode can take as long as the rendering
262 		 * of a full frame, hence the long sleep here
263 		 */
264 		usleep_range(1000, 10000);
265 		count--;
266 	}
267 	WARN(count == 0, "timeout while entering config mode");
268 }
269 
270 static void malidp550_leave_config_mode(struct malidp_hw_device *hwdev)
271 {
272 	u32 status, count = 100;
273 
274 	malidp_hw_clearbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
275 	while (count) {
276 		status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
277 		if ((status & MALIDP550_DC_CONFIG_REQ) == 0)
278 			break;
279 		usleep_range(100, 1000);
280 		count--;
281 	}
282 	WARN(count == 0, "timeout while leaving config mode");
283 }
284 
285 static bool malidp550_in_config_mode(struct malidp_hw_device *hwdev)
286 {
287 	u32 status;
288 
289 	status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
290 	if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ)
291 		return true;
292 
293 	return false;
294 }
295 
296 static void malidp550_set_config_valid(struct malidp_hw_device *hwdev)
297 {
298 	malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID);
299 }
300 
301 static void malidp550_modeset(struct malidp_hw_device *hwdev, struct videomode *mode)
302 {
303 	u32 val = MALIDP_DE_DEFAULT_PREFETCH_START;
304 
305 	malidp_hw_write(hwdev, val, MALIDP550_DE_CONTROL);
306 	/*
307 	 * Mali-DP550 and Mali-DP650 encode the background color like this:
308 	 *   - red   @ MALIDP550_DE_BGND_COLOR[23:16]
309 	 *   - green @ MALIDP550_DE_BGND_COLOR[15:8]
310 	 *   - blue  @ MALIDP550_DE_BGND_COLOR[7:0]
311 	 *
312 	 * We need to truncate the least significant 4 bits from the default
313 	 * MALIDP_BGND_COLOR_x values
314 	 */
315 	val = (((MALIDP_BGND_COLOR_R >> 4) & 0xff) << 16) |
316 	      (((MALIDP_BGND_COLOR_G >> 4) & 0xff) << 8) |
317 	      ((MALIDP_BGND_COLOR_B >> 4) & 0xff);
318 	malidp_hw_write(hwdev, val, MALIDP550_DE_BGND_COLOR);
319 
320 	val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) |
321 		MALIDP_DE_H_BACKPORCH(mode->hback_porch);
322 	malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_H_TIMINGS);
323 
324 	val = MALIDP550_DE_V_FRONTPORCH(mode->vfront_porch) |
325 		MALIDP_DE_V_BACKPORCH(mode->vback_porch);
326 	malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_V_TIMINGS);
327 
328 	val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) |
329 		MALIDP_DE_V_SYNCWIDTH(mode->vsync_len);
330 	if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
331 		val |= MALIDP550_HSYNCPOL;
332 	if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
333 		val |= MALIDP550_VSYNCPOL;
334 	malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH);
335 
336 	val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive);
337 	malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE);
338 
339 	if (mode->flags & DISPLAY_FLAGS_INTERLACED)
340 		malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
341 	else
342 		malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
343 }
344 
345 static int malidp550_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt)
346 {
347 	u32 bytes_per_col;
348 
349 	/* raw RGB888 or BGR888 can't be rotated */
350 	if ((fmt == DRM_FORMAT_RGB888) || (fmt == DRM_FORMAT_BGR888))
351 		return -EINVAL;
352 
353 	switch (fmt) {
354 	/* 8 lines at 4 bytes per pixel */
355 	case DRM_FORMAT_ARGB2101010:
356 	case DRM_FORMAT_ABGR2101010:
357 	case DRM_FORMAT_RGBA1010102:
358 	case DRM_FORMAT_BGRA1010102:
359 	case DRM_FORMAT_ARGB8888:
360 	case DRM_FORMAT_ABGR8888:
361 	case DRM_FORMAT_RGBA8888:
362 	case DRM_FORMAT_BGRA8888:
363 	case DRM_FORMAT_XRGB8888:
364 	case DRM_FORMAT_XBGR8888:
365 	case DRM_FORMAT_RGBX8888:
366 	case DRM_FORMAT_BGRX8888:
367 	case DRM_FORMAT_RGB888:
368 	case DRM_FORMAT_BGR888:
369 	/* 16 lines at 2 bytes per pixel */
370 	case DRM_FORMAT_RGBA5551:
371 	case DRM_FORMAT_ABGR1555:
372 	case DRM_FORMAT_RGB565:
373 	case DRM_FORMAT_BGR565:
374 	case DRM_FORMAT_UYVY:
375 	case DRM_FORMAT_YUYV:
376 		bytes_per_col = 32;
377 		break;
378 	/* 16 lines at 1.5 bytes per pixel */
379 	case DRM_FORMAT_NV12:
380 	case DRM_FORMAT_YUV420:
381 		bytes_per_col = 24;
382 		break;
383 	default:
384 		return -EINVAL;
385 	}
386 
387 	return w * bytes_per_col;
388 }
389 
390 static int malidp650_query_hw(struct malidp_hw_device *hwdev)
391 {
392 	u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID);
393 	u8 ln_size = (conf >> 4) & 0x3, rsize;
394 
395 	hwdev->min_line_size = 4;
396 
397 	switch (ln_size) {
398 	case 0:
399 	case 2:
400 		/* reserved values */
401 		hwdev->max_line_size = 0;
402 		return -EINVAL;
403 	case 1:
404 		hwdev->max_line_size = SZ_4K;
405 		/* two banks of 128KB for rotation memory */
406 		rsize = 128;
407 		break;
408 	case 3:
409 		hwdev->max_line_size = 2560;
410 		/* two banks of 80KB for rotation memory */
411 		rsize = 80;
412 	}
413 
414 	hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K;
415 	return 0;
416 }
417 
418 const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = {
419 	[MALIDP_500] = {
420 		.map = {
421 			.se_base = MALIDP500_SE_BASE,
422 			.dc_base = MALIDP500_DC_BASE,
423 			.out_depth_base = MALIDP500_OUTPUT_DEPTH,
424 			.features = 0,	/* no CLEARIRQ register */
425 			.n_layers = ARRAY_SIZE(malidp500_layers),
426 			.layers = malidp500_layers,
427 			.de_irq_map = {
428 				.irq_mask = MALIDP_DE_IRQ_UNDERRUN |
429 					    MALIDP500_DE_IRQ_AXI_ERR |
430 					    MALIDP500_DE_IRQ_VSYNC |
431 					    MALIDP500_DE_IRQ_GLOBAL,
432 				.vsync_irq = MALIDP500_DE_IRQ_VSYNC,
433 			},
434 			.se_irq_map = {
435 				.irq_mask = MALIDP500_SE_IRQ_CONF_MODE,
436 				.vsync_irq = 0,
437 			},
438 			.dc_irq_map = {
439 				.irq_mask = MALIDP500_DE_IRQ_CONF_VALID,
440 				.vsync_irq = MALIDP500_DE_IRQ_CONF_VALID,
441 			},
442 			.input_formats = malidp500_de_formats,
443 			.n_input_formats = ARRAY_SIZE(malidp500_de_formats),
444 		},
445 		.query_hw = malidp500_query_hw,
446 		.enter_config_mode = malidp500_enter_config_mode,
447 		.leave_config_mode = malidp500_leave_config_mode,
448 		.in_config_mode = malidp500_in_config_mode,
449 		.set_config_valid = malidp500_set_config_valid,
450 		.modeset = malidp500_modeset,
451 		.rotmem_required = malidp500_rotmem_required,
452 	},
453 	[MALIDP_550] = {
454 		.map = {
455 			.se_base = MALIDP550_SE_BASE,
456 			.dc_base = MALIDP550_DC_BASE,
457 			.out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
458 			.features = MALIDP_REGMAP_HAS_CLEARIRQ,
459 			.n_layers = ARRAY_SIZE(malidp550_layers),
460 			.layers = malidp550_layers,
461 			.de_irq_map = {
462 				.irq_mask = MALIDP_DE_IRQ_UNDERRUN |
463 					    MALIDP550_DE_IRQ_VSYNC,
464 				.vsync_irq = MALIDP550_DE_IRQ_VSYNC,
465 			},
466 			.se_irq_map = {
467 				.irq_mask = MALIDP550_SE_IRQ_EOW |
468 					    MALIDP550_SE_IRQ_AXI_ERR,
469 			},
470 			.dc_irq_map = {
471 				.irq_mask = MALIDP550_DC_IRQ_CONF_VALID,
472 				.vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,
473 			},
474 			.input_formats = malidp550_de_formats,
475 			.n_input_formats = ARRAY_SIZE(malidp550_de_formats),
476 		},
477 		.query_hw = malidp550_query_hw,
478 		.enter_config_mode = malidp550_enter_config_mode,
479 		.leave_config_mode = malidp550_leave_config_mode,
480 		.in_config_mode = malidp550_in_config_mode,
481 		.set_config_valid = malidp550_set_config_valid,
482 		.modeset = malidp550_modeset,
483 		.rotmem_required = malidp550_rotmem_required,
484 	},
485 	[MALIDP_650] = {
486 		.map = {
487 			.se_base = MALIDP550_SE_BASE,
488 			.dc_base = MALIDP550_DC_BASE,
489 			.out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
490 			.features = MALIDP_REGMAP_HAS_CLEARIRQ,
491 			.n_layers = ARRAY_SIZE(malidp550_layers),
492 			.layers = malidp550_layers,
493 			.de_irq_map = {
494 				.irq_mask = MALIDP_DE_IRQ_UNDERRUN |
495 					    MALIDP650_DE_IRQ_DRIFT |
496 					    MALIDP550_DE_IRQ_VSYNC,
497 				.vsync_irq = MALIDP550_DE_IRQ_VSYNC,
498 			},
499 			.se_irq_map = {
500 				.irq_mask = MALIDP550_SE_IRQ_EOW |
501 					    MALIDP550_SE_IRQ_AXI_ERR,
502 			},
503 			.dc_irq_map = {
504 				.irq_mask = MALIDP550_DC_IRQ_CONF_VALID,
505 				.vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,
506 			},
507 			.input_formats = malidp550_de_formats,
508 			.n_input_formats = ARRAY_SIZE(malidp550_de_formats),
509 		},
510 		.query_hw = malidp650_query_hw,
511 		.enter_config_mode = malidp550_enter_config_mode,
512 		.leave_config_mode = malidp550_leave_config_mode,
513 		.in_config_mode = malidp550_in_config_mode,
514 		.set_config_valid = malidp550_set_config_valid,
515 		.modeset = malidp550_modeset,
516 		.rotmem_required = malidp550_rotmem_required,
517 	},
518 };
519 
520 u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
521 			   u8 layer_id, u32 format)
522 {
523 	unsigned int i;
524 
525 	for (i = 0; i < map->n_input_formats; i++) {
526 		if (((map->input_formats[i].layer & layer_id) == layer_id) &&
527 		    (map->input_formats[i].format == format))
528 			return map->input_formats[i].id;
529 	}
530 
531 	return MALIDP_INVALID_FORMAT_ID;
532 }
533 
534 static void malidp_hw_clear_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq)
535 {
536 	u32 base = malidp_get_block_base(hwdev, block);
537 
538 	if (hwdev->map.features & MALIDP_REGMAP_HAS_CLEARIRQ)
539 		malidp_hw_write(hwdev, irq, base + MALIDP_REG_CLEARIRQ);
540 	else
541 		malidp_hw_write(hwdev, irq, base + MALIDP_REG_STATUS);
542 }
543 
544 static irqreturn_t malidp_de_irq(int irq, void *arg)
545 {
546 	struct drm_device *drm = arg;
547 	struct malidp_drm *malidp = drm->dev_private;
548 	struct malidp_hw_device *hwdev;
549 	const struct malidp_irq_map *de;
550 	u32 status, mask, dc_status;
551 	irqreturn_t ret = IRQ_NONE;
552 
553 	if (!drm->dev_private)
554 		return IRQ_HANDLED;
555 
556 	hwdev = malidp->dev;
557 	de = &hwdev->map.de_irq_map;
558 
559 	/* first handle the config valid IRQ */
560 	dc_status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
561 	if (dc_status & hwdev->map.dc_irq_map.vsync_irq) {
562 		/* we have a page flip event */
563 		atomic_set(&malidp->config_valid, 1);
564 		malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status);
565 		ret = IRQ_WAKE_THREAD;
566 	}
567 
568 	status = malidp_hw_read(hwdev, MALIDP_REG_STATUS);
569 	if (!(status & de->irq_mask))
570 		return ret;
571 
572 	mask = malidp_hw_read(hwdev, MALIDP_REG_MASKIRQ);
573 	status &= mask;
574 	if (status & de->vsync_irq)
575 		drm_crtc_handle_vblank(&malidp->crtc);
576 
577 	malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, status);
578 
579 	return (ret == IRQ_NONE) ? IRQ_HANDLED : ret;
580 }
581 
582 static irqreturn_t malidp_de_irq_thread_handler(int irq, void *arg)
583 {
584 	struct drm_device *drm = arg;
585 	struct malidp_drm *malidp = drm->dev_private;
586 
587 	wake_up(&malidp->wq);
588 
589 	return IRQ_HANDLED;
590 }
591 
592 int malidp_de_irq_init(struct drm_device *drm, int irq)
593 {
594 	struct malidp_drm *malidp = drm->dev_private;
595 	struct malidp_hw_device *hwdev = malidp->dev;
596 	int ret;
597 
598 	/* ensure interrupts are disabled */
599 	malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
600 	malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
601 	malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
602 	malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
603 
604 	ret = devm_request_threaded_irq(drm->dev, irq, malidp_de_irq,
605 					malidp_de_irq_thread_handler,
606 					IRQF_SHARED, "malidp-de", drm);
607 	if (ret < 0) {
608 		DRM_ERROR("failed to install DE IRQ handler\n");
609 		return ret;
610 	}
611 
612 	/* first enable the DC block IRQs */
613 	malidp_hw_enable_irq(hwdev, MALIDP_DC_BLOCK,
614 			     hwdev->map.dc_irq_map.irq_mask);
615 
616 	/* now enable the DE block IRQs */
617 	malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
618 			     hwdev->map.de_irq_map.irq_mask);
619 
620 	return 0;
621 }
622 
623 void malidp_de_irq_fini(struct drm_device *drm)
624 {
625 	struct malidp_drm *malidp = drm->dev_private;
626 	struct malidp_hw_device *hwdev = malidp->dev;
627 
628 	malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
629 			      hwdev->map.de_irq_map.irq_mask);
630 	malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK,
631 			      hwdev->map.dc_irq_map.irq_mask);
632 }
633 
634 static irqreturn_t malidp_se_irq(int irq, void *arg)
635 {
636 	struct drm_device *drm = arg;
637 	struct malidp_drm *malidp = drm->dev_private;
638 	struct malidp_hw_device *hwdev = malidp->dev;
639 	u32 status, mask;
640 
641 	status = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_STATUS);
642 	if (!(status & hwdev->map.se_irq_map.irq_mask))
643 		return IRQ_NONE;
644 
645 	mask = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_MASKIRQ);
646 	status = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_STATUS);
647 	status &= mask;
648 	/* ToDo: status decoding and firing up of VSYNC and page flip events */
649 
650 	malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, status);
651 
652 	return IRQ_HANDLED;
653 }
654 
655 static irqreturn_t malidp_se_irq_thread_handler(int irq, void *arg)
656 {
657 	return IRQ_HANDLED;
658 }
659 
660 int malidp_se_irq_init(struct drm_device *drm, int irq)
661 {
662 	struct malidp_drm *malidp = drm->dev_private;
663 	struct malidp_hw_device *hwdev = malidp->dev;
664 	int ret;
665 
666 	/* ensure interrupts are disabled */
667 	malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
668 	malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
669 
670 	ret = devm_request_threaded_irq(drm->dev, irq, malidp_se_irq,
671 					malidp_se_irq_thread_handler,
672 					IRQF_SHARED, "malidp-se", drm);
673 	if (ret < 0) {
674 		DRM_ERROR("failed to install SE IRQ handler\n");
675 		return ret;
676 	}
677 
678 	malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK,
679 			     hwdev->map.se_irq_map.irq_mask);
680 
681 	return 0;
682 }
683 
684 void malidp_se_irq_fini(struct drm_device *drm)
685 {
686 	struct malidp_drm *malidp = drm->dev_private;
687 	struct malidp_hw_device *hwdev = malidp->dev;
688 
689 	malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK,
690 			      hwdev->map.se_irq_map.irq_mask);
691 }
692