1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 4 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 5 * 6 * ARM Mali DP500/DP550/DP650 KMS/DRM driver 7 */ 8 9 #include <linux/module.h> 10 #include <linux/clk.h> 11 #include <linux/component.h> 12 #include <linux/of_device.h> 13 #include <linux/of_graph.h> 14 #include <linux/of_reserved_mem.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/debugfs.h> 18 19 #include <drm/clients/drm_client_setup.h> 20 #include <drm/drm_atomic.h> 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_crtc.h> 23 #include <drm/drm_drv.h> 24 #include <drm/drm_fbdev_dma.h> 25 #include <drm/drm_fourcc.h> 26 #include <drm/drm_gem_dma_helper.h> 27 #include <drm/drm_gem_framebuffer_helper.h> 28 #include <drm/drm_managed.h> 29 #include <drm/drm_modeset_helper.h> 30 #include <drm/drm_module.h> 31 #include <drm/drm_of.h> 32 #include <drm/drm_print.h> 33 #include <drm/drm_probe_helper.h> 34 #include <drm/drm_vblank.h> 35 36 #include "malidp_drv.h" 37 #include "malidp_mw.h" 38 #include "malidp_regs.h" 39 #include "malidp_hw.h" 40 41 #define MALIDP_CONF_VALID_TIMEOUT 250 42 #define AFBC_HEADER_SIZE 16 43 #define AFBC_SUPERBLK_ALIGNMENT 128 44 45 static void malidp_write_gamma_table(struct malidp_hw_device *hwdev, 46 u32 data[MALIDP_COEFFTAB_NUM_COEFFS]) 47 { 48 int i; 49 /* Update all channels with a single gamma curve. */ 50 const u32 gamma_write_mask = GENMASK(18, 16); 51 /* 52 * Always write an entire table, so the address field in 53 * DE_COEFFTAB_ADDR is 0 and we can use the gamma_write_mask bitmask 54 * directly. 55 */ 56 malidp_hw_write(hwdev, gamma_write_mask, 57 hwdev->hw->map.coeffs_base + MALIDP_COEF_TABLE_ADDR); 58 for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i) 59 malidp_hw_write(hwdev, data[i], 60 hwdev->hw->map.coeffs_base + 61 MALIDP_COEF_TABLE_DATA); 62 } 63 64 static void malidp_atomic_commit_update_gamma(struct drm_crtc *crtc, 65 struct drm_crtc_state *old_state) 66 { 67 struct malidp_drm *malidp = crtc_to_malidp_device(crtc); 68 struct malidp_hw_device *hwdev = malidp->dev; 69 70 if (!crtc->state->color_mgmt_changed) 71 return; 72 73 if (!crtc->state->gamma_lut) { 74 malidp_hw_clearbits(hwdev, 75 MALIDP_DISP_FUNC_GAMMA, 76 MALIDP_DE_DISPLAY_FUNC); 77 } else { 78 struct malidp_crtc_state *mc = 79 to_malidp_crtc_state(crtc->state); 80 81 if (!old_state->gamma_lut || (crtc->state->gamma_lut->base.id != 82 old_state->gamma_lut->base.id)) 83 malidp_write_gamma_table(hwdev, mc->gamma_coeffs); 84 85 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_GAMMA, 86 MALIDP_DE_DISPLAY_FUNC); 87 } 88 } 89 90 static 91 void malidp_atomic_commit_update_coloradj(struct drm_crtc *crtc, 92 struct drm_crtc_state *old_state) 93 { 94 struct malidp_drm *malidp = crtc_to_malidp_device(crtc); 95 struct malidp_hw_device *hwdev = malidp->dev; 96 int i; 97 98 if (!crtc->state->color_mgmt_changed) 99 return; 100 101 if (!crtc->state->ctm) { 102 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_CADJ, 103 MALIDP_DE_DISPLAY_FUNC); 104 } else { 105 struct malidp_crtc_state *mc = 106 to_malidp_crtc_state(crtc->state); 107 108 if (!old_state->ctm || (crtc->state->ctm->base.id != 109 old_state->ctm->base.id)) 110 for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; ++i) 111 malidp_hw_write(hwdev, 112 mc->coloradj_coeffs[i], 113 hwdev->hw->map.coeffs_base + 114 MALIDP_COLOR_ADJ_COEF + 4 * i); 115 116 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_CADJ, 117 MALIDP_DE_DISPLAY_FUNC); 118 } 119 } 120 121 static void malidp_atomic_commit_se_config(struct drm_crtc *crtc, 122 struct drm_crtc_state *old_state) 123 { 124 struct malidp_crtc_state *cs = to_malidp_crtc_state(crtc->state); 125 struct malidp_crtc_state *old_cs = to_malidp_crtc_state(old_state); 126 struct malidp_drm *malidp = crtc_to_malidp_device(crtc); 127 struct malidp_hw_device *hwdev = malidp->dev; 128 struct malidp_se_config *s = &cs->scaler_config; 129 struct malidp_se_config *old_s = &old_cs->scaler_config; 130 u32 se_control = hwdev->hw->map.se_base + 131 ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ? 132 0x10 : 0xC); 133 u32 layer_control = se_control + MALIDP_SE_LAYER_CONTROL; 134 u32 scr = se_control + MALIDP_SE_SCALING_CONTROL; 135 u32 val; 136 137 /* Set SE_CONTROL */ 138 if (!s->scale_enable) { 139 val = malidp_hw_read(hwdev, se_control); 140 val &= ~MALIDP_SE_SCALING_EN; 141 malidp_hw_write(hwdev, val, se_control); 142 return; 143 } 144 145 hwdev->hw->se_set_scaling_coeffs(hwdev, s, old_s); 146 val = malidp_hw_read(hwdev, se_control); 147 val |= MALIDP_SE_SCALING_EN | MALIDP_SE_ALPHA_EN; 148 149 val &= ~MALIDP_SE_ENH(MALIDP_SE_ENH_MASK); 150 val |= s->enhancer_enable ? MALIDP_SE_ENH(3) : 0; 151 152 val |= MALIDP_SE_RGBO_IF_EN; 153 malidp_hw_write(hwdev, val, se_control); 154 155 /* Set IN_SIZE & OUT_SIZE. */ 156 val = MALIDP_SE_SET_V_SIZE(s->input_h) | 157 MALIDP_SE_SET_H_SIZE(s->input_w); 158 malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_IN_SIZE); 159 val = MALIDP_SE_SET_V_SIZE(s->output_h) | 160 MALIDP_SE_SET_H_SIZE(s->output_w); 161 malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_OUT_SIZE); 162 163 /* Set phase regs. */ 164 malidp_hw_write(hwdev, s->h_init_phase, scr + MALIDP_SE_H_INIT_PH); 165 malidp_hw_write(hwdev, s->h_delta_phase, scr + MALIDP_SE_H_DELTA_PH); 166 malidp_hw_write(hwdev, s->v_init_phase, scr + MALIDP_SE_V_INIT_PH); 167 malidp_hw_write(hwdev, s->v_delta_phase, scr + MALIDP_SE_V_DELTA_PH); 168 } 169 170 /* 171 * set the "config valid" bit and wait until the hardware acts on it 172 */ 173 static int malidp_set_and_wait_config_valid(struct drm_device *drm) 174 { 175 struct malidp_drm *malidp = drm_to_malidp(drm); 176 struct malidp_hw_device *hwdev = malidp->dev; 177 int ret; 178 179 hwdev->hw->set_config_valid(hwdev, 1); 180 /* don't wait for config_valid flag if we are in config mode */ 181 if (hwdev->hw->in_config_mode(hwdev)) { 182 atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_DONE); 183 return 0; 184 } 185 186 ret = wait_event_interruptible_timeout(malidp->wq, 187 atomic_read(&malidp->config_valid) == MALIDP_CONFIG_VALID_DONE, 188 msecs_to_jiffies(MALIDP_CONF_VALID_TIMEOUT)); 189 190 return (ret > 0) ? 0 : -ETIMEDOUT; 191 } 192 193 static void malidp_atomic_commit_hw_done(struct drm_atomic_commit *state) 194 { 195 struct drm_device *drm = state->dev; 196 struct malidp_drm *malidp = drm_to_malidp(drm); 197 int loop = 5; 198 199 malidp->event = malidp->crtc.state->event; 200 malidp->crtc.state->event = NULL; 201 202 if (malidp->crtc.state->active) { 203 /* 204 * if we have an event to deliver to userspace, make sure 205 * the vblank is enabled as we are sending it from the IRQ 206 * handler. 207 */ 208 if (malidp->event) 209 drm_crtc_vblank_get(&malidp->crtc); 210 211 /* only set config_valid if the CRTC is enabled */ 212 if (malidp_set_and_wait_config_valid(drm) < 0) { 213 /* 214 * make a loop around the second CVAL setting and 215 * try 5 times before giving up. 216 */ 217 while (loop--) { 218 if (!malidp_set_and_wait_config_valid(drm)) 219 break; 220 } 221 DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n"); 222 } 223 224 } else if (malidp->event) { 225 /* CRTC inactive means vblank IRQ is disabled, send event directly */ 226 spin_lock_irq(&drm->event_lock); 227 drm_crtc_send_vblank_event(&malidp->crtc, malidp->event); 228 malidp->event = NULL; 229 spin_unlock_irq(&drm->event_lock); 230 } 231 drm_atomic_helper_commit_hw_done(state); 232 } 233 234 static void malidp_atomic_commit_tail(struct drm_atomic_commit *state) 235 { 236 struct drm_device *drm = state->dev; 237 struct malidp_drm *malidp = drm_to_malidp(drm); 238 struct drm_crtc *crtc; 239 struct drm_crtc_state *old_crtc_state; 240 int i; 241 bool fence_cookie = dma_fence_begin_signalling(); 242 243 pm_runtime_get_sync(drm->dev); 244 245 /* 246 * set config_valid to a special value to let IRQ handlers 247 * know that we are updating registers 248 */ 249 atomic_set(&malidp->config_valid, MALIDP_CONFIG_START); 250 malidp->dev->hw->set_config_valid(malidp->dev, 0); 251 252 drm_atomic_helper_commit_modeset_disables(drm, state); 253 254 for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) { 255 malidp_atomic_commit_update_gamma(crtc, old_crtc_state); 256 malidp_atomic_commit_update_coloradj(crtc, old_crtc_state); 257 malidp_atomic_commit_se_config(crtc, old_crtc_state); 258 } 259 260 drm_atomic_helper_commit_planes(drm, state, DRM_PLANE_COMMIT_ACTIVE_ONLY); 261 262 malidp_mw_atomic_commit(drm, state); 263 264 drm_atomic_helper_commit_modeset_enables(drm, state); 265 266 malidp_atomic_commit_hw_done(state); 267 268 dma_fence_end_signalling(fence_cookie); 269 270 pm_runtime_put(drm->dev); 271 272 drm_atomic_helper_cleanup_planes(drm, state); 273 } 274 275 static const struct drm_mode_config_helper_funcs malidp_mode_config_helpers = { 276 .atomic_commit_tail = malidp_atomic_commit_tail, 277 }; 278 279 static bool 280 malidp_verify_afbc_framebuffer_caps(struct drm_device *dev, 281 const struct drm_mode_fb_cmd2 *mode_cmd) 282 { 283 if (malidp_format_mod_supported(dev, mode_cmd->pixel_format, 284 mode_cmd->modifier[0]) == false) 285 return false; 286 287 if (mode_cmd->offsets[0] != 0) { 288 DRM_DEBUG_KMS("AFBC buffers' plane offset should be 0\n"); 289 return false; 290 } 291 292 switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) { 293 case AFBC_SIZE_16X16: 294 if ((mode_cmd->width % 16) || (mode_cmd->height % 16)) { 295 DRM_DEBUG_KMS("AFBC buffers must be aligned to 16 pixels\n"); 296 return false; 297 } 298 break; 299 default: 300 DRM_DEBUG_KMS("Unsupported AFBC block size\n"); 301 return false; 302 } 303 304 return true; 305 } 306 307 static bool 308 malidp_verify_afbc_framebuffer_size(struct drm_device *dev, 309 struct drm_file *file, 310 const struct drm_format_info *info, 311 const struct drm_mode_fb_cmd2 *mode_cmd) 312 { 313 int n_superblocks = 0; 314 struct drm_gem_object *objs = NULL; 315 u32 afbc_superblock_size = 0, afbc_superblock_height = 0; 316 u32 afbc_superblock_width = 0, afbc_size = 0; 317 int bpp = 0; 318 319 switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) { 320 case AFBC_SIZE_16X16: 321 afbc_superblock_height = 16; 322 afbc_superblock_width = 16; 323 break; 324 default: 325 DRM_DEBUG_KMS("AFBC superblock size is not supported\n"); 326 return false; 327 } 328 329 n_superblocks = (mode_cmd->width / afbc_superblock_width) * 330 (mode_cmd->height / afbc_superblock_height); 331 332 bpp = malidp_format_get_bpp(info->format); 333 334 afbc_superblock_size = (bpp * afbc_superblock_width * afbc_superblock_height) 335 / BITS_PER_BYTE; 336 337 afbc_size = ALIGN(n_superblocks * AFBC_HEADER_SIZE, AFBC_SUPERBLK_ALIGNMENT); 338 afbc_size += n_superblocks * ALIGN(afbc_superblock_size, AFBC_SUPERBLK_ALIGNMENT); 339 340 if ((mode_cmd->width * bpp) != (mode_cmd->pitches[0] * BITS_PER_BYTE)) { 341 DRM_DEBUG_KMS("Invalid value of (pitch * BITS_PER_BYTE) (=%u) " 342 "should be same as width (=%u) * bpp (=%u)\n", 343 (mode_cmd->pitches[0] * BITS_PER_BYTE), 344 mode_cmd->width, bpp); 345 return false; 346 } 347 348 objs = drm_gem_object_lookup(file, mode_cmd->handles[0]); 349 if (!objs) { 350 DRM_DEBUG_KMS("Failed to lookup GEM object\n"); 351 return false; 352 } 353 354 if (objs->size < afbc_size) { 355 DRM_DEBUG_KMS("buffer size (%zu) too small for AFBC buffer size = %u\n", 356 objs->size, afbc_size); 357 drm_gem_object_put(objs); 358 return false; 359 } 360 361 drm_gem_object_put(objs); 362 363 return true; 364 } 365 366 static bool 367 malidp_verify_afbc_framebuffer(struct drm_device *dev, struct drm_file *file, 368 const struct drm_format_info *info, 369 const struct drm_mode_fb_cmd2 *mode_cmd) 370 { 371 if (malidp_verify_afbc_framebuffer_caps(dev, mode_cmd)) 372 return malidp_verify_afbc_framebuffer_size(dev, file, info, mode_cmd); 373 374 return false; 375 } 376 377 static struct drm_framebuffer * 378 malidp_fb_create(struct drm_device *dev, struct drm_file *file, 379 const struct drm_format_info *info, 380 const struct drm_mode_fb_cmd2 *mode_cmd) 381 { 382 if (mode_cmd->modifier[0]) { 383 if (!malidp_verify_afbc_framebuffer(dev, file, info, mode_cmd)) 384 return ERR_PTR(-EINVAL); 385 } 386 387 return drm_gem_fb_create(dev, file, info, mode_cmd); 388 } 389 390 static const struct drm_mode_config_funcs malidp_mode_config_funcs = { 391 .fb_create = malidp_fb_create, 392 .atomic_check = drm_atomic_helper_check, 393 .atomic_commit = drm_atomic_helper_commit, 394 }; 395 396 static int malidp_init(struct drm_device *drm) 397 { 398 int ret; 399 struct malidp_drm *malidp = drm_to_malidp(drm); 400 struct malidp_hw_device *hwdev = malidp->dev; 401 402 ret = drmm_mode_config_init(drm); 403 if (ret) 404 goto out; 405 406 drm->mode_config.min_width = hwdev->min_line_size; 407 drm->mode_config.min_height = hwdev->min_line_size; 408 drm->mode_config.max_width = hwdev->max_line_size; 409 drm->mode_config.max_height = hwdev->max_line_size; 410 drm->mode_config.funcs = &malidp_mode_config_funcs; 411 drm->mode_config.helper_private = &malidp_mode_config_helpers; 412 413 ret = malidp_crtc_init(drm); 414 if (ret) 415 goto out; 416 417 ret = malidp_mw_connector_init(drm); 418 if (ret) 419 goto out; 420 421 out: 422 return ret; 423 } 424 425 static int malidp_irq_init(struct platform_device *pdev) 426 { 427 int irq_de, irq_se, ret = 0; 428 struct drm_device *drm = dev_get_drvdata(&pdev->dev); 429 struct malidp_drm *malidp = drm_to_malidp(drm); 430 struct malidp_hw_device *hwdev = malidp->dev; 431 432 /* fetch the interrupts from DT */ 433 irq_de = platform_get_irq_byname(pdev, "DE"); 434 if (irq_de < 0) { 435 DRM_ERROR("no 'DE' IRQ specified!\n"); 436 return irq_de; 437 } 438 irq_se = platform_get_irq_byname(pdev, "SE"); 439 if (irq_se < 0) { 440 DRM_ERROR("no 'SE' IRQ specified!\n"); 441 return irq_se; 442 } 443 444 ret = malidp_de_irq_init(drm, irq_de); 445 if (ret) 446 return ret; 447 448 ret = malidp_se_irq_init(drm, irq_se); 449 if (ret) { 450 malidp_de_irq_fini(hwdev); 451 return ret; 452 } 453 454 return 0; 455 } 456 457 DEFINE_DRM_GEM_DMA_FOPS(fops); 458 459 static int malidp_dumb_create(struct drm_file *file_priv, 460 struct drm_device *drm, 461 struct drm_mode_create_dumb *args) 462 { 463 struct malidp_drm *malidp = drm_to_malidp(drm); 464 /* allocate for the worst case scenario, i.e. rotated buffers */ 465 u8 alignment = malidp_hw_get_pitch_align(malidp->dev, 1); 466 467 args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), alignment); 468 469 return drm_gem_dma_dumb_create_internal(file_priv, drm, args); 470 } 471 472 #ifdef CONFIG_DEBUG_FS 473 474 static void malidp_error_stats_init(struct malidp_error_stats *error_stats) 475 { 476 error_stats->num_errors = 0; 477 error_stats->last_error_status = 0; 478 error_stats->last_error_vblank = -1; 479 } 480 481 void malidp_error(struct malidp_drm *malidp, 482 struct malidp_error_stats *error_stats, u32 status, 483 u64 vblank) 484 { 485 unsigned long irqflags; 486 487 spin_lock_irqsave(&malidp->errors_lock, irqflags); 488 error_stats->last_error_status = status; 489 error_stats->last_error_vblank = vblank; 490 error_stats->num_errors++; 491 spin_unlock_irqrestore(&malidp->errors_lock, irqflags); 492 } 493 494 static void malidp_error_stats_dump(const char *prefix, 495 struct malidp_error_stats error_stats, 496 struct seq_file *m) 497 { 498 seq_printf(m, "[%s] num_errors : %d\n", prefix, 499 error_stats.num_errors); 500 seq_printf(m, "[%s] last_error_status : 0x%08x\n", prefix, 501 error_stats.last_error_status); 502 seq_printf(m, "[%s] last_error_vblank : %lld\n", prefix, 503 error_stats.last_error_vblank); 504 } 505 506 static int malidp_show_stats(struct seq_file *m, void *arg) 507 { 508 struct drm_device *drm = m->private; 509 struct malidp_drm *malidp = drm_to_malidp(drm); 510 unsigned long irqflags; 511 struct malidp_error_stats de_errors, se_errors; 512 513 spin_lock_irqsave(&malidp->errors_lock, irqflags); 514 de_errors = malidp->de_errors; 515 se_errors = malidp->se_errors; 516 spin_unlock_irqrestore(&malidp->errors_lock, irqflags); 517 malidp_error_stats_dump("DE", de_errors, m); 518 malidp_error_stats_dump("SE", se_errors, m); 519 return 0; 520 } 521 522 static int malidp_debugfs_open(struct inode *inode, struct file *file) 523 { 524 return single_open(file, malidp_show_stats, inode->i_private); 525 } 526 527 static ssize_t malidp_debugfs_write(struct file *file, const char __user *ubuf, 528 size_t len, loff_t *offp) 529 { 530 struct seq_file *m = file->private_data; 531 struct drm_device *drm = m->private; 532 struct malidp_drm *malidp = drm_to_malidp(drm); 533 unsigned long irqflags; 534 535 spin_lock_irqsave(&malidp->errors_lock, irqflags); 536 malidp_error_stats_init(&malidp->de_errors); 537 malidp_error_stats_init(&malidp->se_errors); 538 spin_unlock_irqrestore(&malidp->errors_lock, irqflags); 539 return len; 540 } 541 542 static const struct file_operations malidp_debugfs_fops = { 543 .owner = THIS_MODULE, 544 .open = malidp_debugfs_open, 545 .read = seq_read, 546 .write = malidp_debugfs_write, 547 .llseek = seq_lseek, 548 .release = single_release, 549 }; 550 551 static void malidp_debugfs_init(struct drm_minor *minor) 552 { 553 struct malidp_drm *malidp = drm_to_malidp(minor->dev); 554 555 malidp_error_stats_init(&malidp->de_errors); 556 malidp_error_stats_init(&malidp->se_errors); 557 spin_lock_init(&malidp->errors_lock); 558 debugfs_create_file("debug", S_IRUGO | S_IWUSR, minor->debugfs_root, 559 minor->dev, &malidp_debugfs_fops); 560 } 561 562 #endif //CONFIG_DEBUG_FS 563 564 static const struct drm_driver malidp_driver = { 565 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 566 DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(malidp_dumb_create), 567 DRM_FBDEV_DMA_DRIVER_OPS, 568 #ifdef CONFIG_DEBUG_FS 569 .debugfs_init = malidp_debugfs_init, 570 #endif 571 .fops = &fops, 572 .name = "mali-dp", 573 .desc = "ARM Mali Display Processor driver", 574 .major = 1, 575 .minor = 0, 576 }; 577 578 static const struct of_device_id malidp_drm_of_match[] = { 579 { 580 .compatible = "arm,mali-dp500", 581 .data = &malidp_device[MALIDP_500] 582 }, 583 { 584 .compatible = "arm,mali-dp550", 585 .data = &malidp_device[MALIDP_550] 586 }, 587 { 588 .compatible = "arm,mali-dp650", 589 .data = &malidp_device[MALIDP_650] 590 }, 591 {}, 592 }; 593 MODULE_DEVICE_TABLE(of, malidp_drm_of_match); 594 595 static bool malidp_is_compatible_hw_id(struct malidp_hw_device *hwdev, 596 const struct of_device_id *dev_id) 597 { 598 u32 core_id; 599 const char *compatstr_dp500 = "arm,mali-dp500"; 600 bool is_dp500; 601 bool dt_is_dp500; 602 603 /* 604 * The DP500 CORE_ID register is in a different location, so check it 605 * first. If the product id field matches, then this is DP500, otherwise 606 * check the DP550/650 CORE_ID register. 607 */ 608 core_id = malidp_hw_read(hwdev, MALIDP500_DC_BASE + MALIDP_DE_CORE_ID); 609 /* Offset 0x18 will never read 0x500 on products other than DP500. */ 610 is_dp500 = (MALIDP_PRODUCT_ID(core_id) == 0x500); 611 dt_is_dp500 = strnstr(dev_id->compatible, compatstr_dp500, 612 sizeof(dev_id->compatible)) != NULL; 613 if (is_dp500 != dt_is_dp500) { 614 DRM_ERROR("Device-tree expects %s, but hardware %s DP500.\n", 615 dev_id->compatible, is_dp500 ? "is" : "is not"); 616 return false; 617 } else if (!dt_is_dp500) { 618 u16 product_id; 619 char buf[32]; 620 621 core_id = malidp_hw_read(hwdev, 622 MALIDP550_DC_BASE + MALIDP_DE_CORE_ID); 623 product_id = MALIDP_PRODUCT_ID(core_id); 624 snprintf(buf, sizeof(buf), "arm,mali-dp%X", product_id); 625 if (!strnstr(dev_id->compatible, buf, 626 sizeof(dev_id->compatible))) { 627 DRM_ERROR("Device-tree expects %s, but hardware is DP%03X.\n", 628 dev_id->compatible, product_id); 629 return false; 630 } 631 } 632 return true; 633 } 634 635 static bool malidp_has_sufficient_address_space(const struct resource *res, 636 const struct of_device_id *dev_id) 637 { 638 resource_size_t res_size = resource_size(res); 639 const char *compatstr_dp500 = "arm,mali-dp500"; 640 641 if (!strnstr(dev_id->compatible, compatstr_dp500, 642 sizeof(dev_id->compatible))) 643 return res_size >= MALIDP550_ADDR_SPACE_SIZE; 644 else if (res_size < MALIDP500_ADDR_SPACE_SIZE) 645 return false; 646 return true; 647 } 648 649 static ssize_t core_id_show(struct device *dev, struct device_attribute *attr, 650 char *buf) 651 { 652 struct drm_device *drm = dev_get_drvdata(dev); 653 struct malidp_drm *malidp = drm_to_malidp(drm); 654 655 return sysfs_emit(buf, "%08x\n", malidp->core_id); 656 } 657 658 static DEVICE_ATTR_RO(core_id); 659 660 static struct attribute *mali_dp_attrs[] = { 661 &dev_attr_core_id.attr, 662 NULL, 663 }; 664 ATTRIBUTE_GROUPS(mali_dp); 665 666 #define MAX_OUTPUT_CHANNELS 3 667 668 static int malidp_runtime_pm_suspend(struct device *dev) 669 { 670 struct drm_device *drm = dev_get_drvdata(dev); 671 struct malidp_drm *malidp = drm_to_malidp(drm); 672 struct malidp_hw_device *hwdev = malidp->dev; 673 struct clk_bulk_data clks[] = { 674 { .clk = hwdev->pclk }, 675 { .clk = hwdev->aclk }, 676 { .clk = hwdev->mclk }, 677 }; 678 679 /* we can only suspend if the hardware is in config mode */ 680 WARN_ON(!hwdev->hw->in_config_mode(hwdev)); 681 682 malidp_se_irq_fini(hwdev); 683 malidp_de_irq_fini(hwdev); 684 hwdev->pm_suspended = true; 685 clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks); 686 687 return 0; 688 } 689 690 static int malidp_runtime_pm_resume(struct device *dev) 691 { 692 struct drm_device *drm = dev_get_drvdata(dev); 693 struct malidp_drm *malidp = drm_to_malidp(drm); 694 struct malidp_hw_device *hwdev = malidp->dev; 695 struct clk_bulk_data clks[] = { 696 { .clk = hwdev->pclk }, 697 { .clk = hwdev->aclk }, 698 { .clk = hwdev->mclk }, 699 }; 700 int err; 701 702 err = clk_bulk_prepare_enable(ARRAY_SIZE(clks), clks); 703 if (err) 704 return err; 705 706 hwdev->pm_suspended = false; 707 malidp_de_irq_hw_init(hwdev); 708 malidp_se_irq_hw_init(hwdev); 709 710 return 0; 711 } 712 713 static int malidp_bind(struct device *dev) 714 { 715 struct resource *res; 716 struct drm_device *drm; 717 struct malidp_drm *malidp; 718 struct malidp_hw_device *hwdev; 719 struct platform_device *pdev = to_platform_device(dev); 720 struct of_device_id const *dev_id; 721 struct drm_encoder *encoder; 722 /* number of lines for the R, G and B output */ 723 u8 output_width[MAX_OUTPUT_CHANNELS]; 724 int ret = 0, i; 725 u32 version, out_depth = 0; 726 727 malidp = devm_drm_dev_alloc(dev, &malidp_driver, typeof(*malidp), base); 728 if (IS_ERR(malidp)) 729 return PTR_ERR(malidp); 730 731 drm = &malidp->base; 732 733 hwdev = drmm_kzalloc(drm, sizeof(*hwdev), GFP_KERNEL); 734 if (!hwdev) 735 return -ENOMEM; 736 737 hwdev->hw = (struct malidp_hw *)of_device_get_match_data(dev); 738 malidp->dev = hwdev; 739 740 hwdev->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 741 if (IS_ERR(hwdev->regs)) 742 return PTR_ERR(hwdev->regs); 743 744 hwdev->pclk = devm_clk_get(dev, "pclk"); 745 if (IS_ERR(hwdev->pclk)) 746 return PTR_ERR(hwdev->pclk); 747 748 hwdev->aclk = devm_clk_get(dev, "aclk"); 749 if (IS_ERR(hwdev->aclk)) 750 return PTR_ERR(hwdev->aclk); 751 752 hwdev->mclk = devm_clk_get(dev, "mclk"); 753 if (IS_ERR(hwdev->mclk)) 754 return PTR_ERR(hwdev->mclk); 755 756 hwdev->pxlclk = devm_clk_get(dev, "pxlclk"); 757 if (IS_ERR(hwdev->pxlclk)) 758 return PTR_ERR(hwdev->pxlclk); 759 760 /* Get the optional framebuffer memory resource */ 761 ret = of_reserved_mem_device_init(dev); 762 if (ret && ret != -ENODEV) 763 return ret; 764 765 dev_set_drvdata(dev, drm); 766 767 /* Enable power management */ 768 pm_runtime_enable(dev); 769 770 /* Resume device to enable the clocks */ 771 if (pm_runtime_enabled(dev)) 772 pm_runtime_get_sync(dev); 773 else 774 malidp_runtime_pm_resume(dev); 775 776 dev_id = of_match_device(malidp_drm_of_match, dev); 777 if (!dev_id) { 778 ret = -EINVAL; 779 goto query_hw_fail; 780 } 781 782 if (!malidp_has_sufficient_address_space(res, dev_id)) { 783 DRM_ERROR("Insufficient address space in device-tree.\n"); 784 ret = -EINVAL; 785 goto query_hw_fail; 786 } 787 788 if (!malidp_is_compatible_hw_id(hwdev, dev_id)) { 789 ret = -EINVAL; 790 goto query_hw_fail; 791 } 792 793 ret = hwdev->hw->query_hw(hwdev); 794 if (ret) { 795 DRM_ERROR("Invalid HW configuration\n"); 796 goto query_hw_fail; 797 } 798 799 version = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_DE_CORE_ID); 800 DRM_INFO("found ARM Mali-DP%3x version r%dp%d\n", version >> 16, 801 (version >> 12) & 0xf, (version >> 8) & 0xf); 802 803 malidp->core_id = version; 804 805 ret = of_property_read_u32(dev->of_node, 806 "arm,malidp-arqos-value", 807 &hwdev->arqos_value); 808 if (ret) 809 hwdev->arqos_value = 0x0; 810 811 /* set the number of lines used for output of RGB data */ 812 ret = of_property_read_u8_array(dev->of_node, 813 "arm,malidp-output-port-lines", 814 output_width, MAX_OUTPUT_CHANNELS); 815 if (ret) 816 goto query_hw_fail; 817 818 for (i = 0; i < MAX_OUTPUT_CHANNELS; i++) 819 out_depth = (out_depth << 8) | (output_width[i] & 0xf); 820 malidp_hw_write(hwdev, out_depth, hwdev->hw->map.out_depth_base); 821 hwdev->output_color_depth = out_depth; 822 823 atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_INIT); 824 init_waitqueue_head(&malidp->wq); 825 826 ret = malidp_init(drm); 827 if (ret < 0) 828 goto query_hw_fail; 829 830 /* Set the CRTC's port so that the encoder component can find it */ 831 malidp->crtc.port = of_graph_get_port_by_id(dev->of_node, 0); 832 833 ret = component_bind_all(dev, drm); 834 if (ret) { 835 DRM_ERROR("Failed to bind all components\n"); 836 goto bind_fail; 837 } 838 839 /* We expect to have a maximum of two encoders one for the actual 840 * display and a virtual one for the writeback connector 841 */ 842 WARN_ON(drm->mode_config.num_encoder > 2); 843 list_for_each_entry(encoder, &drm->mode_config.encoder_list, head) { 844 encoder->possible_clones = 845 (1 << drm->mode_config.num_encoder) - 1; 846 } 847 848 ret = malidp_irq_init(pdev); 849 if (ret < 0) 850 goto irq_init_fail; 851 852 ret = drm_vblank_init(drm, drm->mode_config.num_crtc); 853 if (ret < 0) { 854 DRM_ERROR("failed to initialise vblank\n"); 855 goto vblank_fail; 856 } 857 pm_runtime_put(dev); 858 859 drm_mode_config_reset(drm); 860 861 drm_kms_helper_poll_init(drm); 862 863 ret = drm_dev_register(drm, 0); 864 if (ret) 865 goto register_fail; 866 867 drm_client_setup(drm, NULL); 868 869 return 0; 870 871 register_fail: 872 drm_kms_helper_poll_fini(drm); 873 pm_runtime_get_sync(dev); 874 vblank_fail: 875 malidp_se_irq_fini(hwdev); 876 malidp_de_irq_fini(hwdev); 877 irq_init_fail: 878 drm_atomic_helper_shutdown(drm); 879 component_unbind_all(dev, drm); 880 bind_fail: 881 of_node_put(malidp->crtc.port); 882 malidp->crtc.port = NULL; 883 query_hw_fail: 884 pm_runtime_put(dev); 885 if (pm_runtime_enabled(dev)) 886 pm_runtime_disable(dev); 887 else 888 malidp_runtime_pm_suspend(dev); 889 dev_set_drvdata(dev, NULL); 890 of_reserved_mem_device_release(dev); 891 892 return ret; 893 } 894 895 static void malidp_unbind(struct device *dev) 896 { 897 struct drm_device *drm = dev_get_drvdata(dev); 898 struct malidp_drm *malidp = drm_to_malidp(drm); 899 struct malidp_hw_device *hwdev = malidp->dev; 900 901 drm_dev_unregister(drm); 902 drm_kms_helper_poll_fini(drm); 903 pm_runtime_get_sync(dev); 904 drm_atomic_helper_shutdown(drm); 905 malidp_se_irq_fini(hwdev); 906 malidp_de_irq_fini(hwdev); 907 component_unbind_all(dev, drm); 908 of_node_put(malidp->crtc.port); 909 malidp->crtc.port = NULL; 910 pm_runtime_put(dev); 911 if (pm_runtime_enabled(dev)) 912 pm_runtime_disable(dev); 913 else 914 malidp_runtime_pm_suspend(dev); 915 dev_set_drvdata(dev, NULL); 916 of_reserved_mem_device_release(dev); 917 } 918 919 static const struct component_master_ops malidp_master_ops = { 920 .bind = malidp_bind, 921 .unbind = malidp_unbind, 922 }; 923 924 static int malidp_compare_dev(struct device *dev, void *data) 925 { 926 struct device_node *np = data; 927 928 return dev->of_node == np; 929 } 930 931 static int malidp_platform_probe(struct platform_device *pdev) 932 { 933 struct device_node *port; 934 struct component_match *match = NULL; 935 936 if (!pdev->dev.of_node) 937 return -ENODEV; 938 939 /* there is only one output port inside each device, find it */ 940 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0); 941 if (!port) 942 return -ENODEV; 943 944 drm_of_component_match_add(&pdev->dev, &match, malidp_compare_dev, 945 port); 946 of_node_put(port); 947 return component_master_add_with_match(&pdev->dev, &malidp_master_ops, 948 match); 949 } 950 951 static void malidp_platform_remove(struct platform_device *pdev) 952 { 953 component_master_del(&pdev->dev, &malidp_master_ops); 954 } 955 956 static void malidp_platform_shutdown(struct platform_device *pdev) 957 { 958 drm_atomic_helper_shutdown(platform_get_drvdata(pdev)); 959 } 960 961 static int __maybe_unused malidp_pm_suspend(struct device *dev) 962 { 963 struct drm_device *drm = dev_get_drvdata(dev); 964 965 return drm_mode_config_helper_suspend(drm); 966 } 967 968 static int __maybe_unused malidp_pm_resume(struct device *dev) 969 { 970 struct drm_device *drm = dev_get_drvdata(dev); 971 972 drm_mode_config_helper_resume(drm); 973 974 return 0; 975 } 976 977 static int __maybe_unused malidp_pm_suspend_late(struct device *dev) 978 { 979 if (!pm_runtime_status_suspended(dev)) { 980 malidp_runtime_pm_suspend(dev); 981 pm_runtime_set_suspended(dev); 982 } 983 return 0; 984 } 985 986 static int __maybe_unused malidp_pm_resume_early(struct device *dev) 987 { 988 malidp_runtime_pm_resume(dev); 989 pm_runtime_set_active(dev); 990 return 0; 991 } 992 993 static const struct dev_pm_ops malidp_pm_ops = { 994 SET_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend, malidp_pm_resume) \ 995 SET_LATE_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend_late, malidp_pm_resume_early) \ 996 SET_RUNTIME_PM_OPS(malidp_runtime_pm_suspend, malidp_runtime_pm_resume, NULL) 997 }; 998 999 static struct platform_driver malidp_platform_driver = { 1000 .probe = malidp_platform_probe, 1001 .remove = malidp_platform_remove, 1002 .shutdown = malidp_platform_shutdown, 1003 .driver = { 1004 .name = "mali-dp", 1005 .pm = &malidp_pm_ops, 1006 .of_match_table = malidp_drm_of_match, 1007 .dev_groups = mali_dp_groups, 1008 }, 1009 }; 1010 1011 drm_module_platform_driver(malidp_platform_driver); 1012 1013 MODULE_AUTHOR("Liviu Dudau <Liviu.Dudau@arm.com>"); 1014 MODULE_DESCRIPTION("ARM Mali DP DRM driver"); 1015 MODULE_LICENSE("GPL v2"); 1016