1 /* 2 * Copyright (C) 2013-2015 ARM Limited 3 * Author: Liviu Dudau <Liviu.Dudau@arm.com> 4 * 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file COPYING in the main directory of this archive 7 * for more details. 8 * 9 * Implementation of a CRTC class for the HDLCD driver. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/of_graph.h> 14 15 #include <video/pixel_format.h> 16 #include <video/videomode.h> 17 18 #include <drm/drm_atomic.h> 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_crtc.h> 21 #include <drm/drm_fb_dma_helper.h> 22 #include <drm/drm_framebuffer.h> 23 #include <drm/drm_gem_dma_helper.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_print.h> 26 #include <drm/drm_probe_helper.h> 27 #include <drm/drm_vblank.h> 28 29 #include "hdlcd_drv.h" 30 #include "hdlcd_regs.h" 31 32 /* 33 * The HDLCD controller is a dumb RGB streamer that gets connected to 34 * a single HDMI transmitter or in the case of the ARM Models it gets 35 * emulated by the software that does the actual rendering. 36 * 37 */ 38 39 static void hdlcd_crtc_cleanup(struct drm_crtc *crtc) 40 { 41 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 42 43 /* stop the controller on cleanup */ 44 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); 45 drm_crtc_cleanup(crtc); 46 } 47 48 static int hdlcd_crtc_enable_vblank(struct drm_crtc *crtc) 49 { 50 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 51 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); 52 53 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC); 54 55 return 0; 56 } 57 58 static void hdlcd_crtc_disable_vblank(struct drm_crtc *crtc) 59 { 60 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 61 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); 62 63 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC); 64 } 65 66 static const struct drm_crtc_funcs hdlcd_crtc_funcs = { 67 .destroy = hdlcd_crtc_cleanup, 68 .set_config = drm_atomic_helper_set_config, 69 .page_flip = drm_atomic_helper_page_flip, 70 .reset = drm_atomic_helper_crtc_reset, 71 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 72 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 73 .enable_vblank = hdlcd_crtc_enable_vblank, 74 .disable_vblank = hdlcd_crtc_disable_vblank, 75 }; 76 77 static const struct { 78 u32 fourcc; 79 struct pixel_format pixel; 80 } supported_formats[] = { 81 { DRM_FORMAT_RGB565, PIXEL_FORMAT_RGB565 }, 82 { DRM_FORMAT_XRGB1555, PIXEL_FORMAT_XRGB1555 }, 83 { DRM_FORMAT_RGB888, PIXEL_FORMAT_RGB888 }, 84 { DRM_FORMAT_XRGB8888, PIXEL_FORMAT_XRGB8888 }, 85 { DRM_FORMAT_XBGR8888, PIXEL_FORMAT_XBGR8888 }, 86 { DRM_FORMAT_XRGB2101010, PIXEL_FORMAT_XRGB2101010}, 87 }; 88 89 /* 90 * Setup the HDLCD registers for decoding the pixels out of the framebuffer 91 */ 92 static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc) 93 { 94 unsigned int btpp; 95 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 96 const struct drm_framebuffer *fb = crtc->primary->state->fb; 97 const struct pixel_format *format = NULL; 98 int i; 99 100 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { 101 if (supported_formats[i].fourcc == fb->format->format) 102 format = &supported_formats[i].pixel; 103 } 104 105 if (WARN_ON(!format)) 106 return 0; 107 108 /* HDLCD uses 'bytes per pixel', zero means 1 byte */ 109 btpp = (format->bits_per_pixel + 7) / 8; 110 hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3); 111 112 /* 113 * The format of the HDLCD_REG_<color>_SELECT register is: 114 * - bits[23:16] - default value for that color component 115 * - bits[11:8] - number of bits to extract for each color component 116 * - bits[4:0] - index of the lowest bit to extract 117 * 118 * The default color value is used when bits[11:8] are zero, when the 119 * pixel is outside the visible frame area or when there is a 120 * buffer underrun. 121 */ 122 hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset | 123 #ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN 124 0x00ff0000 | /* show underruns in red */ 125 #endif 126 ((format->red.length & 0xf) << 8)); 127 hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset | 128 ((format->green.length & 0xf) << 8)); 129 hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset | 130 ((format->blue.length & 0xf) << 8)); 131 132 return 0; 133 } 134 135 static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc) 136 { 137 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 138 struct drm_display_mode *m = &crtc->state->adjusted_mode; 139 struct videomode vm; 140 unsigned int polarities, err; 141 142 vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; 143 vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; 144 vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; 145 vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; 146 vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; 147 vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; 148 149 polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA; 150 151 if (m->flags & DRM_MODE_FLAG_PHSYNC) 152 polarities |= HDLCD_POLARITY_HSYNC; 153 if (m->flags & DRM_MODE_FLAG_PVSYNC) 154 polarities |= HDLCD_POLARITY_VSYNC; 155 156 /* Allow max number of outstanding requests and largest burst size */ 157 hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS, 158 HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16); 159 160 hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1); 161 hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1); 162 hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1); 163 hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1); 164 hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1); 165 hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1); 166 hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1); 167 hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1); 168 hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities); 169 170 err = hdlcd_set_pxl_fmt(crtc); 171 if (err) 172 return; 173 174 clk_set_rate(hdlcd->clk, m->crtc_clock * 1000); 175 } 176 177 static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc, 178 struct drm_atomic_state *state) 179 { 180 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 181 182 clk_prepare_enable(hdlcd->clk); 183 hdlcd_crtc_mode_set_nofb(crtc); 184 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1); 185 drm_crtc_vblank_on(crtc); 186 } 187 188 static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc, 189 struct drm_atomic_state *state) 190 { 191 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 192 193 drm_crtc_vblank_off(crtc); 194 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); 195 clk_disable_unprepare(hdlcd->clk); 196 } 197 198 static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc, 199 const struct drm_display_mode *mode) 200 { 201 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); 202 long rate, clk_rate = mode->clock * 1000; 203 204 rate = clk_round_rate(hdlcd->clk, clk_rate); 205 /* 0.1% seems a close enough tolerance for the TDA19988 on Juno */ 206 if (abs(rate - clk_rate) * 1000 > clk_rate) { 207 /* clock required by mode not supported by hardware */ 208 return MODE_NOCLOCK; 209 } 210 211 return MODE_OK; 212 } 213 214 static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc, 215 struct drm_atomic_state *state) 216 { 217 struct drm_pending_vblank_event *event = crtc->state->event; 218 219 if (event) { 220 crtc->state->event = NULL; 221 222 spin_lock_irq(&crtc->dev->event_lock); 223 if (drm_crtc_vblank_get(crtc) == 0) 224 drm_crtc_arm_vblank_event(crtc, event); 225 else 226 drm_crtc_send_vblank_event(crtc, event); 227 spin_unlock_irq(&crtc->dev->event_lock); 228 } 229 } 230 231 static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = { 232 .mode_valid = hdlcd_crtc_mode_valid, 233 .atomic_begin = hdlcd_crtc_atomic_begin, 234 .atomic_enable = hdlcd_crtc_atomic_enable, 235 .atomic_disable = hdlcd_crtc_atomic_disable, 236 }; 237 238 static int hdlcd_plane_atomic_check(struct drm_plane *plane, 239 struct drm_atomic_state *state) 240 { 241 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 242 plane); 243 int i; 244 struct drm_crtc *crtc; 245 struct drm_crtc_state *crtc_state; 246 u32 src_h = new_plane_state->src_h >> 16; 247 248 /* only the HDLCD_REG_FB_LINE_COUNT register has a limit */ 249 if (src_h >= HDLCD_MAX_YRES) { 250 DRM_DEBUG_KMS("Invalid source width: %d\n", src_h); 251 return -EINVAL; 252 } 253 254 for_each_new_crtc_in_state(state, crtc, crtc_state, 255 i) { 256 /* we cannot disable the plane while the CRTC is active */ 257 if (!new_plane_state->fb && crtc_state->active) 258 return -EINVAL; 259 return drm_atomic_helper_check_plane_state(new_plane_state, 260 crtc_state, 261 DRM_PLANE_NO_SCALING, 262 DRM_PLANE_NO_SCALING, 263 false, true); 264 } 265 266 return 0; 267 } 268 269 static void hdlcd_plane_atomic_update(struct drm_plane *plane, 270 struct drm_atomic_state *state) 271 { 272 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 273 plane); 274 struct drm_framebuffer *fb = new_plane_state->fb; 275 struct hdlcd_drm_private *hdlcd; 276 u32 dest_h; 277 dma_addr_t scanout_start; 278 279 if (!fb) 280 return; 281 282 dest_h = drm_rect_height(&new_plane_state->dst); 283 scanout_start = drm_fb_dma_get_gem_addr(fb, new_plane_state, 0); 284 285 hdlcd = drm_to_hdlcd_priv(plane->dev); 286 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]); 287 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]); 288 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1); 289 hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start); 290 } 291 292 static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = { 293 .atomic_check = hdlcd_plane_atomic_check, 294 .atomic_update = hdlcd_plane_atomic_update, 295 }; 296 297 static const struct drm_plane_funcs hdlcd_plane_funcs = { 298 .update_plane = drm_atomic_helper_update_plane, 299 .disable_plane = drm_atomic_helper_disable_plane, 300 .reset = drm_atomic_helper_plane_reset, 301 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 302 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 303 }; 304 305 static struct drm_plane *hdlcd_plane_init(struct drm_device *drm) 306 { 307 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm); 308 struct drm_plane *plane = NULL; 309 u32 formats[ARRAY_SIZE(supported_formats)], i; 310 311 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) 312 formats[i] = supported_formats[i].fourcc; 313 314 plane = drmm_universal_plane_alloc(drm, struct drm_plane, dev, 0xff, 315 &hdlcd_plane_funcs, 316 formats, ARRAY_SIZE(formats), 317 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 318 if (IS_ERR(plane)) 319 return plane; 320 321 drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs); 322 hdlcd->plane = plane; 323 324 return plane; 325 } 326 327 int hdlcd_setup_crtc(struct drm_device *drm) 328 { 329 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm); 330 struct drm_plane *primary; 331 int ret; 332 333 primary = hdlcd_plane_init(drm); 334 if (IS_ERR(primary)) 335 return PTR_ERR(primary); 336 337 ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL, 338 &hdlcd_crtc_funcs, NULL); 339 if (ret) 340 return ret; 341 342 drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs); 343 return 0; 344 } 345