1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef __RAS_SYS_H__ 26 #define __RAS_SYS_H__ 27 #include <linux/stdarg.h> 28 #include <linux/printk.h> 29 #include <linux/dev_printk.h> 30 #include <linux/mempool.h> 31 #include "amdgpu.h" 32 33 #define RAS_DEV_ERR(device, fmt, ...) \ 34 do { \ 35 if (device) \ 36 dev_err(((struct amdgpu_device *)device)->dev, fmt, ##__VA_ARGS__); \ 37 else \ 38 printk(KERN_ERR fmt, ##__VA_ARGS__); \ 39 } while (0) 40 41 #define RAS_DEV_WARN(device, fmt, ...) \ 42 do { \ 43 if (device) \ 44 dev_warn(((struct amdgpu_device *)device)->dev, fmt, ##__VA_ARGS__); \ 45 else \ 46 printk(KERN_WARNING fmt, ##__VA_ARGS__); \ 47 } while (0) 48 49 #define RAS_DEV_WARN_RATELIMITED(device, fmt, ...) \ 50 do { \ 51 if (device) \ 52 dev_warn_ratelimited(((struct amdgpu_device *)device)->dev, \ 53 fmt, ##__VA_ARGS__); \ 54 else \ 55 printk_ratelimited(KERN_WARNING fmt, ##__VA_ARGS__); \ 56 } while (0) 57 58 #define RAS_DEV_INFO(device, fmt, ...) \ 59 do { \ 60 if (device) \ 61 dev_info(((struct amdgpu_device *)device)->dev, fmt, ##__VA_ARGS__); \ 62 else \ 63 printk(KERN_INFO fmt, ##__VA_ARGS__); \ 64 } while (0) 65 66 #define RAS_DEV_DBG(device, fmt, ...) \ 67 do { \ 68 if (device) \ 69 dev_dbg(((struct amdgpu_device *)device)->dev, fmt, ##__VA_ARGS__); \ 70 else \ 71 printk(KERN_DEBUG fmt, ##__VA_ARGS__); \ 72 } while (0) 73 74 #define RAS_INFO(fmt, ...) printk(KERN_INFO fmt, ##__VA_ARGS__) 75 76 #define RAS_DEV_RREG32_SOC15(dev, ip, inst, reg) \ 77 ({ \ 78 struct amdgpu_device *adev = (struct amdgpu_device *)dev; \ 79 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ 80 0, ip##_HWIP, inst); \ 81 }) 82 83 #define RAS_DEV_WREG32_SOC15(dev, ip, inst, reg, value) \ 84 ({ \ 85 struct amdgpu_device *adev = (struct amdgpu_device *)dev; \ 86 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \ 87 value, 0, ip##_HWIP, inst); \ 88 }) 89 90 /* GET_INST returns the physical instance corresponding to a logical instance */ 91 #define RAS_GET_INST(dev, ip, inst) \ 92 ({ \ 93 struct amdgpu_device *adev = (struct amdgpu_device *)dev; \ 94 adev->ip_map.logical_to_dev_inst ? \ 95 adev->ip_map.logical_to_dev_inst(adev, ip##_HWIP, inst) : inst; \ 96 }) 97 98 #define RAS_GET_MASK(dev, ip, mask) \ 99 ({ \ 100 struct amdgpu_device *adev = (struct amdgpu_device *)dev; \ 101 (adev->ip_map.logical_to_dev_mask ? \ 102 adev->ip_map.logical_to_dev_mask(adev, ip##_HWIP, mask) : mask); \ 103 }) 104 105 static inline void *ras_radix_tree_delete_iter(struct radix_tree_root *root, void *iter) 106 { 107 return radix_tree_delete(root, ((struct radix_tree_iter *)iter)->index); 108 } 109 110 static inline long ras_wait_event_interruptible_timeout(void *wq_head, 111 int (*condition)(void *param), void *param, unsigned int timeout) 112 { 113 return wait_event_interruptible_timeout(*(wait_queue_head_t *)wq_head, 114 condition(param), timeout); 115 } 116 117 extern const struct ras_sys_func amdgpu_ras_sys_fn; 118 119 #endif 120