1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef __RAS_SYS_H__ 26 #define __RAS_SYS_H__ 27 #include <linux/stdarg.h> 28 #include <linux/printk.h> 29 #include <linux/dev_printk.h> 30 #include <linux/mempool.h> 31 #include "amdgpu.h" 32 33 /* inject address is 52 bits */ 34 #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) 35 36 #define RAS_DEV_ERR(device, fmt, ...) \ 37 do { \ 38 if (device) \ 39 dev_err(((struct amdgpu_device *)device)->dev, fmt, ##__VA_ARGS__); \ 40 else \ 41 printk(KERN_ERR fmt, ##__VA_ARGS__); \ 42 } while (0) 43 44 #define RAS_DEV_WARN(device, fmt, ...) \ 45 do { \ 46 if (device) \ 47 dev_warn(((struct amdgpu_device *)device)->dev, fmt, ##__VA_ARGS__); \ 48 else \ 49 printk(KERN_WARNING fmt, ##__VA_ARGS__); \ 50 } while (0) 51 52 #define RAS_DEV_WARN_RATELIMITED(device, fmt, ...) \ 53 do { \ 54 if (device) \ 55 dev_warn_ratelimited(((struct amdgpu_device *)device)->dev, \ 56 fmt, ##__VA_ARGS__); \ 57 else \ 58 printk_ratelimited(KERN_WARNING fmt, ##__VA_ARGS__); \ 59 } while (0) 60 61 #define RAS_DEV_INFO(device, fmt, ...) \ 62 do { \ 63 if (device) \ 64 dev_info(((struct amdgpu_device *)device)->dev, fmt, ##__VA_ARGS__); \ 65 else \ 66 printk(KERN_INFO fmt, ##__VA_ARGS__); \ 67 } while (0) 68 69 #define RAS_DEV_DBG(device, fmt, ...) \ 70 do { \ 71 if (device) \ 72 dev_dbg(((struct amdgpu_device *)device)->dev, fmt, ##__VA_ARGS__); \ 73 else \ 74 printk(KERN_DEBUG fmt, ##__VA_ARGS__); \ 75 } while (0) 76 77 #define RAS_INFO(fmt, ...) printk(KERN_INFO fmt, ##__VA_ARGS__) 78 79 #define RAS_DEV_RREG32_SOC15(dev, ip, inst, reg) \ 80 ({ \ 81 struct amdgpu_device *adev = (struct amdgpu_device *)dev; \ 82 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ 83 0, ip##_HWIP, inst); \ 84 }) 85 86 #define RAS_DEV_WREG32_SOC15(dev, ip, inst, reg, value) \ 87 ({ \ 88 struct amdgpu_device *adev = (struct amdgpu_device *)dev; \ 89 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \ 90 value, 0, ip##_HWIP, inst); \ 91 }) 92 93 /* GET_INST returns the physical instance corresponding to a logical instance */ 94 #define RAS_GET_INST(dev, ip, inst) \ 95 ({ \ 96 struct amdgpu_device *adev = (struct amdgpu_device *)dev; \ 97 adev->ip_map.logical_to_dev_inst ? \ 98 adev->ip_map.logical_to_dev_inst(adev, ip##_HWIP, inst) : inst; \ 99 }) 100 101 #define RAS_GET_MASK(dev, ip, mask) \ 102 ({ \ 103 struct amdgpu_device *adev = (struct amdgpu_device *)dev; \ 104 (adev->ip_map.logical_to_dev_mask ? \ 105 adev->ip_map.logical_to_dev_mask(adev, ip##_HWIP, mask) : mask); \ 106 }) 107 108 static inline void *ras_radix_tree_delete_iter(struct radix_tree_root *root, void *iter) 109 { 110 return radix_tree_delete(root, ((struct radix_tree_iter *)iter)->index); 111 } 112 113 static inline long ras_wait_event_interruptible_timeout(void *wq_head, 114 int (*condition)(void *param), void *param, unsigned int timeout) 115 { 116 return wait_event_interruptible_timeout(*(wait_queue_head_t *)wq_head, 117 condition(param), timeout); 118 } 119 120 extern const struct ras_sys_func amdgpu_ras_sys_fn; 121 122 #endif 123