xref: /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c (revision c5dbf04160005e07e8ca7232a7faa77ab1547ae0)
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #define SWSMU_CODE_LAYER_L2
25 
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_dpm.h"
29 #include "amdgpu_smu.h"
30 #include "atomfirmware.h"
31 #include "amdgpu_atomfirmware.h"
32 #include "amdgpu_atombios.h"
33 #include "smu_v13_0.h"
34 #include "smu13_driver_if_aldebaran.h"
35 #include "soc15_common.h"
36 #include "atom.h"
37 #include "aldebaran_ppt.h"
38 #include "smu_v13_0_pptable.h"
39 #include "aldebaran_ppsmc.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/pci.h>
46 #include "amdgpu_ras.h"
47 #include "smu_cmn.h"
48 #include "mp/mp_13_0_2_offset.h"
49 
50 /*
51  * DO NOT use these for err/warn/info/debug messages.
52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53  * They are more MGPU friendly.
54  */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59 
60 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \
61 	[smu_feature] = {1, (aldebaran_feature)}
62 
63 #define FEATURE_MASK(feature) (1ULL << feature)
64 #define SMC_DPM_FEATURE ( \
65 			  FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \
66 			  FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)	| \
67 			  FEATURE_MASK(FEATURE_DPM_UCLK_BIT)	| \
68 			  FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)	| \
69 			  FEATURE_MASK(FEATURE_DPM_FCLK_BIT)	| \
70 			  FEATURE_MASK(FEATURE_DPM_LCLK_BIT)	| \
71 			  FEATURE_MASK(FEATURE_DPM_XGMI_BIT)	| \
72 			  FEATURE_MASK(FEATURE_DPM_VCN_BIT))
73 
74 /* possible frequency drift (1Mhz) */
75 #define EPSILON				1
76 
77 #define smnPCIE_ESM_CTRL			0x111003D0
78 
79 /*
80  * SMU support ECCTABLE since version 68.42.0,
81  * use this to check ECCTALE feature whether support
82  */
83 #define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00
84 
85 /*
86  * SMU support mca_ceumc_addr in ECCTABLE since version 68.55.0,
87  * use this to check mca_ceumc_addr record whether support
88  */
89 #define SUPPORT_ECCTABLE_V2_SMU_VERSION 0x00443700
90 
91 /*
92  * SMU support BAD CHENNEL info MSG since version 68.51.00,
93  * use this to check ECCTALE feature whether support
94  */
95 #define SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION 0x00443300
96 
97 static const struct smu_temperature_range smu13_thermal_policy[] = {
98 	{-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
99 	{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
100 };
101 
102 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
103 	MSG_MAP(TestMessage,			     PPSMC_MSG_TestMessage,			0),
104 	MSG_MAP(GetSmuVersion,			     PPSMC_MSG_GetSmuVersion,			1),
105 	MSG_MAP(GetDriverIfVersion,		     PPSMC_MSG_GetDriverIfVersion,		1),
106 	MSG_MAP(EnableAllSmuFeatures,		     PPSMC_MSG_EnableAllSmuFeatures,		0),
107 	MSG_MAP(DisableAllSmuFeatures,		     PPSMC_MSG_DisableAllSmuFeatures,		0),
108 	MSG_MAP(GetEnabledSmuFeaturesLow,	     PPSMC_MSG_GetEnabledSmuFeaturesLow,	1),
109 	MSG_MAP(GetEnabledSmuFeaturesHigh,	     PPSMC_MSG_GetEnabledSmuFeaturesHigh,	1),
110 	MSG_MAP(SetDriverDramAddrHigh,		     PPSMC_MSG_SetDriverDramAddrHigh,		1),
111 	MSG_MAP(SetDriverDramAddrLow,		     PPSMC_MSG_SetDriverDramAddrLow,		1),
112 	MSG_MAP(SetToolsDramAddrHigh,		     PPSMC_MSG_SetToolsDramAddrHigh,		0),
113 	MSG_MAP(SetToolsDramAddrLow,		     PPSMC_MSG_SetToolsDramAddrLow,		0),
114 	MSG_MAP(TransferTableSmu2Dram,		     PPSMC_MSG_TransferTableSmu2Dram,		1),
115 	MSG_MAP(TransferTableDram2Smu,		     PPSMC_MSG_TransferTableDram2Smu,		0),
116 	MSG_MAP(UseDefaultPPTable,		     PPSMC_MSG_UseDefaultPPTable,		0),
117 	MSG_MAP(SetSystemVirtualDramAddrHigh,	     PPSMC_MSG_SetSystemVirtualDramAddrHigh,	0),
118 	MSG_MAP(SetSystemVirtualDramAddrLow,	     PPSMC_MSG_SetSystemVirtualDramAddrLow,	0),
119 	MSG_MAP(SetSoftMinByFreq,		     PPSMC_MSG_SetSoftMinByFreq,		0),
120 	MSG_MAP(SetSoftMaxByFreq,		     PPSMC_MSG_SetSoftMaxByFreq,		0),
121 	MSG_MAP(SetHardMinByFreq,		     PPSMC_MSG_SetHardMinByFreq,		0),
122 	MSG_MAP(SetHardMaxByFreq,		     PPSMC_MSG_SetHardMaxByFreq,		0),
123 	MSG_MAP(GetMinDpmFreq,			     PPSMC_MSG_GetMinDpmFreq,			0),
124 	MSG_MAP(GetMaxDpmFreq,			     PPSMC_MSG_GetMaxDpmFreq,			0),
125 	MSG_MAP(GetDpmFreqByIndex,		     PPSMC_MSG_GetDpmFreqByIndex,		1),
126 	MSG_MAP(SetWorkloadMask,		     PPSMC_MSG_SetWorkloadMask,			1),
127 	MSG_MAP(GetVoltageByDpm,		     PPSMC_MSG_GetVoltageByDpm,			0),
128 	MSG_MAP(GetVoltageByDpmOverdrive,	     PPSMC_MSG_GetVoltageByDpmOverdrive,	0),
129 	MSG_MAP(SetPptLimit,			     PPSMC_MSG_SetPptLimit,			0),
130 	MSG_MAP(GetPptLimit,			     PPSMC_MSG_GetPptLimit,			1),
131 	MSG_MAP(PrepareMp1ForUnload,		     PPSMC_MSG_PrepareMp1ForUnload,		0),
132 	MSG_MAP(GfxDeviceDriverReset,		     PPSMC_MSG_GfxDriverReset,			0),
133 	MSG_MAP(RunDcBtc,			     PPSMC_MSG_RunDcBtc,			0),
134 	MSG_MAP(DramLogSetDramAddrHigh,		     PPSMC_MSG_DramLogSetDramAddrHigh,		0),
135 	MSG_MAP(DramLogSetDramAddrLow,		     PPSMC_MSG_DramLogSetDramAddrLow,		0),
136 	MSG_MAP(DramLogSetDramSize,		     PPSMC_MSG_DramLogSetDramSize,		0),
137 	MSG_MAP(GetDebugData,			     PPSMC_MSG_GetDebugData,			0),
138 	MSG_MAP(WaflTest,			     PPSMC_MSG_WaflTest,			0),
139 	MSG_MAP(SetMemoryChannelEnable,		     PPSMC_MSG_SetMemoryChannelEnable,		0),
140 	MSG_MAP(SetNumBadHbmPagesRetired,	     PPSMC_MSG_SetNumBadHbmPagesRetired,	0),
141 	MSG_MAP(DFCstateControl,		     PPSMC_MSG_DFCstateControl,			0),
142 	MSG_MAP(GetGmiPwrDnHyst,		     PPSMC_MSG_GetGmiPwrDnHyst,			0),
143 	MSG_MAP(SetGmiPwrDnHyst,		     PPSMC_MSG_SetGmiPwrDnHyst,			0),
144 	MSG_MAP(GmiPwrDnControl,		     PPSMC_MSG_GmiPwrDnControl,			0),
145 	MSG_MAP(EnterGfxoff,			     PPSMC_MSG_EnterGfxoff,			0),
146 	MSG_MAP(ExitGfxoff,			     PPSMC_MSG_ExitGfxoff,			0),
147 	MSG_MAP(SetExecuteDMATest,		     PPSMC_MSG_SetExecuteDMATest,		0),
148 	MSG_MAP(EnableDeterminism,		     PPSMC_MSG_EnableDeterminism,		0),
149 	MSG_MAP(DisableDeterminism,		     PPSMC_MSG_DisableDeterminism,		0),
150 	MSG_MAP(SetUclkDpmMode,			     PPSMC_MSG_SetUclkDpmMode,			0),
151 	MSG_MAP(GfxDriverResetRecovery,		     PPSMC_MSG_GfxDriverResetRecovery,		0),
152 	MSG_MAP(BoardPowerCalibration,		     PPSMC_MSG_BoardPowerCalibration,		0),
153 	MSG_MAP(HeavySBR,                            PPSMC_MSG_HeavySBR,                        0),
154 	MSG_MAP(SetBadHBMPagesRetiredFlagsPerChannel,	PPSMC_MSG_SetBadHBMPagesRetiredFlagsPerChannel,	0),
155 };
156 
157 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
158 	CLK_MAP(GFXCLK, PPCLK_GFXCLK),
159 	CLK_MAP(SCLK,	PPCLK_GFXCLK),
160 	CLK_MAP(SOCCLK, PPCLK_SOCCLK),
161 	CLK_MAP(FCLK, PPCLK_FCLK),
162 	CLK_MAP(UCLK, PPCLK_UCLK),
163 	CLK_MAP(MCLK, PPCLK_UCLK),
164 	CLK_MAP(DCLK, PPCLK_DCLK),
165 	CLK_MAP(VCLK, PPCLK_VCLK),
166 	CLK_MAP(LCLK, 	PPCLK_LCLK),
167 };
168 
169 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = {
170 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, 		FEATURE_DATA_CALCULATIONS),
171 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, 			FEATURE_DPM_GFXCLK_BIT),
172 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, 			FEATURE_DPM_UCLK_BIT),
173 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, 			FEATURE_DPM_SOCCLK_BIT),
174 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, 			FEATURE_DPM_FCLK_BIT),
175 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, 			FEATURE_DPM_LCLK_BIT),
176 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, 				FEATURE_DPM_XGMI_BIT),
177 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, 			FEATURE_DS_GFXCLK_BIT),
178 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, 			FEATURE_DS_SOCCLK_BIT),
179 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, 				FEATURE_DS_LCLK_BIT),
180 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, 				FEATURE_DS_FCLK_BIT),
181 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT,				FEATURE_DS_UCLK_BIT),
182 	ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, 				FEATURE_GFX_SS_BIT),
183 	ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, 				FEATURE_DPM_VCN_BIT),
184 	ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, 			FEATURE_RSMU_SMN_CG_BIT),
185 	ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, 				FEATURE_WAFL_CG_BIT),
186 	ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, 					FEATURE_PPT_BIT),
187 	ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, 					FEATURE_TDC_BIT),
188 	ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, 			FEATURE_APCC_PLUS_BIT),
189 	ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, 			FEATURE_APCC_DFLL_BIT),
190 	ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, 				FEATURE_FUSE_CG_BIT),
191 	ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, 				FEATURE_MP1_CG_BIT),
192 	ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, 			FEATURE_SMUIO_CG_BIT),
193 	ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, 				FEATURE_THM_CG_BIT),
194 	ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, 				FEATURE_CLK_CG_BIT),
195 	ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, 				FEATURE_FW_CTF_BIT),
196 	ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, 				FEATURE_THERMAL_BIT),
197 	ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, 	FEATURE_OUT_OF_BAND_MONITOR_BIT),
198 	ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DWN),
199 	ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, 			FEATURE_DF_CSTATE),
200 };
201 
202 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = {
203 	TAB_MAP(PPTABLE),
204 	TAB_MAP(AVFS_PSM_DEBUG),
205 	TAB_MAP(AVFS_FUSE_OVERRIDE),
206 	TAB_MAP(PMSTATUSLOG),
207 	TAB_MAP(SMU_METRICS),
208 	TAB_MAP(DRIVER_SMU_CONFIG),
209 	TAB_MAP(I2C_COMMANDS),
210 	TAB_MAP(ECCINFO),
211 };
212 
213 static const uint8_t aldebaran_throttler_map[] = {
214 	[THROTTLER_PPT0_BIT]		= (SMU_THROTTLER_PPT0_BIT),
215 	[THROTTLER_PPT1_BIT]		= (SMU_THROTTLER_PPT1_BIT),
216 	[THROTTLER_TDC_GFX_BIT]		= (SMU_THROTTLER_TDC_GFX_BIT),
217 	[THROTTLER_TDC_SOC_BIT]		= (SMU_THROTTLER_TDC_SOC_BIT),
218 	[THROTTLER_TDC_HBM_BIT]		= (SMU_THROTTLER_TDC_MEM_BIT),
219 	[THROTTLER_TEMP_GPU_BIT]	= (SMU_THROTTLER_TEMP_GPU_BIT),
220 	[THROTTLER_TEMP_MEM_BIT]	= (SMU_THROTTLER_TEMP_MEM_BIT),
221 	[THROTTLER_TEMP_VR_GFX_BIT]	= (SMU_THROTTLER_TEMP_VR_GFX_BIT),
222 	[THROTTLER_TEMP_VR_SOC_BIT]	= (SMU_THROTTLER_TEMP_VR_SOC_BIT),
223 	[THROTTLER_TEMP_VR_MEM_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
224 	[THROTTLER_APCC_BIT]		= (SMU_THROTTLER_APCC_BIT),
225 };
226 
227 static int aldebaran_tables_init(struct smu_context *smu)
228 {
229 	struct smu_table_context *smu_table = &smu->smu_table;
230 	struct smu_table *tables = smu_table->tables;
231 
232 	SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
233 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
234 
235 	SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
236 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
237 
238 	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
239 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
240 
241 	SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
242 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
243 
244 	SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
245 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
246 
247 	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
248 	if (!smu_table->metrics_table)
249 		return -ENOMEM;
250 	smu_table->metrics_time = 0;
251 
252 	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
253 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
254 	if (!smu_table->gpu_metrics_table) {
255 		kfree(smu_table->metrics_table);
256 		return -ENOMEM;
257 	}
258 
259 	smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
260 	if (!smu_table->ecc_table)
261 		return -ENOMEM;
262 
263 	return 0;
264 }
265 
266 static int aldebaran_allocate_dpm_context(struct smu_context *smu)
267 {
268 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
269 
270 	smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
271 				       GFP_KERNEL);
272 	if (!smu_dpm->dpm_context)
273 		return -ENOMEM;
274 	smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
275 
276 	return 0;
277 }
278 
279 static int aldebaran_init_smc_tables(struct smu_context *smu)
280 {
281 	int ret = 0;
282 
283 	ret = aldebaran_tables_init(smu);
284 	if (ret)
285 		return ret;
286 
287 	ret = aldebaran_allocate_dpm_context(smu);
288 	if (ret)
289 		return ret;
290 
291 	return smu_v13_0_init_smc_tables(smu);
292 }
293 
294 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu,
295 					      uint32_t *feature_mask, uint32_t num)
296 {
297 	if (num > 2)
298 		return -EINVAL;
299 
300 	/* pptable will handle the features to enable */
301 	memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
302 
303 	return 0;
304 }
305 
306 static int aldebaran_set_default_dpm_table(struct smu_context *smu)
307 {
308 	struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
309 	struct smu_13_0_dpm_table *dpm_table = NULL;
310 	PPTable_t *pptable = smu->smu_table.driver_pptable;
311 	int ret = 0;
312 
313 	/* socclk dpm table setup */
314 	dpm_table = &dpm_context->dpm_tables.soc_table;
315 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
316 		ret = smu_v13_0_set_single_dpm_table(smu,
317 						     SMU_SOCCLK,
318 						     dpm_table);
319 		if (ret)
320 			return ret;
321 	} else {
322 		dpm_table->count = 1;
323 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
324 		dpm_table->dpm_levels[0].enabled = true;
325 		dpm_table->min = dpm_table->dpm_levels[0].value;
326 		dpm_table->max = dpm_table->dpm_levels[0].value;
327 	}
328 
329 	/* gfxclk dpm table setup */
330 	dpm_table = &dpm_context->dpm_tables.gfx_table;
331 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
332 		/* in the case of gfxclk, only fine-grained dpm is honored */
333 		dpm_table->count = 2;
334 		dpm_table->dpm_levels[0].value = pptable->GfxclkFmin;
335 		dpm_table->dpm_levels[0].enabled = true;
336 		dpm_table->dpm_levels[1].value = pptable->GfxclkFmax;
337 		dpm_table->dpm_levels[1].enabled = true;
338 		dpm_table->min = dpm_table->dpm_levels[0].value;
339 		dpm_table->max = dpm_table->dpm_levels[1].value;
340 	} else {
341 		dpm_table->count = 1;
342 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
343 		dpm_table->dpm_levels[0].enabled = true;
344 		dpm_table->min = dpm_table->dpm_levels[0].value;
345 		dpm_table->max = dpm_table->dpm_levels[0].value;
346 	}
347 
348 	/* memclk dpm table setup */
349 	dpm_table = &dpm_context->dpm_tables.uclk_table;
350 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
351 		ret = smu_v13_0_set_single_dpm_table(smu,
352 						     SMU_UCLK,
353 						     dpm_table);
354 		if (ret)
355 			return ret;
356 	} else {
357 		dpm_table->count = 1;
358 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
359 		dpm_table->dpm_levels[0].enabled = true;
360 		dpm_table->min = dpm_table->dpm_levels[0].value;
361 		dpm_table->max = dpm_table->dpm_levels[0].value;
362 	}
363 
364 	/* fclk dpm table setup */
365 	dpm_table = &dpm_context->dpm_tables.fclk_table;
366 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
367 		ret = smu_v13_0_set_single_dpm_table(smu,
368 						     SMU_FCLK,
369 						     dpm_table);
370 		if (ret)
371 			return ret;
372 	} else {
373 		dpm_table->count = 1;
374 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
375 		dpm_table->dpm_levels[0].enabled = true;
376 		dpm_table->min = dpm_table->dpm_levels[0].value;
377 		dpm_table->max = dpm_table->dpm_levels[0].value;
378 	}
379 
380 	return 0;
381 }
382 
383 static int aldebaran_check_powerplay_table(struct smu_context *smu)
384 {
385 	struct smu_table_context *table_context = &smu->smu_table;
386 	struct smu_13_0_powerplay_table *powerplay_table =
387 		table_context->power_play_table;
388 
389 	table_context->thermal_controller_type =
390 		powerplay_table->thermal_controller_type;
391 
392 	return 0;
393 }
394 
395 static int aldebaran_store_powerplay_table(struct smu_context *smu)
396 {
397 	struct smu_table_context *table_context = &smu->smu_table;
398 	struct smu_13_0_powerplay_table *powerplay_table =
399 		table_context->power_play_table;
400 	memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
401 	       sizeof(PPTable_t));
402 
403 	return 0;
404 }
405 
406 static int aldebaran_append_powerplay_table(struct smu_context *smu)
407 {
408 	struct smu_table_context *table_context = &smu->smu_table;
409 	PPTable_t *smc_pptable = table_context->driver_pptable;
410 	struct atom_smc_dpm_info_v4_10 *smc_dpm_table;
411 	int index, ret;
412 
413 	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
414 					   smc_dpm_info);
415 
416 	ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
417 				      (uint8_t **)&smc_dpm_table);
418 	if (ret)
419 		return ret;
420 
421 	dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
422 			smc_dpm_table->table_header.format_revision,
423 			smc_dpm_table->table_header.content_revision);
424 
425 	if ((smc_dpm_table->table_header.format_revision == 4) &&
426 	    (smc_dpm_table->table_header.content_revision == 10))
427 		smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved,
428 				    smc_dpm_table, GfxMaxCurrent);
429 	return 0;
430 }
431 
432 static int aldebaran_setup_pptable(struct smu_context *smu)
433 {
434 	int ret = 0;
435 
436 	/* VBIOS pptable is the first choice */
437 	smu->smu_table.boot_values.pp_table_id = 0;
438 
439 	ret = smu_v13_0_setup_pptable(smu);
440 	if (ret)
441 		return ret;
442 
443 	ret = aldebaran_store_powerplay_table(smu);
444 	if (ret)
445 		return ret;
446 
447 	ret = aldebaran_append_powerplay_table(smu);
448 	if (ret)
449 		return ret;
450 
451 	ret = aldebaran_check_powerplay_table(smu);
452 	if (ret)
453 		return ret;
454 
455 	return ret;
456 }
457 
458 static bool aldebaran_is_primary(struct smu_context *smu)
459 {
460 	struct amdgpu_device *adev = smu->adev;
461 
462 	if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)
463 		return adev->smuio.funcs->get_die_id(adev) == 0;
464 
465 	return true;
466 }
467 
468 static int aldebaran_run_board_btc(struct smu_context *smu)
469 {
470 	int ret;
471 
472 	if (!aldebaran_is_primary(smu))
473 		return 0;
474 
475 	if (smu->smc_fw_version <= 0x00441d00)
476 		return 0;
477 
478 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL);
479 	if (ret)
480 		dev_err(smu->adev->dev, "Board power calibration failed!\n");
481 
482 	return ret;
483 }
484 
485 static int aldebaran_run_btc(struct smu_context *smu)
486 {
487 	int ret;
488 
489 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
490 	if (ret)
491 		dev_err(smu->adev->dev, "RunDcBtc failed!\n");
492 	else
493 		ret = aldebaran_run_board_btc(smu);
494 
495 	return ret;
496 }
497 
498 static int aldebaran_populate_umd_state_clk(struct smu_context *smu)
499 {
500 	struct smu_13_0_dpm_context *dpm_context =
501 		smu->smu_dpm.dpm_context;
502 	struct smu_13_0_dpm_table *gfx_table =
503 		&dpm_context->dpm_tables.gfx_table;
504 	struct smu_13_0_dpm_table *mem_table =
505 		&dpm_context->dpm_tables.uclk_table;
506 	struct smu_13_0_dpm_table *soc_table =
507 		&dpm_context->dpm_tables.soc_table;
508 	struct smu_umd_pstate_table *pstate_table =
509 		&smu->pstate_table;
510 
511 	pstate_table->gfxclk_pstate.min = gfx_table->min;
512 	pstate_table->gfxclk_pstate.peak = gfx_table->max;
513 	pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
514 	pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
515 
516 	pstate_table->uclk_pstate.min = mem_table->min;
517 	pstate_table->uclk_pstate.peak = mem_table->max;
518 	pstate_table->uclk_pstate.curr.min = mem_table->min;
519 	pstate_table->uclk_pstate.curr.max = mem_table->max;
520 
521 	pstate_table->socclk_pstate.min = soc_table->min;
522 	pstate_table->socclk_pstate.peak = soc_table->max;
523 	pstate_table->socclk_pstate.curr.min = soc_table->min;
524 	pstate_table->socclk_pstate.curr.max = soc_table->max;
525 
526 	if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&
527 	    mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&
528 	    soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) {
529 		pstate_table->gfxclk_pstate.standard =
530 			gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value;
531 		pstate_table->uclk_pstate.standard =
532 			mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value;
533 		pstate_table->socclk_pstate.standard =
534 			soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value;
535 	} else {
536 		pstate_table->gfxclk_pstate.standard =
537 			pstate_table->gfxclk_pstate.min;
538 		pstate_table->uclk_pstate.standard =
539 			pstate_table->uclk_pstate.min;
540 		pstate_table->socclk_pstate.standard =
541 			pstate_table->socclk_pstate.min;
542 	}
543 
544 	return 0;
545 }
546 
547 static void aldebaran_get_clk_table(struct smu_context *smu,
548 				    struct pp_clock_levels_with_latency *clocks,
549 				    struct smu_13_0_dpm_table *dpm_table)
550 {
551 	uint32_t i;
552 
553 	clocks->num_levels = min_t(uint32_t,
554 				   dpm_table->count,
555 				   (uint32_t)PP_MAX_CLOCK_LEVELS);
556 
557 	for (i = 0; i < clocks->num_levels; i++) {
558 		clocks->data[i].clocks_in_khz =
559 			dpm_table->dpm_levels[i].value * 1000;
560 		clocks->data[i].latency_in_us = 0;
561 	}
562 
563 }
564 
565 static int aldebaran_freqs_in_same_level(int32_t frequency1,
566 					 int32_t frequency2)
567 {
568 	return (abs(frequency1 - frequency2) <= EPSILON);
569 }
570 
571 static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
572 					  MetricsMember_t member,
573 					  uint32_t *value)
574 {
575 	struct smu_table_context *smu_table = &smu->smu_table;
576 	SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
577 	int ret = 0;
578 
579 	ret = smu_cmn_get_metrics_table(smu,
580 					NULL,
581 					false);
582 	if (ret)
583 		return ret;
584 
585 	switch (member) {
586 	case METRICS_CURR_GFXCLK:
587 		*value = metrics->CurrClock[PPCLK_GFXCLK];
588 		break;
589 	case METRICS_CURR_SOCCLK:
590 		*value = metrics->CurrClock[PPCLK_SOCCLK];
591 		break;
592 	case METRICS_CURR_UCLK:
593 		*value = metrics->CurrClock[PPCLK_UCLK];
594 		break;
595 	case METRICS_CURR_VCLK:
596 		*value = metrics->CurrClock[PPCLK_VCLK];
597 		break;
598 	case METRICS_CURR_DCLK:
599 		*value = metrics->CurrClock[PPCLK_DCLK];
600 		break;
601 	case METRICS_CURR_FCLK:
602 		*value = metrics->CurrClock[PPCLK_FCLK];
603 		break;
604 	case METRICS_AVERAGE_GFXCLK:
605 		*value = metrics->AverageGfxclkFrequency;
606 		break;
607 	case METRICS_AVERAGE_SOCCLK:
608 		*value = metrics->AverageSocclkFrequency;
609 		break;
610 	case METRICS_AVERAGE_UCLK:
611 		*value = metrics->AverageUclkFrequency;
612 		break;
613 	case METRICS_AVERAGE_GFXACTIVITY:
614 		*value = metrics->AverageGfxActivity;
615 		break;
616 	case METRICS_AVERAGE_MEMACTIVITY:
617 		*value = metrics->AverageUclkActivity;
618 		break;
619 	case METRICS_AVERAGE_SOCKETPOWER:
620 		/* Valid power data is available only from primary die */
621 		if (aldebaran_is_primary(smu))
622 			*value = metrics->AverageSocketPower << 8;
623 		else
624 			ret = -EOPNOTSUPP;
625 		break;
626 	case METRICS_TEMPERATURE_EDGE:
627 		*value = metrics->TemperatureEdge *
628 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
629 		break;
630 	case METRICS_TEMPERATURE_HOTSPOT:
631 		*value = metrics->TemperatureHotspot *
632 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
633 		break;
634 	case METRICS_TEMPERATURE_MEM:
635 		*value = metrics->TemperatureHBM *
636 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
637 		break;
638 	case METRICS_TEMPERATURE_VRGFX:
639 		*value = metrics->TemperatureVrGfx *
640 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
641 		break;
642 	case METRICS_TEMPERATURE_VRSOC:
643 		*value = metrics->TemperatureVrSoc *
644 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
645 		break;
646 	case METRICS_TEMPERATURE_VRMEM:
647 		*value = metrics->TemperatureVrMem *
648 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
649 		break;
650 	case METRICS_THROTTLER_STATUS:
651 		*value = metrics->ThrottlerStatus;
652 		break;
653 	case METRICS_UNIQUE_ID_UPPER32:
654 		*value = metrics->PublicSerialNumUpper32;
655 		break;
656 	case METRICS_UNIQUE_ID_LOWER32:
657 		*value = metrics->PublicSerialNumLower32;
658 		break;
659 	default:
660 		*value = UINT_MAX;
661 		break;
662 	}
663 
664 	return ret;
665 }
666 
667 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu,
668 						   enum smu_clk_type clk_type,
669 						   uint32_t *value)
670 {
671 	MetricsMember_t member_type;
672 	int clk_id = 0;
673 
674 	if (!value)
675 		return -EINVAL;
676 
677 	clk_id = smu_cmn_to_asic_specific_index(smu,
678 						CMN2ASIC_MAPPING_CLK,
679 						clk_type);
680 	if (clk_id < 0)
681 		return -EINVAL;
682 
683 	switch (clk_id) {
684 	case PPCLK_GFXCLK:
685 		/*
686 		 * CurrClock[clk_id] can provide accurate
687 		 *   output only when the dpm feature is enabled.
688 		 * We can use Average_* for dpm disabled case.
689 		 *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
690 		 */
691 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
692 			member_type = METRICS_CURR_GFXCLK;
693 		else
694 			member_type = METRICS_AVERAGE_GFXCLK;
695 		break;
696 	case PPCLK_UCLK:
697 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
698 			member_type = METRICS_CURR_UCLK;
699 		else
700 			member_type = METRICS_AVERAGE_UCLK;
701 		break;
702 	case PPCLK_SOCCLK:
703 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
704 			member_type = METRICS_CURR_SOCCLK;
705 		else
706 			member_type = METRICS_AVERAGE_SOCCLK;
707 		break;
708 	case PPCLK_VCLK:
709 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
710 			member_type = METRICS_CURR_VCLK;
711 		else
712 			member_type = METRICS_AVERAGE_VCLK;
713 		break;
714 	case PPCLK_DCLK:
715 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
716 			member_type = METRICS_CURR_DCLK;
717 		else
718 			member_type = METRICS_AVERAGE_DCLK;
719 		break;
720 	case PPCLK_FCLK:
721 		member_type = METRICS_CURR_FCLK;
722 		break;
723 	default:
724 		return -EINVAL;
725 	}
726 
727 	return aldebaran_get_smu_metrics_data(smu,
728 					      member_type,
729 					      value);
730 }
731 
732 static int aldebaran_emit_clk_levels(struct smu_context *smu,
733 				     enum smu_clk_type type, char *buf, int *offset)
734 {
735 	int ret = 0;
736 	struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
737 	struct pp_clock_levels_with_latency clocks;
738 	struct smu_13_0_dpm_table *single_dpm_table;
739 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
740 	struct smu_13_0_dpm_context *dpm_context = NULL;
741 	uint32_t i;
742 	int display_levels;
743 	uint32_t freq_values[3] = {0};
744 	uint32_t min_clk, max_clk, cur_value = 0;
745 	bool freq_match;
746 	unsigned int clock_mhz;
747 	static const char attempt_string[] = "Attempt to get current";
748 
749 	if (amdgpu_ras_intr_triggered()) {
750 		*offset += sysfs_emit_at(buf, *offset, "unavailable\n");
751 		return -EBUSY;
752 	}
753 
754 	dpm_context = smu_dpm->dpm_context;
755 
756 	switch (type) {
757 
758 	case SMU_OD_SCLK:
759 		*offset += sysfs_emit_at(buf, *offset, "%s:\n", "GFXCLK");
760 		fallthrough;
761 	case SMU_SCLK:
762 		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &cur_value);
763 		if (ret) {
764 			dev_err(smu->adev->dev, "%s gfx clk Failed!", attempt_string);
765 			return ret;
766 		}
767 
768 		single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
769 		aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
770 
771 		display_levels = (clocks.num_levels == 1) ? 1 : 2;
772 
773 		min_clk = pstate_table->gfxclk_pstate.curr.min;
774 		max_clk = pstate_table->gfxclk_pstate.curr.max;
775 
776 		freq_values[0] = min_clk;
777 		freq_values[1] = max_clk;
778 
779 		/* fine-grained dpm has only 2 levels */
780 		if (cur_value > min_clk && cur_value < max_clk) {
781 			display_levels++;
782 			freq_values[2] = max_clk;
783 			freq_values[1] = cur_value;
784 		}
785 		break;
786 
787 	case SMU_OD_MCLK:
788 		*offset += sysfs_emit_at(buf, *offset, "%s:\n", "MCLK");
789 		fallthrough;
790 	case SMU_MCLK:
791 		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &cur_value);
792 		if (ret) {
793 			dev_err(smu->adev->dev, "%s mclk Failed!", attempt_string);
794 			return ret;
795 		}
796 
797 		single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
798 		aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
799 		break;
800 
801 	case SMU_SOCCLK:
802 		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &cur_value);
803 		if (ret) {
804 			dev_err(smu->adev->dev, "%s socclk Failed!", attempt_string);
805 			return ret;
806 		}
807 
808 		single_dpm_table = &(dpm_context->dpm_tables.soc_table);
809 		aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
810 		break;
811 
812 	case SMU_FCLK:
813 		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &cur_value);
814 		if (ret) {
815 			dev_err(smu->adev->dev, "%s fclk Failed!", attempt_string);
816 			return ret;
817 		}
818 
819 		single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
820 		aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
821 		break;
822 
823 	case SMU_VCLK:
824 		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &cur_value);
825 		if (ret) {
826 			dev_err(smu->adev->dev, "%s vclk Failed!", attempt_string);
827 			return ret;
828 		}
829 
830 		single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
831 		aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
832 		break;
833 
834 	case SMU_DCLK:
835 		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &cur_value);
836 		if (ret) {
837 			dev_err(smu->adev->dev, "%s dclk Failed!", attempt_string);
838 			return ret;
839 		}
840 
841 		single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
842 		aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
843 		break;
844 
845 	default:
846 		return -EINVAL;
847 	}
848 
849 	switch (type) {
850 	case SMU_OD_SCLK:
851 	case SMU_SCLK:
852 		for (i = 0; i < display_levels; i++) {
853 			clock_mhz = freq_values[i];
854 			freq_match = aldebaran_freqs_in_same_level(clock_mhz, cur_value);
855 			freq_match |= (display_levels == 1);
856 
857 			*offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", i,
858 				clock_mhz,
859 				(freq_match) ? "*" : "");
860 		}
861 		break;
862 
863 	case SMU_OD_MCLK:
864 	case SMU_MCLK:
865 	case SMU_SOCCLK:
866 	case SMU_FCLK:
867 	case SMU_VCLK:
868 	case SMU_DCLK:
869 		for (i = 0; i < clocks.num_levels; i++) {
870 			clock_mhz = clocks.data[i].clocks_in_khz / 1000;
871 			freq_match = aldebaran_freqs_in_same_level(clock_mhz, cur_value);
872 			freq_match |= (clocks.num_levels == 1);
873 
874 			*offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
875 				i, clock_mhz,
876 				(freq_match) ? "*" : "");
877 		}
878 		break;
879 	default:
880 		return -EINVAL;
881 	}
882 
883 	return 0;
884 }
885 
886 static int aldebaran_upload_dpm_level(struct smu_context *smu,
887 				      bool max,
888 				      uint32_t feature_mask,
889 				      uint32_t level)
890 {
891 	struct smu_13_0_dpm_context *dpm_context =
892 		smu->smu_dpm.dpm_context;
893 	uint32_t freq;
894 	int ret = 0;
895 
896 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
897 	    (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) {
898 		freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
899 		ret = smu_cmn_send_smc_msg_with_param(smu,
900 						      (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
901 						      (PPCLK_GFXCLK << 16) | (freq & 0xffff),
902 						      NULL);
903 		if (ret) {
904 			dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
905 				max ? "max" : "min");
906 			return ret;
907 		}
908 	}
909 
910 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
911 	    (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) {
912 		freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
913 		ret = smu_cmn_send_smc_msg_with_param(smu,
914 						      (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
915 						      (PPCLK_UCLK << 16) | (freq & 0xffff),
916 						      NULL);
917 		if (ret) {
918 			dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
919 				max ? "max" : "min");
920 			return ret;
921 		}
922 	}
923 
924 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
925 	    (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) {
926 		freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
927 		ret = smu_cmn_send_smc_msg_with_param(smu,
928 						      (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
929 						      (PPCLK_SOCCLK << 16) | (freq & 0xffff),
930 						      NULL);
931 		if (ret) {
932 			dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
933 				max ? "max" : "min");
934 			return ret;
935 		}
936 	}
937 
938 	return ret;
939 }
940 
941 static int aldebaran_force_clk_levels(struct smu_context *smu,
942 				      enum smu_clk_type type, uint32_t mask)
943 {
944 	struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
945 	struct smu_13_0_dpm_table *single_dpm_table = NULL;
946 	uint32_t soft_min_level, soft_max_level;
947 	int ret = 0;
948 
949 	soft_min_level = mask ? (ffs(mask) - 1) : 0;
950 	soft_max_level = mask ? (fls(mask) - 1) : 0;
951 
952 	switch (type) {
953 	case SMU_SCLK:
954 		single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
955 		if (soft_max_level >= single_dpm_table->count) {
956 			dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
957 				soft_max_level, single_dpm_table->count - 1);
958 			ret = -EINVAL;
959 			break;
960 		}
961 
962 		ret = aldebaran_upload_dpm_level(smu,
963 						 false,
964 						 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
965 						 soft_min_level);
966 		if (ret) {
967 			dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
968 			break;
969 		}
970 
971 		ret = aldebaran_upload_dpm_level(smu,
972 						 true,
973 						 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
974 						 soft_max_level);
975 		if (ret)
976 			dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
977 
978 		break;
979 
980 	case SMU_MCLK:
981 	case SMU_SOCCLK:
982 	case SMU_FCLK:
983 		/*
984 		 * Should not arrive here since aldebaran does not
985 		 * support mclk/socclk/fclk softmin/softmax settings
986 		 */
987 		ret = -EINVAL;
988 		break;
989 
990 	default:
991 		break;
992 	}
993 
994 	return ret;
995 }
996 
997 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu,
998 						   struct smu_temperature_range *range)
999 {
1000 	struct smu_table_context *table_context = &smu->smu_table;
1001 	struct smu_13_0_powerplay_table *powerplay_table =
1002 		table_context->power_play_table;
1003 	PPTable_t *pptable = smu->smu_table.driver_pptable;
1004 
1005 	if (!range)
1006 		return -EINVAL;
1007 
1008 	memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1009 
1010 	range->hotspot_crit_max = pptable->ThotspotLimit *
1011 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1012 	range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1013 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1014 	range->mem_crit_max = pptable->TmemLimit *
1015 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1016 	range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1017 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1018 	range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1019 
1020 	return 0;
1021 }
1022 
1023 static int aldebaran_get_current_activity_percent(struct smu_context *smu,
1024 						  enum amd_pp_sensors sensor,
1025 						  uint32_t *value)
1026 {
1027 	int ret = 0;
1028 
1029 	if (!value)
1030 		return -EINVAL;
1031 
1032 	switch (sensor) {
1033 	case AMDGPU_PP_SENSOR_GPU_LOAD:
1034 		ret = aldebaran_get_smu_metrics_data(smu,
1035 						     METRICS_AVERAGE_GFXACTIVITY,
1036 						     value);
1037 		break;
1038 	case AMDGPU_PP_SENSOR_MEM_LOAD:
1039 		ret = aldebaran_get_smu_metrics_data(smu,
1040 						     METRICS_AVERAGE_MEMACTIVITY,
1041 						     value);
1042 		break;
1043 	default:
1044 		dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1045 		return -EINVAL;
1046 	}
1047 
1048 	return ret;
1049 }
1050 
1051 static int aldebaran_thermal_get_temperature(struct smu_context *smu,
1052 					     enum amd_pp_sensors sensor,
1053 					     uint32_t *value)
1054 {
1055 	int ret = 0;
1056 
1057 	if (!value)
1058 		return -EINVAL;
1059 
1060 	switch (sensor) {
1061 	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1062 		ret = aldebaran_get_smu_metrics_data(smu,
1063 						     METRICS_TEMPERATURE_HOTSPOT,
1064 						     value);
1065 		break;
1066 	case AMDGPU_PP_SENSOR_EDGE_TEMP:
1067 		ret = aldebaran_get_smu_metrics_data(smu,
1068 						     METRICS_TEMPERATURE_EDGE,
1069 						     value);
1070 		break;
1071 	case AMDGPU_PP_SENSOR_MEM_TEMP:
1072 		ret = aldebaran_get_smu_metrics_data(smu,
1073 						     METRICS_TEMPERATURE_MEM,
1074 						     value);
1075 		break;
1076 	default:
1077 		dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1078 		return -EINVAL;
1079 	}
1080 
1081 	return ret;
1082 }
1083 
1084 static int aldebaran_read_sensor(struct smu_context *smu,
1085 				 enum amd_pp_sensors sensor,
1086 				 void *data, uint32_t *size)
1087 {
1088 	int ret = 0;
1089 
1090 	if (amdgpu_ras_intr_triggered())
1091 		return 0;
1092 
1093 	if (!data || !size)
1094 		return -EINVAL;
1095 
1096 	switch (sensor) {
1097 	case AMDGPU_PP_SENSOR_MEM_LOAD:
1098 	case AMDGPU_PP_SENSOR_GPU_LOAD:
1099 		ret = aldebaran_get_current_activity_percent(smu,
1100 							     sensor,
1101 							     (uint32_t *)data);
1102 		*size = 4;
1103 		break;
1104 	case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1105 		ret = aldebaran_get_smu_metrics_data(smu,
1106 						     METRICS_AVERAGE_SOCKETPOWER,
1107 						     (uint32_t *)data);
1108 		*size = 4;
1109 		break;
1110 	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1111 	case AMDGPU_PP_SENSOR_EDGE_TEMP:
1112 	case AMDGPU_PP_SENSOR_MEM_TEMP:
1113 		ret = aldebaran_thermal_get_temperature(smu, sensor,
1114 							(uint32_t *)data);
1115 		*size = 4;
1116 		break;
1117 	case AMDGPU_PP_SENSOR_GFX_MCLK:
1118 		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1119 		/* the output clock frequency in 10K unit */
1120 		*(uint32_t *)data *= 100;
1121 		*size = 4;
1122 		break;
1123 	case AMDGPU_PP_SENSOR_GFX_SCLK:
1124 		ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1125 		*(uint32_t *)data *= 100;
1126 		*size = 4;
1127 		break;
1128 	case AMDGPU_PP_SENSOR_VDDGFX:
1129 		ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1130 		*size = 4;
1131 		break;
1132 	case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1133 	default:
1134 		ret = -EOPNOTSUPP;
1135 		break;
1136 	}
1137 
1138 	return ret;
1139 }
1140 
1141 static int aldebaran_get_power_limit(struct smu_context *smu,
1142 						uint32_t *current_power_limit,
1143 						uint32_t *default_power_limit,
1144 						uint32_t *max_power_limit,
1145 						uint32_t *min_power_limit)
1146 {
1147 	PPTable_t *pptable = smu->smu_table.driver_pptable;
1148 	uint32_t power_limit = 0;
1149 	int ret;
1150 
1151 	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1152 		if (current_power_limit)
1153 			*current_power_limit = 0;
1154 		if (default_power_limit)
1155 			*default_power_limit = 0;
1156 		if (max_power_limit)
1157 			*max_power_limit = 0;
1158 		if (min_power_limit)
1159 			*min_power_limit = 0;
1160 		dev_warn(smu->adev->dev,
1161 			"PPT feature is not enabled, power values can't be fetched.");
1162 
1163 		return 0;
1164 	}
1165 
1166 	/* Valid power data is available only from primary die.
1167 	 * For secondary die show the value as 0.
1168 	 */
1169 	if (aldebaran_is_primary(smu)) {
1170 		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit,
1171 					   &power_limit);
1172 
1173 		if (ret) {
1174 			/* the last hope to figure out the ppt limit */
1175 			if (!pptable) {
1176 				dev_err(smu->adev->dev,
1177 					"Cannot get PPT limit due to pptable missing!");
1178 				return -EINVAL;
1179 			}
1180 			power_limit = pptable->PptLimit;
1181 		}
1182 	}
1183 
1184 	if (current_power_limit)
1185 		*current_power_limit = power_limit;
1186 	if (default_power_limit)
1187 		*default_power_limit = power_limit;
1188 
1189 	if (max_power_limit) {
1190 		if (pptable)
1191 			*max_power_limit = pptable->PptLimit;
1192 	}
1193 
1194 	if (min_power_limit)
1195 		*min_power_limit = 0;
1196 
1197 	return 0;
1198 }
1199 
1200 static int aldebaran_set_power_limit(struct smu_context *smu,
1201 				     enum smu_ppt_limit_type limit_type,
1202 				     uint32_t limit)
1203 {
1204 	/* Power limit can be set only through primary die */
1205 	if (aldebaran_is_primary(smu))
1206 		return smu_v13_0_set_power_limit(smu, limit_type, limit);
1207 
1208 	return -EINVAL;
1209 }
1210 
1211 static int aldebaran_system_features_control(struct  smu_context *smu, bool enable)
1212 {
1213 	int ret;
1214 
1215 	ret = smu_v13_0_system_features_control(smu, enable);
1216 	if (!ret && enable)
1217 		ret = aldebaran_run_btc(smu);
1218 
1219 	return ret;
1220 }
1221 
1222 static int aldebaran_set_performance_level(struct smu_context *smu,
1223 					   enum amd_dpm_forced_level level)
1224 {
1225 	struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1226 	struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1227 	struct smu_13_0_dpm_table *gfx_table =
1228 		&dpm_context->dpm_tables.gfx_table;
1229 	struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1230 
1231 	/* Disable determinism if switching to another mode */
1232 	if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1233 	    (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1234 		smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1235 		pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1236 	}
1237 
1238 	switch (level) {
1239 
1240 	case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1241 		return 0;
1242 
1243 	case AMD_DPM_FORCED_LEVEL_HIGH:
1244 	case AMD_DPM_FORCED_LEVEL_LOW:
1245 	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1246 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1247 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1248 	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1249 	default:
1250 		break;
1251 	}
1252 
1253 	return smu_v13_0_set_performance_level(smu, level);
1254 }
1255 
1256 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
1257 					  enum smu_clk_type clk_type,
1258 					  uint32_t min,
1259 					  uint32_t max)
1260 {
1261 	struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1262 	struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1263 	struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1264 	struct amdgpu_device *adev = smu->adev;
1265 	uint32_t min_clk;
1266 	uint32_t max_clk;
1267 	int ret = 0;
1268 
1269 	if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK)
1270 		return -EINVAL;
1271 
1272 	if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1273 			&& (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1274 		return -EINVAL;
1275 
1276 	if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1277 		if (min >= max) {
1278 			dev_err(smu->adev->dev,
1279 				"Minimum GFX clk should be less than the maximum allowed clock\n");
1280 			return -EINVAL;
1281 		}
1282 
1283 		if ((min == pstate_table->gfxclk_pstate.curr.min) &&
1284 		    (max == pstate_table->gfxclk_pstate.curr.max))
1285 			return 0;
1286 
1287 		ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK,
1288 							    min, max);
1289 		if (!ret) {
1290 			pstate_table->gfxclk_pstate.curr.min = min;
1291 			pstate_table->gfxclk_pstate.curr.max = max;
1292 		}
1293 
1294 		return ret;
1295 	}
1296 
1297 	if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1298 		if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
1299 			(max > dpm_context->dpm_tables.gfx_table.max)) {
1300 			dev_warn(adev->dev,
1301 					"Invalid max frequency %d MHz specified for determinism\n", max);
1302 			return -EINVAL;
1303 		}
1304 
1305 		/* Restore default min/max clocks and enable determinism */
1306 		min_clk = dpm_context->dpm_tables.gfx_table.min;
1307 		max_clk = dpm_context->dpm_tables.gfx_table.max;
1308 		ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1309 		if (!ret) {
1310 			usleep_range(500, 1000);
1311 			ret = smu_cmn_send_smc_msg_with_param(smu,
1312 					SMU_MSG_EnableDeterminism,
1313 					max, NULL);
1314 			if (ret) {
1315 				dev_err(adev->dev,
1316 						"Failed to enable determinism at GFX clock %d MHz\n", max);
1317 			} else {
1318 				pstate_table->gfxclk_pstate.curr.min = min_clk;
1319 				pstate_table->gfxclk_pstate.curr.max = max;
1320 			}
1321 		}
1322 	}
1323 
1324 	return ret;
1325 }
1326 
1327 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
1328 							long input[], uint32_t size)
1329 {
1330 	struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1331 	struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1332 	struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1333 	uint32_t min_clk;
1334 	uint32_t max_clk;
1335 	int ret = 0;
1336 
1337 	/* Only allowed in manual or determinism mode */
1338 	if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1339 			&& (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1340 		return -EINVAL;
1341 
1342 	switch (type) {
1343 	case PP_OD_EDIT_SCLK_VDDC_TABLE:
1344 		if (size != 2) {
1345 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
1346 			return -EINVAL;
1347 		}
1348 
1349 		if (input[0] == 0) {
1350 			if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
1351 				dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
1352 					input[1], dpm_context->dpm_tables.gfx_table.min);
1353 				pstate_table->gfxclk_pstate.custom.min =
1354 					pstate_table->gfxclk_pstate.curr.min;
1355 				return -EINVAL;
1356 			}
1357 
1358 			pstate_table->gfxclk_pstate.custom.min = input[1];
1359 		} else if (input[0] == 1) {
1360 			if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
1361 				dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1362 					input[1], dpm_context->dpm_tables.gfx_table.max);
1363 				pstate_table->gfxclk_pstate.custom.max =
1364 					pstate_table->gfxclk_pstate.curr.max;
1365 				return -EINVAL;
1366 			}
1367 
1368 			pstate_table->gfxclk_pstate.custom.max = input[1];
1369 		} else {
1370 			return -EINVAL;
1371 		}
1372 		break;
1373 	case PP_OD_RESTORE_DEFAULT_TABLE:
1374 		if (size != 0) {
1375 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
1376 			return -EINVAL;
1377 		} else {
1378 			/* Use the default frequencies for manual and determinism mode */
1379 			min_clk = dpm_context->dpm_tables.gfx_table.min;
1380 			max_clk = dpm_context->dpm_tables.gfx_table.max;
1381 
1382 			return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1383 		}
1384 		break;
1385 	case PP_OD_COMMIT_DPM_TABLE:
1386 		if (size != 0) {
1387 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
1388 			return -EINVAL;
1389 		} else {
1390 			if (!pstate_table->gfxclk_pstate.custom.min)
1391 				pstate_table->gfxclk_pstate.custom.min =
1392 					pstate_table->gfxclk_pstate.curr.min;
1393 
1394 			if (!pstate_table->gfxclk_pstate.custom.max)
1395 				pstate_table->gfxclk_pstate.custom.max =
1396 					pstate_table->gfxclk_pstate.curr.max;
1397 
1398 			min_clk = pstate_table->gfxclk_pstate.custom.min;
1399 			max_clk = pstate_table->gfxclk_pstate.custom.max;
1400 
1401 			return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1402 		}
1403 		break;
1404 	default:
1405 		return -ENOSYS;
1406 	}
1407 
1408 	return ret;
1409 }
1410 
1411 static bool aldebaran_is_dpm_running(struct smu_context *smu)
1412 {
1413 	int ret;
1414 	uint64_t feature_enabled;
1415 
1416 	ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1417 	if (ret)
1418 		return false;
1419 	return !!(feature_enabled & SMC_DPM_FEATURE);
1420 }
1421 
1422 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
1423 			      struct i2c_msg *msg, int num_msgs)
1424 {
1425 	struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
1426 	struct amdgpu_device *adev = smu_i2c->adev;
1427 	struct smu_context *smu = adev->powerplay.pp_handle;
1428 	struct smu_table_context *smu_table = &smu->smu_table;
1429 	struct smu_table *table = &smu_table->driver_table;
1430 	SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1431 	int i, j, r, c;
1432 	u16 dir;
1433 
1434 	if (!adev->pm.dpm_enabled)
1435 		return -EBUSY;
1436 
1437 	req = kzalloc(sizeof(*req), GFP_KERNEL);
1438 	if (!req)
1439 		return -ENOMEM;
1440 
1441 	req->I2CcontrollerPort = smu_i2c->port;
1442 	req->I2CSpeed = I2C_SPEED_FAST_400K;
1443 	req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1444 	dir = msg[0].flags & I2C_M_RD;
1445 
1446 	for (c = i = 0; i < num_msgs; i++) {
1447 		for (j = 0; j < msg[i].len; j++, c++) {
1448 			SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1449 
1450 			if (!(msg[i].flags & I2C_M_RD)) {
1451 				/* write */
1452 				cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
1453 				cmd->ReadWriteData = msg[i].buf[j];
1454 			}
1455 
1456 			if ((dir ^ msg[i].flags) & I2C_M_RD) {
1457 				/* The direction changes.
1458 				 */
1459 				dir = msg[i].flags & I2C_M_RD;
1460 				cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1461 			}
1462 
1463 			req->NumCmds++;
1464 
1465 			/*
1466 			 * Insert STOP if we are at the last byte of either last
1467 			 * message for the transaction or the client explicitly
1468 			 * requires a STOP at this particular message.
1469 			 */
1470 			if ((j == msg[i].len - 1) &&
1471 			    ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1472 				cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1473 				cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1474 			}
1475 		}
1476 	}
1477 	mutex_lock(&adev->pm.mutex);
1478 	r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1479 	if (r)
1480 		goto fail;
1481 
1482 	for (c = i = 0; i < num_msgs; i++) {
1483 		if (!(msg[i].flags & I2C_M_RD)) {
1484 			c += msg[i].len;
1485 			continue;
1486 		}
1487 		for (j = 0; j < msg[i].len; j++, c++) {
1488 			SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1489 
1490 			msg[i].buf[j] = cmd->ReadWriteData;
1491 		}
1492 	}
1493 	r = num_msgs;
1494 fail:
1495 	mutex_unlock(&adev->pm.mutex);
1496 	kfree(req);
1497 	return r;
1498 }
1499 
1500 static u32 aldebaran_i2c_func(struct i2c_adapter *adap)
1501 {
1502 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1503 }
1504 
1505 
1506 static const struct i2c_algorithm aldebaran_i2c_algo = {
1507 	.master_xfer = aldebaran_i2c_xfer,
1508 	.functionality = aldebaran_i2c_func,
1509 };
1510 
1511 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = {
1512 	.flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1513 	.max_read_len  = MAX_SW_I2C_COMMANDS,
1514 	.max_write_len = MAX_SW_I2C_COMMANDS,
1515 	.max_comb_1st_msg_len = 2,
1516 	.max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1517 };
1518 
1519 static int aldebaran_i2c_control_init(struct smu_context *smu)
1520 {
1521 	struct amdgpu_device *adev = smu->adev;
1522 	struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0];
1523 	struct i2c_adapter *control = &smu_i2c->adapter;
1524 	int res;
1525 
1526 	smu_i2c->adev = adev;
1527 	smu_i2c->port = 0;
1528 	mutex_init(&smu_i2c->mutex);
1529 	control->owner = THIS_MODULE;
1530 	control->class = I2C_CLASS_SPD;
1531 	control->dev.parent = &adev->pdev->dev;
1532 	control->algo = &aldebaran_i2c_algo;
1533 	snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0");
1534 	control->quirks = &aldebaran_i2c_control_quirks;
1535 	i2c_set_adapdata(control, smu_i2c);
1536 
1537 	res = i2c_add_adapter(control);
1538 	if (res) {
1539 		DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1540 		goto Out_err;
1541 	}
1542 
1543 	adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1544 	adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1545 
1546 	return 0;
1547 Out_err:
1548 	i2c_del_adapter(control);
1549 
1550 	return res;
1551 }
1552 
1553 static void aldebaran_i2c_control_fini(struct smu_context *smu)
1554 {
1555 	struct amdgpu_device *adev = smu->adev;
1556 	int i;
1557 
1558 	for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
1559 		struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1560 		struct i2c_adapter *control = &smu_i2c->adapter;
1561 
1562 		i2c_del_adapter(control);
1563 	}
1564 	adev->pm.ras_eeprom_i2c_bus = NULL;
1565 	adev->pm.fru_eeprom_i2c_bus = NULL;
1566 }
1567 
1568 static void aldebaran_get_unique_id(struct smu_context *smu)
1569 {
1570 	struct amdgpu_device *adev = smu->adev;
1571 	uint32_t upper32 = 0, lower32 = 0;
1572 
1573 	if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1574 		goto out;
1575 	if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1576 		goto out;
1577 
1578 out:
1579 	adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1580 }
1581 
1582 static bool aldebaran_is_baco_supported(struct smu_context *smu)
1583 {
1584 	/* aldebaran is not support baco */
1585 
1586 	return false;
1587 }
1588 
1589 static int aldebaran_set_df_cstate(struct smu_context *smu,
1590 				   enum pp_df_cstate state)
1591 {
1592 	struct amdgpu_device *adev = smu->adev;
1593 
1594 	/*
1595 	 * Aldebaran does not need the cstate disablement
1596 	 * prerequisite for gpu reset.
1597 	 */
1598 	if (amdgpu_in_reset(adev) || adev->in_suspend)
1599 		return 0;
1600 
1601 	return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
1602 }
1603 
1604 static int aldebaran_select_xgmi_plpd_policy(struct smu_context *smu,
1605 					     enum pp_xgmi_plpd_mode mode)
1606 {
1607 	struct amdgpu_device *adev = smu->adev;
1608 
1609 	/* The message only works on master die and NACK will be sent
1610 	   back for other dies, only send it on master die */
1611 	if (adev->smuio.funcs->get_socket_id(adev) ||
1612 	    adev->smuio.funcs->get_die_id(adev))
1613 		return 0;
1614 
1615 	if (mode == XGMI_PLPD_DEFAULT)
1616 		return smu_cmn_send_smc_msg_with_param(smu,
1617 						       SMU_MSG_GmiPwrDnControl,
1618 						       0, NULL);
1619 	else if (mode == XGMI_PLPD_DISALLOW)
1620 		return smu_cmn_send_smc_msg_with_param(smu,
1621 						       SMU_MSG_GmiPwrDnControl,
1622 						       1, NULL);
1623 	else
1624 		return -EINVAL;
1625 }
1626 
1627 static const struct throttling_logging_label {
1628 	uint32_t feature_mask;
1629 	const char *label;
1630 } logging_label[] = {
1631 	{(1U << THROTTLER_TEMP_GPU_BIT), "GPU"},
1632 	{(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
1633 	{(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
1634 	{(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
1635 	{(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
1636 };
1637 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu)
1638 {
1639 	int ret;
1640 	int throttler_idx, throttling_events = 0, buf_idx = 0;
1641 	struct amdgpu_device *adev = smu->adev;
1642 	uint32_t throttler_status;
1643 	char log_buf[256];
1644 
1645 	ret = aldebaran_get_smu_metrics_data(smu,
1646 					     METRICS_THROTTLER_STATUS,
1647 					     &throttler_status);
1648 	if (ret)
1649 		return;
1650 
1651 	memset(log_buf, 0, sizeof(log_buf));
1652 	for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
1653 	     throttler_idx++) {
1654 		if (throttler_status & logging_label[throttler_idx].feature_mask) {
1655 			throttling_events++;
1656 			buf_idx += snprintf(log_buf + buf_idx,
1657 					    sizeof(log_buf) - buf_idx,
1658 					    "%s%s",
1659 					    throttling_events > 1 ? " and " : "",
1660 					    logging_label[throttler_idx].label);
1661 			if (buf_idx >= sizeof(log_buf)) {
1662 				dev_err(adev->dev, "buffer overflow!\n");
1663 				log_buf[sizeof(log_buf) - 1] = '\0';
1664 				break;
1665 			}
1666 		}
1667 	}
1668 
1669 	dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
1670 		 log_buf);
1671 	kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
1672 		smu_cmn_get_indep_throttler_status(throttler_status,
1673 						   aldebaran_throttler_map));
1674 }
1675 
1676 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu)
1677 {
1678 	struct amdgpu_device *adev = smu->adev;
1679 	uint32_t esm_ctrl;
1680 
1681 	/* TODO: confirm this on real target */
1682 	esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
1683 	if ((esm_ctrl >> 15) & 0x1FFFF)
1684 		return (((esm_ctrl >> 8) & 0x3F) + 128);
1685 
1686 	return smu_v13_0_get_current_pcie_link_speed(smu);
1687 }
1688 
1689 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
1690 					 void **table)
1691 {
1692 	struct smu_table_context *smu_table = &smu->smu_table;
1693 	struct gpu_metrics_v1_3 *gpu_metrics =
1694 		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1695 	SmuMetrics_t metrics;
1696 	int i, ret = 0;
1697 
1698 	ret = smu_cmn_get_metrics_table(smu,
1699 					&metrics,
1700 					true);
1701 	if (ret)
1702 		return ret;
1703 
1704 	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1705 
1706 	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
1707 	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
1708 	gpu_metrics->temperature_mem = metrics.TemperatureHBM;
1709 	gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
1710 	gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
1711 	gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
1712 
1713 	gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1714 	gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
1715 	gpu_metrics->average_mm_activity = 0;
1716 
1717 	/* Valid power data is available only from primary die */
1718 	if (aldebaran_is_primary(smu)) {
1719 		gpu_metrics->average_socket_power = metrics.AverageSocketPower;
1720 		gpu_metrics->energy_accumulator =
1721 			(uint64_t)metrics.EnergyAcc64bitHigh << 32 |
1722 			metrics.EnergyAcc64bitLow;
1723 	} else {
1724 		gpu_metrics->average_socket_power = 0;
1725 		gpu_metrics->energy_accumulator = 0;
1726 	}
1727 
1728 	gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1729 	gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1730 	gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
1731 	gpu_metrics->average_vclk0_frequency = 0;
1732 	gpu_metrics->average_dclk0_frequency = 0;
1733 
1734 	gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
1735 	gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
1736 	gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
1737 	gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
1738 	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
1739 
1740 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1741 	gpu_metrics->indep_throttle_status =
1742 			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1743 							   aldebaran_throttler_map);
1744 
1745 	gpu_metrics->current_fan_speed = 0;
1746 
1747 	gpu_metrics->pcie_link_width =
1748 		smu_v13_0_get_current_pcie_link_width(smu);
1749 	gpu_metrics->pcie_link_speed =
1750 		aldebaran_get_current_pcie_link_speed(smu);
1751 
1752 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1753 
1754 	gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc;
1755 	gpu_metrics->mem_activity_acc = metrics.DramBusyAcc;
1756 
1757 	for (i = 0; i < NUM_HBM_INSTANCES; i++)
1758 		gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i];
1759 
1760 	gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) |
1761 					metrics.TimeStampLow;
1762 
1763 	*table = (void *)gpu_metrics;
1764 
1765 	return sizeof(struct gpu_metrics_v1_3);
1766 }
1767 
1768 static int aldebaran_check_ecc_table_support(struct smu_context *smu,
1769 		int *ecctable_version)
1770 {
1771 	if (smu->smc_fw_version < SUPPORT_ECCTABLE_SMU_VERSION)
1772 		return -EOPNOTSUPP;
1773 	else if (smu->smc_fw_version >= SUPPORT_ECCTABLE_SMU_VERSION &&
1774 			smu->smc_fw_version < SUPPORT_ECCTABLE_V2_SMU_VERSION)
1775 		*ecctable_version = 1;
1776 	else
1777 		*ecctable_version = 2;
1778 
1779 	return 0;
1780 }
1781 
1782 static ssize_t aldebaran_get_ecc_info(struct smu_context *smu,
1783 					 void *table)
1784 {
1785 	struct smu_table_context *smu_table = &smu->smu_table;
1786 	EccInfoTable_t *ecc_table = NULL;
1787 	struct ecc_info_per_ch *ecc_info_per_channel = NULL;
1788 	int i, ret = 0;
1789 	int table_version = 0;
1790 	struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
1791 
1792 	ret = aldebaran_check_ecc_table_support(smu, &table_version);
1793 	if (ret)
1794 		return ret;
1795 
1796 	ret = smu_cmn_update_table(smu,
1797 			       SMU_TABLE_ECCINFO,
1798 			       0,
1799 			       smu_table->ecc_table,
1800 			       false);
1801 	if (ret) {
1802 		dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
1803 		return ret;
1804 	}
1805 
1806 	ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
1807 
1808 	if (table_version == 1) {
1809 		for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) {
1810 			ecc_info_per_channel = &(eccinfo->ecc[i]);
1811 			ecc_info_per_channel->ce_count_lo_chip =
1812 				ecc_table->EccInfo[i].ce_count_lo_chip;
1813 			ecc_info_per_channel->ce_count_hi_chip =
1814 				ecc_table->EccInfo[i].ce_count_hi_chip;
1815 			ecc_info_per_channel->mca_umc_status =
1816 				ecc_table->EccInfo[i].mca_umc_status;
1817 			ecc_info_per_channel->mca_umc_addr =
1818 				ecc_table->EccInfo[i].mca_umc_addr;
1819 		}
1820 	} else if (table_version == 2) {
1821 		for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) {
1822 			ecc_info_per_channel = &(eccinfo->ecc[i]);
1823 			ecc_info_per_channel->ce_count_lo_chip =
1824 				ecc_table->EccInfo_V2[i].ce_count_lo_chip;
1825 			ecc_info_per_channel->ce_count_hi_chip =
1826 				ecc_table->EccInfo_V2[i].ce_count_hi_chip;
1827 			ecc_info_per_channel->mca_umc_status =
1828 				ecc_table->EccInfo_V2[i].mca_umc_status;
1829 			ecc_info_per_channel->mca_umc_addr =
1830 				ecc_table->EccInfo_V2[i].mca_umc_addr;
1831 			ecc_info_per_channel->mca_ceumc_addr =
1832 				ecc_table->EccInfo_V2[i].mca_ceumc_addr;
1833 		}
1834 		eccinfo->record_ce_addr_supported = 1;
1835 	}
1836 
1837 	return ret;
1838 }
1839 
1840 static int aldebaran_mode1_reset(struct smu_context *smu)
1841 {
1842 	u32 fatal_err, param;
1843 	int ret = 0;
1844 	struct amdgpu_device *adev = smu->adev;
1845 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1846 
1847 	fatal_err = 0;
1848 	param = SMU_RESET_MODE_1;
1849 
1850 	/*
1851 	* PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07
1852 	*/
1853 	if (smu->smc_fw_version < 0x00440700) {
1854 		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1855 	} else {
1856 		/* fatal error triggered by ras, PMFW supports the flag
1857 		   from 68.44.0 */
1858 		if ((smu->smc_fw_version >= 0x00442c00) && ras &&
1859 		    atomic_read(&ras->in_recovery))
1860 			fatal_err = 1;
1861 
1862 		param |= (fatal_err << 16);
1863 		ret = smu_cmn_send_smc_msg_with_param(smu,
1864 					SMU_MSG_GfxDeviceDriverReset, param, NULL);
1865 	}
1866 
1867 	if (!ret)
1868 		msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1869 
1870 	return ret;
1871 }
1872 
1873 static int aldebaran_mode2_reset(struct smu_context *smu)
1874 {
1875 	int ret = 0, index;
1876 	struct amdgpu_device *adev = smu->adev;
1877 	int timeout = 10;
1878 
1879 	index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1880 						SMU_MSG_GfxDeviceDriverReset);
1881 
1882 	mutex_lock(&smu->message_lock);
1883 	if (smu->smc_fw_version >= 0x00441400) {
1884 		ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2);
1885 		/* This is similar to FLR, wait till max FLR timeout */
1886 		msleep(100);
1887 		dev_dbg(smu->adev->dev, "restore config space...\n");
1888 		/* Restore the config space saved during init */
1889 		amdgpu_device_load_pci_state(adev->pdev);
1890 
1891 		dev_dbg(smu->adev->dev, "wait for reset ack\n");
1892 		while (ret == -ETIME && timeout)  {
1893 			ret = smu_cmn_wait_for_response(smu);
1894 			/* Wait a bit more time for getting ACK */
1895 			if (ret == -ETIME) {
1896 				--timeout;
1897 				usleep_range(500, 1000);
1898 				continue;
1899 			}
1900 
1901 			if (ret != 1) {
1902 				dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n",
1903 						SMU_RESET_MODE_2, ret);
1904 				goto out;
1905 			}
1906 		}
1907 
1908 	} else {
1909 		dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n",
1910 				smu->smc_fw_version);
1911 	}
1912 
1913 	if (ret == 1)
1914 		ret = 0;
1915 out:
1916 	mutex_unlock(&smu->message_lock);
1917 
1918 	return ret;
1919 }
1920 
1921 static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
1922 {
1923 	int ret = 0;
1924 	ret =  smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL);
1925 
1926 	return ret;
1927 }
1928 
1929 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
1930 {
1931 #if 0
1932 	struct amdgpu_device *adev = smu->adev;
1933 	uint32_t val;
1934 	uint32_t smu_version;
1935 	int ret;
1936 
1937 	/**
1938 	 * PM FW version support mode1 reset from 68.07
1939 	 */
1940 	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1941 	if (ret)
1942 		return false;
1943 
1944 	if ((smu_version < 0x00440700))
1945 		return false;
1946 
1947 	/**
1948 	 * mode1 reset relies on PSP, so we should check if
1949 	 * PSP is alive.
1950 	 */
1951 	val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
1952 
1953 	return val != 0x0;
1954 #endif
1955 	return true;
1956 }
1957 
1958 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu)
1959 {
1960 	return true;
1961 }
1962 
1963 static int aldebaran_set_mp1_state(struct smu_context *smu,
1964 				   enum pp_mp1_state mp1_state)
1965 {
1966 	switch (mp1_state) {
1967 	case PP_MP1_STATE_UNLOAD:
1968 		return smu_cmn_set_mp1_state(smu, mp1_state);
1969 	default:
1970 		return 0;
1971 	}
1972 }
1973 
1974 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu,
1975 		uint32_t size)
1976 {
1977 	int ret = 0;
1978 
1979 	/* message SMU to update the bad page number on SMUBUS */
1980 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
1981 	if (ret)
1982 		dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n",
1983 				__func__);
1984 
1985 	return ret;
1986 }
1987 
1988 static int aldebaran_check_bad_channel_info_support(struct smu_context *smu)
1989 {
1990 	if (smu->smc_fw_version < SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION)
1991 		return -EOPNOTSUPP;
1992 
1993 	return 0;
1994 }
1995 
1996 static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu,
1997 		uint32_t size)
1998 {
1999 	int ret = 0;
2000 
2001 	ret = aldebaran_check_bad_channel_info_support(smu);
2002 	if (ret)
2003 		return ret;
2004 
2005 	/* message SMU to update the bad channel info on SMUBUS */
2006 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetBadHBMPagesRetiredFlagsPerChannel, size, NULL);
2007 	if (ret)
2008 		dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad channel info\n",
2009 				__func__);
2010 
2011 	return ret;
2012 }
2013 
2014 static const struct pptable_funcs aldebaran_ppt_funcs = {
2015 	/* init dpm */
2016 	.get_allowed_feature_mask = aldebaran_get_allowed_feature_mask,
2017 	/* dpm/clk tables */
2018 	.set_default_dpm_table = aldebaran_set_default_dpm_table,
2019 	.populate_umd_state_clk = aldebaran_populate_umd_state_clk,
2020 	.get_thermal_temperature_range = aldebaran_get_thermal_temperature_range,
2021 	.emit_clk_levels = aldebaran_emit_clk_levels,
2022 	.force_clk_levels = aldebaran_force_clk_levels,
2023 	.read_sensor = aldebaran_read_sensor,
2024 	.set_performance_level = aldebaran_set_performance_level,
2025 	.get_power_limit = aldebaran_get_power_limit,
2026 	.is_dpm_running = aldebaran_is_dpm_running,
2027 	.get_unique_id = aldebaran_get_unique_id,
2028 	.init_microcode = smu_v13_0_init_microcode,
2029 	.load_microcode = smu_v13_0_load_microcode,
2030 	.fini_microcode = smu_v13_0_fini_microcode,
2031 	.init_smc_tables = aldebaran_init_smc_tables,
2032 	.fini_smc_tables = smu_v13_0_fini_smc_tables,
2033 	.init_power = smu_v13_0_init_power,
2034 	.fini_power = smu_v13_0_fini_power,
2035 	.check_fw_status = smu_v13_0_check_fw_status,
2036 	/* pptable related */
2037 	.setup_pptable = aldebaran_setup_pptable,
2038 	.get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
2039 	.check_fw_version = smu_v13_0_check_fw_version,
2040 	.write_pptable = smu_cmn_write_pptable,
2041 	.set_driver_table_location = smu_v13_0_set_driver_table_location,
2042 	.set_tool_table_location = smu_v13_0_set_tool_table_location,
2043 	.notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
2044 	.system_features_control = aldebaran_system_features_control,
2045 	.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2046 	.send_smc_msg = smu_cmn_send_smc_msg,
2047 	.get_enabled_mask = smu_cmn_get_enabled_mask,
2048 	.feature_is_enabled = smu_cmn_feature_is_enabled,
2049 	.disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2050 	.set_power_limit = aldebaran_set_power_limit,
2051 	.init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks,
2052 	.enable_thermal_alert = smu_v13_0_enable_thermal_alert,
2053 	.disable_thermal_alert = smu_v13_0_disable_thermal_alert,
2054 	.set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
2055 	.register_irq_handler = smu_v13_0_register_irq_handler,
2056 	.set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme,
2057 	.get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc,
2058 	.baco_is_support = aldebaran_is_baco_supported,
2059 	.get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
2060 	.set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range,
2061 	.od_edit_dpm_table = aldebaran_usr_edit_dpm_table,
2062 	.set_df_cstate = aldebaran_set_df_cstate,
2063 	.select_xgmi_plpd_policy = aldebaran_select_xgmi_plpd_policy,
2064 	.log_thermal_throttling_event = aldebaran_log_thermal_throttling_event,
2065 	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2066 	.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2067 	.get_gpu_metrics = aldebaran_get_gpu_metrics,
2068 	.mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
2069 	.mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
2070 	.smu_handle_passthrough_sbr = aldebaran_smu_handle_passthrough_sbr,
2071 	.mode1_reset = aldebaran_mode1_reset,
2072 	.set_mp1_state = aldebaran_set_mp1_state,
2073 	.mode2_reset = aldebaran_mode2_reset,
2074 	.wait_for_event = smu_v13_0_wait_for_event,
2075 	.i2c_init = aldebaran_i2c_control_init,
2076 	.i2c_fini = aldebaran_i2c_control_fini,
2077 	.send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num,
2078 	.get_ecc_info = aldebaran_get_ecc_info,
2079 	.send_hbm_bad_channel_flag = aldebaran_send_hbm_bad_channel_flag,
2080 };
2081 
2082 void aldebaran_set_ppt_funcs(struct smu_context *smu)
2083 {
2084 	smu->ppt_funcs = &aldebaran_ppt_funcs;
2085 	smu->message_map = aldebaran_message_map;
2086 	smu->clock_map = aldebaran_clk_map;
2087 	smu->feature_map = aldebaran_feature_mask_map;
2088 	smu->table_map = aldebaran_table_map;
2089 	smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
2090 	smu_v13_0_set_smu_mailbox_registers(smu);
2091 }
2092