1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include "amdgpu.h" 28 #include "amdgpu_dpm.h" 29 #include "amdgpu_smu.h" 30 #include "atomfirmware.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_atombios.h" 33 #include "smu_v13_0.h" 34 #include "smu13_driver_if_aldebaran.h" 35 #include "soc15_common.h" 36 #include "atom.h" 37 #include "aldebaran_ppt.h" 38 #include "smu_v13_0_pptable.h" 39 #include "aldebaran_ppsmc.h" 40 #include "nbio/nbio_7_4_offset.h" 41 #include "nbio/nbio_7_4_sh_mask.h" 42 #include "thm/thm_11_0_2_offset.h" 43 #include "thm/thm_11_0_2_sh_mask.h" 44 #include "amdgpu_xgmi.h" 45 #include <linux/pci.h> 46 #include "amdgpu_ras.h" 47 #include "smu_cmn.h" 48 #include "mp/mp_13_0_2_offset.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \ 61 [smu_feature] = {1, (aldebaran_feature)} 62 63 #define FEATURE_MASK(feature) (1ULL << feature) 64 #define SMC_DPM_FEATURE ( \ 65 FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \ 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_VCN_BIT)) 73 74 /* possible frequency drift (1Mhz) */ 75 #define EPSILON 1 76 77 #define smnPCIE_ESM_CTRL 0x111003D0 78 79 /* 80 * SMU support ECCTABLE since version 68.42.0, 81 * use this to check ECCTALE feature whether support 82 */ 83 #define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00 84 85 /* 86 * SMU support mca_ceumc_addr in ECCTABLE since version 68.55.0, 87 * use this to check mca_ceumc_addr record whether support 88 */ 89 #define SUPPORT_ECCTABLE_V2_SMU_VERSION 0x00443700 90 91 /* 92 * SMU support BAD CHENNEL info MSG since version 68.51.00, 93 * use this to check ECCTALE feature whether support 94 */ 95 #define SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION 0x00443300 96 97 static const struct smu_temperature_range smu13_thermal_policy[] = { 98 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 99 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 100 }; 101 102 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = { 103 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 104 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 105 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 106 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 107 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 108 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 109 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 110 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 111 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 112 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 113 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 114 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 115 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 116 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 117 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 118 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 119 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 120 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), 121 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 122 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 123 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0), 124 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0), 125 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 126 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 127 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 128 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 129 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 130 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), 131 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 132 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, 0), 133 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 134 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 135 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 136 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 137 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 138 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0), 139 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0), 140 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0), 141 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), 142 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0), 143 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0), 144 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0), 145 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0), 146 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0), 147 MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0), 148 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0), 149 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0), 150 MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0), 151 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0), 152 MSG_MAP(BoardPowerCalibration, PPSMC_MSG_BoardPowerCalibration, 0), 153 MSG_MAP(HeavySBR, PPSMC_MSG_HeavySBR, 0), 154 MSG_MAP(SetBadHBMPagesRetiredFlagsPerChannel, PPSMC_MSG_SetBadHBMPagesRetiredFlagsPerChannel, 0), 155 }; 156 157 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = { 158 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 159 CLK_MAP(SCLK, PPCLK_GFXCLK), 160 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 161 CLK_MAP(FCLK, PPCLK_FCLK), 162 CLK_MAP(UCLK, PPCLK_UCLK), 163 CLK_MAP(MCLK, PPCLK_UCLK), 164 CLK_MAP(DCLK, PPCLK_DCLK), 165 CLK_MAP(VCLK, PPCLK_VCLK), 166 CLK_MAP(LCLK, PPCLK_LCLK), 167 }; 168 169 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = { 170 ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATIONS), 171 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK_BIT), 172 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK_BIT), 173 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK_BIT), 174 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK_BIT), 175 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK_BIT), 176 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI_BIT), 177 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK_BIT), 178 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK_BIT), 179 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK_BIT), 180 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK_BIT), 181 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT, FEATURE_DS_UCLK_BIT), 182 ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, FEATURE_GFX_SS_BIT), 183 ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT), 184 ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, FEATURE_RSMU_SMN_CG_BIT), 185 ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, FEATURE_WAFL_CG_BIT), 186 ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT_BIT), 187 ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC_BIT), 188 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, FEATURE_APCC_PLUS_BIT), 189 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL_BIT), 190 ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, FEATURE_FUSE_CG_BIT), 191 ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_MP1_CG_BIT), 192 ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, FEATURE_SMUIO_CG_BIT), 193 ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, FEATURE_THM_CG_BIT), 194 ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, FEATURE_CLK_CG_BIT), 195 ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF_BIT), 196 ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL_BIT), 197 ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, FEATURE_OUT_OF_BAND_MONITOR_BIT), 198 ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DWN), 199 ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE), 200 }; 201 202 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = { 203 TAB_MAP(PPTABLE), 204 TAB_MAP(AVFS_PSM_DEBUG), 205 TAB_MAP(AVFS_FUSE_OVERRIDE), 206 TAB_MAP(PMSTATUSLOG), 207 TAB_MAP(SMU_METRICS), 208 TAB_MAP(DRIVER_SMU_CONFIG), 209 TAB_MAP(I2C_COMMANDS), 210 TAB_MAP(ECCINFO), 211 }; 212 213 static const uint8_t aldebaran_throttler_map[] = { 214 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 215 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 216 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 217 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 218 [THROTTLER_TDC_HBM_BIT] = (SMU_THROTTLER_TDC_MEM_BIT), 219 [THROTTLER_TEMP_GPU_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT), 220 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 221 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 222 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 223 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 224 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 225 }; 226 227 static int aldebaran_tables_init(struct smu_context *smu) 228 { 229 struct smu_table_context *smu_table = &smu->smu_table; 230 struct smu_table *tables = smu_table->tables; 231 232 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 233 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 234 235 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 236 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 237 238 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 239 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 240 241 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 242 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 243 244 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t), 245 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 246 247 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 248 if (!smu_table->metrics_table) 249 return -ENOMEM; 250 smu_table->metrics_time = 0; 251 252 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 253 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 254 if (!smu_table->gpu_metrics_table) { 255 kfree(smu_table->metrics_table); 256 return -ENOMEM; 257 } 258 259 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); 260 if (!smu_table->ecc_table) { 261 kfree(smu_table->metrics_table); 262 kfree(smu_table->gpu_metrics_table); 263 return -ENOMEM; 264 } 265 266 return 0; 267 } 268 269 static int aldebaran_select_plpd_policy(struct smu_context *smu, int level) 270 { 271 struct amdgpu_device *adev = smu->adev; 272 273 /* The message only works on master die and NACK will be sent 274 * back for other dies, only send it on master die. 275 */ 276 if (adev->smuio.funcs->get_socket_id(adev) || 277 adev->smuio.funcs->get_die_id(adev)) 278 return 0; 279 280 if (level == XGMI_PLPD_DEFAULT) 281 return smu_cmn_send_smc_msg_with_param( 282 smu, SMU_MSG_GmiPwrDnControl, 0, NULL); 283 else if (level == XGMI_PLPD_DISALLOW) 284 return smu_cmn_send_smc_msg_with_param( 285 smu, SMU_MSG_GmiPwrDnControl, 1, NULL); 286 else 287 return -EINVAL; 288 } 289 290 static int aldebaran_allocate_dpm_context(struct smu_context *smu) 291 { 292 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 293 struct smu_dpm_policy *policy; 294 295 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 296 GFP_KERNEL); 297 if (!smu_dpm->dpm_context) 298 return -ENOMEM; 299 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 300 301 smu_dpm->dpm_policies = 302 kzalloc(sizeof(struct smu_dpm_policy_ctxt), GFP_KERNEL); 303 304 if (!smu_dpm->dpm_policies) 305 return -ENOMEM; 306 307 policy = &(smu_dpm->dpm_policies->policies[0]); 308 policy->policy_type = PP_PM_POLICY_XGMI_PLPD; 309 policy->level_mask = BIT(XGMI_PLPD_DISALLOW) | BIT(XGMI_PLPD_DEFAULT); 310 policy->current_level = XGMI_PLPD_DEFAULT; 311 policy->set_policy = aldebaran_select_plpd_policy; 312 smu_cmn_generic_plpd_policy_desc(policy); 313 smu_dpm->dpm_policies->policy_mask |= BIT(PP_PM_POLICY_XGMI_PLPD); 314 315 return 0; 316 } 317 318 static int aldebaran_init_smc_tables(struct smu_context *smu) 319 { 320 int ret = 0; 321 322 ret = aldebaran_tables_init(smu); 323 if (ret) 324 return ret; 325 326 ret = aldebaran_allocate_dpm_context(smu); 327 if (ret) 328 return ret; 329 330 return smu_v13_0_init_smc_tables(smu); 331 } 332 333 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu, 334 uint32_t *feature_mask, uint32_t num) 335 { 336 if (num > 2) 337 return -EINVAL; 338 339 /* pptable will handle the features to enable */ 340 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 341 342 return 0; 343 } 344 345 static int aldebaran_set_default_dpm_table(struct smu_context *smu) 346 { 347 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 348 struct smu_13_0_dpm_table *dpm_table = NULL; 349 PPTable_t *pptable = smu->smu_table.driver_pptable; 350 int ret = 0; 351 352 /* socclk dpm table setup */ 353 dpm_table = &dpm_context->dpm_tables.soc_table; 354 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 355 ret = smu_v13_0_set_single_dpm_table(smu, 356 SMU_SOCCLK, 357 dpm_table); 358 if (ret) 359 return ret; 360 } else { 361 dpm_table->count = 1; 362 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 363 dpm_table->dpm_levels[0].enabled = true; 364 dpm_table->min = dpm_table->dpm_levels[0].value; 365 dpm_table->max = dpm_table->dpm_levels[0].value; 366 } 367 368 /* gfxclk dpm table setup */ 369 dpm_table = &dpm_context->dpm_tables.gfx_table; 370 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 371 /* in the case of gfxclk, only fine-grained dpm is honored */ 372 dpm_table->count = 2; 373 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin; 374 dpm_table->dpm_levels[0].enabled = true; 375 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax; 376 dpm_table->dpm_levels[1].enabled = true; 377 dpm_table->min = dpm_table->dpm_levels[0].value; 378 dpm_table->max = dpm_table->dpm_levels[1].value; 379 } else { 380 dpm_table->count = 1; 381 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 382 dpm_table->dpm_levels[0].enabled = true; 383 dpm_table->min = dpm_table->dpm_levels[0].value; 384 dpm_table->max = dpm_table->dpm_levels[0].value; 385 } 386 387 /* memclk dpm table setup */ 388 dpm_table = &dpm_context->dpm_tables.uclk_table; 389 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 390 ret = smu_v13_0_set_single_dpm_table(smu, 391 SMU_UCLK, 392 dpm_table); 393 if (ret) 394 return ret; 395 } else { 396 dpm_table->count = 1; 397 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 398 dpm_table->dpm_levels[0].enabled = true; 399 dpm_table->min = dpm_table->dpm_levels[0].value; 400 dpm_table->max = dpm_table->dpm_levels[0].value; 401 } 402 403 /* fclk dpm table setup */ 404 dpm_table = &dpm_context->dpm_tables.fclk_table; 405 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 406 ret = smu_v13_0_set_single_dpm_table(smu, 407 SMU_FCLK, 408 dpm_table); 409 if (ret) 410 return ret; 411 } else { 412 dpm_table->count = 1; 413 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 414 dpm_table->dpm_levels[0].enabled = true; 415 dpm_table->min = dpm_table->dpm_levels[0].value; 416 dpm_table->max = dpm_table->dpm_levels[0].value; 417 } 418 419 return 0; 420 } 421 422 static int aldebaran_check_powerplay_table(struct smu_context *smu) 423 { 424 struct smu_table_context *table_context = &smu->smu_table; 425 struct smu_13_0_powerplay_table *powerplay_table = 426 table_context->power_play_table; 427 428 table_context->thermal_controller_type = 429 powerplay_table->thermal_controller_type; 430 431 return 0; 432 } 433 434 static int aldebaran_store_powerplay_table(struct smu_context *smu) 435 { 436 struct smu_table_context *table_context = &smu->smu_table; 437 struct smu_13_0_powerplay_table *powerplay_table = 438 table_context->power_play_table; 439 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 440 sizeof(PPTable_t)); 441 442 return 0; 443 } 444 445 static int aldebaran_append_powerplay_table(struct smu_context *smu) 446 { 447 struct smu_table_context *table_context = &smu->smu_table; 448 PPTable_t *smc_pptable = table_context->driver_pptable; 449 struct atom_smc_dpm_info_v4_10 *smc_dpm_table; 450 int index, ret; 451 452 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 453 smc_dpm_info); 454 455 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 456 (uint8_t **)&smc_dpm_table); 457 if (ret) 458 return ret; 459 460 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 461 smc_dpm_table->table_header.format_revision, 462 smc_dpm_table->table_header.content_revision); 463 464 if ((smc_dpm_table->table_header.format_revision == 4) && 465 (smc_dpm_table->table_header.content_revision == 10)) 466 smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved, 467 smc_dpm_table, GfxMaxCurrent); 468 return 0; 469 } 470 471 static int aldebaran_setup_pptable(struct smu_context *smu) 472 { 473 int ret = 0; 474 475 /* VBIOS pptable is the first choice */ 476 smu->smu_table.boot_values.pp_table_id = 0; 477 478 ret = smu_v13_0_setup_pptable(smu); 479 if (ret) 480 return ret; 481 482 ret = aldebaran_store_powerplay_table(smu); 483 if (ret) 484 return ret; 485 486 ret = aldebaran_append_powerplay_table(smu); 487 if (ret) 488 return ret; 489 490 ret = aldebaran_check_powerplay_table(smu); 491 if (ret) 492 return ret; 493 494 return ret; 495 } 496 497 static bool aldebaran_is_primary(struct smu_context *smu) 498 { 499 struct amdgpu_device *adev = smu->adev; 500 501 if (adev->smuio.funcs && adev->smuio.funcs->get_die_id) 502 return adev->smuio.funcs->get_die_id(adev) == 0; 503 504 return true; 505 } 506 507 static int aldebaran_run_board_btc(struct smu_context *smu) 508 { 509 int ret; 510 511 if (!aldebaran_is_primary(smu)) 512 return 0; 513 514 if (smu->smc_fw_version <= 0x00441d00) 515 return 0; 516 517 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL); 518 if (ret) 519 dev_err(smu->adev->dev, "Board power calibration failed!\n"); 520 521 return ret; 522 } 523 524 static int aldebaran_run_btc(struct smu_context *smu) 525 { 526 int ret; 527 528 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 529 if (ret) 530 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 531 else 532 ret = aldebaran_run_board_btc(smu); 533 534 return ret; 535 } 536 537 static int aldebaran_populate_umd_state_clk(struct smu_context *smu) 538 { 539 struct smu_13_0_dpm_context *dpm_context = 540 smu->smu_dpm.dpm_context; 541 struct smu_13_0_dpm_table *gfx_table = 542 &dpm_context->dpm_tables.gfx_table; 543 struct smu_13_0_dpm_table *mem_table = 544 &dpm_context->dpm_tables.uclk_table; 545 struct smu_13_0_dpm_table *soc_table = 546 &dpm_context->dpm_tables.soc_table; 547 struct smu_umd_pstate_table *pstate_table = 548 &smu->pstate_table; 549 550 pstate_table->gfxclk_pstate.min = gfx_table->min; 551 pstate_table->gfxclk_pstate.peak = gfx_table->max; 552 pstate_table->gfxclk_pstate.curr.min = gfx_table->min; 553 pstate_table->gfxclk_pstate.curr.max = gfx_table->max; 554 555 pstate_table->uclk_pstate.min = mem_table->min; 556 pstate_table->uclk_pstate.peak = mem_table->max; 557 pstate_table->uclk_pstate.curr.min = mem_table->min; 558 pstate_table->uclk_pstate.curr.max = mem_table->max; 559 560 pstate_table->socclk_pstate.min = soc_table->min; 561 pstate_table->socclk_pstate.peak = soc_table->max; 562 pstate_table->socclk_pstate.curr.min = soc_table->min; 563 pstate_table->socclk_pstate.curr.max = soc_table->max; 564 565 if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL && 566 mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL && 567 soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) { 568 pstate_table->gfxclk_pstate.standard = 569 gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value; 570 pstate_table->uclk_pstate.standard = 571 mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value; 572 pstate_table->socclk_pstate.standard = 573 soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value; 574 } else { 575 pstate_table->gfxclk_pstate.standard = 576 pstate_table->gfxclk_pstate.min; 577 pstate_table->uclk_pstate.standard = 578 pstate_table->uclk_pstate.min; 579 pstate_table->socclk_pstate.standard = 580 pstate_table->socclk_pstate.min; 581 } 582 583 return 0; 584 } 585 586 static void aldebaran_get_clk_table(struct smu_context *smu, 587 struct pp_clock_levels_with_latency *clocks, 588 struct smu_13_0_dpm_table *dpm_table) 589 { 590 uint32_t i; 591 592 clocks->num_levels = min_t(uint32_t, 593 dpm_table->count, 594 (uint32_t)PP_MAX_CLOCK_LEVELS); 595 596 for (i = 0; i < clocks->num_levels; i++) { 597 clocks->data[i].clocks_in_khz = 598 dpm_table->dpm_levels[i].value * 1000; 599 clocks->data[i].latency_in_us = 0; 600 } 601 602 } 603 604 static int aldebaran_freqs_in_same_level(int32_t frequency1, 605 int32_t frequency2) 606 { 607 return (abs(frequency1 - frequency2) <= EPSILON); 608 } 609 610 static int aldebaran_get_smu_metrics_data(struct smu_context *smu, 611 MetricsMember_t member, 612 uint32_t *value) 613 { 614 struct smu_table_context *smu_table = &smu->smu_table; 615 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 616 int ret = 0; 617 618 ret = smu_cmn_get_metrics_table(smu, 619 NULL, 620 false); 621 if (ret) 622 return ret; 623 624 switch (member) { 625 case METRICS_CURR_GFXCLK: 626 *value = metrics->CurrClock[PPCLK_GFXCLK]; 627 break; 628 case METRICS_CURR_SOCCLK: 629 *value = metrics->CurrClock[PPCLK_SOCCLK]; 630 break; 631 case METRICS_CURR_UCLK: 632 *value = metrics->CurrClock[PPCLK_UCLK]; 633 break; 634 case METRICS_CURR_VCLK: 635 *value = metrics->CurrClock[PPCLK_VCLK]; 636 break; 637 case METRICS_CURR_DCLK: 638 *value = metrics->CurrClock[PPCLK_DCLK]; 639 break; 640 case METRICS_CURR_FCLK: 641 *value = metrics->CurrClock[PPCLK_FCLK]; 642 break; 643 case METRICS_AVERAGE_GFXCLK: 644 *value = metrics->AverageGfxclkFrequency; 645 break; 646 case METRICS_AVERAGE_SOCCLK: 647 *value = metrics->AverageSocclkFrequency; 648 break; 649 case METRICS_AVERAGE_UCLK: 650 *value = metrics->AverageUclkFrequency; 651 break; 652 case METRICS_AVERAGE_GFXACTIVITY: 653 *value = metrics->AverageGfxActivity; 654 break; 655 case METRICS_AVERAGE_MEMACTIVITY: 656 *value = metrics->AverageUclkActivity; 657 break; 658 case METRICS_AVERAGE_SOCKETPOWER: 659 /* Valid power data is available only from primary die */ 660 if (aldebaran_is_primary(smu)) 661 *value = metrics->AverageSocketPower << 8; 662 else 663 ret = -EOPNOTSUPP; 664 break; 665 case METRICS_TEMPERATURE_EDGE: 666 *value = metrics->TemperatureEdge * 667 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 668 break; 669 case METRICS_TEMPERATURE_HOTSPOT: 670 *value = metrics->TemperatureHotspot * 671 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 672 break; 673 case METRICS_TEMPERATURE_MEM: 674 *value = metrics->TemperatureHBM * 675 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 676 break; 677 case METRICS_TEMPERATURE_VRGFX: 678 *value = metrics->TemperatureVrGfx * 679 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 680 break; 681 case METRICS_TEMPERATURE_VRSOC: 682 *value = metrics->TemperatureVrSoc * 683 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 684 break; 685 case METRICS_TEMPERATURE_VRMEM: 686 *value = metrics->TemperatureVrMem * 687 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 688 break; 689 case METRICS_THROTTLER_STATUS: 690 *value = metrics->ThrottlerStatus; 691 break; 692 case METRICS_UNIQUE_ID_UPPER32: 693 *value = metrics->PublicSerialNumUpper32; 694 break; 695 case METRICS_UNIQUE_ID_LOWER32: 696 *value = metrics->PublicSerialNumLower32; 697 break; 698 default: 699 *value = UINT_MAX; 700 break; 701 } 702 703 return ret; 704 } 705 706 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu, 707 enum smu_clk_type clk_type, 708 uint32_t *value) 709 { 710 MetricsMember_t member_type; 711 int clk_id = 0; 712 713 if (!value) 714 return -EINVAL; 715 716 clk_id = smu_cmn_to_asic_specific_index(smu, 717 CMN2ASIC_MAPPING_CLK, 718 clk_type); 719 if (clk_id < 0) 720 return -EINVAL; 721 722 switch (clk_id) { 723 case PPCLK_GFXCLK: 724 /* 725 * CurrClock[clk_id] can provide accurate 726 * output only when the dpm feature is enabled. 727 * We can use Average_* for dpm disabled case. 728 * But this is available for gfxclk/uclk/socclk/vclk/dclk. 729 */ 730 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) 731 member_type = METRICS_CURR_GFXCLK; 732 else 733 member_type = METRICS_AVERAGE_GFXCLK; 734 break; 735 case PPCLK_UCLK: 736 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 737 member_type = METRICS_CURR_UCLK; 738 else 739 member_type = METRICS_AVERAGE_UCLK; 740 break; 741 case PPCLK_SOCCLK: 742 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) 743 member_type = METRICS_CURR_SOCCLK; 744 else 745 member_type = METRICS_AVERAGE_SOCCLK; 746 break; 747 case PPCLK_VCLK: 748 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 749 member_type = METRICS_CURR_VCLK; 750 else 751 member_type = METRICS_AVERAGE_VCLK; 752 break; 753 case PPCLK_DCLK: 754 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 755 member_type = METRICS_CURR_DCLK; 756 else 757 member_type = METRICS_AVERAGE_DCLK; 758 break; 759 case PPCLK_FCLK: 760 member_type = METRICS_CURR_FCLK; 761 break; 762 default: 763 return -EINVAL; 764 } 765 766 return aldebaran_get_smu_metrics_data(smu, 767 member_type, 768 value); 769 } 770 771 static int aldebaran_emit_clk_levels(struct smu_context *smu, 772 enum smu_clk_type type, char *buf, int *offset) 773 { 774 int ret = 0; 775 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 776 struct pp_clock_levels_with_latency clocks; 777 struct smu_13_0_dpm_table *single_dpm_table; 778 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 779 struct smu_13_0_dpm_context *dpm_context = NULL; 780 uint32_t i; 781 int display_levels; 782 uint32_t freq_values[3] = {0}; 783 uint32_t min_clk, max_clk, cur_value = 0; 784 bool freq_match; 785 unsigned int clock_mhz; 786 static const char attempt_string[] = "Attempt to get current"; 787 788 if (amdgpu_ras_intr_triggered()) { 789 *offset += sysfs_emit_at(buf, *offset, "unavailable\n"); 790 return -EBUSY; 791 } 792 793 dpm_context = smu_dpm->dpm_context; 794 795 switch (type) { 796 797 case SMU_OD_SCLK: 798 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_SCLK"); 799 *offset += sysfs_emit_at(buf, *offset, "0: %uMhz\n1: %uMhz\n", 800 pstate_table->gfxclk_pstate.curr.min, 801 pstate_table->gfxclk_pstate.curr.max); 802 return 0; 803 case SMU_SCLK: 804 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &cur_value); 805 if (ret) { 806 dev_err(smu->adev->dev, "%s gfx clk Failed!", attempt_string); 807 return ret; 808 } 809 810 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 811 aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 812 813 display_levels = (clocks.num_levels == 1) ? 1 : 2; 814 815 min_clk = pstate_table->gfxclk_pstate.curr.min; 816 max_clk = pstate_table->gfxclk_pstate.curr.max; 817 818 freq_values[0] = min_clk; 819 freq_values[1] = max_clk; 820 821 /* fine-grained dpm has only 2 levels */ 822 if (cur_value > min_clk && cur_value < max_clk) { 823 display_levels++; 824 freq_values[2] = max_clk; 825 freq_values[1] = cur_value; 826 } 827 break; 828 829 case SMU_OD_MCLK: 830 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_MCLK"); 831 *offset += sysfs_emit_at(buf, *offset, "0: %uMhz\n1: %uMhz\n", 832 pstate_table->uclk_pstate.curr.min, 833 pstate_table->uclk_pstate.curr.max); 834 return 0; 835 case SMU_MCLK: 836 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &cur_value); 837 if (ret) { 838 dev_err(smu->adev->dev, "%s mclk Failed!", attempt_string); 839 return ret; 840 } 841 842 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 843 aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 844 break; 845 846 case SMU_SOCCLK: 847 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &cur_value); 848 if (ret) { 849 dev_err(smu->adev->dev, "%s socclk Failed!", attempt_string); 850 return ret; 851 } 852 853 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 854 aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 855 break; 856 857 case SMU_FCLK: 858 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &cur_value); 859 if (ret) { 860 dev_err(smu->adev->dev, "%s fclk Failed!", attempt_string); 861 return ret; 862 } 863 864 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 865 aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 866 break; 867 868 case SMU_VCLK: 869 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &cur_value); 870 if (ret) { 871 dev_err(smu->adev->dev, "%s vclk Failed!", attempt_string); 872 return ret; 873 } 874 875 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 876 aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 877 break; 878 879 case SMU_DCLK: 880 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &cur_value); 881 if (ret) { 882 dev_err(smu->adev->dev, "%s dclk Failed!", attempt_string); 883 return ret; 884 } 885 886 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 887 aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 888 break; 889 890 default: 891 return -EINVAL; 892 } 893 894 switch (type) { 895 case SMU_SCLK: 896 for (i = 0; i < display_levels; i++) { 897 clock_mhz = freq_values[i]; 898 freq_match = aldebaran_freqs_in_same_level(clock_mhz, cur_value); 899 freq_match |= (display_levels == 1); 900 901 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", i, 902 clock_mhz, 903 (freq_match) ? "*" : ""); 904 } 905 break; 906 907 case SMU_MCLK: 908 case SMU_SOCCLK: 909 case SMU_FCLK: 910 case SMU_VCLK: 911 case SMU_DCLK: 912 for (i = 0; i < clocks.num_levels; i++) { 913 clock_mhz = clocks.data[i].clocks_in_khz / 1000; 914 freq_match = aldebaran_freqs_in_same_level(clock_mhz, cur_value); 915 freq_match |= (clocks.num_levels == 1); 916 917 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 918 i, clock_mhz, 919 (freq_match) ? "*" : ""); 920 } 921 break; 922 default: 923 return -EINVAL; 924 } 925 926 return 0; 927 } 928 929 static int aldebaran_upload_dpm_level(struct smu_context *smu, 930 bool max, 931 uint32_t feature_mask, 932 uint32_t level) 933 { 934 struct smu_13_0_dpm_context *dpm_context = 935 smu->smu_dpm.dpm_context; 936 uint32_t freq; 937 int ret = 0; 938 939 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 940 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) { 941 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value; 942 ret = smu_cmn_send_smc_msg_with_param(smu, 943 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 944 (PPCLK_GFXCLK << 16) | (freq & 0xffff), 945 NULL); 946 if (ret) { 947 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n", 948 max ? "max" : "min"); 949 return ret; 950 } 951 } 952 953 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 954 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) { 955 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value; 956 ret = smu_cmn_send_smc_msg_with_param(smu, 957 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 958 (PPCLK_UCLK << 16) | (freq & 0xffff), 959 NULL); 960 if (ret) { 961 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n", 962 max ? "max" : "min"); 963 return ret; 964 } 965 } 966 967 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) && 968 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) { 969 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value; 970 ret = smu_cmn_send_smc_msg_with_param(smu, 971 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 972 (PPCLK_SOCCLK << 16) | (freq & 0xffff), 973 NULL); 974 if (ret) { 975 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n", 976 max ? "max" : "min"); 977 return ret; 978 } 979 } 980 981 return ret; 982 } 983 984 static int aldebaran_force_clk_levels(struct smu_context *smu, 985 enum smu_clk_type type, uint32_t mask) 986 { 987 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 988 struct smu_13_0_dpm_table *single_dpm_table = NULL; 989 uint32_t soft_min_level, soft_max_level; 990 int ret = 0; 991 992 soft_min_level = mask ? (ffs(mask) - 1) : 0; 993 soft_max_level = mask ? (fls(mask) - 1) : 0; 994 995 switch (type) { 996 case SMU_SCLK: 997 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 998 if (soft_max_level >= single_dpm_table->count) { 999 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n", 1000 soft_max_level, single_dpm_table->count - 1); 1001 ret = -EINVAL; 1002 break; 1003 } 1004 1005 ret = aldebaran_upload_dpm_level(smu, 1006 false, 1007 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 1008 soft_min_level); 1009 if (ret) { 1010 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n"); 1011 break; 1012 } 1013 1014 ret = aldebaran_upload_dpm_level(smu, 1015 true, 1016 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 1017 soft_max_level); 1018 if (ret) 1019 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n"); 1020 1021 break; 1022 1023 case SMU_MCLK: 1024 case SMU_SOCCLK: 1025 case SMU_FCLK: 1026 /* 1027 * Should not arrive here since aldebaran does not 1028 * support mclk/socclk/fclk softmin/softmax settings 1029 */ 1030 ret = -EINVAL; 1031 break; 1032 1033 default: 1034 break; 1035 } 1036 1037 return ret; 1038 } 1039 1040 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu, 1041 struct smu_temperature_range *range) 1042 { 1043 struct smu_table_context *table_context = &smu->smu_table; 1044 struct smu_13_0_powerplay_table *powerplay_table = 1045 table_context->power_play_table; 1046 PPTable_t *pptable = smu->smu_table.driver_pptable; 1047 1048 if (!range) 1049 return -EINVAL; 1050 1051 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 1052 1053 range->hotspot_crit_max = pptable->ThotspotLimit * 1054 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1055 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 1056 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1057 range->mem_crit_max = pptable->TmemLimit * 1058 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1059 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 1060 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1061 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1062 1063 return 0; 1064 } 1065 1066 static int aldebaran_get_current_activity_percent(struct smu_context *smu, 1067 enum amd_pp_sensors sensor, 1068 uint32_t *value) 1069 { 1070 int ret = 0; 1071 1072 if (!value) 1073 return -EINVAL; 1074 1075 switch (sensor) { 1076 case AMDGPU_PP_SENSOR_GPU_LOAD: 1077 ret = aldebaran_get_smu_metrics_data(smu, 1078 METRICS_AVERAGE_GFXACTIVITY, 1079 value); 1080 break; 1081 case AMDGPU_PP_SENSOR_MEM_LOAD: 1082 ret = aldebaran_get_smu_metrics_data(smu, 1083 METRICS_AVERAGE_MEMACTIVITY, 1084 value); 1085 break; 1086 default: 1087 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n"); 1088 return -EINVAL; 1089 } 1090 1091 return ret; 1092 } 1093 1094 static int aldebaran_thermal_get_temperature(struct smu_context *smu, 1095 enum amd_pp_sensors sensor, 1096 uint32_t *value) 1097 { 1098 int ret = 0; 1099 1100 if (!value) 1101 return -EINVAL; 1102 1103 switch (sensor) { 1104 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1105 ret = aldebaran_get_smu_metrics_data(smu, 1106 METRICS_TEMPERATURE_HOTSPOT, 1107 value); 1108 break; 1109 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1110 ret = aldebaran_get_smu_metrics_data(smu, 1111 METRICS_TEMPERATURE_EDGE, 1112 value); 1113 break; 1114 case AMDGPU_PP_SENSOR_MEM_TEMP: 1115 ret = aldebaran_get_smu_metrics_data(smu, 1116 METRICS_TEMPERATURE_MEM, 1117 value); 1118 break; 1119 default: 1120 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n"); 1121 return -EINVAL; 1122 } 1123 1124 return ret; 1125 } 1126 1127 static int aldebaran_read_sensor(struct smu_context *smu, 1128 enum amd_pp_sensors sensor, 1129 void *data, uint32_t *size) 1130 { 1131 int ret = 0; 1132 1133 if (amdgpu_ras_intr_triggered()) 1134 return 0; 1135 1136 if (!data || !size) 1137 return -EINVAL; 1138 1139 switch (sensor) { 1140 case AMDGPU_PP_SENSOR_MEM_LOAD: 1141 case AMDGPU_PP_SENSOR_GPU_LOAD: 1142 ret = aldebaran_get_current_activity_percent(smu, 1143 sensor, 1144 (uint32_t *)data); 1145 *size = 4; 1146 break; 1147 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 1148 ret = aldebaran_get_smu_metrics_data(smu, 1149 METRICS_AVERAGE_SOCKETPOWER, 1150 (uint32_t *)data); 1151 *size = 4; 1152 break; 1153 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1154 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1155 case AMDGPU_PP_SENSOR_MEM_TEMP: 1156 ret = aldebaran_thermal_get_temperature(smu, sensor, 1157 (uint32_t *)data); 1158 *size = 4; 1159 break; 1160 case AMDGPU_PP_SENSOR_GFX_MCLK: 1161 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1162 /* the output clock frequency in 10K unit */ 1163 *(uint32_t *)data *= 100; 1164 *size = 4; 1165 break; 1166 case AMDGPU_PP_SENSOR_GFX_SCLK: 1167 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1168 *(uint32_t *)data *= 100; 1169 *size = 4; 1170 break; 1171 case AMDGPU_PP_SENSOR_VDDGFX: 1172 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data); 1173 *size = 4; 1174 break; 1175 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 1176 default: 1177 ret = -EOPNOTSUPP; 1178 break; 1179 } 1180 1181 return ret; 1182 } 1183 1184 static int aldebaran_get_power_limit(struct smu_context *smu, 1185 uint32_t *current_power_limit, 1186 uint32_t *default_power_limit, 1187 uint32_t *max_power_limit, 1188 uint32_t *min_power_limit) 1189 { 1190 PPTable_t *pptable = smu->smu_table.driver_pptable; 1191 uint32_t power_limit = 0; 1192 int ret; 1193 1194 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 1195 if (current_power_limit) 1196 *current_power_limit = 0; 1197 if (default_power_limit) 1198 *default_power_limit = 0; 1199 if (max_power_limit) 1200 *max_power_limit = 0; 1201 if (min_power_limit) 1202 *min_power_limit = 0; 1203 dev_warn(smu->adev->dev, 1204 "PPT feature is not enabled, power values can't be fetched."); 1205 1206 return 0; 1207 } 1208 1209 /* Valid power data is available only from primary die. 1210 * For secondary die show the value as 0. 1211 */ 1212 if (aldebaran_is_primary(smu)) { 1213 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, 1214 &power_limit); 1215 1216 if (ret) { 1217 /* the last hope to figure out the ppt limit */ 1218 if (!pptable) { 1219 dev_err(smu->adev->dev, 1220 "Cannot get PPT limit due to pptable missing!"); 1221 return -EINVAL; 1222 } 1223 power_limit = pptable->PptLimit; 1224 } 1225 } 1226 1227 if (current_power_limit) 1228 *current_power_limit = power_limit; 1229 if (default_power_limit) 1230 *default_power_limit = power_limit; 1231 1232 if (max_power_limit) { 1233 if (pptable) 1234 *max_power_limit = pptable->PptLimit; 1235 } 1236 1237 if (min_power_limit) 1238 *min_power_limit = 0; 1239 1240 return 0; 1241 } 1242 1243 static int aldebaran_set_power_limit(struct smu_context *smu, 1244 enum smu_ppt_limit_type limit_type, 1245 uint32_t limit) 1246 { 1247 /* Power limit can be set only through primary die */ 1248 if (aldebaran_is_primary(smu)) 1249 return smu_v13_0_set_power_limit(smu, limit_type, limit); 1250 1251 return -EINVAL; 1252 } 1253 1254 static int aldebaran_system_features_control(struct smu_context *smu, bool enable) 1255 { 1256 int ret; 1257 1258 ret = smu_v13_0_system_features_control(smu, enable); 1259 if (!ret && enable) 1260 ret = aldebaran_run_btc(smu); 1261 1262 return ret; 1263 } 1264 1265 static int aldebaran_set_performance_level(struct smu_context *smu, 1266 enum amd_dpm_forced_level level) 1267 { 1268 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1269 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1270 struct smu_13_0_dpm_table *gfx_table = 1271 &dpm_context->dpm_tables.gfx_table; 1272 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1273 1274 /* Disable determinism if switching to another mode */ 1275 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) && 1276 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) { 1277 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL); 1278 pstate_table->gfxclk_pstate.curr.max = gfx_table->max; 1279 } 1280 1281 switch (level) { 1282 1283 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM: 1284 return 0; 1285 1286 case AMD_DPM_FORCED_LEVEL_HIGH: 1287 case AMD_DPM_FORCED_LEVEL_LOW: 1288 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1289 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1290 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1291 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1292 default: 1293 break; 1294 } 1295 1296 return smu_v13_0_set_performance_level(smu, level); 1297 } 1298 1299 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu, 1300 enum smu_clk_type clk_type, 1301 uint32_t min, 1302 uint32_t max) 1303 { 1304 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1305 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1306 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1307 struct amdgpu_device *adev = smu->adev; 1308 uint32_t min_clk; 1309 uint32_t max_clk; 1310 int ret = 0; 1311 1312 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) 1313 return -EINVAL; 1314 1315 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1316 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1317 return -EINVAL; 1318 1319 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 1320 if (min >= max) { 1321 dev_err(smu->adev->dev, 1322 "Minimum GFX clk should be less than the maximum allowed clock\n"); 1323 return -EINVAL; 1324 } 1325 1326 if ((min == pstate_table->gfxclk_pstate.curr.min) && 1327 (max == pstate_table->gfxclk_pstate.curr.max)) 1328 return 0; 1329 1330 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, 1331 min, max); 1332 if (!ret) { 1333 pstate_table->gfxclk_pstate.curr.min = min; 1334 pstate_table->gfxclk_pstate.curr.max = max; 1335 } 1336 1337 return ret; 1338 } 1339 1340 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1341 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) || 1342 (max > dpm_context->dpm_tables.gfx_table.max)) { 1343 dev_warn(adev->dev, 1344 "Invalid max frequency %d MHz specified for determinism\n", max); 1345 return -EINVAL; 1346 } 1347 1348 /* Restore default min/max clocks and enable determinism */ 1349 min_clk = dpm_context->dpm_tables.gfx_table.min; 1350 max_clk = dpm_context->dpm_tables.gfx_table.max; 1351 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1352 if (!ret) { 1353 usleep_range(500, 1000); 1354 ret = smu_cmn_send_smc_msg_with_param(smu, 1355 SMU_MSG_EnableDeterminism, 1356 max, NULL); 1357 if (ret) { 1358 dev_err(adev->dev, 1359 "Failed to enable determinism at GFX clock %d MHz\n", max); 1360 } else { 1361 pstate_table->gfxclk_pstate.curr.min = min_clk; 1362 pstate_table->gfxclk_pstate.curr.max = max; 1363 } 1364 } 1365 } 1366 1367 return ret; 1368 } 1369 1370 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1371 long input[], uint32_t size) 1372 { 1373 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1374 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1375 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1376 uint32_t min_clk; 1377 uint32_t max_clk; 1378 int ret = 0; 1379 1380 /* Only allowed in manual or determinism mode */ 1381 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1382 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1383 return -EINVAL; 1384 1385 switch (type) { 1386 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1387 if (size != 2) { 1388 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1389 return -EINVAL; 1390 } 1391 1392 if (input[0] == 0) { 1393 if (input[1] < dpm_context->dpm_tables.gfx_table.min) { 1394 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", 1395 input[1], dpm_context->dpm_tables.gfx_table.min); 1396 pstate_table->gfxclk_pstate.custom.min = 1397 pstate_table->gfxclk_pstate.curr.min; 1398 return -EINVAL; 1399 } 1400 1401 pstate_table->gfxclk_pstate.custom.min = input[1]; 1402 } else if (input[0] == 1) { 1403 if (input[1] > dpm_context->dpm_tables.gfx_table.max) { 1404 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", 1405 input[1], dpm_context->dpm_tables.gfx_table.max); 1406 pstate_table->gfxclk_pstate.custom.max = 1407 pstate_table->gfxclk_pstate.curr.max; 1408 return -EINVAL; 1409 } 1410 1411 pstate_table->gfxclk_pstate.custom.max = input[1]; 1412 } else { 1413 return -EINVAL; 1414 } 1415 break; 1416 case PP_OD_RESTORE_DEFAULT_TABLE: 1417 if (size != 0) { 1418 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1419 return -EINVAL; 1420 } else { 1421 /* Use the default frequencies for manual and determinism mode */ 1422 min_clk = dpm_context->dpm_tables.gfx_table.min; 1423 max_clk = dpm_context->dpm_tables.gfx_table.max; 1424 1425 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1426 } 1427 break; 1428 case PP_OD_COMMIT_DPM_TABLE: 1429 if (size != 0) { 1430 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1431 return -EINVAL; 1432 } else { 1433 if (!pstate_table->gfxclk_pstate.custom.min) 1434 pstate_table->gfxclk_pstate.custom.min = 1435 pstate_table->gfxclk_pstate.curr.min; 1436 1437 if (!pstate_table->gfxclk_pstate.custom.max) 1438 pstate_table->gfxclk_pstate.custom.max = 1439 pstate_table->gfxclk_pstate.curr.max; 1440 1441 min_clk = pstate_table->gfxclk_pstate.custom.min; 1442 max_clk = pstate_table->gfxclk_pstate.custom.max; 1443 1444 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1445 } 1446 break; 1447 default: 1448 return -ENOSYS; 1449 } 1450 1451 return ret; 1452 } 1453 1454 static bool aldebaran_is_dpm_running(struct smu_context *smu) 1455 { 1456 int ret; 1457 uint64_t feature_enabled; 1458 1459 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1460 if (ret) 1461 return false; 1462 return !!(feature_enabled & SMC_DPM_FEATURE); 1463 } 1464 1465 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap, 1466 struct i2c_msg *msg, int num_msgs) 1467 { 1468 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 1469 struct amdgpu_device *adev = smu_i2c->adev; 1470 struct smu_context *smu = adev->powerplay.pp_handle; 1471 struct smu_table_context *smu_table = &smu->smu_table; 1472 struct smu_table *table = &smu_table->driver_table; 1473 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 1474 int i, j, r, c; 1475 u16 dir; 1476 1477 if (!adev->pm.dpm_enabled) 1478 return -EBUSY; 1479 1480 req = kzalloc(sizeof(*req), GFP_KERNEL); 1481 if (!req) 1482 return -ENOMEM; 1483 1484 req->I2CcontrollerPort = smu_i2c->port; 1485 req->I2CSpeed = I2C_SPEED_FAST_400K; 1486 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 1487 dir = msg[0].flags & I2C_M_RD; 1488 1489 for (c = i = 0; i < num_msgs; i++) { 1490 for (j = 0; j < msg[i].len; j++, c++) { 1491 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 1492 1493 if (!(msg[i].flags & I2C_M_RD)) { 1494 /* write */ 1495 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 1496 cmd->ReadWriteData = msg[i].buf[j]; 1497 } 1498 1499 if ((dir ^ msg[i].flags) & I2C_M_RD) { 1500 /* The direction changes. 1501 */ 1502 dir = msg[i].flags & I2C_M_RD; 1503 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 1504 } 1505 1506 req->NumCmds++; 1507 1508 /* 1509 * Insert STOP if we are at the last byte of either last 1510 * message for the transaction or the client explicitly 1511 * requires a STOP at this particular message. 1512 */ 1513 if ((j == msg[i].len - 1) && 1514 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 1515 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 1516 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 1517 } 1518 } 1519 } 1520 mutex_lock(&adev->pm.mutex); 1521 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 1522 if (r) 1523 goto fail; 1524 1525 for (c = i = 0; i < num_msgs; i++) { 1526 if (!(msg[i].flags & I2C_M_RD)) { 1527 c += msg[i].len; 1528 continue; 1529 } 1530 for (j = 0; j < msg[i].len; j++, c++) { 1531 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 1532 1533 msg[i].buf[j] = cmd->ReadWriteData; 1534 } 1535 } 1536 r = num_msgs; 1537 fail: 1538 mutex_unlock(&adev->pm.mutex); 1539 kfree(req); 1540 return r; 1541 } 1542 1543 static u32 aldebaran_i2c_func(struct i2c_adapter *adap) 1544 { 1545 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1546 } 1547 1548 1549 static const struct i2c_algorithm aldebaran_i2c_algo = { 1550 .master_xfer = aldebaran_i2c_xfer, 1551 .functionality = aldebaran_i2c_func, 1552 }; 1553 1554 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = { 1555 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 1556 .max_read_len = MAX_SW_I2C_COMMANDS, 1557 .max_write_len = MAX_SW_I2C_COMMANDS, 1558 .max_comb_1st_msg_len = 2, 1559 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 1560 }; 1561 1562 static int aldebaran_i2c_control_init(struct smu_context *smu) 1563 { 1564 struct amdgpu_device *adev = smu->adev; 1565 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0]; 1566 struct i2c_adapter *control = &smu_i2c->adapter; 1567 int res; 1568 1569 smu_i2c->adev = adev; 1570 smu_i2c->port = 0; 1571 mutex_init(&smu_i2c->mutex); 1572 control->owner = THIS_MODULE; 1573 control->dev.parent = &adev->pdev->dev; 1574 control->algo = &aldebaran_i2c_algo; 1575 snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0"); 1576 control->quirks = &aldebaran_i2c_control_quirks; 1577 i2c_set_adapdata(control, smu_i2c); 1578 1579 res = i2c_add_adapter(control); 1580 if (res) { 1581 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 1582 goto Out_err; 1583 } 1584 1585 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 1586 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 1587 1588 return 0; 1589 Out_err: 1590 i2c_del_adapter(control); 1591 1592 return res; 1593 } 1594 1595 static void aldebaran_i2c_control_fini(struct smu_context *smu) 1596 { 1597 struct amdgpu_device *adev = smu->adev; 1598 int i; 1599 1600 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 1601 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 1602 struct i2c_adapter *control = &smu_i2c->adapter; 1603 1604 i2c_del_adapter(control); 1605 } 1606 adev->pm.ras_eeprom_i2c_bus = NULL; 1607 adev->pm.fru_eeprom_i2c_bus = NULL; 1608 } 1609 1610 static void aldebaran_get_unique_id(struct smu_context *smu) 1611 { 1612 struct amdgpu_device *adev = smu->adev; 1613 uint32_t upper32 = 0, lower32 = 0; 1614 1615 if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32)) 1616 goto out; 1617 if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32)) 1618 goto out; 1619 1620 out: 1621 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1622 } 1623 1624 static int aldebaran_get_bamaco_support(struct smu_context *smu) 1625 { 1626 /* aldebaran is not support baco */ 1627 1628 return 0; 1629 } 1630 1631 static int aldebaran_set_df_cstate(struct smu_context *smu, 1632 enum pp_df_cstate state) 1633 { 1634 struct amdgpu_device *adev = smu->adev; 1635 1636 /* 1637 * Aldebaran does not need the cstate disablement 1638 * prerequisite for gpu reset. 1639 */ 1640 if (amdgpu_in_reset(adev) || adev->in_suspend) 1641 return 0; 1642 1643 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL); 1644 } 1645 1646 static const struct throttling_logging_label { 1647 uint32_t feature_mask; 1648 const char *label; 1649 } logging_label[] = { 1650 {(1U << THROTTLER_TEMP_GPU_BIT), "GPU"}, 1651 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"}, 1652 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"}, 1653 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"}, 1654 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"}, 1655 }; 1656 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu) 1657 { 1658 int ret; 1659 int throttler_idx, throttling_events = 0, buf_idx = 0; 1660 struct amdgpu_device *adev = smu->adev; 1661 uint32_t throttler_status; 1662 char log_buf[256]; 1663 1664 ret = aldebaran_get_smu_metrics_data(smu, 1665 METRICS_THROTTLER_STATUS, 1666 &throttler_status); 1667 if (ret) 1668 return; 1669 1670 memset(log_buf, 0, sizeof(log_buf)); 1671 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label); 1672 throttler_idx++) { 1673 if (throttler_status & logging_label[throttler_idx].feature_mask) { 1674 throttling_events++; 1675 buf_idx += snprintf(log_buf + buf_idx, 1676 sizeof(log_buf) - buf_idx, 1677 "%s%s", 1678 throttling_events > 1 ? " and " : "", 1679 logging_label[throttler_idx].label); 1680 if (buf_idx >= sizeof(log_buf)) { 1681 dev_err(adev->dev, "buffer overflow!\n"); 1682 log_buf[sizeof(log_buf) - 1] = '\0'; 1683 break; 1684 } 1685 } 1686 } 1687 1688 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n", 1689 log_buf); 1690 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, 1691 smu_cmn_get_indep_throttler_status(throttler_status, 1692 aldebaran_throttler_map)); 1693 } 1694 1695 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu) 1696 { 1697 struct amdgpu_device *adev = smu->adev; 1698 uint32_t esm_ctrl; 1699 1700 /* TODO: confirm this on real target */ 1701 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); 1702 if ((esm_ctrl >> 15) & 0x1) 1703 return (((esm_ctrl >> 8) & 0x7F) + 128); 1704 1705 return smu_v13_0_get_current_pcie_link_speed(smu); 1706 } 1707 1708 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, 1709 void **table) 1710 { 1711 struct smu_table_context *smu_table = &smu->smu_table; 1712 struct gpu_metrics_v1_3 *gpu_metrics = 1713 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 1714 SmuMetrics_t metrics; 1715 int i, ret = 0; 1716 1717 ret = smu_cmn_get_metrics_table(smu, 1718 &metrics, 1719 true); 1720 if (ret) 1721 return ret; 1722 1723 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 1724 1725 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 1726 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 1727 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 1728 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 1729 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 1730 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 1731 1732 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1733 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 1734 gpu_metrics->average_mm_activity = 0; 1735 1736 /* Valid power data is available only from primary die */ 1737 if (aldebaran_is_primary(smu)) { 1738 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 1739 gpu_metrics->energy_accumulator = 1740 (uint64_t)metrics.EnergyAcc64bitHigh << 32 | 1741 metrics.EnergyAcc64bitLow; 1742 } else { 1743 gpu_metrics->average_socket_power = 0; 1744 gpu_metrics->energy_accumulator = 0; 1745 } 1746 1747 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1748 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1749 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 1750 gpu_metrics->average_vclk0_frequency = 0; 1751 gpu_metrics->average_dclk0_frequency = 0; 1752 1753 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 1754 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 1755 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 1756 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 1757 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 1758 1759 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1760 gpu_metrics->indep_throttle_status = 1761 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1762 aldebaran_throttler_map); 1763 1764 gpu_metrics->current_fan_speed = 0; 1765 1766 if (!amdgpu_sriov_vf(smu->adev)) { 1767 gpu_metrics->pcie_link_width = 1768 smu_v13_0_get_current_pcie_link_width(smu); 1769 gpu_metrics->pcie_link_speed = 1770 aldebaran_get_current_pcie_link_speed(smu); 1771 } 1772 1773 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1774 1775 gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc; 1776 gpu_metrics->mem_activity_acc = metrics.DramBusyAcc; 1777 1778 for (i = 0; i < NUM_HBM_INSTANCES; i++) 1779 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i]; 1780 1781 gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) | 1782 metrics.TimeStampLow; 1783 1784 *table = (void *)gpu_metrics; 1785 1786 return sizeof(struct gpu_metrics_v1_3); 1787 } 1788 1789 static int aldebaran_check_ecc_table_support(struct smu_context *smu, 1790 int *ecctable_version) 1791 { 1792 if (smu->smc_fw_version < SUPPORT_ECCTABLE_SMU_VERSION) 1793 return -EOPNOTSUPP; 1794 else if (smu->smc_fw_version >= SUPPORT_ECCTABLE_SMU_VERSION && 1795 smu->smc_fw_version < SUPPORT_ECCTABLE_V2_SMU_VERSION) 1796 *ecctable_version = 1; 1797 else 1798 *ecctable_version = 2; 1799 1800 return 0; 1801 } 1802 1803 static ssize_t aldebaran_get_ecc_info(struct smu_context *smu, 1804 void *table) 1805 { 1806 struct smu_table_context *smu_table = &smu->smu_table; 1807 EccInfoTable_t *ecc_table = NULL; 1808 struct ecc_info_per_ch *ecc_info_per_channel = NULL; 1809 int i, ret = 0; 1810 int table_version = 0; 1811 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; 1812 1813 ret = aldebaran_check_ecc_table_support(smu, &table_version); 1814 if (ret) 1815 return ret; 1816 1817 ret = smu_cmn_update_table(smu, 1818 SMU_TABLE_ECCINFO, 1819 0, 1820 smu_table->ecc_table, 1821 false); 1822 if (ret) { 1823 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n"); 1824 return ret; 1825 } 1826 1827 ecc_table = (EccInfoTable_t *)smu_table->ecc_table; 1828 1829 if (table_version == 1) { 1830 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) { 1831 ecc_info_per_channel = &(eccinfo->ecc[i]); 1832 ecc_info_per_channel->ce_count_lo_chip = 1833 ecc_table->EccInfo[i].ce_count_lo_chip; 1834 ecc_info_per_channel->ce_count_hi_chip = 1835 ecc_table->EccInfo[i].ce_count_hi_chip; 1836 ecc_info_per_channel->mca_umc_status = 1837 ecc_table->EccInfo[i].mca_umc_status; 1838 ecc_info_per_channel->mca_umc_addr = 1839 ecc_table->EccInfo[i].mca_umc_addr; 1840 } 1841 } else if (table_version == 2) { 1842 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) { 1843 ecc_info_per_channel = &(eccinfo->ecc[i]); 1844 ecc_info_per_channel->ce_count_lo_chip = 1845 ecc_table->EccInfo_V2[i].ce_count_lo_chip; 1846 ecc_info_per_channel->ce_count_hi_chip = 1847 ecc_table->EccInfo_V2[i].ce_count_hi_chip; 1848 ecc_info_per_channel->mca_umc_status = 1849 ecc_table->EccInfo_V2[i].mca_umc_status; 1850 ecc_info_per_channel->mca_umc_addr = 1851 ecc_table->EccInfo_V2[i].mca_umc_addr; 1852 ecc_info_per_channel->mca_ceumc_addr = 1853 ecc_table->EccInfo_V2[i].mca_ceumc_addr; 1854 } 1855 eccinfo->record_ce_addr_supported = 1; 1856 } 1857 1858 return ret; 1859 } 1860 1861 static int aldebaran_mode1_reset(struct smu_context *smu) 1862 { 1863 u32 fatal_err, param; 1864 int ret = 0; 1865 struct amdgpu_device *adev = smu->adev; 1866 1867 fatal_err = 0; 1868 param = SMU_RESET_MODE_1; 1869 1870 /* 1871 * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07 1872 */ 1873 if (smu->smc_fw_version < 0x00440700) { 1874 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 1875 } else { 1876 /* fatal error triggered by ras, PMFW supports the flag 1877 from 68.44.0 */ 1878 if ((smu->smc_fw_version >= 0x00442c00) && 1879 amdgpu_ras_get_fed_status(adev)) 1880 fatal_err = 1; 1881 1882 param |= (fatal_err << 16); 1883 ret = smu_cmn_send_smc_msg_with_param(smu, 1884 SMU_MSG_GfxDeviceDriverReset, param, NULL); 1885 } 1886 1887 if (!ret) 1888 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); 1889 1890 return ret; 1891 } 1892 1893 static int aldebaran_mode2_reset(struct smu_context *smu) 1894 { 1895 int ret = 0, index; 1896 struct amdgpu_device *adev = smu->adev; 1897 int timeout = 10; 1898 1899 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 1900 SMU_MSG_GfxDeviceDriverReset); 1901 if (index < 0 ) 1902 return -EINVAL; 1903 mutex_lock(&smu->message_lock); 1904 if (smu->smc_fw_version >= 0x00441400) { 1905 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2); 1906 /* This is similar to FLR, wait till max FLR timeout */ 1907 msleep(100); 1908 dev_dbg(smu->adev->dev, "restore config space...\n"); 1909 /* Restore the config space saved during init */ 1910 amdgpu_device_load_pci_state(adev->pdev); 1911 1912 dev_dbg(smu->adev->dev, "wait for reset ack\n"); 1913 while (ret == -ETIME && timeout) { 1914 ret = smu_cmn_wait_for_response(smu); 1915 /* Wait a bit more time for getting ACK */ 1916 if (ret == -ETIME) { 1917 --timeout; 1918 usleep_range(500, 1000); 1919 continue; 1920 } 1921 1922 if (ret != 1) { 1923 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n", 1924 SMU_RESET_MODE_2, ret); 1925 goto out; 1926 } 1927 } 1928 1929 } else { 1930 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n", 1931 smu->smc_fw_version); 1932 } 1933 1934 if (ret == 1) 1935 ret = 0; 1936 out: 1937 mutex_unlock(&smu->message_lock); 1938 1939 return ret; 1940 } 1941 1942 static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 1943 { 1944 int ret = 0; 1945 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL); 1946 1947 return ret; 1948 } 1949 1950 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu) 1951 { 1952 #if 0 1953 struct amdgpu_device *adev = smu->adev; 1954 uint32_t val; 1955 uint32_t smu_version; 1956 int ret; 1957 1958 /** 1959 * PM FW version support mode1 reset from 68.07 1960 */ 1961 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 1962 if (ret) 1963 return false; 1964 1965 if ((smu_version < 0x00440700)) 1966 return false; 1967 1968 /** 1969 * mode1 reset relies on PSP, so we should check if 1970 * PSP is alive. 1971 */ 1972 val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 1973 1974 return val != 0x0; 1975 #endif 1976 return true; 1977 } 1978 1979 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu) 1980 { 1981 return true; 1982 } 1983 1984 static int aldebaran_set_mp1_state(struct smu_context *smu, 1985 enum pp_mp1_state mp1_state) 1986 { 1987 switch (mp1_state) { 1988 case PP_MP1_STATE_UNLOAD: 1989 return smu_cmn_set_mp1_state(smu, mp1_state); 1990 default: 1991 return 0; 1992 } 1993 } 1994 1995 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu, 1996 uint32_t size) 1997 { 1998 int ret = 0; 1999 2000 /* message SMU to update the bad page number on SMUBUS */ 2001 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL); 2002 if (ret) 2003 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n", 2004 __func__); 2005 2006 return ret; 2007 } 2008 2009 static int aldebaran_check_bad_channel_info_support(struct smu_context *smu) 2010 { 2011 if (smu->smc_fw_version < SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION) 2012 return -EOPNOTSUPP; 2013 2014 return 0; 2015 } 2016 2017 static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu, 2018 uint32_t size) 2019 { 2020 int ret = 0; 2021 2022 ret = aldebaran_check_bad_channel_info_support(smu); 2023 if (ret) 2024 return ret; 2025 2026 /* message SMU to update the bad channel info on SMUBUS */ 2027 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetBadHBMPagesRetiredFlagsPerChannel, size, NULL); 2028 if (ret) 2029 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad channel info\n", 2030 __func__); 2031 2032 return ret; 2033 } 2034 2035 static const struct pptable_funcs aldebaran_ppt_funcs = { 2036 /* init dpm */ 2037 .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask, 2038 /* dpm/clk tables */ 2039 .set_default_dpm_table = aldebaran_set_default_dpm_table, 2040 .populate_umd_state_clk = aldebaran_populate_umd_state_clk, 2041 .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range, 2042 .emit_clk_levels = aldebaran_emit_clk_levels, 2043 .force_clk_levels = aldebaran_force_clk_levels, 2044 .read_sensor = aldebaran_read_sensor, 2045 .set_performance_level = aldebaran_set_performance_level, 2046 .get_power_limit = aldebaran_get_power_limit, 2047 .is_dpm_running = aldebaran_is_dpm_running, 2048 .get_unique_id = aldebaran_get_unique_id, 2049 .init_microcode = smu_v13_0_init_microcode, 2050 .load_microcode = smu_v13_0_load_microcode, 2051 .fini_microcode = smu_v13_0_fini_microcode, 2052 .init_smc_tables = aldebaran_init_smc_tables, 2053 .fini_smc_tables = smu_v13_0_fini_smc_tables, 2054 .init_power = smu_v13_0_init_power, 2055 .fini_power = smu_v13_0_fini_power, 2056 .check_fw_status = smu_v13_0_check_fw_status, 2057 /* pptable related */ 2058 .setup_pptable = aldebaran_setup_pptable, 2059 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 2060 .check_fw_version = smu_v13_0_check_fw_version, 2061 .write_pptable = smu_cmn_write_pptable, 2062 .set_driver_table_location = smu_v13_0_set_driver_table_location, 2063 .set_tool_table_location = smu_v13_0_set_tool_table_location, 2064 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 2065 .system_features_control = aldebaran_system_features_control, 2066 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2067 .send_smc_msg = smu_cmn_send_smc_msg, 2068 .get_enabled_mask = smu_cmn_get_enabled_mask, 2069 .feature_is_enabled = smu_cmn_feature_is_enabled, 2070 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 2071 .set_power_limit = aldebaran_set_power_limit, 2072 .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks, 2073 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 2074 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 2075 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate, 2076 .register_irq_handler = smu_v13_0_register_irq_handler, 2077 .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme, 2078 .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc, 2079 .get_bamaco_support = aldebaran_get_bamaco_support, 2080 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, 2081 .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range, 2082 .od_edit_dpm_table = aldebaran_usr_edit_dpm_table, 2083 .set_df_cstate = aldebaran_set_df_cstate, 2084 .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event, 2085 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2086 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 2087 .get_gpu_metrics = aldebaran_get_gpu_metrics, 2088 .mode1_reset_is_support = aldebaran_is_mode1_reset_supported, 2089 .mode2_reset_is_support = aldebaran_is_mode2_reset_supported, 2090 .smu_handle_passthrough_sbr = aldebaran_smu_handle_passthrough_sbr, 2091 .mode1_reset = aldebaran_mode1_reset, 2092 .set_mp1_state = aldebaran_set_mp1_state, 2093 .mode2_reset = aldebaran_mode2_reset, 2094 .wait_for_event = smu_v13_0_wait_for_event, 2095 .i2c_init = aldebaran_i2c_control_init, 2096 .i2c_fini = aldebaran_i2c_control_fini, 2097 .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num, 2098 .get_ecc_info = aldebaran_get_ecc_info, 2099 .send_hbm_bad_channel_flag = aldebaran_send_hbm_bad_channel_flag, 2100 }; 2101 2102 void aldebaran_set_ppt_funcs(struct smu_context *smu) 2103 { 2104 smu->ppt_funcs = &aldebaran_ppt_funcs; 2105 smu->message_map = aldebaran_message_map; 2106 smu->clock_map = aldebaran_clk_map; 2107 smu->feature_map = aldebaran_feature_mask_map; 2108 smu->table_map = aldebaran_table_map; 2109 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE; 2110 smu_v13_0_set_smu_mailbox_registers(smu); 2111 } 2112