1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include "amdgpu.h" 28 #include "amdgpu_dpm.h" 29 #include "amdgpu_smu.h" 30 #include "atomfirmware.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_atombios.h" 33 #include "smu_v13_0.h" 34 #include "smu13_driver_if_aldebaran.h" 35 #include "soc15_common.h" 36 #include "atom.h" 37 #include "aldebaran_ppt.h" 38 #include "smu_v13_0_pptable.h" 39 #include "aldebaran_ppsmc.h" 40 #include "nbio/nbio_7_4_offset.h" 41 #include "nbio/nbio_7_4_sh_mask.h" 42 #include "thm/thm_11_0_2_offset.h" 43 #include "thm/thm_11_0_2_sh_mask.h" 44 #include "amdgpu_xgmi.h" 45 #include <linux/pci.h> 46 #include "amdgpu_ras.h" 47 #include "smu_cmn.h" 48 #include "mp/mp_13_0_2_offset.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \ 61 [smu_feature] = {1, (aldebaran_feature)} 62 63 #define FEATURE_MASK(feature) (1ULL << feature) 64 #define SMC_DPM_FEATURE ( \ 65 FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \ 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_VCN_BIT)) 73 74 /* possible frequency drift (1Mhz) */ 75 #define EPSILON 1 76 77 #define smnPCIE_ESM_CTRL 0x111003D0 78 79 /* 80 * SMU support ECCTABLE since version 68.42.0, 81 * use this to check ECCTALE feature whether support 82 */ 83 #define SUPPORT_ECCTABLE_SMU_VERSION 0x00442a00 84 85 /* 86 * SMU support mca_ceumc_addr in ECCTABLE since version 68.55.0, 87 * use this to check mca_ceumc_addr record whether support 88 */ 89 #define SUPPORT_ECCTABLE_V2_SMU_VERSION 0x00443700 90 91 /* 92 * SMU support BAD CHENNEL info MSG since version 68.51.00, 93 * use this to check ECCTALE feature whether support 94 */ 95 #define SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION 0x00443300 96 97 static const struct smu_temperature_range smu13_thermal_policy[] = { 98 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 99 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 100 }; 101 102 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = { 103 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 104 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 105 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 106 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 107 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 108 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 109 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 110 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 111 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 112 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 113 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 114 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 115 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 116 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 117 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 118 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 119 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 120 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), 121 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 122 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 123 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0), 124 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0), 125 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 126 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 127 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 128 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 129 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 130 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), 131 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 132 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, 0), 133 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 134 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 135 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 136 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 137 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 138 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0), 139 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0), 140 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0), 141 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), 142 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0), 143 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0), 144 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0), 145 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0), 146 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0), 147 MSG_MAP(SetExecuteDMATest, PPSMC_MSG_SetExecuteDMATest, 0), 148 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0), 149 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0), 150 MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0), 151 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0), 152 MSG_MAP(BoardPowerCalibration, PPSMC_MSG_BoardPowerCalibration, 0), 153 MSG_MAP(HeavySBR, PPSMC_MSG_HeavySBR, 0), 154 MSG_MAP(SetBadHBMPagesRetiredFlagsPerChannel, PPSMC_MSG_SetBadHBMPagesRetiredFlagsPerChannel, 0), 155 }; 156 157 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = { 158 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 159 CLK_MAP(SCLK, PPCLK_GFXCLK), 160 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 161 CLK_MAP(FCLK, PPCLK_FCLK), 162 CLK_MAP(UCLK, PPCLK_UCLK), 163 CLK_MAP(MCLK, PPCLK_UCLK), 164 CLK_MAP(DCLK, PPCLK_DCLK), 165 CLK_MAP(VCLK, PPCLK_VCLK), 166 CLK_MAP(LCLK, PPCLK_LCLK), 167 }; 168 169 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = { 170 ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATIONS), 171 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK_BIT), 172 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK_BIT), 173 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK_BIT), 174 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK_BIT), 175 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK_BIT), 176 ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI_BIT), 177 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK_BIT), 178 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK_BIT), 179 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK_BIT), 180 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK_BIT), 181 ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT, FEATURE_DS_UCLK_BIT), 182 ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT, FEATURE_GFX_SS_BIT), 183 ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT), 184 ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT, FEATURE_RSMU_SMN_CG_BIT), 185 ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT, FEATURE_WAFL_CG_BIT), 186 ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT_BIT), 187 ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC_BIT), 188 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT, FEATURE_APCC_PLUS_BIT), 189 ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL_BIT), 190 ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT, FEATURE_FUSE_CG_BIT), 191 ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_MP1_CG_BIT), 192 ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT, FEATURE_SMUIO_CG_BIT), 193 ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT, FEATURE_THM_CG_BIT), 194 ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT, FEATURE_CLK_CG_BIT), 195 ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF_BIT), 196 ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL_BIT), 197 ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, FEATURE_OUT_OF_BAND_MONITOR_BIT), 198 ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DWN), 199 ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE), 200 }; 201 202 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = { 203 TAB_MAP(PPTABLE), 204 TAB_MAP(AVFS_PSM_DEBUG), 205 TAB_MAP(AVFS_FUSE_OVERRIDE), 206 TAB_MAP(PMSTATUSLOG), 207 TAB_MAP(SMU_METRICS), 208 TAB_MAP(DRIVER_SMU_CONFIG), 209 TAB_MAP(I2C_COMMANDS), 210 TAB_MAP(ECCINFO), 211 }; 212 213 static const uint8_t aldebaran_throttler_map[] = { 214 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 215 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 216 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 217 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 218 [THROTTLER_TDC_HBM_BIT] = (SMU_THROTTLER_TDC_MEM_BIT), 219 [THROTTLER_TEMP_GPU_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT), 220 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 221 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 222 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 223 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 224 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 225 }; 226 227 static int aldebaran_tables_init(struct smu_context *smu) 228 { 229 struct smu_table_context *smu_table = &smu->smu_table; 230 struct smu_table *tables = smu_table->tables; 231 232 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 233 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 234 235 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 236 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 237 238 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 239 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 240 241 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 242 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 243 244 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t), 245 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 246 247 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 248 if (!smu_table->metrics_table) 249 return -ENOMEM; 250 smu_table->metrics_time = 0; 251 252 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 253 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 254 if (!smu_table->gpu_metrics_table) { 255 kfree(smu_table->metrics_table); 256 return -ENOMEM; 257 } 258 259 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); 260 if (!smu_table->ecc_table) { 261 kfree(smu_table->metrics_table); 262 kfree(smu_table->gpu_metrics_table); 263 return -ENOMEM; 264 } 265 266 return 0; 267 } 268 269 static int aldebaran_allocate_dpm_context(struct smu_context *smu) 270 { 271 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 272 273 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 274 GFP_KERNEL); 275 if (!smu_dpm->dpm_context) 276 return -ENOMEM; 277 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 278 279 return 0; 280 } 281 282 static int aldebaran_init_smc_tables(struct smu_context *smu) 283 { 284 int ret = 0; 285 286 ret = aldebaran_tables_init(smu); 287 if (ret) 288 return ret; 289 290 ret = aldebaran_allocate_dpm_context(smu); 291 if (ret) 292 return ret; 293 294 return smu_v13_0_init_smc_tables(smu); 295 } 296 297 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu, 298 uint32_t *feature_mask, uint32_t num) 299 { 300 if (num > 2) 301 return -EINVAL; 302 303 /* pptable will handle the features to enable */ 304 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 305 306 return 0; 307 } 308 309 static int aldebaran_set_default_dpm_table(struct smu_context *smu) 310 { 311 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 312 struct smu_13_0_dpm_table *dpm_table = NULL; 313 PPTable_t *pptable = smu->smu_table.driver_pptable; 314 int ret = 0; 315 316 /* socclk dpm table setup */ 317 dpm_table = &dpm_context->dpm_tables.soc_table; 318 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 319 ret = smu_v13_0_set_single_dpm_table(smu, 320 SMU_SOCCLK, 321 dpm_table); 322 if (ret) 323 return ret; 324 } else { 325 dpm_table->count = 1; 326 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 327 dpm_table->dpm_levels[0].enabled = true; 328 dpm_table->min = dpm_table->dpm_levels[0].value; 329 dpm_table->max = dpm_table->dpm_levels[0].value; 330 } 331 332 /* gfxclk dpm table setup */ 333 dpm_table = &dpm_context->dpm_tables.gfx_table; 334 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 335 /* in the case of gfxclk, only fine-grained dpm is honored */ 336 dpm_table->count = 2; 337 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin; 338 dpm_table->dpm_levels[0].enabled = true; 339 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax; 340 dpm_table->dpm_levels[1].enabled = true; 341 dpm_table->min = dpm_table->dpm_levels[0].value; 342 dpm_table->max = dpm_table->dpm_levels[1].value; 343 } else { 344 dpm_table->count = 1; 345 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 346 dpm_table->dpm_levels[0].enabled = true; 347 dpm_table->min = dpm_table->dpm_levels[0].value; 348 dpm_table->max = dpm_table->dpm_levels[0].value; 349 } 350 351 /* memclk dpm table setup */ 352 dpm_table = &dpm_context->dpm_tables.uclk_table; 353 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 354 ret = smu_v13_0_set_single_dpm_table(smu, 355 SMU_UCLK, 356 dpm_table); 357 if (ret) 358 return ret; 359 } else { 360 dpm_table->count = 1; 361 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 362 dpm_table->dpm_levels[0].enabled = true; 363 dpm_table->min = dpm_table->dpm_levels[0].value; 364 dpm_table->max = dpm_table->dpm_levels[0].value; 365 } 366 367 /* fclk dpm table setup */ 368 dpm_table = &dpm_context->dpm_tables.fclk_table; 369 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 370 ret = smu_v13_0_set_single_dpm_table(smu, 371 SMU_FCLK, 372 dpm_table); 373 if (ret) 374 return ret; 375 } else { 376 dpm_table->count = 1; 377 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 378 dpm_table->dpm_levels[0].enabled = true; 379 dpm_table->min = dpm_table->dpm_levels[0].value; 380 dpm_table->max = dpm_table->dpm_levels[0].value; 381 } 382 383 return 0; 384 } 385 386 static int aldebaran_check_powerplay_table(struct smu_context *smu) 387 { 388 struct smu_table_context *table_context = &smu->smu_table; 389 struct smu_13_0_powerplay_table *powerplay_table = 390 table_context->power_play_table; 391 392 table_context->thermal_controller_type = 393 powerplay_table->thermal_controller_type; 394 395 return 0; 396 } 397 398 static int aldebaran_store_powerplay_table(struct smu_context *smu) 399 { 400 struct smu_table_context *table_context = &smu->smu_table; 401 struct smu_13_0_powerplay_table *powerplay_table = 402 table_context->power_play_table; 403 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 404 sizeof(PPTable_t)); 405 406 return 0; 407 } 408 409 static int aldebaran_append_powerplay_table(struct smu_context *smu) 410 { 411 struct smu_table_context *table_context = &smu->smu_table; 412 PPTable_t *smc_pptable = table_context->driver_pptable; 413 struct atom_smc_dpm_info_v4_10 *smc_dpm_table; 414 int index, ret; 415 416 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 417 smc_dpm_info); 418 419 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 420 (uint8_t **)&smc_dpm_table); 421 if (ret) 422 return ret; 423 424 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 425 smc_dpm_table->table_header.format_revision, 426 smc_dpm_table->table_header.content_revision); 427 428 if ((smc_dpm_table->table_header.format_revision == 4) && 429 (smc_dpm_table->table_header.content_revision == 10)) 430 smu_memcpy_trailing(smc_pptable, GfxMaxCurrent, reserved, 431 smc_dpm_table, GfxMaxCurrent); 432 return 0; 433 } 434 435 static int aldebaran_setup_pptable(struct smu_context *smu) 436 { 437 int ret = 0; 438 439 /* VBIOS pptable is the first choice */ 440 smu->smu_table.boot_values.pp_table_id = 0; 441 442 ret = smu_v13_0_setup_pptable(smu); 443 if (ret) 444 return ret; 445 446 ret = aldebaran_store_powerplay_table(smu); 447 if (ret) 448 return ret; 449 450 ret = aldebaran_append_powerplay_table(smu); 451 if (ret) 452 return ret; 453 454 ret = aldebaran_check_powerplay_table(smu); 455 if (ret) 456 return ret; 457 458 return ret; 459 } 460 461 static bool aldebaran_is_primary(struct smu_context *smu) 462 { 463 struct amdgpu_device *adev = smu->adev; 464 465 if (adev->smuio.funcs && adev->smuio.funcs->get_die_id) 466 return adev->smuio.funcs->get_die_id(adev) == 0; 467 468 return true; 469 } 470 471 static int aldebaran_run_board_btc(struct smu_context *smu) 472 { 473 int ret; 474 475 if (!aldebaran_is_primary(smu)) 476 return 0; 477 478 if (smu->smc_fw_version <= 0x00441d00) 479 return 0; 480 481 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL); 482 if (ret) 483 dev_err(smu->adev->dev, "Board power calibration failed!\n"); 484 485 return ret; 486 } 487 488 static int aldebaran_run_btc(struct smu_context *smu) 489 { 490 int ret; 491 492 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 493 if (ret) 494 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 495 else 496 ret = aldebaran_run_board_btc(smu); 497 498 return ret; 499 } 500 501 static int aldebaran_populate_umd_state_clk(struct smu_context *smu) 502 { 503 struct smu_13_0_dpm_context *dpm_context = 504 smu->smu_dpm.dpm_context; 505 struct smu_13_0_dpm_table *gfx_table = 506 &dpm_context->dpm_tables.gfx_table; 507 struct smu_13_0_dpm_table *mem_table = 508 &dpm_context->dpm_tables.uclk_table; 509 struct smu_13_0_dpm_table *soc_table = 510 &dpm_context->dpm_tables.soc_table; 511 struct smu_umd_pstate_table *pstate_table = 512 &smu->pstate_table; 513 514 pstate_table->gfxclk_pstate.min = gfx_table->min; 515 pstate_table->gfxclk_pstate.peak = gfx_table->max; 516 pstate_table->gfxclk_pstate.curr.min = gfx_table->min; 517 pstate_table->gfxclk_pstate.curr.max = gfx_table->max; 518 519 pstate_table->uclk_pstate.min = mem_table->min; 520 pstate_table->uclk_pstate.peak = mem_table->max; 521 pstate_table->uclk_pstate.curr.min = mem_table->min; 522 pstate_table->uclk_pstate.curr.max = mem_table->max; 523 524 pstate_table->socclk_pstate.min = soc_table->min; 525 pstate_table->socclk_pstate.peak = soc_table->max; 526 pstate_table->socclk_pstate.curr.min = soc_table->min; 527 pstate_table->socclk_pstate.curr.max = soc_table->max; 528 529 if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL && 530 mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL && 531 soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) { 532 pstate_table->gfxclk_pstate.standard = 533 gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value; 534 pstate_table->uclk_pstate.standard = 535 mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value; 536 pstate_table->socclk_pstate.standard = 537 soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value; 538 } else { 539 pstate_table->gfxclk_pstate.standard = 540 pstate_table->gfxclk_pstate.min; 541 pstate_table->uclk_pstate.standard = 542 pstate_table->uclk_pstate.min; 543 pstate_table->socclk_pstate.standard = 544 pstate_table->socclk_pstate.min; 545 } 546 547 return 0; 548 } 549 550 static void aldebaran_get_clk_table(struct smu_context *smu, 551 struct pp_clock_levels_with_latency *clocks, 552 struct smu_13_0_dpm_table *dpm_table) 553 { 554 uint32_t i; 555 556 clocks->num_levels = min_t(uint32_t, 557 dpm_table->count, 558 (uint32_t)PP_MAX_CLOCK_LEVELS); 559 560 for (i = 0; i < clocks->num_levels; i++) { 561 clocks->data[i].clocks_in_khz = 562 dpm_table->dpm_levels[i].value * 1000; 563 clocks->data[i].latency_in_us = 0; 564 } 565 566 } 567 568 static int aldebaran_freqs_in_same_level(int32_t frequency1, 569 int32_t frequency2) 570 { 571 return (abs(frequency1 - frequency2) <= EPSILON); 572 } 573 574 static int aldebaran_get_smu_metrics_data(struct smu_context *smu, 575 MetricsMember_t member, 576 uint32_t *value) 577 { 578 struct smu_table_context *smu_table = &smu->smu_table; 579 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 580 int ret = 0; 581 582 ret = smu_cmn_get_metrics_table(smu, 583 NULL, 584 false); 585 if (ret) 586 return ret; 587 588 switch (member) { 589 case METRICS_CURR_GFXCLK: 590 *value = metrics->CurrClock[PPCLK_GFXCLK]; 591 break; 592 case METRICS_CURR_SOCCLK: 593 *value = metrics->CurrClock[PPCLK_SOCCLK]; 594 break; 595 case METRICS_CURR_UCLK: 596 *value = metrics->CurrClock[PPCLK_UCLK]; 597 break; 598 case METRICS_CURR_VCLK: 599 *value = metrics->CurrClock[PPCLK_VCLK]; 600 break; 601 case METRICS_CURR_DCLK: 602 *value = metrics->CurrClock[PPCLK_DCLK]; 603 break; 604 case METRICS_CURR_FCLK: 605 *value = metrics->CurrClock[PPCLK_FCLK]; 606 break; 607 case METRICS_AVERAGE_GFXCLK: 608 *value = metrics->AverageGfxclkFrequency; 609 break; 610 case METRICS_AVERAGE_SOCCLK: 611 *value = metrics->AverageSocclkFrequency; 612 break; 613 case METRICS_AVERAGE_UCLK: 614 *value = metrics->AverageUclkFrequency; 615 break; 616 case METRICS_AVERAGE_GFXACTIVITY: 617 *value = metrics->AverageGfxActivity; 618 break; 619 case METRICS_AVERAGE_MEMACTIVITY: 620 *value = metrics->AverageUclkActivity; 621 break; 622 case METRICS_AVERAGE_SOCKETPOWER: 623 /* Valid power data is available only from primary die */ 624 if (aldebaran_is_primary(smu)) 625 *value = metrics->AverageSocketPower << 8; 626 else 627 ret = -EOPNOTSUPP; 628 break; 629 case METRICS_TEMPERATURE_EDGE: 630 *value = metrics->TemperatureEdge * 631 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 632 break; 633 case METRICS_TEMPERATURE_HOTSPOT: 634 *value = metrics->TemperatureHotspot * 635 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 636 break; 637 case METRICS_TEMPERATURE_MEM: 638 *value = metrics->TemperatureHBM * 639 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 640 break; 641 case METRICS_TEMPERATURE_VRGFX: 642 *value = metrics->TemperatureVrGfx * 643 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 644 break; 645 case METRICS_TEMPERATURE_VRSOC: 646 *value = metrics->TemperatureVrSoc * 647 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 648 break; 649 case METRICS_TEMPERATURE_VRMEM: 650 *value = metrics->TemperatureVrMem * 651 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 652 break; 653 case METRICS_THROTTLER_STATUS: 654 *value = metrics->ThrottlerStatus; 655 break; 656 case METRICS_UNIQUE_ID_UPPER32: 657 *value = metrics->PublicSerialNumUpper32; 658 break; 659 case METRICS_UNIQUE_ID_LOWER32: 660 *value = metrics->PublicSerialNumLower32; 661 break; 662 default: 663 *value = UINT_MAX; 664 break; 665 } 666 667 return ret; 668 } 669 670 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu, 671 enum smu_clk_type clk_type, 672 uint32_t *value) 673 { 674 MetricsMember_t member_type; 675 int clk_id = 0; 676 677 if (!value) 678 return -EINVAL; 679 680 clk_id = smu_cmn_to_asic_specific_index(smu, 681 CMN2ASIC_MAPPING_CLK, 682 clk_type); 683 if (clk_id < 0) 684 return -EINVAL; 685 686 switch (clk_id) { 687 case PPCLK_GFXCLK: 688 /* 689 * CurrClock[clk_id] can provide accurate 690 * output only when the dpm feature is enabled. 691 * We can use Average_* for dpm disabled case. 692 * But this is available for gfxclk/uclk/socclk/vclk/dclk. 693 */ 694 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) 695 member_type = METRICS_CURR_GFXCLK; 696 else 697 member_type = METRICS_AVERAGE_GFXCLK; 698 break; 699 case PPCLK_UCLK: 700 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 701 member_type = METRICS_CURR_UCLK; 702 else 703 member_type = METRICS_AVERAGE_UCLK; 704 break; 705 case PPCLK_SOCCLK: 706 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) 707 member_type = METRICS_CURR_SOCCLK; 708 else 709 member_type = METRICS_AVERAGE_SOCCLK; 710 break; 711 case PPCLK_VCLK: 712 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 713 member_type = METRICS_CURR_VCLK; 714 else 715 member_type = METRICS_AVERAGE_VCLK; 716 break; 717 case PPCLK_DCLK: 718 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 719 member_type = METRICS_CURR_DCLK; 720 else 721 member_type = METRICS_AVERAGE_DCLK; 722 break; 723 case PPCLK_FCLK: 724 member_type = METRICS_CURR_FCLK; 725 break; 726 default: 727 return -EINVAL; 728 } 729 730 return aldebaran_get_smu_metrics_data(smu, 731 member_type, 732 value); 733 } 734 735 static int aldebaran_emit_clk_levels(struct smu_context *smu, 736 enum smu_clk_type type, char *buf, int *offset) 737 { 738 int ret = 0; 739 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 740 struct pp_clock_levels_with_latency clocks; 741 struct smu_13_0_dpm_table *single_dpm_table; 742 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 743 struct smu_13_0_dpm_context *dpm_context = NULL; 744 uint32_t i; 745 int display_levels; 746 uint32_t freq_values[3] = {0}; 747 uint32_t min_clk, max_clk, cur_value = 0; 748 bool freq_match; 749 unsigned int clock_mhz; 750 static const char attempt_string[] = "Attempt to get current"; 751 752 if (amdgpu_ras_intr_triggered()) { 753 *offset += sysfs_emit_at(buf, *offset, "unavailable\n"); 754 return -EBUSY; 755 } 756 757 dpm_context = smu_dpm->dpm_context; 758 759 switch (type) { 760 761 case SMU_OD_SCLK: 762 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_SCLK"); 763 *offset += sysfs_emit_at(buf, *offset, "0: %uMhz\n1: %uMhz\n", 764 pstate_table->gfxclk_pstate.curr.min, 765 pstate_table->gfxclk_pstate.curr.max); 766 return 0; 767 case SMU_SCLK: 768 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &cur_value); 769 if (ret) { 770 dev_err(smu->adev->dev, "%s gfx clk Failed!", attempt_string); 771 return ret; 772 } 773 774 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 775 aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 776 777 display_levels = (clocks.num_levels == 1) ? 1 : 2; 778 779 min_clk = pstate_table->gfxclk_pstate.curr.min; 780 max_clk = pstate_table->gfxclk_pstate.curr.max; 781 782 freq_values[0] = min_clk; 783 freq_values[1] = max_clk; 784 785 /* fine-grained dpm has only 2 levels */ 786 if (cur_value > min_clk && cur_value < max_clk) { 787 display_levels++; 788 freq_values[2] = max_clk; 789 freq_values[1] = cur_value; 790 } 791 break; 792 793 case SMU_OD_MCLK: 794 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_MCLK"); 795 *offset += sysfs_emit_at(buf, *offset, "0: %uMhz\n1: %uMhz\n", 796 pstate_table->uclk_pstate.curr.min, 797 pstate_table->uclk_pstate.curr.max); 798 return 0; 799 case SMU_MCLK: 800 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &cur_value); 801 if (ret) { 802 dev_err(smu->adev->dev, "%s mclk Failed!", attempt_string); 803 return ret; 804 } 805 806 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 807 aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 808 break; 809 810 case SMU_SOCCLK: 811 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &cur_value); 812 if (ret) { 813 dev_err(smu->adev->dev, "%s socclk Failed!", attempt_string); 814 return ret; 815 } 816 817 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 818 aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 819 break; 820 821 case SMU_FCLK: 822 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &cur_value); 823 if (ret) { 824 dev_err(smu->adev->dev, "%s fclk Failed!", attempt_string); 825 return ret; 826 } 827 828 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 829 aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 830 break; 831 832 case SMU_VCLK: 833 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &cur_value); 834 if (ret) { 835 dev_err(smu->adev->dev, "%s vclk Failed!", attempt_string); 836 return ret; 837 } 838 839 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 840 aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 841 break; 842 843 case SMU_DCLK: 844 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &cur_value); 845 if (ret) { 846 dev_err(smu->adev->dev, "%s dclk Failed!", attempt_string); 847 return ret; 848 } 849 850 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 851 aldebaran_get_clk_table(smu, &clocks, single_dpm_table); 852 break; 853 854 default: 855 return -EINVAL; 856 } 857 858 switch (type) { 859 case SMU_SCLK: 860 for (i = 0; i < display_levels; i++) { 861 clock_mhz = freq_values[i]; 862 freq_match = aldebaran_freqs_in_same_level(clock_mhz, cur_value); 863 freq_match |= (display_levels == 1); 864 865 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", i, 866 clock_mhz, 867 (freq_match) ? "*" : ""); 868 } 869 break; 870 871 case SMU_MCLK: 872 case SMU_SOCCLK: 873 case SMU_FCLK: 874 case SMU_VCLK: 875 case SMU_DCLK: 876 for (i = 0; i < clocks.num_levels; i++) { 877 clock_mhz = clocks.data[i].clocks_in_khz / 1000; 878 freq_match = aldebaran_freqs_in_same_level(clock_mhz, cur_value); 879 freq_match |= (clocks.num_levels == 1); 880 881 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 882 i, clock_mhz, 883 (freq_match) ? "*" : ""); 884 } 885 break; 886 default: 887 return -EINVAL; 888 } 889 890 return 0; 891 } 892 893 static int aldebaran_upload_dpm_level(struct smu_context *smu, 894 bool max, 895 uint32_t feature_mask, 896 uint32_t level) 897 { 898 struct smu_13_0_dpm_context *dpm_context = 899 smu->smu_dpm.dpm_context; 900 uint32_t freq; 901 int ret = 0; 902 903 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 904 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) { 905 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value; 906 ret = smu_cmn_send_smc_msg_with_param(smu, 907 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 908 (PPCLK_GFXCLK << 16) | (freq & 0xffff), 909 NULL); 910 if (ret) { 911 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n", 912 max ? "max" : "min"); 913 return ret; 914 } 915 } 916 917 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 918 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) { 919 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value; 920 ret = smu_cmn_send_smc_msg_with_param(smu, 921 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 922 (PPCLK_UCLK << 16) | (freq & 0xffff), 923 NULL); 924 if (ret) { 925 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n", 926 max ? "max" : "min"); 927 return ret; 928 } 929 } 930 931 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) && 932 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) { 933 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value; 934 ret = smu_cmn_send_smc_msg_with_param(smu, 935 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 936 (PPCLK_SOCCLK << 16) | (freq & 0xffff), 937 NULL); 938 if (ret) { 939 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n", 940 max ? "max" : "min"); 941 return ret; 942 } 943 } 944 945 return ret; 946 } 947 948 static int aldebaran_force_clk_levels(struct smu_context *smu, 949 enum smu_clk_type type, uint32_t mask) 950 { 951 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 952 struct smu_13_0_dpm_table *single_dpm_table = NULL; 953 uint32_t soft_min_level, soft_max_level; 954 int ret = 0; 955 956 soft_min_level = mask ? (ffs(mask) - 1) : 0; 957 soft_max_level = mask ? (fls(mask) - 1) : 0; 958 959 switch (type) { 960 case SMU_SCLK: 961 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 962 if (soft_max_level >= single_dpm_table->count) { 963 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n", 964 soft_max_level, single_dpm_table->count - 1); 965 ret = -EINVAL; 966 break; 967 } 968 969 ret = aldebaran_upload_dpm_level(smu, 970 false, 971 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 972 soft_min_level); 973 if (ret) { 974 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n"); 975 break; 976 } 977 978 ret = aldebaran_upload_dpm_level(smu, 979 true, 980 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT), 981 soft_max_level); 982 if (ret) 983 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n"); 984 985 break; 986 987 case SMU_MCLK: 988 case SMU_SOCCLK: 989 case SMU_FCLK: 990 /* 991 * Should not arrive here since aldebaran does not 992 * support mclk/socclk/fclk softmin/softmax settings 993 */ 994 ret = -EINVAL; 995 break; 996 997 default: 998 break; 999 } 1000 1001 return ret; 1002 } 1003 1004 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu, 1005 struct smu_temperature_range *range) 1006 { 1007 struct smu_table_context *table_context = &smu->smu_table; 1008 struct smu_13_0_powerplay_table *powerplay_table = 1009 table_context->power_play_table; 1010 PPTable_t *pptable = smu->smu_table.driver_pptable; 1011 1012 if (!range) 1013 return -EINVAL; 1014 1015 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 1016 1017 range->hotspot_crit_max = pptable->ThotspotLimit * 1018 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1019 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 1020 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1021 range->mem_crit_max = pptable->TmemLimit * 1022 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1023 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 1024 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1025 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1026 1027 return 0; 1028 } 1029 1030 static int aldebaran_get_current_activity_percent(struct smu_context *smu, 1031 enum amd_pp_sensors sensor, 1032 uint32_t *value) 1033 { 1034 int ret = 0; 1035 1036 if (!value) 1037 return -EINVAL; 1038 1039 switch (sensor) { 1040 case AMDGPU_PP_SENSOR_GPU_LOAD: 1041 ret = aldebaran_get_smu_metrics_data(smu, 1042 METRICS_AVERAGE_GFXACTIVITY, 1043 value); 1044 break; 1045 case AMDGPU_PP_SENSOR_MEM_LOAD: 1046 ret = aldebaran_get_smu_metrics_data(smu, 1047 METRICS_AVERAGE_MEMACTIVITY, 1048 value); 1049 break; 1050 default: 1051 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n"); 1052 return -EINVAL; 1053 } 1054 1055 return ret; 1056 } 1057 1058 static int aldebaran_thermal_get_temperature(struct smu_context *smu, 1059 enum amd_pp_sensors sensor, 1060 uint32_t *value) 1061 { 1062 int ret = 0; 1063 1064 if (!value) 1065 return -EINVAL; 1066 1067 switch (sensor) { 1068 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1069 ret = aldebaran_get_smu_metrics_data(smu, 1070 METRICS_TEMPERATURE_HOTSPOT, 1071 value); 1072 break; 1073 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1074 ret = aldebaran_get_smu_metrics_data(smu, 1075 METRICS_TEMPERATURE_EDGE, 1076 value); 1077 break; 1078 case AMDGPU_PP_SENSOR_MEM_TEMP: 1079 ret = aldebaran_get_smu_metrics_data(smu, 1080 METRICS_TEMPERATURE_MEM, 1081 value); 1082 break; 1083 default: 1084 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n"); 1085 return -EINVAL; 1086 } 1087 1088 return ret; 1089 } 1090 1091 static int aldebaran_read_sensor(struct smu_context *smu, 1092 enum amd_pp_sensors sensor, 1093 void *data, uint32_t *size) 1094 { 1095 int ret = 0; 1096 1097 if (amdgpu_ras_intr_triggered()) 1098 return 0; 1099 1100 if (!data || !size) 1101 return -EINVAL; 1102 1103 switch (sensor) { 1104 case AMDGPU_PP_SENSOR_MEM_LOAD: 1105 case AMDGPU_PP_SENSOR_GPU_LOAD: 1106 ret = aldebaran_get_current_activity_percent(smu, 1107 sensor, 1108 (uint32_t *)data); 1109 *size = 4; 1110 break; 1111 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 1112 ret = aldebaran_get_smu_metrics_data(smu, 1113 METRICS_AVERAGE_SOCKETPOWER, 1114 (uint32_t *)data); 1115 *size = 4; 1116 break; 1117 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1118 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1119 case AMDGPU_PP_SENSOR_MEM_TEMP: 1120 ret = aldebaran_thermal_get_temperature(smu, sensor, 1121 (uint32_t *)data); 1122 *size = 4; 1123 break; 1124 case AMDGPU_PP_SENSOR_GFX_MCLK: 1125 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1126 /* the output clock frequency in 10K unit */ 1127 *(uint32_t *)data *= 100; 1128 *size = 4; 1129 break; 1130 case AMDGPU_PP_SENSOR_GFX_SCLK: 1131 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1132 *(uint32_t *)data *= 100; 1133 *size = 4; 1134 break; 1135 case AMDGPU_PP_SENSOR_VDDGFX: 1136 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data); 1137 *size = 4; 1138 break; 1139 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 1140 default: 1141 ret = -EOPNOTSUPP; 1142 break; 1143 } 1144 1145 return ret; 1146 } 1147 1148 static int aldebaran_get_power_limit(struct smu_context *smu, 1149 uint32_t *current_power_limit, 1150 uint32_t *default_power_limit, 1151 uint32_t *max_power_limit, 1152 uint32_t *min_power_limit) 1153 { 1154 PPTable_t *pptable = smu->smu_table.driver_pptable; 1155 uint32_t power_limit = 0; 1156 int ret; 1157 1158 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 1159 if (current_power_limit) 1160 *current_power_limit = 0; 1161 if (default_power_limit) 1162 *default_power_limit = 0; 1163 if (max_power_limit) 1164 *max_power_limit = 0; 1165 if (min_power_limit) 1166 *min_power_limit = 0; 1167 dev_warn(smu->adev->dev, 1168 "PPT feature is not enabled, power values can't be fetched."); 1169 1170 return 0; 1171 } 1172 1173 /* Valid power data is available only from primary die. 1174 * For secondary die show the value as 0. 1175 */ 1176 if (aldebaran_is_primary(smu)) { 1177 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, 1178 &power_limit); 1179 1180 if (ret) { 1181 /* the last hope to figure out the ppt limit */ 1182 if (!pptable) { 1183 dev_err(smu->adev->dev, 1184 "Cannot get PPT limit due to pptable missing!"); 1185 return -EINVAL; 1186 } 1187 power_limit = pptable->PptLimit; 1188 } 1189 } 1190 1191 if (current_power_limit) 1192 *current_power_limit = power_limit; 1193 if (default_power_limit) 1194 *default_power_limit = power_limit; 1195 1196 if (max_power_limit) { 1197 if (pptable) 1198 *max_power_limit = pptable->PptLimit; 1199 } 1200 1201 if (min_power_limit) 1202 *min_power_limit = 0; 1203 1204 return 0; 1205 } 1206 1207 static int aldebaran_set_power_limit(struct smu_context *smu, 1208 enum smu_ppt_limit_type limit_type, 1209 uint32_t limit) 1210 { 1211 /* Power limit can be set only through primary die */ 1212 if (aldebaran_is_primary(smu)) 1213 return smu_v13_0_set_power_limit(smu, limit_type, limit); 1214 1215 return -EINVAL; 1216 } 1217 1218 static int aldebaran_system_features_control(struct smu_context *smu, bool enable) 1219 { 1220 int ret; 1221 1222 ret = smu_v13_0_system_features_control(smu, enable); 1223 if (!ret && enable) 1224 ret = aldebaran_run_btc(smu); 1225 1226 return ret; 1227 } 1228 1229 static int aldebaran_set_performance_level(struct smu_context *smu, 1230 enum amd_dpm_forced_level level) 1231 { 1232 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1233 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1234 struct smu_13_0_dpm_table *gfx_table = 1235 &dpm_context->dpm_tables.gfx_table; 1236 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1237 1238 /* Disable determinism if switching to another mode */ 1239 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) && 1240 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) { 1241 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL); 1242 pstate_table->gfxclk_pstate.curr.max = gfx_table->max; 1243 } 1244 1245 switch (level) { 1246 1247 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM: 1248 return 0; 1249 1250 case AMD_DPM_FORCED_LEVEL_HIGH: 1251 case AMD_DPM_FORCED_LEVEL_LOW: 1252 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1253 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1254 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1255 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1256 default: 1257 break; 1258 } 1259 1260 return smu_v13_0_set_performance_level(smu, level); 1261 } 1262 1263 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu, 1264 enum smu_clk_type clk_type, 1265 uint32_t min, 1266 uint32_t max) 1267 { 1268 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1269 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1270 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1271 struct amdgpu_device *adev = smu->adev; 1272 uint32_t min_clk; 1273 uint32_t max_clk; 1274 int ret = 0; 1275 1276 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) 1277 return -EINVAL; 1278 1279 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1280 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1281 return -EINVAL; 1282 1283 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 1284 if (min >= max) { 1285 dev_err(smu->adev->dev, 1286 "Minimum GFX clk should be less than the maximum allowed clock\n"); 1287 return -EINVAL; 1288 } 1289 1290 if ((min == pstate_table->gfxclk_pstate.curr.min) && 1291 (max == pstate_table->gfxclk_pstate.curr.max)) 1292 return 0; 1293 1294 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, 1295 min, max); 1296 if (!ret) { 1297 pstate_table->gfxclk_pstate.curr.min = min; 1298 pstate_table->gfxclk_pstate.curr.max = max; 1299 } 1300 1301 return ret; 1302 } 1303 1304 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1305 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) || 1306 (max > dpm_context->dpm_tables.gfx_table.max)) { 1307 dev_warn(adev->dev, 1308 "Invalid max frequency %d MHz specified for determinism\n", max); 1309 return -EINVAL; 1310 } 1311 1312 /* Restore default min/max clocks and enable determinism */ 1313 min_clk = dpm_context->dpm_tables.gfx_table.min; 1314 max_clk = dpm_context->dpm_tables.gfx_table.max; 1315 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1316 if (!ret) { 1317 usleep_range(500, 1000); 1318 ret = smu_cmn_send_smc_msg_with_param(smu, 1319 SMU_MSG_EnableDeterminism, 1320 max, NULL); 1321 if (ret) { 1322 dev_err(adev->dev, 1323 "Failed to enable determinism at GFX clock %d MHz\n", max); 1324 } else { 1325 pstate_table->gfxclk_pstate.curr.min = min_clk; 1326 pstate_table->gfxclk_pstate.curr.max = max; 1327 } 1328 } 1329 } 1330 1331 return ret; 1332 } 1333 1334 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 1335 long input[], uint32_t size) 1336 { 1337 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1338 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1339 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1340 uint32_t min_clk; 1341 uint32_t max_clk; 1342 int ret = 0; 1343 1344 /* Only allowed in manual or determinism mode */ 1345 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1346 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) 1347 return -EINVAL; 1348 1349 switch (type) { 1350 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1351 if (size != 2) { 1352 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1353 return -EINVAL; 1354 } 1355 1356 if (input[0] == 0) { 1357 if (input[1] < dpm_context->dpm_tables.gfx_table.min) { 1358 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", 1359 input[1], dpm_context->dpm_tables.gfx_table.min); 1360 pstate_table->gfxclk_pstate.custom.min = 1361 pstate_table->gfxclk_pstate.curr.min; 1362 return -EINVAL; 1363 } 1364 1365 pstate_table->gfxclk_pstate.custom.min = input[1]; 1366 } else if (input[0] == 1) { 1367 if (input[1] > dpm_context->dpm_tables.gfx_table.max) { 1368 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", 1369 input[1], dpm_context->dpm_tables.gfx_table.max); 1370 pstate_table->gfxclk_pstate.custom.max = 1371 pstate_table->gfxclk_pstate.curr.max; 1372 return -EINVAL; 1373 } 1374 1375 pstate_table->gfxclk_pstate.custom.max = input[1]; 1376 } else { 1377 return -EINVAL; 1378 } 1379 break; 1380 case PP_OD_RESTORE_DEFAULT_TABLE: 1381 if (size != 0) { 1382 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1383 return -EINVAL; 1384 } else { 1385 /* Use the default frequencies for manual and determinism mode */ 1386 min_clk = dpm_context->dpm_tables.gfx_table.min; 1387 max_clk = dpm_context->dpm_tables.gfx_table.max; 1388 1389 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1390 } 1391 break; 1392 case PP_OD_COMMIT_DPM_TABLE: 1393 if (size != 0) { 1394 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1395 return -EINVAL; 1396 } else { 1397 if (!pstate_table->gfxclk_pstate.custom.min) 1398 pstate_table->gfxclk_pstate.custom.min = 1399 pstate_table->gfxclk_pstate.curr.min; 1400 1401 if (!pstate_table->gfxclk_pstate.custom.max) 1402 pstate_table->gfxclk_pstate.custom.max = 1403 pstate_table->gfxclk_pstate.curr.max; 1404 1405 min_clk = pstate_table->gfxclk_pstate.custom.min; 1406 max_clk = pstate_table->gfxclk_pstate.custom.max; 1407 1408 return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); 1409 } 1410 break; 1411 default: 1412 return -ENOSYS; 1413 } 1414 1415 return ret; 1416 } 1417 1418 static bool aldebaran_is_dpm_running(struct smu_context *smu) 1419 { 1420 int ret; 1421 uint64_t feature_enabled; 1422 1423 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1424 if (ret) 1425 return false; 1426 return !!(feature_enabled & SMC_DPM_FEATURE); 1427 } 1428 1429 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap, 1430 struct i2c_msg *msg, int num_msgs) 1431 { 1432 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 1433 struct amdgpu_device *adev = smu_i2c->adev; 1434 struct smu_context *smu = adev->powerplay.pp_handle; 1435 struct smu_table_context *smu_table = &smu->smu_table; 1436 struct smu_table *table = &smu_table->driver_table; 1437 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 1438 int i, j, r, c; 1439 u16 dir; 1440 1441 if (!adev->pm.dpm_enabled) 1442 return -EBUSY; 1443 1444 req = kzalloc(sizeof(*req), GFP_KERNEL); 1445 if (!req) 1446 return -ENOMEM; 1447 1448 req->I2CcontrollerPort = smu_i2c->port; 1449 req->I2CSpeed = I2C_SPEED_FAST_400K; 1450 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 1451 dir = msg[0].flags & I2C_M_RD; 1452 1453 for (c = i = 0; i < num_msgs; i++) { 1454 for (j = 0; j < msg[i].len; j++, c++) { 1455 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 1456 1457 if (!(msg[i].flags & I2C_M_RD)) { 1458 /* write */ 1459 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 1460 cmd->ReadWriteData = msg[i].buf[j]; 1461 } 1462 1463 if ((dir ^ msg[i].flags) & I2C_M_RD) { 1464 /* The direction changes. 1465 */ 1466 dir = msg[i].flags & I2C_M_RD; 1467 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 1468 } 1469 1470 req->NumCmds++; 1471 1472 /* 1473 * Insert STOP if we are at the last byte of either last 1474 * message for the transaction or the client explicitly 1475 * requires a STOP at this particular message. 1476 */ 1477 if ((j == msg[i].len - 1) && 1478 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 1479 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 1480 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 1481 } 1482 } 1483 } 1484 mutex_lock(&adev->pm.mutex); 1485 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 1486 if (r) 1487 goto fail; 1488 1489 for (c = i = 0; i < num_msgs; i++) { 1490 if (!(msg[i].flags & I2C_M_RD)) { 1491 c += msg[i].len; 1492 continue; 1493 } 1494 for (j = 0; j < msg[i].len; j++, c++) { 1495 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 1496 1497 msg[i].buf[j] = cmd->ReadWriteData; 1498 } 1499 } 1500 r = num_msgs; 1501 fail: 1502 mutex_unlock(&adev->pm.mutex); 1503 kfree(req); 1504 return r; 1505 } 1506 1507 static u32 aldebaran_i2c_func(struct i2c_adapter *adap) 1508 { 1509 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1510 } 1511 1512 1513 static const struct i2c_algorithm aldebaran_i2c_algo = { 1514 .master_xfer = aldebaran_i2c_xfer, 1515 .functionality = aldebaran_i2c_func, 1516 }; 1517 1518 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = { 1519 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 1520 .max_read_len = MAX_SW_I2C_COMMANDS, 1521 .max_write_len = MAX_SW_I2C_COMMANDS, 1522 .max_comb_1st_msg_len = 2, 1523 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 1524 }; 1525 1526 static int aldebaran_i2c_control_init(struct smu_context *smu) 1527 { 1528 struct amdgpu_device *adev = smu->adev; 1529 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0]; 1530 struct i2c_adapter *control = &smu_i2c->adapter; 1531 int res; 1532 1533 smu_i2c->adev = adev; 1534 smu_i2c->port = 0; 1535 mutex_init(&smu_i2c->mutex); 1536 control->owner = THIS_MODULE; 1537 control->dev.parent = &adev->pdev->dev; 1538 control->algo = &aldebaran_i2c_algo; 1539 snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0"); 1540 control->quirks = &aldebaran_i2c_control_quirks; 1541 i2c_set_adapdata(control, smu_i2c); 1542 1543 res = i2c_add_adapter(control); 1544 if (res) { 1545 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 1546 goto Out_err; 1547 } 1548 1549 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 1550 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 1551 1552 return 0; 1553 Out_err: 1554 i2c_del_adapter(control); 1555 1556 return res; 1557 } 1558 1559 static void aldebaran_i2c_control_fini(struct smu_context *smu) 1560 { 1561 struct amdgpu_device *adev = smu->adev; 1562 int i; 1563 1564 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 1565 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 1566 struct i2c_adapter *control = &smu_i2c->adapter; 1567 1568 i2c_del_adapter(control); 1569 } 1570 adev->pm.ras_eeprom_i2c_bus = NULL; 1571 adev->pm.fru_eeprom_i2c_bus = NULL; 1572 } 1573 1574 static void aldebaran_get_unique_id(struct smu_context *smu) 1575 { 1576 struct amdgpu_device *adev = smu->adev; 1577 uint32_t upper32 = 0, lower32 = 0; 1578 1579 if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32)) 1580 goto out; 1581 if (aldebaran_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32)) 1582 goto out; 1583 1584 out: 1585 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1586 } 1587 1588 static int aldebaran_get_bamaco_support(struct smu_context *smu) 1589 { 1590 /* aldebaran is not support baco */ 1591 1592 return 0; 1593 } 1594 1595 static int aldebaran_set_df_cstate(struct smu_context *smu, 1596 enum pp_df_cstate state) 1597 { 1598 struct amdgpu_device *adev = smu->adev; 1599 1600 /* 1601 * Aldebaran does not need the cstate disablement 1602 * prerequisite for gpu reset. 1603 */ 1604 if (amdgpu_in_reset(adev) || adev->in_suspend) 1605 return 0; 1606 1607 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL); 1608 } 1609 1610 static int aldebaran_select_xgmi_plpd_policy(struct smu_context *smu, 1611 enum pp_xgmi_plpd_mode mode) 1612 { 1613 struct amdgpu_device *adev = smu->adev; 1614 1615 /* The message only works on master die and NACK will be sent 1616 back for other dies, only send it on master die */ 1617 if (adev->smuio.funcs->get_socket_id(adev) || 1618 adev->smuio.funcs->get_die_id(adev)) 1619 return 0; 1620 1621 if (mode == XGMI_PLPD_DEFAULT) 1622 return smu_cmn_send_smc_msg_with_param(smu, 1623 SMU_MSG_GmiPwrDnControl, 1624 0, NULL); 1625 else if (mode == XGMI_PLPD_DISALLOW) 1626 return smu_cmn_send_smc_msg_with_param(smu, 1627 SMU_MSG_GmiPwrDnControl, 1628 1, NULL); 1629 else 1630 return -EINVAL; 1631 } 1632 1633 static const struct throttling_logging_label { 1634 uint32_t feature_mask; 1635 const char *label; 1636 } logging_label[] = { 1637 {(1U << THROTTLER_TEMP_GPU_BIT), "GPU"}, 1638 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"}, 1639 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"}, 1640 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"}, 1641 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"}, 1642 }; 1643 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu) 1644 { 1645 int ret; 1646 int throttler_idx, throttling_events = 0, buf_idx = 0; 1647 struct amdgpu_device *adev = smu->adev; 1648 uint32_t throttler_status; 1649 char log_buf[256]; 1650 1651 ret = aldebaran_get_smu_metrics_data(smu, 1652 METRICS_THROTTLER_STATUS, 1653 &throttler_status); 1654 if (ret) 1655 return; 1656 1657 memset(log_buf, 0, sizeof(log_buf)); 1658 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label); 1659 throttler_idx++) { 1660 if (throttler_status & logging_label[throttler_idx].feature_mask) { 1661 throttling_events++; 1662 buf_idx += snprintf(log_buf + buf_idx, 1663 sizeof(log_buf) - buf_idx, 1664 "%s%s", 1665 throttling_events > 1 ? " and " : "", 1666 logging_label[throttler_idx].label); 1667 if (buf_idx >= sizeof(log_buf)) { 1668 dev_err(adev->dev, "buffer overflow!\n"); 1669 log_buf[sizeof(log_buf) - 1] = '\0'; 1670 break; 1671 } 1672 } 1673 } 1674 1675 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n", 1676 log_buf); 1677 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, 1678 smu_cmn_get_indep_throttler_status(throttler_status, 1679 aldebaran_throttler_map)); 1680 } 1681 1682 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu) 1683 { 1684 struct amdgpu_device *adev = smu->adev; 1685 uint32_t esm_ctrl; 1686 1687 /* TODO: confirm this on real target */ 1688 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); 1689 if ((esm_ctrl >> 15) & 0x1) 1690 return (((esm_ctrl >> 8) & 0x7F) + 128); 1691 1692 return smu_v13_0_get_current_pcie_link_speed(smu); 1693 } 1694 1695 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, 1696 void **table) 1697 { 1698 struct smu_table_context *smu_table = &smu->smu_table; 1699 struct gpu_metrics_v1_3 *gpu_metrics = 1700 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 1701 SmuMetrics_t metrics; 1702 int i, ret = 0; 1703 1704 ret = smu_cmn_get_metrics_table(smu, 1705 &metrics, 1706 true); 1707 if (ret) 1708 return ret; 1709 1710 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 1711 1712 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 1713 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 1714 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 1715 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 1716 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 1717 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 1718 1719 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 1720 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 1721 gpu_metrics->average_mm_activity = 0; 1722 1723 /* Valid power data is available only from primary die */ 1724 if (aldebaran_is_primary(smu)) { 1725 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 1726 gpu_metrics->energy_accumulator = 1727 (uint64_t)metrics.EnergyAcc64bitHigh << 32 | 1728 metrics.EnergyAcc64bitLow; 1729 } else { 1730 gpu_metrics->average_socket_power = 0; 1731 gpu_metrics->energy_accumulator = 0; 1732 } 1733 1734 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 1735 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 1736 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 1737 gpu_metrics->average_vclk0_frequency = 0; 1738 gpu_metrics->average_dclk0_frequency = 0; 1739 1740 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 1741 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 1742 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 1743 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 1744 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 1745 1746 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1747 gpu_metrics->indep_throttle_status = 1748 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1749 aldebaran_throttler_map); 1750 1751 gpu_metrics->current_fan_speed = 0; 1752 1753 if (!amdgpu_sriov_vf(smu->adev)) { 1754 gpu_metrics->pcie_link_width = 1755 smu_v13_0_get_current_pcie_link_width(smu); 1756 gpu_metrics->pcie_link_speed = 1757 aldebaran_get_current_pcie_link_speed(smu); 1758 } 1759 1760 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1761 1762 gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc; 1763 gpu_metrics->mem_activity_acc = metrics.DramBusyAcc; 1764 1765 for (i = 0; i < NUM_HBM_INSTANCES; i++) 1766 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i]; 1767 1768 gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) | 1769 metrics.TimeStampLow; 1770 1771 *table = (void *)gpu_metrics; 1772 1773 return sizeof(struct gpu_metrics_v1_3); 1774 } 1775 1776 static int aldebaran_check_ecc_table_support(struct smu_context *smu, 1777 int *ecctable_version) 1778 { 1779 if (smu->smc_fw_version < SUPPORT_ECCTABLE_SMU_VERSION) 1780 return -EOPNOTSUPP; 1781 else if (smu->smc_fw_version >= SUPPORT_ECCTABLE_SMU_VERSION && 1782 smu->smc_fw_version < SUPPORT_ECCTABLE_V2_SMU_VERSION) 1783 *ecctable_version = 1; 1784 else 1785 *ecctable_version = 2; 1786 1787 return 0; 1788 } 1789 1790 static ssize_t aldebaran_get_ecc_info(struct smu_context *smu, 1791 void *table) 1792 { 1793 struct smu_table_context *smu_table = &smu->smu_table; 1794 EccInfoTable_t *ecc_table = NULL; 1795 struct ecc_info_per_ch *ecc_info_per_channel = NULL; 1796 int i, ret = 0; 1797 int table_version = 0; 1798 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; 1799 1800 ret = aldebaran_check_ecc_table_support(smu, &table_version); 1801 if (ret) 1802 return ret; 1803 1804 ret = smu_cmn_update_table(smu, 1805 SMU_TABLE_ECCINFO, 1806 0, 1807 smu_table->ecc_table, 1808 false); 1809 if (ret) { 1810 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n"); 1811 return ret; 1812 } 1813 1814 ecc_table = (EccInfoTable_t *)smu_table->ecc_table; 1815 1816 if (table_version == 1) { 1817 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) { 1818 ecc_info_per_channel = &(eccinfo->ecc[i]); 1819 ecc_info_per_channel->ce_count_lo_chip = 1820 ecc_table->EccInfo[i].ce_count_lo_chip; 1821 ecc_info_per_channel->ce_count_hi_chip = 1822 ecc_table->EccInfo[i].ce_count_hi_chip; 1823 ecc_info_per_channel->mca_umc_status = 1824 ecc_table->EccInfo[i].mca_umc_status; 1825 ecc_info_per_channel->mca_umc_addr = 1826 ecc_table->EccInfo[i].mca_umc_addr; 1827 } 1828 } else if (table_version == 2) { 1829 for (i = 0; i < ALDEBARAN_UMC_CHANNEL_NUM; i++) { 1830 ecc_info_per_channel = &(eccinfo->ecc[i]); 1831 ecc_info_per_channel->ce_count_lo_chip = 1832 ecc_table->EccInfo_V2[i].ce_count_lo_chip; 1833 ecc_info_per_channel->ce_count_hi_chip = 1834 ecc_table->EccInfo_V2[i].ce_count_hi_chip; 1835 ecc_info_per_channel->mca_umc_status = 1836 ecc_table->EccInfo_V2[i].mca_umc_status; 1837 ecc_info_per_channel->mca_umc_addr = 1838 ecc_table->EccInfo_V2[i].mca_umc_addr; 1839 ecc_info_per_channel->mca_ceumc_addr = 1840 ecc_table->EccInfo_V2[i].mca_ceumc_addr; 1841 } 1842 eccinfo->record_ce_addr_supported = 1; 1843 } 1844 1845 return ret; 1846 } 1847 1848 static int aldebaran_mode1_reset(struct smu_context *smu) 1849 { 1850 u32 fatal_err, param; 1851 int ret = 0; 1852 struct amdgpu_device *adev = smu->adev; 1853 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1854 1855 fatal_err = 0; 1856 param = SMU_RESET_MODE_1; 1857 1858 /* 1859 * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07 1860 */ 1861 if (smu->smc_fw_version < 0x00440700) { 1862 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 1863 } else { 1864 /* fatal error triggered by ras, PMFW supports the flag 1865 from 68.44.0 */ 1866 if ((smu->smc_fw_version >= 0x00442c00) && ras && 1867 atomic_read(&ras->in_recovery)) 1868 fatal_err = 1; 1869 1870 param |= (fatal_err << 16); 1871 ret = smu_cmn_send_smc_msg_with_param(smu, 1872 SMU_MSG_GfxDeviceDriverReset, param, NULL); 1873 } 1874 1875 if (!ret) 1876 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); 1877 1878 return ret; 1879 } 1880 1881 static int aldebaran_mode2_reset(struct smu_context *smu) 1882 { 1883 int ret = 0, index; 1884 struct amdgpu_device *adev = smu->adev; 1885 int timeout = 10; 1886 1887 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 1888 SMU_MSG_GfxDeviceDriverReset); 1889 1890 mutex_lock(&smu->message_lock); 1891 if (smu->smc_fw_version >= 0x00441400) { 1892 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2); 1893 /* This is similar to FLR, wait till max FLR timeout */ 1894 msleep(100); 1895 dev_dbg(smu->adev->dev, "restore config space...\n"); 1896 /* Restore the config space saved during init */ 1897 amdgpu_device_load_pci_state(adev->pdev); 1898 1899 dev_dbg(smu->adev->dev, "wait for reset ack\n"); 1900 while (ret == -ETIME && timeout) { 1901 ret = smu_cmn_wait_for_response(smu); 1902 /* Wait a bit more time for getting ACK */ 1903 if (ret == -ETIME) { 1904 --timeout; 1905 usleep_range(500, 1000); 1906 continue; 1907 } 1908 1909 if (ret != 1) { 1910 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n", 1911 SMU_RESET_MODE_2, ret); 1912 goto out; 1913 } 1914 } 1915 1916 } else { 1917 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n", 1918 smu->smc_fw_version); 1919 } 1920 1921 if (ret == 1) 1922 ret = 0; 1923 out: 1924 mutex_unlock(&smu->message_lock); 1925 1926 return ret; 1927 } 1928 1929 static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 1930 { 1931 int ret = 0; 1932 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL); 1933 1934 return ret; 1935 } 1936 1937 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu) 1938 { 1939 #if 0 1940 struct amdgpu_device *adev = smu->adev; 1941 uint32_t val; 1942 uint32_t smu_version; 1943 int ret; 1944 1945 /** 1946 * PM FW version support mode1 reset from 68.07 1947 */ 1948 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 1949 if (ret) 1950 return false; 1951 1952 if ((smu_version < 0x00440700)) 1953 return false; 1954 1955 /** 1956 * mode1 reset relies on PSP, so we should check if 1957 * PSP is alive. 1958 */ 1959 val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 1960 1961 return val != 0x0; 1962 #endif 1963 return true; 1964 } 1965 1966 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu) 1967 { 1968 return true; 1969 } 1970 1971 static int aldebaran_set_mp1_state(struct smu_context *smu, 1972 enum pp_mp1_state mp1_state) 1973 { 1974 switch (mp1_state) { 1975 case PP_MP1_STATE_UNLOAD: 1976 return smu_cmn_set_mp1_state(smu, mp1_state); 1977 default: 1978 return 0; 1979 } 1980 } 1981 1982 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu, 1983 uint32_t size) 1984 { 1985 int ret = 0; 1986 1987 /* message SMU to update the bad page number on SMUBUS */ 1988 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL); 1989 if (ret) 1990 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n", 1991 __func__); 1992 1993 return ret; 1994 } 1995 1996 static int aldebaran_check_bad_channel_info_support(struct smu_context *smu) 1997 { 1998 if (smu->smc_fw_version < SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION) 1999 return -EOPNOTSUPP; 2000 2001 return 0; 2002 } 2003 2004 static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu, 2005 uint32_t size) 2006 { 2007 int ret = 0; 2008 2009 ret = aldebaran_check_bad_channel_info_support(smu); 2010 if (ret) 2011 return ret; 2012 2013 /* message SMU to update the bad channel info on SMUBUS */ 2014 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetBadHBMPagesRetiredFlagsPerChannel, size, NULL); 2015 if (ret) 2016 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad channel info\n", 2017 __func__); 2018 2019 return ret; 2020 } 2021 2022 static const struct pptable_funcs aldebaran_ppt_funcs = { 2023 /* init dpm */ 2024 .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask, 2025 /* dpm/clk tables */ 2026 .set_default_dpm_table = aldebaran_set_default_dpm_table, 2027 .populate_umd_state_clk = aldebaran_populate_umd_state_clk, 2028 .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range, 2029 .emit_clk_levels = aldebaran_emit_clk_levels, 2030 .force_clk_levels = aldebaran_force_clk_levels, 2031 .read_sensor = aldebaran_read_sensor, 2032 .set_performance_level = aldebaran_set_performance_level, 2033 .get_power_limit = aldebaran_get_power_limit, 2034 .is_dpm_running = aldebaran_is_dpm_running, 2035 .get_unique_id = aldebaran_get_unique_id, 2036 .init_microcode = smu_v13_0_init_microcode, 2037 .load_microcode = smu_v13_0_load_microcode, 2038 .fini_microcode = smu_v13_0_fini_microcode, 2039 .init_smc_tables = aldebaran_init_smc_tables, 2040 .fini_smc_tables = smu_v13_0_fini_smc_tables, 2041 .init_power = smu_v13_0_init_power, 2042 .fini_power = smu_v13_0_fini_power, 2043 .check_fw_status = smu_v13_0_check_fw_status, 2044 /* pptable related */ 2045 .setup_pptable = aldebaran_setup_pptable, 2046 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 2047 .check_fw_version = smu_v13_0_check_fw_version, 2048 .write_pptable = smu_cmn_write_pptable, 2049 .set_driver_table_location = smu_v13_0_set_driver_table_location, 2050 .set_tool_table_location = smu_v13_0_set_tool_table_location, 2051 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 2052 .system_features_control = aldebaran_system_features_control, 2053 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2054 .send_smc_msg = smu_cmn_send_smc_msg, 2055 .get_enabled_mask = smu_cmn_get_enabled_mask, 2056 .feature_is_enabled = smu_cmn_feature_is_enabled, 2057 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 2058 .set_power_limit = aldebaran_set_power_limit, 2059 .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks, 2060 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 2061 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 2062 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate, 2063 .register_irq_handler = smu_v13_0_register_irq_handler, 2064 .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme, 2065 .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc, 2066 .get_bamaco_support = aldebaran_get_bamaco_support, 2067 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, 2068 .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range, 2069 .od_edit_dpm_table = aldebaran_usr_edit_dpm_table, 2070 .set_df_cstate = aldebaran_set_df_cstate, 2071 .select_xgmi_plpd_policy = aldebaran_select_xgmi_plpd_policy, 2072 .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event, 2073 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2074 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 2075 .get_gpu_metrics = aldebaran_get_gpu_metrics, 2076 .mode1_reset_is_support = aldebaran_is_mode1_reset_supported, 2077 .mode2_reset_is_support = aldebaran_is_mode2_reset_supported, 2078 .smu_handle_passthrough_sbr = aldebaran_smu_handle_passthrough_sbr, 2079 .mode1_reset = aldebaran_mode1_reset, 2080 .set_mp1_state = aldebaran_set_mp1_state, 2081 .mode2_reset = aldebaran_mode2_reset, 2082 .wait_for_event = smu_v13_0_wait_for_event, 2083 .i2c_init = aldebaran_i2c_control_init, 2084 .i2c_fini = aldebaran_i2c_control_fini, 2085 .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num, 2086 .get_ecc_info = aldebaran_get_ecc_info, 2087 .send_hbm_bad_channel_flag = aldebaran_send_hbm_bad_channel_flag, 2088 }; 2089 2090 void aldebaran_set_ppt_funcs(struct smu_context *smu) 2091 { 2092 smu->ppt_funcs = &aldebaran_ppt_funcs; 2093 smu->message_map = aldebaran_message_map; 2094 smu->clock_map = aldebaran_clk_map; 2095 smu->feature_map = aldebaran_feature_mask_map; 2096 smu->table_map = aldebaran_table_map; 2097 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE; 2098 smu_v13_0_set_smu_mailbox_registers(smu); 2099 } 2100