xref: /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c (revision fd7d598270724cc787982ea48bbe17ad383a8b7f)
1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #define SWSMU_CODE_LAYER_L2
25 
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "smu_v11_0.h"
29 #include "smu11_driver_if_vangogh.h"
30 #include "vangogh_ppt.h"
31 #include "smu_v11_5_ppsmc.h"
32 #include "smu_v11_5_pmfw.h"
33 #include "smu_cmn.h"
34 #include "soc15_common.h"
35 #include "asic_reg/gc/gc_10_3_0_offset.h"
36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h"
37 #include <asm/processor.h>
38 
39 /*
40  * DO NOT use these for err/warn/info/debug messages.
41  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
42  * They are more MGPU friendly.
43  */
44 #undef pr_err
45 #undef pr_warn
46 #undef pr_info
47 #undef pr_debug
48 
49 // Registers related to GFXOFF
50 // addressBlock: smuio_smuio_SmuSmuioDec
51 // base address: 0x5a000
52 #define mmSMUIO_GFX_MISC_CNTL			0x00c5
53 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX		0
54 
55 //SMUIO_GFX_MISC_CNTL
56 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT	0x0
57 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT		0x1
58 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK	0x00000001L
59 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK		0x00000006L
60 
61 #define FEATURE_MASK(feature) (1ULL << feature)
62 #define SMC_DPM_FEATURE ( \
63 	FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
64 	FEATURE_MASK(FEATURE_VCN_DPM_BIT)	 | \
65 	FEATURE_MASK(FEATURE_FCLK_DPM_BIT)	 | \
66 	FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)	 | \
67 	FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)	 | \
68 	FEATURE_MASK(FEATURE_LCLK_DPM_BIT)	 | \
69 	FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)	 | \
70 	FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
71 	FEATURE_MASK(FEATURE_GFX_DPM_BIT))
72 
73 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
74 	MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,			0),
75 	MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,		0),
76 	MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,	0),
77 	MSG_MAP(EnableGfxOff,                   PPSMC_MSG_EnableGfxOff,			0),
78 	MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,          0),
79 	MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,		0),
80 	MSG_MAP(PowerDownIspByTile,             PPSMC_MSG_PowerDownIspByTile,	0),
81 	MSG_MAP(PowerUpIspByTile,               PPSMC_MSG_PowerUpIspByTile,		0),
82 	MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,			0),
83 	MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,			0),
84 	MSG_MAP(RlcPowerNotify,                 PPSMC_MSG_RlcPowerNotify,		0),
85 	MSG_MAP(SetHardMinVcn,                  PPSMC_MSG_SetHardMinVcn,		0),
86 	MSG_MAP(SetSoftMinGfxclk,               PPSMC_MSG_SetSoftMinGfxclk,		0),
87 	MSG_MAP(ActiveProcessNotify,            PPSMC_MSG_ActiveProcessNotify,		0),
88 	MSG_MAP(SetHardMinIspiclkByFreq,        PPSMC_MSG_SetHardMinIspiclkByFreq,	0),
89 	MSG_MAP(SetHardMinIspxclkByFreq,        PPSMC_MSG_SetHardMinIspxclkByFreq,	0),
90 	MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,	0),
91 	MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,		0),
92 	MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,	0),
93 	MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,	0),
94 	MSG_MAP(GfxDeviceDriverReset,           PPSMC_MSG_GfxDeviceDriverReset,		0),
95 	MSG_MAP(GetEnabledSmuFeatures,          PPSMC_MSG_GetEnabledSmuFeatures,	0),
96 	MSG_MAP(SetHardMinSocclkByFreq,         PPSMC_MSG_SetHardMinSocclkByFreq,	0),
97 	MSG_MAP(SetSoftMinFclk,                 PPSMC_MSG_SetSoftMinFclk,		0),
98 	MSG_MAP(SetSoftMinVcn,                  PPSMC_MSG_SetSoftMinVcn,		0),
99 	MSG_MAP(EnablePostCode,                 PPSMC_MSG_EnablePostCode,		0),
100 	MSG_MAP(GetGfxclkFrequency,             PPSMC_MSG_GetGfxclkFrequency,	0),
101 	MSG_MAP(GetFclkFrequency,               PPSMC_MSG_GetFclkFrequency,		0),
102 	MSG_MAP(SetSoftMaxGfxClk,               PPSMC_MSG_SetSoftMaxGfxClk,		0),
103 	MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk,		0),
104 	MSG_MAP(SetSoftMaxSocclkByFreq,         PPSMC_MSG_SetSoftMaxSocclkByFreq,	0),
105 	MSG_MAP(SetSoftMaxFclkByFreq,           PPSMC_MSG_SetSoftMaxFclkByFreq,		0),
106 	MSG_MAP(SetSoftMaxVcn,                  PPSMC_MSG_SetSoftMaxVcn,			0),
107 	MSG_MAP(SetPowerLimitPercentage,        PPSMC_MSG_SetPowerLimitPercentage,	0),
108 	MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,			0),
109 	MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,				0),
110 	MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq,		0),
111 	MSG_MAP(SetSoftMinSocclkByFreq,         PPSMC_MSG_SetSoftMinSocclkByFreq,	0),
112 	MSG_MAP(PowerUpCvip,                    PPSMC_MSG_PowerUpCvip,				0),
113 	MSG_MAP(PowerDownCvip,                  PPSMC_MSG_PowerDownCvip,			0),
114 	MSG_MAP(GetPptLimit,                        PPSMC_MSG_GetPptLimit,			0),
115 	MSG_MAP(GetThermalLimit,                    PPSMC_MSG_GetThermalLimit,		0),
116 	MSG_MAP(GetCurrentTemperature,              PPSMC_MSG_GetCurrentTemperature, 0),
117 	MSG_MAP(GetCurrentPower,                    PPSMC_MSG_GetCurrentPower,		 0),
118 	MSG_MAP(GetCurrentVoltage,                  PPSMC_MSG_GetCurrentVoltage,	 0),
119 	MSG_MAP(GetCurrentCurrent,                  PPSMC_MSG_GetCurrentCurrent,	 0),
120 	MSG_MAP(GetAverageCpuActivity,              PPSMC_MSG_GetAverageCpuActivity, 0),
121 	MSG_MAP(GetAverageGfxActivity,              PPSMC_MSG_GetAverageGfxActivity, 0),
122 	MSG_MAP(GetAveragePower,                    PPSMC_MSG_GetAveragePower,		 0),
123 	MSG_MAP(GetAverageTemperature,              PPSMC_MSG_GetAverageTemperature, 0),
124 	MSG_MAP(SetAveragePowerTimeConstant,        PPSMC_MSG_SetAveragePowerTimeConstant,			0),
125 	MSG_MAP(SetAverageActivityTimeConstant,     PPSMC_MSG_SetAverageActivityTimeConstant,		0),
126 	MSG_MAP(SetAverageTemperatureTimeConstant,  PPSMC_MSG_SetAverageTemperatureTimeConstant,	0),
127 	MSG_MAP(SetMitigationEndHysteresis,         PPSMC_MSG_SetMitigationEndHysteresis,			0),
128 	MSG_MAP(GetCurrentFreq,                     PPSMC_MSG_GetCurrentFreq,						0),
129 	MSG_MAP(SetReducedPptLimit,                 PPSMC_MSG_SetReducedPptLimit,					0),
130 	MSG_MAP(SetReducedThermalLimit,             PPSMC_MSG_SetReducedThermalLimit,				0),
131 	MSG_MAP(DramLogSetDramAddr,                 PPSMC_MSG_DramLogSetDramAddr,					0),
132 	MSG_MAP(StartDramLogging,                   PPSMC_MSG_StartDramLogging,						0),
133 	MSG_MAP(StopDramLogging,                    PPSMC_MSG_StopDramLogging,						0),
134 	MSG_MAP(SetSoftMinCclk,                     PPSMC_MSG_SetSoftMinCclk,						0),
135 	MSG_MAP(SetSoftMaxCclk,                     PPSMC_MSG_SetSoftMaxCclk,						0),
136 	MSG_MAP(RequestActiveWgp,                   PPSMC_MSG_RequestActiveWgp,                     0),
137 	MSG_MAP(SetFastPPTLimit,                    PPSMC_MSG_SetFastPPTLimit,						0),
138 	MSG_MAP(SetSlowPPTLimit,                    PPSMC_MSG_SetSlowPPTLimit,						0),
139 	MSG_MAP(GetFastPPTLimit,                    PPSMC_MSG_GetFastPPTLimit,						0),
140 	MSG_MAP(GetSlowPPTLimit,                    PPSMC_MSG_GetSlowPPTLimit,						0),
141 	MSG_MAP(GetGfxOffStatus,		    PPSMC_MSG_GetGfxOffStatus,						0),
142 	MSG_MAP(GetGfxOffEntryCount,		    PPSMC_MSG_GetGfxOffEntryCount,					0),
143 	MSG_MAP(LogGfxOffResidency,		    PPSMC_MSG_LogGfxOffResidency,					0),
144 };
145 
146 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
147 	FEA_MAP(PPT),
148 	FEA_MAP(TDC),
149 	FEA_MAP(THERMAL),
150 	FEA_MAP(DS_GFXCLK),
151 	FEA_MAP(DS_SOCCLK),
152 	FEA_MAP(DS_LCLK),
153 	FEA_MAP(DS_FCLK),
154 	FEA_MAP(DS_MP1CLK),
155 	FEA_MAP(DS_MP0CLK),
156 	FEA_MAP(ATHUB_PG),
157 	FEA_MAP(CCLK_DPM),
158 	FEA_MAP(FAN_CONTROLLER),
159 	FEA_MAP(ULV),
160 	FEA_MAP(VCN_DPM),
161 	FEA_MAP(LCLK_DPM),
162 	FEA_MAP(SHUBCLK_DPM),
163 	FEA_MAP(DCFCLK_DPM),
164 	FEA_MAP(DS_DCFCLK),
165 	FEA_MAP(S0I2),
166 	FEA_MAP(SMU_LOW_POWER),
167 	FEA_MAP(GFX_DEM),
168 	FEA_MAP(PSI),
169 	FEA_MAP(PROCHOT),
170 	FEA_MAP(CPUOFF),
171 	FEA_MAP(STAPM),
172 	FEA_MAP(S0I3),
173 	FEA_MAP(DF_CSTATES),
174 	FEA_MAP(PERF_LIMIT),
175 	FEA_MAP(CORE_DLDO),
176 	FEA_MAP(RSMU_LOW_POWER),
177 	FEA_MAP(SMN_LOW_POWER),
178 	FEA_MAP(THM_LOW_POWER),
179 	FEA_MAP(SMUIO_LOW_POWER),
180 	FEA_MAP(MP1_LOW_POWER),
181 	FEA_MAP(DS_VCN),
182 	FEA_MAP(CPPC),
183 	FEA_MAP(OS_CSTATES),
184 	FEA_MAP(ISP_DPM),
185 	FEA_MAP(A55_DPM),
186 	FEA_MAP(CVIP_DSP_DPM),
187 	FEA_MAP(MSMU_LOW_POWER),
188 	FEA_MAP_REVERSE(SOCCLK),
189 	FEA_MAP_REVERSE(FCLK),
190 	FEA_MAP_HALF_REVERSE(GFX),
191 };
192 
193 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = {
194 	TAB_MAP_VALID(WATERMARKS),
195 	TAB_MAP_VALID(SMU_METRICS),
196 	TAB_MAP_VALID(CUSTOM_DPM),
197 	TAB_MAP_VALID(DPMCLOCKS),
198 };
199 
200 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
201 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,		WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
202 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,		WORKLOAD_PPLIB_VIDEO_BIT),
203 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,			WORKLOAD_PPLIB_VR_BIT),
204 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_COMPUTE_BIT),
205 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
206 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CAPPED,		WORKLOAD_PPLIB_CAPPED_BIT),
207 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_UNCAPPED,		WORKLOAD_PPLIB_UNCAPPED_BIT),
208 };
209 
210 static const uint8_t vangogh_throttler_map[] = {
211 	[THROTTLER_STATUS_BIT_SPL]	= (SMU_THROTTLER_SPL_BIT),
212 	[THROTTLER_STATUS_BIT_FPPT]	= (SMU_THROTTLER_FPPT_BIT),
213 	[THROTTLER_STATUS_BIT_SPPT]	= (SMU_THROTTLER_SPPT_BIT),
214 	[THROTTLER_STATUS_BIT_SPPT_APU]	= (SMU_THROTTLER_SPPT_APU_BIT),
215 	[THROTTLER_STATUS_BIT_THM_CORE]	= (SMU_THROTTLER_TEMP_CORE_BIT),
216 	[THROTTLER_STATUS_BIT_THM_GFX]	= (SMU_THROTTLER_TEMP_GPU_BIT),
217 	[THROTTLER_STATUS_BIT_THM_SOC]	= (SMU_THROTTLER_TEMP_SOC_BIT),
218 	[THROTTLER_STATUS_BIT_TDC_VDD]	= (SMU_THROTTLER_TDC_VDD_BIT),
219 	[THROTTLER_STATUS_BIT_TDC_SOC]	= (SMU_THROTTLER_TDC_SOC_BIT),
220 	[THROTTLER_STATUS_BIT_TDC_GFX]	= (SMU_THROTTLER_TDC_GFX_BIT),
221 	[THROTTLER_STATUS_BIT_TDC_CVIP]	= (SMU_THROTTLER_TDC_CVIP_BIT),
222 };
223 
224 static int vangogh_tables_init(struct smu_context *smu)
225 {
226 	struct smu_table_context *smu_table = &smu->smu_table;
227 	struct smu_table *tables = smu_table->tables;
228 
229 	SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
230 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
231 	SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
232 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
233 	SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
234 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
235 	SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t),
236 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
237 
238 	if (smu->smc_fw_if_version < 0x3) {
239 		SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_legacy_t),
240 				PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
241 		smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_legacy_t), GFP_KERNEL);
242 	} else {
243 		SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
244 				PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
245 		smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
246 	}
247 	if (!smu_table->metrics_table)
248 		goto err0_out;
249 	smu_table->metrics_time = 0;
250 
251 	if (smu->smc_fw_version >= 0x043F3E00)
252 		smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_3);
253 	else
254 		smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
255 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
256 	if (!smu_table->gpu_metrics_table)
257 		goto err1_out;
258 
259 	smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
260 	if (!smu_table->watermarks_table)
261 		goto err2_out;
262 
263 	smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
264 	if (!smu_table->clocks_table)
265 		goto err3_out;
266 
267 	return 0;
268 
269 err3_out:
270 	kfree(smu_table->watermarks_table);
271 err2_out:
272 	kfree(smu_table->gpu_metrics_table);
273 err1_out:
274 	kfree(smu_table->metrics_table);
275 err0_out:
276 	return -ENOMEM;
277 }
278 
279 static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu,
280 				       MetricsMember_t member,
281 				       uint32_t *value)
282 {
283 	struct smu_table_context *smu_table = &smu->smu_table;
284 	SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table;
285 	int ret = 0;
286 
287 	ret = smu_cmn_get_metrics_table(smu,
288 					NULL,
289 					false);
290 	if (ret)
291 		return ret;
292 
293 	switch (member) {
294 	case METRICS_CURR_GFXCLK:
295 		*value = metrics->GfxclkFrequency;
296 		break;
297 	case METRICS_AVERAGE_SOCCLK:
298 		*value = metrics->SocclkFrequency;
299 		break;
300 	case METRICS_AVERAGE_VCLK:
301 		*value = metrics->VclkFrequency;
302 		break;
303 	case METRICS_AVERAGE_DCLK:
304 		*value = metrics->DclkFrequency;
305 		break;
306 	case METRICS_CURR_UCLK:
307 		*value = metrics->MemclkFrequency;
308 		break;
309 	case METRICS_AVERAGE_GFXACTIVITY:
310 		*value = metrics->GfxActivity / 100;
311 		break;
312 	case METRICS_AVERAGE_VCNACTIVITY:
313 		*value = metrics->UvdActivity;
314 		break;
315 	case METRICS_AVERAGE_SOCKETPOWER:
316 		*value = (metrics->CurrentSocketPower << 8) /
317 		1000 ;
318 		break;
319 	case METRICS_TEMPERATURE_EDGE:
320 		*value = metrics->GfxTemperature / 100 *
321 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
322 		break;
323 	case METRICS_TEMPERATURE_HOTSPOT:
324 		*value = metrics->SocTemperature / 100 *
325 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
326 		break;
327 	case METRICS_THROTTLER_STATUS:
328 		*value = metrics->ThrottlerStatus;
329 		break;
330 	case METRICS_VOLTAGE_VDDGFX:
331 		*value = metrics->Voltage[2];
332 		break;
333 	case METRICS_VOLTAGE_VDDSOC:
334 		*value = metrics->Voltage[1];
335 		break;
336 	case METRICS_AVERAGE_CPUCLK:
337 		memcpy(value, &metrics->CoreFrequency[0],
338 		       smu->cpu_core_num * sizeof(uint16_t));
339 		break;
340 	default:
341 		*value = UINT_MAX;
342 		break;
343 	}
344 
345 	return ret;
346 }
347 
348 static int vangogh_get_smu_metrics_data(struct smu_context *smu,
349 				       MetricsMember_t member,
350 				       uint32_t *value)
351 {
352 	struct smu_table_context *smu_table = &smu->smu_table;
353 	SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
354 	int ret = 0;
355 
356 	ret = smu_cmn_get_metrics_table(smu,
357 					NULL,
358 					false);
359 	if (ret)
360 		return ret;
361 
362 	switch (member) {
363 	case METRICS_CURR_GFXCLK:
364 		*value = metrics->Current.GfxclkFrequency;
365 		break;
366 	case METRICS_AVERAGE_SOCCLK:
367 		*value = metrics->Current.SocclkFrequency;
368 		break;
369 	case METRICS_AVERAGE_VCLK:
370 		*value = metrics->Current.VclkFrequency;
371 		break;
372 	case METRICS_AVERAGE_DCLK:
373 		*value = metrics->Current.DclkFrequency;
374 		break;
375 	case METRICS_CURR_UCLK:
376 		*value = metrics->Current.MemclkFrequency;
377 		break;
378 	case METRICS_AVERAGE_GFXACTIVITY:
379 		*value = metrics->Current.GfxActivity;
380 		break;
381 	case METRICS_AVERAGE_VCNACTIVITY:
382 		*value = metrics->Current.UvdActivity;
383 		break;
384 	case METRICS_AVERAGE_SOCKETPOWER:
385 		*value = (metrics->Average.CurrentSocketPower << 8) /
386 		1000;
387 		break;
388 	case METRICS_CURR_SOCKETPOWER:
389 		*value = (metrics->Current.CurrentSocketPower << 8) /
390 		1000;
391 		break;
392 	case METRICS_TEMPERATURE_EDGE:
393 		*value = metrics->Current.GfxTemperature / 100 *
394 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
395 		break;
396 	case METRICS_TEMPERATURE_HOTSPOT:
397 		*value = metrics->Current.SocTemperature / 100 *
398 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
399 		break;
400 	case METRICS_THROTTLER_STATUS:
401 		*value = metrics->Current.ThrottlerStatus;
402 		break;
403 	case METRICS_VOLTAGE_VDDGFX:
404 		*value = metrics->Current.Voltage[2];
405 		break;
406 	case METRICS_VOLTAGE_VDDSOC:
407 		*value = metrics->Current.Voltage[1];
408 		break;
409 	case METRICS_AVERAGE_CPUCLK:
410 		memcpy(value, &metrics->Current.CoreFrequency[0],
411 		       smu->cpu_core_num * sizeof(uint16_t));
412 		break;
413 	default:
414 		*value = UINT_MAX;
415 		break;
416 	}
417 
418 	return ret;
419 }
420 
421 static int vangogh_common_get_smu_metrics_data(struct smu_context *smu,
422 				       MetricsMember_t member,
423 				       uint32_t *value)
424 {
425 	int ret = 0;
426 
427 	if (smu->smc_fw_if_version < 0x3)
428 		ret = vangogh_get_legacy_smu_metrics_data(smu, member, value);
429 	else
430 		ret = vangogh_get_smu_metrics_data(smu, member, value);
431 
432 	return ret;
433 }
434 
435 static int vangogh_allocate_dpm_context(struct smu_context *smu)
436 {
437 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
438 
439 	smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
440 				       GFP_KERNEL);
441 	if (!smu_dpm->dpm_context)
442 		return -ENOMEM;
443 
444 	smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
445 
446 	return 0;
447 }
448 
449 static int vangogh_init_smc_tables(struct smu_context *smu)
450 {
451 	int ret = 0;
452 
453 	ret = vangogh_tables_init(smu);
454 	if (ret)
455 		return ret;
456 
457 	ret = vangogh_allocate_dpm_context(smu);
458 	if (ret)
459 		return ret;
460 
461 #ifdef CONFIG_X86
462 	/* AMD x86 APU only */
463 	smu->cpu_core_num = boot_cpu_data.x86_max_cores;
464 #else
465 	smu->cpu_core_num = 4;
466 #endif
467 
468 	return smu_v11_0_init_smc_tables(smu);
469 }
470 
471 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
472 {
473 	int ret = 0;
474 
475 	if (enable) {
476 		/* vcn dpm on is a prerequisite for vcn power gate messages */
477 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
478 		if (ret)
479 			return ret;
480 	} else {
481 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
482 		if (ret)
483 			return ret;
484 	}
485 
486 	return ret;
487 }
488 
489 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
490 {
491 	int ret = 0;
492 
493 	if (enable) {
494 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
495 		if (ret)
496 			return ret;
497 	} else {
498 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
499 		if (ret)
500 			return ret;
501 	}
502 
503 	return ret;
504 }
505 
506 static bool vangogh_is_dpm_running(struct smu_context *smu)
507 {
508 	struct amdgpu_device *adev = smu->adev;
509 	int ret = 0;
510 	uint64_t feature_enabled;
511 
512 	/* we need to re-init after suspend so return false */
513 	if (adev->in_suspend)
514 		return false;
515 
516 	ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
517 
518 	if (ret)
519 		return false;
520 
521 	return !!(feature_enabled & SMC_DPM_FEATURE);
522 }
523 
524 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
525 						uint32_t dpm_level, uint32_t *freq)
526 {
527 	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
528 
529 	if (!clk_table || clk_type >= SMU_CLK_COUNT)
530 		return -EINVAL;
531 
532 	switch (clk_type) {
533 	case SMU_SOCCLK:
534 		if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
535 			return -EINVAL;
536 		*freq = clk_table->SocClocks[dpm_level];
537 		break;
538 	case SMU_VCLK:
539 		if (dpm_level >= clk_table->VcnClkLevelsEnabled)
540 			return -EINVAL;
541 		*freq = clk_table->VcnClocks[dpm_level].vclk;
542 		break;
543 	case SMU_DCLK:
544 		if (dpm_level >= clk_table->VcnClkLevelsEnabled)
545 			return -EINVAL;
546 		*freq = clk_table->VcnClocks[dpm_level].dclk;
547 		break;
548 	case SMU_UCLK:
549 	case SMU_MCLK:
550 		if (dpm_level >= clk_table->NumDfPstatesEnabled)
551 			return -EINVAL;
552 		*freq = clk_table->DfPstateTable[dpm_level].memclk;
553 
554 		break;
555 	case SMU_FCLK:
556 		if (dpm_level >= clk_table->NumDfPstatesEnabled)
557 			return -EINVAL;
558 		*freq = clk_table->DfPstateTable[dpm_level].fclk;
559 		break;
560 	default:
561 		return -EINVAL;
562 	}
563 
564 	return 0;
565 }
566 
567 static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
568 			enum smu_clk_type clk_type, char *buf)
569 {
570 	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
571 	SmuMetrics_legacy_t metrics;
572 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
573 	int i, idx, size = 0, ret = 0;
574 	uint32_t cur_value = 0, value = 0, count = 0;
575 	bool cur_value_match_level = false;
576 
577 	memset(&metrics, 0, sizeof(metrics));
578 
579 	ret = smu_cmn_get_metrics_table(smu, &metrics, false);
580 	if (ret)
581 		return ret;
582 
583 	smu_cmn_get_sysfs_buf(&buf, &size);
584 
585 	switch (clk_type) {
586 	case SMU_OD_SCLK:
587 		if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
588 			size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
589 			size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
590 			(smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
591 			size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
592 			(smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
593 		}
594 		break;
595 	case SMU_OD_CCLK:
596 		if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
597 			size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);
598 			size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
599 			(smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
600 			size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
601 			(smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
602 		}
603 		break;
604 	case SMU_OD_RANGE:
605 		if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
606 			size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
607 			size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
608 				smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
609 			size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
610 				smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
611 		}
612 		break;
613 	case SMU_SOCCLK:
614 		/* the level 3 ~ 6 of socclk use the same frequency for vangogh */
615 		count = clk_table->NumSocClkLevelsEnabled;
616 		cur_value = metrics.SocclkFrequency;
617 		break;
618 	case SMU_VCLK:
619 		count = clk_table->VcnClkLevelsEnabled;
620 		cur_value = metrics.VclkFrequency;
621 		break;
622 	case SMU_DCLK:
623 		count = clk_table->VcnClkLevelsEnabled;
624 		cur_value = metrics.DclkFrequency;
625 		break;
626 	case SMU_MCLK:
627 		count = clk_table->NumDfPstatesEnabled;
628 		cur_value = metrics.MemclkFrequency;
629 		break;
630 	case SMU_FCLK:
631 		count = clk_table->NumDfPstatesEnabled;
632 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
633 		if (ret)
634 			return ret;
635 		break;
636 	default:
637 		break;
638 	}
639 
640 	switch (clk_type) {
641 	case SMU_SOCCLK:
642 	case SMU_VCLK:
643 	case SMU_DCLK:
644 	case SMU_MCLK:
645 	case SMU_FCLK:
646 		for (i = 0; i < count; i++) {
647 			idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
648 			ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
649 			if (ret)
650 				return ret;
651 			if (!value)
652 				continue;
653 			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
654 					cur_value == value ? "*" : "");
655 			if (cur_value == value)
656 				cur_value_match_level = true;
657 		}
658 
659 		if (!cur_value_match_level)
660 			size += sysfs_emit_at(buf, size, "   %uMhz *\n", cur_value);
661 		break;
662 	default:
663 		break;
664 	}
665 
666 	return size;
667 }
668 
669 static int vangogh_print_clk_levels(struct smu_context *smu,
670 			enum smu_clk_type clk_type, char *buf)
671 {
672 	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
673 	SmuMetrics_t metrics;
674 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
675 	int i, idx, size = 0, ret = 0;
676 	uint32_t cur_value = 0, value = 0, count = 0;
677 	bool cur_value_match_level = false;
678 	uint32_t min, max;
679 
680 	memset(&metrics, 0, sizeof(metrics));
681 
682 	ret = smu_cmn_get_metrics_table(smu, &metrics, false);
683 	if (ret)
684 		return ret;
685 
686 	smu_cmn_get_sysfs_buf(&buf, &size);
687 
688 	switch (clk_type) {
689 	case SMU_OD_SCLK:
690 		if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
691 			size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
692 			size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
693 			(smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
694 			size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
695 			(smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
696 		}
697 		break;
698 	case SMU_OD_CCLK:
699 		if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
700 			size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);
701 			size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
702 			(smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
703 			size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
704 			(smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
705 		}
706 		break;
707 	case SMU_OD_RANGE:
708 		if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
709 			size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
710 			size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
711 				smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
712 			size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
713 				smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
714 		}
715 		break;
716 	case SMU_SOCCLK:
717 		/* the level 3 ~ 6 of socclk use the same frequency for vangogh */
718 		count = clk_table->NumSocClkLevelsEnabled;
719 		cur_value = metrics.Current.SocclkFrequency;
720 		break;
721 	case SMU_VCLK:
722 		count = clk_table->VcnClkLevelsEnabled;
723 		cur_value = metrics.Current.VclkFrequency;
724 		break;
725 	case SMU_DCLK:
726 		count = clk_table->VcnClkLevelsEnabled;
727 		cur_value = metrics.Current.DclkFrequency;
728 		break;
729 	case SMU_MCLK:
730 		count = clk_table->NumDfPstatesEnabled;
731 		cur_value = metrics.Current.MemclkFrequency;
732 		break;
733 	case SMU_FCLK:
734 		count = clk_table->NumDfPstatesEnabled;
735 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
736 		if (ret)
737 			return ret;
738 		break;
739 	case SMU_GFXCLK:
740 	case SMU_SCLK:
741 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value);
742 		if (ret) {
743 			return ret;
744 		}
745 		break;
746 	default:
747 		break;
748 	}
749 
750 	switch (clk_type) {
751 	case SMU_SOCCLK:
752 	case SMU_VCLK:
753 	case SMU_DCLK:
754 	case SMU_MCLK:
755 	case SMU_FCLK:
756 		for (i = 0; i < count; i++) {
757 			idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
758 			ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
759 			if (ret)
760 				return ret;
761 			if (!value)
762 				continue;
763 			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
764 					cur_value == value ? "*" : "");
765 			if (cur_value == value)
766 				cur_value_match_level = true;
767 		}
768 
769 		if (!cur_value_match_level)
770 			size += sysfs_emit_at(buf, size, "   %uMhz *\n", cur_value);
771 		break;
772 	case SMU_GFXCLK:
773 	case SMU_SCLK:
774 		min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
775 		max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
776 		if (cur_value  == max)
777 			i = 2;
778 		else if (cur_value == min)
779 			i = 0;
780 		else
781 			i = 1;
782 		size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
783 				i == 0 ? "*" : "");
784 		size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
785 				i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK,
786 				i == 1 ? "*" : "");
787 		size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
788 				i == 2 ? "*" : "");
789 		break;
790 	default:
791 		break;
792 	}
793 
794 	return size;
795 }
796 
797 static int vangogh_common_print_clk_levels(struct smu_context *smu,
798 			enum smu_clk_type clk_type, char *buf)
799 {
800 	int ret = 0;
801 
802 	if (smu->smc_fw_if_version < 0x3)
803 		ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf);
804 	else
805 		ret = vangogh_print_clk_levels(smu, clk_type, buf);
806 
807 	return ret;
808 }
809 
810 static int vangogh_get_profiling_clk_mask(struct smu_context *smu,
811 					 enum amd_dpm_forced_level level,
812 					 uint32_t *vclk_mask,
813 					 uint32_t *dclk_mask,
814 					 uint32_t *mclk_mask,
815 					 uint32_t *fclk_mask,
816 					 uint32_t *soc_mask)
817 {
818 	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
819 
820 	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
821 		if (mclk_mask)
822 			*mclk_mask = clk_table->NumDfPstatesEnabled - 1;
823 
824 		if (fclk_mask)
825 			*fclk_mask = clk_table->NumDfPstatesEnabled - 1;
826 
827 		if (soc_mask)
828 			*soc_mask = 0;
829 	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
830 		if (mclk_mask)
831 			*mclk_mask = 0;
832 
833 		if (fclk_mask)
834 			*fclk_mask = 0;
835 
836 		if (soc_mask)
837 			*soc_mask = 1;
838 
839 		if (vclk_mask)
840 			*vclk_mask = 1;
841 
842 		if (dclk_mask)
843 			*dclk_mask = 1;
844 	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) {
845 		if (mclk_mask)
846 			*mclk_mask = 0;
847 
848 		if (fclk_mask)
849 			*fclk_mask = 0;
850 
851 		if (soc_mask)
852 			*soc_mask = 1;
853 
854 		if (vclk_mask)
855 			*vclk_mask = 1;
856 
857 		if (dclk_mask)
858 			*dclk_mask = 1;
859 	}
860 
861 	return 0;
862 }
863 
864 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu,
865 				enum smu_clk_type clk_type)
866 {
867 	enum smu_feature_mask feature_id = 0;
868 
869 	switch (clk_type) {
870 	case SMU_MCLK:
871 	case SMU_UCLK:
872 	case SMU_FCLK:
873 		feature_id = SMU_FEATURE_DPM_FCLK_BIT;
874 		break;
875 	case SMU_GFXCLK:
876 	case SMU_SCLK:
877 		feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
878 		break;
879 	case SMU_SOCCLK:
880 		feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
881 		break;
882 	case SMU_VCLK:
883 	case SMU_DCLK:
884 		feature_id = SMU_FEATURE_VCN_DPM_BIT;
885 		break;
886 	default:
887 		return true;
888 	}
889 
890 	if (!smu_cmn_feature_is_enabled(smu, feature_id))
891 		return false;
892 
893 	return true;
894 }
895 
896 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu,
897 					enum smu_clk_type clk_type,
898 					uint32_t *min,
899 					uint32_t *max)
900 {
901 	int ret = 0;
902 	uint32_t soc_mask;
903 	uint32_t vclk_mask;
904 	uint32_t dclk_mask;
905 	uint32_t mclk_mask;
906 	uint32_t fclk_mask;
907 	uint32_t clock_limit;
908 
909 	if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) {
910 		switch (clk_type) {
911 		case SMU_MCLK:
912 		case SMU_UCLK:
913 			clock_limit = smu->smu_table.boot_values.uclk;
914 			break;
915 		case SMU_FCLK:
916 			clock_limit = smu->smu_table.boot_values.fclk;
917 			break;
918 		case SMU_GFXCLK:
919 		case SMU_SCLK:
920 			clock_limit = smu->smu_table.boot_values.gfxclk;
921 			break;
922 		case SMU_SOCCLK:
923 			clock_limit = smu->smu_table.boot_values.socclk;
924 			break;
925 		case SMU_VCLK:
926 			clock_limit = smu->smu_table.boot_values.vclk;
927 			break;
928 		case SMU_DCLK:
929 			clock_limit = smu->smu_table.boot_values.dclk;
930 			break;
931 		default:
932 			clock_limit = 0;
933 			break;
934 		}
935 
936 		/* clock in Mhz unit */
937 		if (min)
938 			*min = clock_limit / 100;
939 		if (max)
940 			*max = clock_limit / 100;
941 
942 		return 0;
943 	}
944 	if (max) {
945 		ret = vangogh_get_profiling_clk_mask(smu,
946 							AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
947 							&vclk_mask,
948 							&dclk_mask,
949 							&mclk_mask,
950 							&fclk_mask,
951 							&soc_mask);
952 		if (ret)
953 			goto failed;
954 
955 		switch (clk_type) {
956 		case SMU_UCLK:
957 		case SMU_MCLK:
958 			ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
959 			if (ret)
960 				goto failed;
961 			break;
962 		case SMU_SOCCLK:
963 			ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
964 			if (ret)
965 				goto failed;
966 			break;
967 		case SMU_FCLK:
968 			ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max);
969 			if (ret)
970 				goto failed;
971 			break;
972 		case SMU_VCLK:
973 			ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max);
974 			if (ret)
975 				goto failed;
976 			break;
977 		case SMU_DCLK:
978 			ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max);
979 			if (ret)
980 				goto failed;
981 			break;
982 		default:
983 			ret = -EINVAL;
984 			goto failed;
985 		}
986 	}
987 	if (min) {
988 		switch (clk_type) {
989 		case SMU_UCLK:
990 		case SMU_MCLK:
991 			ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min);
992 			if (ret)
993 				goto failed;
994 			break;
995 		case SMU_SOCCLK:
996 			ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min);
997 			if (ret)
998 				goto failed;
999 			break;
1000 		case SMU_FCLK:
1001 			ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min);
1002 			if (ret)
1003 				goto failed;
1004 			break;
1005 		case SMU_VCLK:
1006 			ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min);
1007 			if (ret)
1008 				goto failed;
1009 			break;
1010 		case SMU_DCLK:
1011 			ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min);
1012 			if (ret)
1013 				goto failed;
1014 			break;
1015 		default:
1016 			ret = -EINVAL;
1017 			goto failed;
1018 		}
1019 	}
1020 failed:
1021 	return ret;
1022 }
1023 
1024 static int vangogh_get_power_profile_mode(struct smu_context *smu,
1025 					   char *buf)
1026 {
1027 	uint32_t i, size = 0;
1028 	int16_t workload_type = 0;
1029 
1030 	if (!buf)
1031 		return -EINVAL;
1032 
1033 	for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
1034 		/*
1035 		 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1036 		 * Not all profile modes are supported on vangogh.
1037 		 */
1038 		workload_type = smu_cmn_to_asic_specific_index(smu,
1039 							       CMN2ASIC_MAPPING_WORKLOAD,
1040 							       i);
1041 
1042 		if (workload_type < 0)
1043 			continue;
1044 
1045 		size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1046 			i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1047 	}
1048 
1049 	return size;
1050 }
1051 
1052 static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1053 {
1054 	int workload_type, ret;
1055 	uint32_t profile_mode = input[size];
1056 
1057 	if (profile_mode >= PP_SMC_POWER_PROFILE_COUNT) {
1058 		dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1059 		return -EINVAL;
1060 	}
1061 
1062 	if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
1063 			profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
1064 		return 0;
1065 
1066 	/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1067 	workload_type = smu_cmn_to_asic_specific_index(smu,
1068 						       CMN2ASIC_MAPPING_WORKLOAD,
1069 						       profile_mode);
1070 	if (workload_type < 0) {
1071 		dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n",
1072 					profile_mode);
1073 		return -EINVAL;
1074 	}
1075 
1076 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
1077 				    1 << workload_type,
1078 				    NULL);
1079 	if (ret) {
1080 		dev_err_once(smu->adev->dev, "Fail to set workload type %d\n",
1081 					workload_type);
1082 		return ret;
1083 	}
1084 
1085 	smu->power_profile_mode = profile_mode;
1086 
1087 	return 0;
1088 }
1089 
1090 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu,
1091 					  enum smu_clk_type clk_type,
1092 					  uint32_t min,
1093 					  uint32_t max)
1094 {
1095 	int ret = 0;
1096 
1097 	if (!vangogh_clk_dpm_is_enabled(smu, clk_type))
1098 		return 0;
1099 
1100 	switch (clk_type) {
1101 	case SMU_GFXCLK:
1102 	case SMU_SCLK:
1103 		ret = smu_cmn_send_smc_msg_with_param(smu,
1104 							SMU_MSG_SetHardMinGfxClk,
1105 							min, NULL);
1106 		if (ret)
1107 			return ret;
1108 
1109 		ret = smu_cmn_send_smc_msg_with_param(smu,
1110 							SMU_MSG_SetSoftMaxGfxClk,
1111 							max, NULL);
1112 		if (ret)
1113 			return ret;
1114 		break;
1115 	case SMU_FCLK:
1116 		ret = smu_cmn_send_smc_msg_with_param(smu,
1117 							SMU_MSG_SetHardMinFclkByFreq,
1118 							min, NULL);
1119 		if (ret)
1120 			return ret;
1121 
1122 		ret = smu_cmn_send_smc_msg_with_param(smu,
1123 							SMU_MSG_SetSoftMaxFclkByFreq,
1124 							max, NULL);
1125 		if (ret)
1126 			return ret;
1127 		break;
1128 	case SMU_SOCCLK:
1129 		ret = smu_cmn_send_smc_msg_with_param(smu,
1130 							SMU_MSG_SetHardMinSocclkByFreq,
1131 							min, NULL);
1132 		if (ret)
1133 			return ret;
1134 
1135 		ret = smu_cmn_send_smc_msg_with_param(smu,
1136 							SMU_MSG_SetSoftMaxSocclkByFreq,
1137 							max, NULL);
1138 		if (ret)
1139 			return ret;
1140 		break;
1141 	case SMU_VCLK:
1142 		ret = smu_cmn_send_smc_msg_with_param(smu,
1143 							SMU_MSG_SetHardMinVcn,
1144 							min << 16, NULL);
1145 		if (ret)
1146 			return ret;
1147 		ret = smu_cmn_send_smc_msg_with_param(smu,
1148 							SMU_MSG_SetSoftMaxVcn,
1149 							max << 16, NULL);
1150 		if (ret)
1151 			return ret;
1152 		break;
1153 	case SMU_DCLK:
1154 		ret = smu_cmn_send_smc_msg_with_param(smu,
1155 							SMU_MSG_SetHardMinVcn,
1156 							min, NULL);
1157 		if (ret)
1158 			return ret;
1159 		ret = smu_cmn_send_smc_msg_with_param(smu,
1160 							SMU_MSG_SetSoftMaxVcn,
1161 							max, NULL);
1162 		if (ret)
1163 			return ret;
1164 		break;
1165 	default:
1166 		return -EINVAL;
1167 	}
1168 
1169 	return ret;
1170 }
1171 
1172 static int vangogh_force_clk_levels(struct smu_context *smu,
1173 				   enum smu_clk_type clk_type, uint32_t mask)
1174 {
1175 	uint32_t soft_min_level = 0, soft_max_level = 0;
1176 	uint32_t min_freq = 0, max_freq = 0;
1177 	int ret = 0 ;
1178 
1179 	soft_min_level = mask ? (ffs(mask) - 1) : 0;
1180 	soft_max_level = mask ? (fls(mask) - 1) : 0;
1181 
1182 	switch (clk_type) {
1183 	case SMU_SOCCLK:
1184 		ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1185 						soft_min_level, &min_freq);
1186 		if (ret)
1187 			return ret;
1188 		ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1189 						soft_max_level, &max_freq);
1190 		if (ret)
1191 			return ret;
1192 		ret = smu_cmn_send_smc_msg_with_param(smu,
1193 								SMU_MSG_SetSoftMaxSocclkByFreq,
1194 								max_freq, NULL);
1195 		if (ret)
1196 			return ret;
1197 		ret = smu_cmn_send_smc_msg_with_param(smu,
1198 								SMU_MSG_SetHardMinSocclkByFreq,
1199 								min_freq, NULL);
1200 		if (ret)
1201 			return ret;
1202 		break;
1203 	case SMU_FCLK:
1204 		ret = vangogh_get_dpm_clk_limited(smu,
1205 							clk_type, soft_min_level, &min_freq);
1206 		if (ret)
1207 			return ret;
1208 		ret = vangogh_get_dpm_clk_limited(smu,
1209 							clk_type, soft_max_level, &max_freq);
1210 		if (ret)
1211 			return ret;
1212 		ret = smu_cmn_send_smc_msg_with_param(smu,
1213 								SMU_MSG_SetSoftMaxFclkByFreq,
1214 								max_freq, NULL);
1215 		if (ret)
1216 			return ret;
1217 		ret = smu_cmn_send_smc_msg_with_param(smu,
1218 								SMU_MSG_SetHardMinFclkByFreq,
1219 								min_freq, NULL);
1220 		if (ret)
1221 			return ret;
1222 		break;
1223 	case SMU_VCLK:
1224 		ret = vangogh_get_dpm_clk_limited(smu,
1225 							clk_type, soft_min_level, &min_freq);
1226 		if (ret)
1227 			return ret;
1228 
1229 		ret = vangogh_get_dpm_clk_limited(smu,
1230 							clk_type, soft_max_level, &max_freq);
1231 		if (ret)
1232 			return ret;
1233 
1234 
1235 		ret = smu_cmn_send_smc_msg_with_param(smu,
1236 								SMU_MSG_SetHardMinVcn,
1237 								min_freq << 16, NULL);
1238 		if (ret)
1239 			return ret;
1240 
1241 		ret = smu_cmn_send_smc_msg_with_param(smu,
1242 								SMU_MSG_SetSoftMaxVcn,
1243 								max_freq << 16, NULL);
1244 		if (ret)
1245 			return ret;
1246 
1247 		break;
1248 	case SMU_DCLK:
1249 		ret = vangogh_get_dpm_clk_limited(smu,
1250 							clk_type, soft_min_level, &min_freq);
1251 		if (ret)
1252 			return ret;
1253 
1254 		ret = vangogh_get_dpm_clk_limited(smu,
1255 							clk_type, soft_max_level, &max_freq);
1256 		if (ret)
1257 			return ret;
1258 
1259 		ret = smu_cmn_send_smc_msg_with_param(smu,
1260 							SMU_MSG_SetHardMinVcn,
1261 							min_freq, NULL);
1262 		if (ret)
1263 			return ret;
1264 
1265 		ret = smu_cmn_send_smc_msg_with_param(smu,
1266 							SMU_MSG_SetSoftMaxVcn,
1267 							max_freq, NULL);
1268 		if (ret)
1269 			return ret;
1270 
1271 		break;
1272 	default:
1273 		break;
1274 	}
1275 
1276 	return ret;
1277 }
1278 
1279 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest)
1280 {
1281 	int ret = 0, i = 0;
1282 	uint32_t min_freq, max_freq, force_freq;
1283 	enum smu_clk_type clk_type;
1284 
1285 	enum smu_clk_type clks[] = {
1286 		SMU_SOCCLK,
1287 		SMU_VCLK,
1288 		SMU_DCLK,
1289 		SMU_FCLK,
1290 	};
1291 
1292 	for (i = 0; i < ARRAY_SIZE(clks); i++) {
1293 		clk_type = clks[i];
1294 		ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1295 		if (ret)
1296 			return ret;
1297 
1298 		force_freq = highest ? max_freq : min_freq;
1299 		ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
1300 		if (ret)
1301 			return ret;
1302 	}
1303 
1304 	return ret;
1305 }
1306 
1307 static int vangogh_unforce_dpm_levels(struct smu_context *smu)
1308 {
1309 	int ret = 0, i = 0;
1310 	uint32_t min_freq, max_freq;
1311 	enum smu_clk_type clk_type;
1312 
1313 	struct clk_feature_map {
1314 		enum smu_clk_type clk_type;
1315 		uint32_t	feature;
1316 	} clk_feature_map[] = {
1317 		{SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT},
1318 		{SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
1319 		{SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT},
1320 		{SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT},
1321 	};
1322 
1323 	for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
1324 
1325 		if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
1326 		    continue;
1327 
1328 		clk_type = clk_feature_map[i].clk_type;
1329 
1330 		ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1331 
1332 		if (ret)
1333 			return ret;
1334 
1335 		ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1336 
1337 		if (ret)
1338 			return ret;
1339 	}
1340 
1341 	return ret;
1342 }
1343 
1344 static int vangogh_set_peak_clock_by_device(struct smu_context *smu)
1345 {
1346 	int ret = 0;
1347 	uint32_t socclk_freq = 0, fclk_freq = 0;
1348 	uint32_t vclk_freq = 0, dclk_freq = 0;
1349 
1350 	ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq);
1351 	if (ret)
1352 		return ret;
1353 
1354 	ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq);
1355 	if (ret)
1356 		return ret;
1357 
1358 	ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq);
1359 	if (ret)
1360 		return ret;
1361 
1362 	ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq);
1363 	if (ret)
1364 		return ret;
1365 
1366 	ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq);
1367 	if (ret)
1368 		return ret;
1369 
1370 	ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq);
1371 	if (ret)
1372 		return ret;
1373 
1374 	ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq);
1375 	if (ret)
1376 		return ret;
1377 
1378 	ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq);
1379 	if (ret)
1380 		return ret;
1381 
1382 	return ret;
1383 }
1384 
1385 static int vangogh_set_performance_level(struct smu_context *smu,
1386 					enum amd_dpm_forced_level level)
1387 {
1388 	int ret = 0, i;
1389 	uint32_t soc_mask, mclk_mask, fclk_mask;
1390 	uint32_t vclk_mask = 0, dclk_mask = 0;
1391 
1392 	smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1393 	smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1394 
1395 	switch (level) {
1396 	case AMD_DPM_FORCED_LEVEL_HIGH:
1397 		smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq;
1398 		smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1399 
1400 
1401 		ret = vangogh_force_dpm_limit_value(smu, true);
1402 		if (ret)
1403 			return ret;
1404 		break;
1405 	case AMD_DPM_FORCED_LEVEL_LOW:
1406 		smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1407 		smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1408 
1409 		ret = vangogh_force_dpm_limit_value(smu, false);
1410 		if (ret)
1411 			return ret;
1412 		break;
1413 	case AMD_DPM_FORCED_LEVEL_AUTO:
1414 		smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1415 		smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1416 
1417 		ret = vangogh_unforce_dpm_levels(smu);
1418 		if (ret)
1419 			return ret;
1420 		break;
1421 	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1422 		smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1423 		smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1424 
1425 		ret = vangogh_get_profiling_clk_mask(smu, level,
1426 							&vclk_mask,
1427 							&dclk_mask,
1428 							&mclk_mask,
1429 							&fclk_mask,
1430 							&soc_mask);
1431 		if (ret)
1432 			return ret;
1433 
1434 		vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1435 		vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1436 		vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask);
1437 		vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask);
1438 		break;
1439 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1440 		smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1441 		smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1442 		break;
1443 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1444 		smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1445 		smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1446 
1447 		ret = vangogh_get_profiling_clk_mask(smu, level,
1448 							NULL,
1449 							NULL,
1450 							&mclk_mask,
1451 							&fclk_mask,
1452 							NULL);
1453 		if (ret)
1454 			return ret;
1455 
1456 		vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1457 		break;
1458 	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1459 		smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1460 		smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1461 
1462 		ret = vangogh_set_peak_clock_by_device(smu);
1463 		if (ret)
1464 			return ret;
1465 		break;
1466 	case AMD_DPM_FORCED_LEVEL_MANUAL:
1467 	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1468 	default:
1469 		return 0;
1470 	}
1471 
1472 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1473 					      smu->gfx_actual_hard_min_freq, NULL);
1474 	if (ret)
1475 		return ret;
1476 
1477 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1478 					      smu->gfx_actual_soft_max_freq, NULL);
1479 	if (ret)
1480 		return ret;
1481 
1482 	if (smu->adev->pm.fw_version >= 0x43f1b00) {
1483 		for (i = 0; i < smu->cpu_core_num; i++) {
1484 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
1485 							      ((i << 20)
1486 							       | smu->cpu_actual_soft_min_freq),
1487 							      NULL);
1488 			if (ret)
1489 				return ret;
1490 
1491 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
1492 							      ((i << 20)
1493 							       | smu->cpu_actual_soft_max_freq),
1494 							      NULL);
1495 			if (ret)
1496 				return ret;
1497 		}
1498 	}
1499 
1500 	return ret;
1501 }
1502 
1503 static int vangogh_read_sensor(struct smu_context *smu,
1504 				 enum amd_pp_sensors sensor,
1505 				 void *data, uint32_t *size)
1506 {
1507 	int ret = 0;
1508 
1509 	if (!data || !size)
1510 		return -EINVAL;
1511 
1512 	switch (sensor) {
1513 	case AMDGPU_PP_SENSOR_GPU_LOAD:
1514 		ret = vangogh_common_get_smu_metrics_data(smu,
1515 						   METRICS_AVERAGE_GFXACTIVITY,
1516 						   (uint32_t *)data);
1517 		*size = 4;
1518 		break;
1519 	case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1520 		ret = vangogh_common_get_smu_metrics_data(smu,
1521 						   METRICS_AVERAGE_SOCKETPOWER,
1522 						   (uint32_t *)data);
1523 		*size = 4;
1524 		break;
1525 	case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1526 		ret = vangogh_common_get_smu_metrics_data(smu,
1527 						   METRICS_CURR_SOCKETPOWER,
1528 						   (uint32_t *)data);
1529 		*size = 4;
1530 		break;
1531 	case AMDGPU_PP_SENSOR_EDGE_TEMP:
1532 		ret = vangogh_common_get_smu_metrics_data(smu,
1533 						   METRICS_TEMPERATURE_EDGE,
1534 						   (uint32_t *)data);
1535 		*size = 4;
1536 		break;
1537 	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1538 		ret = vangogh_common_get_smu_metrics_data(smu,
1539 						   METRICS_TEMPERATURE_HOTSPOT,
1540 						   (uint32_t *)data);
1541 		*size = 4;
1542 		break;
1543 	case AMDGPU_PP_SENSOR_GFX_MCLK:
1544 		ret = vangogh_common_get_smu_metrics_data(smu,
1545 						   METRICS_CURR_UCLK,
1546 						   (uint32_t *)data);
1547 		*(uint32_t *)data *= 100;
1548 		*size = 4;
1549 		break;
1550 	case AMDGPU_PP_SENSOR_GFX_SCLK:
1551 		ret = vangogh_common_get_smu_metrics_data(smu,
1552 						   METRICS_CURR_GFXCLK,
1553 						   (uint32_t *)data);
1554 		*(uint32_t *)data *= 100;
1555 		*size = 4;
1556 		break;
1557 	case AMDGPU_PP_SENSOR_VDDGFX:
1558 		ret = vangogh_common_get_smu_metrics_data(smu,
1559 						   METRICS_VOLTAGE_VDDGFX,
1560 						   (uint32_t *)data);
1561 		*size = 4;
1562 		break;
1563 	case AMDGPU_PP_SENSOR_VDDNB:
1564 		ret = vangogh_common_get_smu_metrics_data(smu,
1565 						   METRICS_VOLTAGE_VDDSOC,
1566 						   (uint32_t *)data);
1567 		*size = 4;
1568 		break;
1569 	case AMDGPU_PP_SENSOR_CPU_CLK:
1570 		ret = vangogh_common_get_smu_metrics_data(smu,
1571 						   METRICS_AVERAGE_CPUCLK,
1572 						   (uint32_t *)data);
1573 		*size = smu->cpu_core_num * sizeof(uint16_t);
1574 		break;
1575 	default:
1576 		ret = -EOPNOTSUPP;
1577 		break;
1578 	}
1579 
1580 	return ret;
1581 }
1582 
1583 static int vangogh_get_apu_thermal_limit(struct smu_context *smu, uint32_t *limit)
1584 {
1585 	return smu_cmn_send_smc_msg_with_param(smu,
1586 					      SMU_MSG_GetThermalLimit,
1587 					      0, limit);
1588 }
1589 
1590 static int vangogh_set_apu_thermal_limit(struct smu_context *smu, uint32_t limit)
1591 {
1592 	return smu_cmn_send_smc_msg_with_param(smu,
1593 					      SMU_MSG_SetReducedThermalLimit,
1594 					      limit, NULL);
1595 }
1596 
1597 
1598 static int vangogh_set_watermarks_table(struct smu_context *smu,
1599 				       struct pp_smu_wm_range_sets *clock_ranges)
1600 {
1601 	int i;
1602 	int ret = 0;
1603 	Watermarks_t *table = smu->smu_table.watermarks_table;
1604 
1605 	if (!table || !clock_ranges)
1606 		return -EINVAL;
1607 
1608 	if (clock_ranges) {
1609 		if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1610 			clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1611 			return -EINVAL;
1612 
1613 		for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1614 			table->WatermarkRow[WM_DCFCLK][i].MinClock =
1615 				clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1616 			table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1617 				clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1618 			table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1619 				clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1620 			table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1621 				clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1622 
1623 			table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1624 				clock_ranges->reader_wm_sets[i].wm_inst;
1625 		}
1626 
1627 		for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1628 			table->WatermarkRow[WM_SOCCLK][i].MinClock =
1629 				clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1630 			table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1631 				clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1632 			table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1633 				clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1634 			table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
1635 				clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1636 
1637 			table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1638 				clock_ranges->writer_wm_sets[i].wm_inst;
1639 		}
1640 
1641 		smu->watermarks_bitmap |= WATERMARKS_EXIST;
1642 	}
1643 
1644 	/* pass data to smu controller */
1645 	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1646 	     !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1647 		ret = smu_cmn_write_watermarks_table(smu);
1648 		if (ret) {
1649 			dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1650 			return ret;
1651 		}
1652 		smu->watermarks_bitmap |= WATERMARKS_LOADED;
1653 	}
1654 
1655 	return 0;
1656 }
1657 
1658 static ssize_t vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context *smu,
1659 				      void **table)
1660 {
1661 	struct smu_table_context *smu_table = &smu->smu_table;
1662 	struct gpu_metrics_v2_3 *gpu_metrics =
1663 		(struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table;
1664 	SmuMetrics_legacy_t metrics;
1665 	int ret = 0;
1666 
1667 	ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1668 	if (ret)
1669 		return ret;
1670 
1671 	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3);
1672 
1673 	gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1674 	gpu_metrics->temperature_soc = metrics.SocTemperature;
1675 	memcpy(&gpu_metrics->temperature_core[0],
1676 		&metrics.CoreTemperature[0],
1677 		sizeof(uint16_t) * 4);
1678 	gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1679 
1680 	gpu_metrics->average_gfx_activity = metrics.GfxActivity;
1681 	gpu_metrics->average_mm_activity = metrics.UvdActivity;
1682 
1683 	gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1684 	gpu_metrics->average_cpu_power = metrics.Power[0];
1685 	gpu_metrics->average_soc_power = metrics.Power[1];
1686 	gpu_metrics->average_gfx_power = metrics.Power[2];
1687 	memcpy(&gpu_metrics->average_core_power[0],
1688 		&metrics.CorePower[0],
1689 		sizeof(uint16_t) * 4);
1690 
1691 	gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
1692 	gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
1693 	gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
1694 	gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
1695 	gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
1696 	gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
1697 
1698 	memcpy(&gpu_metrics->current_coreclk[0],
1699 		&metrics.CoreFrequency[0],
1700 		sizeof(uint16_t) * 4);
1701 	gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1702 
1703 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1704 	gpu_metrics->indep_throttle_status =
1705 			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1706 							   vangogh_throttler_map);
1707 
1708 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1709 
1710 	*table = (void *)gpu_metrics;
1711 
1712 	return sizeof(struct gpu_metrics_v2_3);
1713 }
1714 
1715 static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu,
1716 				      void **table)
1717 {
1718 	struct smu_table_context *smu_table = &smu->smu_table;
1719 	struct gpu_metrics_v2_2 *gpu_metrics =
1720 		(struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1721 	SmuMetrics_legacy_t metrics;
1722 	int ret = 0;
1723 
1724 	ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1725 	if (ret)
1726 		return ret;
1727 
1728 	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1729 
1730 	gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1731 	gpu_metrics->temperature_soc = metrics.SocTemperature;
1732 	memcpy(&gpu_metrics->temperature_core[0],
1733 		&metrics.CoreTemperature[0],
1734 		sizeof(uint16_t) * 4);
1735 	gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1736 
1737 	gpu_metrics->average_gfx_activity = metrics.GfxActivity;
1738 	gpu_metrics->average_mm_activity = metrics.UvdActivity;
1739 
1740 	gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1741 	gpu_metrics->average_cpu_power = metrics.Power[0];
1742 	gpu_metrics->average_soc_power = metrics.Power[1];
1743 	gpu_metrics->average_gfx_power = metrics.Power[2];
1744 	memcpy(&gpu_metrics->average_core_power[0],
1745 		&metrics.CorePower[0],
1746 		sizeof(uint16_t) * 4);
1747 
1748 	gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
1749 	gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
1750 	gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
1751 	gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
1752 	gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
1753 	gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
1754 
1755 	memcpy(&gpu_metrics->current_coreclk[0],
1756 		&metrics.CoreFrequency[0],
1757 		sizeof(uint16_t) * 4);
1758 	gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1759 
1760 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1761 	gpu_metrics->indep_throttle_status =
1762 			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1763 							   vangogh_throttler_map);
1764 
1765 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1766 
1767 	*table = (void *)gpu_metrics;
1768 
1769 	return sizeof(struct gpu_metrics_v2_2);
1770 }
1771 
1772 static ssize_t vangogh_get_gpu_metrics_v2_3(struct smu_context *smu,
1773 				      void **table)
1774 {
1775 	struct smu_table_context *smu_table = &smu->smu_table;
1776 	struct gpu_metrics_v2_3 *gpu_metrics =
1777 		(struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table;
1778 	SmuMetrics_t metrics;
1779 	int ret = 0;
1780 
1781 	ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1782 	if (ret)
1783 		return ret;
1784 
1785 	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3);
1786 
1787 	gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1788 	gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1789 	memcpy(&gpu_metrics->temperature_core[0],
1790 		&metrics.Current.CoreTemperature[0],
1791 		sizeof(uint16_t) * 4);
1792 	gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1793 
1794 	gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature;
1795 	gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature;
1796 	memcpy(&gpu_metrics->average_temperature_core[0],
1797 		&metrics.Average.CoreTemperature[0],
1798 		sizeof(uint16_t) * 4);
1799 	gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0];
1800 
1801 	gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
1802 	gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1803 
1804 	gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
1805 	gpu_metrics->average_cpu_power = metrics.Current.Power[0];
1806 	gpu_metrics->average_soc_power = metrics.Current.Power[1];
1807 	gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1808 	memcpy(&gpu_metrics->average_core_power[0],
1809 		&metrics.Average.CorePower[0],
1810 		sizeof(uint16_t) * 4);
1811 
1812 	gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1813 	gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1814 	gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1815 	gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1816 	gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1817 	gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1818 
1819 	gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1820 	gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1821 	gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1822 	gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1823 	gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1824 	gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1825 
1826 	memcpy(&gpu_metrics->current_coreclk[0],
1827 		&metrics.Current.CoreFrequency[0],
1828 		sizeof(uint16_t) * 4);
1829 	gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1830 
1831 	gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1832 	gpu_metrics->indep_throttle_status =
1833 			smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1834 							   vangogh_throttler_map);
1835 
1836 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1837 
1838 	*table = (void *)gpu_metrics;
1839 
1840 	return sizeof(struct gpu_metrics_v2_3);
1841 }
1842 
1843 static ssize_t vangogh_get_gpu_metrics_v2_4(struct smu_context *smu,
1844 					    void **table)
1845 {
1846 	SmuMetrics_t metrics;
1847 	struct smu_table_context *smu_table = &smu->smu_table;
1848 	struct gpu_metrics_v2_4 *gpu_metrics =
1849 				(struct gpu_metrics_v2_4 *)smu_table->gpu_metrics_table;
1850 	int ret = 0;
1851 
1852 	ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1853 	if (ret)
1854 		return ret;
1855 
1856 	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 4);
1857 
1858 	gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1859 	gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1860 	memcpy(&gpu_metrics->temperature_core[0],
1861 	       &metrics.Current.CoreTemperature[0],
1862 	       sizeof(uint16_t) * 4);
1863 	gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1864 
1865 	gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature;
1866 	gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature;
1867 	memcpy(&gpu_metrics->average_temperature_core[0],
1868 	       &metrics.Average.CoreTemperature[0],
1869 	       sizeof(uint16_t) * 4);
1870 	gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0];
1871 
1872 	gpu_metrics->average_gfx_activity = metrics.Average.GfxActivity;
1873 	gpu_metrics->average_mm_activity = metrics.Average.UvdActivity;
1874 
1875 	gpu_metrics->average_socket_power = metrics.Average.CurrentSocketPower;
1876 	gpu_metrics->average_cpu_power = metrics.Average.Power[0];
1877 	gpu_metrics->average_soc_power = metrics.Average.Power[1];
1878 	gpu_metrics->average_gfx_power = metrics.Average.Power[2];
1879 
1880 	gpu_metrics->average_cpu_voltage = metrics.Average.Voltage[0];
1881 	gpu_metrics->average_soc_voltage = metrics.Average.Voltage[1];
1882 	gpu_metrics->average_gfx_voltage = metrics.Average.Voltage[2];
1883 
1884 	gpu_metrics->average_cpu_current = metrics.Average.Current[0];
1885 	gpu_metrics->average_soc_current = metrics.Average.Current[1];
1886 	gpu_metrics->average_gfx_current = metrics.Average.Current[2];
1887 
1888 	memcpy(&gpu_metrics->average_core_power[0],
1889 	       &metrics.Average.CorePower[0],
1890 	       sizeof(uint16_t) * 4);
1891 
1892 	gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1893 	gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1894 	gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1895 	gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1896 	gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1897 	gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1898 
1899 	gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1900 	gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1901 	gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1902 	gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1903 	gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1904 	gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1905 
1906 	memcpy(&gpu_metrics->current_coreclk[0],
1907 	       &metrics.Current.CoreFrequency[0],
1908 	       sizeof(uint16_t) * 4);
1909 	gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1910 
1911 	gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1912 	gpu_metrics->indep_throttle_status =
1913 			smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1914 							   vangogh_throttler_map);
1915 
1916 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1917 
1918 	*table = (void *)gpu_metrics;
1919 
1920 	return sizeof(struct gpu_metrics_v2_4);
1921 }
1922 
1923 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
1924 				      void **table)
1925 {
1926 	struct smu_table_context *smu_table = &smu->smu_table;
1927 	struct gpu_metrics_v2_2 *gpu_metrics =
1928 		(struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1929 	SmuMetrics_t metrics;
1930 	int ret = 0;
1931 
1932 	ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1933 	if (ret)
1934 		return ret;
1935 
1936 	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1937 
1938 	gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1939 	gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1940 	memcpy(&gpu_metrics->temperature_core[0],
1941 		&metrics.Current.CoreTemperature[0],
1942 		sizeof(uint16_t) * 4);
1943 	gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1944 
1945 	gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
1946 	gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1947 
1948 	gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
1949 	gpu_metrics->average_cpu_power = metrics.Current.Power[0];
1950 	gpu_metrics->average_soc_power = metrics.Current.Power[1];
1951 	gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1952 	memcpy(&gpu_metrics->average_core_power[0],
1953 		&metrics.Average.CorePower[0],
1954 		sizeof(uint16_t) * 4);
1955 
1956 	gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1957 	gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1958 	gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1959 	gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1960 	gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1961 	gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1962 
1963 	gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1964 	gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1965 	gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1966 	gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1967 	gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1968 	gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1969 
1970 	memcpy(&gpu_metrics->current_coreclk[0],
1971 		&metrics.Current.CoreFrequency[0],
1972 		sizeof(uint16_t) * 4);
1973 	gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1974 
1975 	gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1976 	gpu_metrics->indep_throttle_status =
1977 			smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1978 							   vangogh_throttler_map);
1979 
1980 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1981 
1982 	*table = (void *)gpu_metrics;
1983 
1984 	return sizeof(struct gpu_metrics_v2_2);
1985 }
1986 
1987 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu,
1988 				      void **table)
1989 {
1990 	uint32_t smu_program;
1991 	uint32_t fw_version;
1992 	int ret = 0;
1993 
1994 	smu_program = (smu->smc_fw_version >> 24) & 0xff;
1995 	fw_version = smu->smc_fw_version & 0xffffff;
1996 	if (smu_program == 6) {
1997 		if (fw_version >= 0x3F0800)
1998 			ret = vangogh_get_gpu_metrics_v2_4(smu, table);
1999 		else
2000 			ret = vangogh_get_gpu_metrics_v2_3(smu, table);
2001 
2002 	} else {
2003 		if (smu->smc_fw_version >= 0x043F3E00) {
2004 			if (smu->smc_fw_if_version < 0x3)
2005 				ret = vangogh_get_legacy_gpu_metrics_v2_3(smu, table);
2006 			else
2007 				ret = vangogh_get_gpu_metrics_v2_3(smu, table);
2008 		} else {
2009 			if (smu->smc_fw_if_version < 0x3)
2010 				ret = vangogh_get_legacy_gpu_metrics(smu, table);
2011 			else
2012 				ret = vangogh_get_gpu_metrics(smu, table);
2013 		}
2014 	}
2015 
2016 	return ret;
2017 }
2018 
2019 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
2020 					long input[], uint32_t size)
2021 {
2022 	int ret = 0;
2023 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2024 
2025 	if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
2026 		dev_warn(smu->adev->dev,
2027 			"pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
2028 		return -EINVAL;
2029 	}
2030 
2031 	switch (type) {
2032 	case PP_OD_EDIT_CCLK_VDDC_TABLE:
2033 		if (size != 3) {
2034 			dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
2035 			return -EINVAL;
2036 		}
2037 		if (input[0] >= smu->cpu_core_num) {
2038 			dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
2039 				smu->cpu_core_num);
2040 		}
2041 		smu->cpu_core_id_select = input[0];
2042 		if (input[1] == 0) {
2043 			if (input[2] < smu->cpu_default_soft_min_freq) {
2044 				dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2045 					input[2], smu->cpu_default_soft_min_freq);
2046 				return -EINVAL;
2047 			}
2048 			smu->cpu_actual_soft_min_freq = input[2];
2049 		} else if (input[1] == 1) {
2050 			if (input[2] > smu->cpu_default_soft_max_freq) {
2051 				dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2052 					input[2], smu->cpu_default_soft_max_freq);
2053 				return -EINVAL;
2054 			}
2055 			smu->cpu_actual_soft_max_freq = input[2];
2056 		} else {
2057 			return -EINVAL;
2058 		}
2059 		break;
2060 	case PP_OD_EDIT_SCLK_VDDC_TABLE:
2061 		if (size != 2) {
2062 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
2063 			return -EINVAL;
2064 		}
2065 
2066 		if (input[0] == 0) {
2067 			if (input[1] < smu->gfx_default_hard_min_freq) {
2068 				dev_warn(smu->adev->dev,
2069 					"Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2070 					input[1], smu->gfx_default_hard_min_freq);
2071 				return -EINVAL;
2072 			}
2073 			smu->gfx_actual_hard_min_freq = input[1];
2074 		} else if (input[0] == 1) {
2075 			if (input[1] > smu->gfx_default_soft_max_freq) {
2076 				dev_warn(smu->adev->dev,
2077 					"Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2078 					input[1], smu->gfx_default_soft_max_freq);
2079 				return -EINVAL;
2080 			}
2081 			smu->gfx_actual_soft_max_freq = input[1];
2082 		} else {
2083 			return -EINVAL;
2084 		}
2085 		break;
2086 	case PP_OD_RESTORE_DEFAULT_TABLE:
2087 		if (size != 0) {
2088 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
2089 			return -EINVAL;
2090 		} else {
2091 			smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2092 			smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2093 			smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
2094 			smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
2095 		}
2096 		break;
2097 	case PP_OD_COMMIT_DPM_TABLE:
2098 		if (size != 0) {
2099 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
2100 			return -EINVAL;
2101 		} else {
2102 			if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2103 				dev_err(smu->adev->dev,
2104 					"The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2105 					smu->gfx_actual_hard_min_freq,
2106 					smu->gfx_actual_soft_max_freq);
2107 				return -EINVAL;
2108 			}
2109 
2110 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2111 									smu->gfx_actual_hard_min_freq, NULL);
2112 			if (ret) {
2113 				dev_err(smu->adev->dev, "Set hard min sclk failed!");
2114 				return ret;
2115 			}
2116 
2117 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2118 									smu->gfx_actual_soft_max_freq, NULL);
2119 			if (ret) {
2120 				dev_err(smu->adev->dev, "Set soft max sclk failed!");
2121 				return ret;
2122 			}
2123 
2124 			if (smu->adev->pm.fw_version < 0x43f1b00) {
2125 				dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n");
2126 				break;
2127 			}
2128 
2129 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
2130 							      ((smu->cpu_core_id_select << 20)
2131 							       | smu->cpu_actual_soft_min_freq),
2132 							      NULL);
2133 			if (ret) {
2134 				dev_err(smu->adev->dev, "Set hard min cclk failed!");
2135 				return ret;
2136 			}
2137 
2138 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
2139 							      ((smu->cpu_core_id_select << 20)
2140 							       | smu->cpu_actual_soft_max_freq),
2141 							      NULL);
2142 			if (ret) {
2143 				dev_err(smu->adev->dev, "Set soft max cclk failed!");
2144 				return ret;
2145 			}
2146 		}
2147 		break;
2148 	default:
2149 		return -ENOSYS;
2150 	}
2151 
2152 	return ret;
2153 }
2154 
2155 static int vangogh_set_default_dpm_tables(struct smu_context *smu)
2156 {
2157 	struct smu_table_context *smu_table = &smu->smu_table;
2158 
2159 	return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
2160 }
2161 
2162 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
2163 {
2164 	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
2165 
2166 	smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
2167 	smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
2168 	smu->gfx_actual_hard_min_freq = 0;
2169 	smu->gfx_actual_soft_max_freq = 0;
2170 
2171 	smu->cpu_default_soft_min_freq = 1400;
2172 	smu->cpu_default_soft_max_freq = 3500;
2173 	smu->cpu_actual_soft_min_freq = 0;
2174 	smu->cpu_actual_soft_max_freq = 0;
2175 
2176 	return 0;
2177 }
2178 
2179 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
2180 {
2181 	DpmClocks_t *table = smu->smu_table.clocks_table;
2182 	int i;
2183 
2184 	if (!clock_table || !table)
2185 		return -EINVAL;
2186 
2187 	for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
2188 		clock_table->SocClocks[i].Freq = table->SocClocks[i];
2189 		clock_table->SocClocks[i].Vol = table->SocVoltage[i];
2190 	}
2191 
2192 	for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2193 		clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk;
2194 		clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage;
2195 	}
2196 
2197 	for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2198 		clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk;
2199 		clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage;
2200 	}
2201 
2202 	return 0;
2203 }
2204 
2205 
2206 static int vangogh_system_features_control(struct smu_context *smu, bool en)
2207 {
2208 	struct amdgpu_device *adev = smu->adev;
2209 	int ret = 0;
2210 
2211 	if (adev->pm.fw_version >= 0x43f1700 && !en)
2212 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify,
2213 						      RLC_STATUS_OFF, NULL);
2214 
2215 	return ret;
2216 }
2217 
2218 static int vangogh_post_smu_init(struct smu_context *smu)
2219 {
2220 	struct amdgpu_device *adev = smu->adev;
2221 	uint32_t tmp;
2222 	int ret = 0;
2223 	uint8_t aon_bits = 0;
2224 	/* Two CUs in one WGP */
2225 	uint32_t req_active_wgps = adev->gfx.cu_info.number/2;
2226 	uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
2227 		adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2228 
2229 	/* allow message will be sent after enable message on Vangogh*/
2230 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
2231 			(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2232 		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
2233 		if (ret) {
2234 			dev_err(adev->dev, "Failed to Enable GfxOff!\n");
2235 			return ret;
2236 		}
2237 	} else {
2238 		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2239 		dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n");
2240 	}
2241 
2242 	/* if all CUs are active, no need to power off any WGPs */
2243 	if (total_cu == adev->gfx.cu_info.number)
2244 		return 0;
2245 
2246 	/*
2247 	 * Calculate the total bits number of always on WGPs for all SA/SEs in
2248 	 * RLC_PG_ALWAYS_ON_WGP_MASK.
2249 	 */
2250 	tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK));
2251 	tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK;
2252 
2253 	aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2254 
2255 	/* Do not request any WGPs less than set in the AON_WGP_MASK */
2256 	if (aon_bits > req_active_wgps) {
2257 		dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n");
2258 		return 0;
2259 	} else {
2260 		return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL);
2261 	}
2262 }
2263 
2264 static int vangogh_mode_reset(struct smu_context *smu, int type)
2265 {
2266 	int ret = 0, index = 0;
2267 
2268 	index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2269 					       SMU_MSG_GfxDeviceDriverReset);
2270 	if (index < 0)
2271 		return index == -EACCES ? 0 : index;
2272 
2273 	mutex_lock(&smu->message_lock);
2274 
2275 	ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
2276 
2277 	mutex_unlock(&smu->message_lock);
2278 
2279 	mdelay(10);
2280 
2281 	return ret;
2282 }
2283 
2284 static int vangogh_mode2_reset(struct smu_context *smu)
2285 {
2286 	return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
2287 }
2288 
2289 /**
2290  * vangogh_get_gfxoff_status - Get gfxoff status
2291  *
2292  * @smu: amdgpu_device pointer
2293  *
2294  * Get current gfxoff status
2295  *
2296  * Return:
2297  * * 0	- GFXOFF (default if enabled).
2298  * * 1	- Transition out of GFX State.
2299  * * 2	- Not in GFXOFF.
2300  * * 3	- Transition into GFXOFF.
2301  */
2302 static u32 vangogh_get_gfxoff_status(struct smu_context *smu)
2303 {
2304 	struct amdgpu_device *adev = smu->adev;
2305 	u32 reg, gfxoff_status;
2306 
2307 	reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);
2308 	gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
2309 		>> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
2310 
2311 	return gfxoff_status;
2312 }
2313 
2314 static int vangogh_get_power_limit(struct smu_context *smu,
2315 				   uint32_t *current_power_limit,
2316 				   uint32_t *default_power_limit,
2317 				   uint32_t *max_power_limit,
2318 				   uint32_t *min_power_limit)
2319 {
2320 	struct smu_11_5_power_context *power_context =
2321 								smu->smu_power.power_context;
2322 	uint32_t ppt_limit;
2323 	int ret = 0;
2324 
2325 	if (smu->adev->pm.fw_version < 0x43f1e00)
2326 		return ret;
2327 
2328 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit);
2329 	if (ret) {
2330 		dev_err(smu->adev->dev, "Get slow PPT limit failed!\n");
2331 		return ret;
2332 	}
2333 	/* convert from milliwatt to watt */
2334 	if (current_power_limit)
2335 		*current_power_limit = ppt_limit / 1000;
2336 	if (default_power_limit)
2337 		*default_power_limit = ppt_limit / 1000;
2338 	if (max_power_limit)
2339 		*max_power_limit = 29;
2340 	if (min_power_limit)
2341 		*min_power_limit = 0;
2342 
2343 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit);
2344 	if (ret) {
2345 		dev_err(smu->adev->dev, "Get fast PPT limit failed!\n");
2346 		return ret;
2347 	}
2348 	/* convert from milliwatt to watt */
2349 	power_context->current_fast_ppt_limit =
2350 			power_context->default_fast_ppt_limit = ppt_limit / 1000;
2351 	power_context->max_fast_ppt_limit = 30;
2352 
2353 	return ret;
2354 }
2355 
2356 static int vangogh_get_ppt_limit(struct smu_context *smu,
2357 								uint32_t *ppt_limit,
2358 								enum smu_ppt_limit_type type,
2359 								enum smu_ppt_limit_level level)
2360 {
2361 	struct smu_11_5_power_context *power_context =
2362 							smu->smu_power.power_context;
2363 
2364 	if (!power_context)
2365 		return -EOPNOTSUPP;
2366 
2367 	if (type == SMU_FAST_PPT_LIMIT) {
2368 		switch (level) {
2369 		case SMU_PPT_LIMIT_MAX:
2370 			*ppt_limit = power_context->max_fast_ppt_limit;
2371 			break;
2372 		case SMU_PPT_LIMIT_CURRENT:
2373 			*ppt_limit = power_context->current_fast_ppt_limit;
2374 			break;
2375 		case SMU_PPT_LIMIT_DEFAULT:
2376 			*ppt_limit = power_context->default_fast_ppt_limit;
2377 			break;
2378 		default:
2379 			break;
2380 		}
2381 	}
2382 
2383 	return 0;
2384 }
2385 
2386 static int vangogh_set_power_limit(struct smu_context *smu,
2387 				   enum smu_ppt_limit_type limit_type,
2388 				   uint32_t ppt_limit)
2389 {
2390 	struct smu_11_5_power_context *power_context =
2391 			smu->smu_power.power_context;
2392 	int ret = 0;
2393 
2394 	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
2395 		dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
2396 		return -EOPNOTSUPP;
2397 	}
2398 
2399 	switch (limit_type) {
2400 	case SMU_DEFAULT_PPT_LIMIT:
2401 		ret = smu_cmn_send_smc_msg_with_param(smu,
2402 				SMU_MSG_SetSlowPPTLimit,
2403 				ppt_limit * 1000, /* convert from watt to milliwatt */
2404 				NULL);
2405 		if (ret)
2406 			return ret;
2407 
2408 		smu->current_power_limit = ppt_limit;
2409 		break;
2410 	case SMU_FAST_PPT_LIMIT:
2411 		ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24);
2412 		if (ppt_limit > power_context->max_fast_ppt_limit) {
2413 			dev_err(smu->adev->dev,
2414 				"New power limit (%d) is over the max allowed %d\n",
2415 				ppt_limit, power_context->max_fast_ppt_limit);
2416 			return ret;
2417 		}
2418 
2419 		ret = smu_cmn_send_smc_msg_with_param(smu,
2420 				SMU_MSG_SetFastPPTLimit,
2421 				ppt_limit * 1000, /* convert from watt to milliwatt */
2422 				NULL);
2423 		if (ret)
2424 			return ret;
2425 
2426 		power_context->current_fast_ppt_limit = ppt_limit;
2427 		break;
2428 	default:
2429 		return -EINVAL;
2430 	}
2431 
2432 	return ret;
2433 }
2434 
2435 /**
2436  * vangogh_set_gfxoff_residency
2437  *
2438  * @smu: amdgpu_device pointer
2439  * @start: start/stop residency log
2440  *
2441  * This function will be used to log gfxoff residency
2442  *
2443  *
2444  * Returns standard response codes.
2445  */
2446 static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start)
2447 {
2448 	int ret = 0;
2449 	u32 residency;
2450 	struct amdgpu_device *adev = smu->adev;
2451 
2452 	if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
2453 		return 0;
2454 
2455 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency,
2456 					      start, &residency);
2457 
2458 	if (!start)
2459 		adev->gfx.gfx_off_residency = residency;
2460 
2461 	return ret;
2462 }
2463 
2464 /**
2465  * vangogh_get_gfxoff_residency
2466  *
2467  * @smu: amdgpu_device pointer
2468  * @residency: placeholder for return value
2469  *
2470  * This function will be used to get gfxoff residency.
2471  *
2472  * Returns standard response codes.
2473  */
2474 static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency)
2475 {
2476 	struct amdgpu_device *adev = smu->adev;
2477 
2478 	*residency = adev->gfx.gfx_off_residency;
2479 
2480 	return 0;
2481 }
2482 
2483 /**
2484  * vangogh_get_gfxoff_entrycount - get gfxoff entry count
2485  *
2486  * @smu: amdgpu_device pointer
2487  * @entrycount: placeholder for return value
2488  *
2489  * This function will be used to get gfxoff entry count
2490  *
2491  * Returns standard response codes.
2492  */
2493 static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t *entrycount)
2494 {
2495 	int ret = 0, value = 0;
2496 	struct amdgpu_device *adev = smu->adev;
2497 
2498 	if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
2499 		return 0;
2500 
2501 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryCount, &value);
2502 	*entrycount = value + adev->gfx.gfx_off_entrycount;
2503 
2504 	return ret;
2505 }
2506 
2507 static const struct pptable_funcs vangogh_ppt_funcs = {
2508 
2509 	.check_fw_status = smu_v11_0_check_fw_status,
2510 	.check_fw_version = smu_v11_0_check_fw_version,
2511 	.init_smc_tables = vangogh_init_smc_tables,
2512 	.fini_smc_tables = smu_v11_0_fini_smc_tables,
2513 	.init_power = smu_v11_0_init_power,
2514 	.fini_power = smu_v11_0_fini_power,
2515 	.register_irq_handler = smu_v11_0_register_irq_handler,
2516 	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2517 	.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2518 	.send_smc_msg = smu_cmn_send_smc_msg,
2519 	.dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable,
2520 	.dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,
2521 	.is_dpm_running = vangogh_is_dpm_running,
2522 	.read_sensor = vangogh_read_sensor,
2523 	.get_apu_thermal_limit = vangogh_get_apu_thermal_limit,
2524 	.set_apu_thermal_limit = vangogh_set_apu_thermal_limit,
2525 	.get_enabled_mask = smu_cmn_get_enabled_mask,
2526 	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2527 	.set_watermarks_table = vangogh_set_watermarks_table,
2528 	.set_driver_table_location = smu_v11_0_set_driver_table_location,
2529 	.interrupt_work = smu_v11_0_interrupt_work,
2530 	.get_gpu_metrics = vangogh_common_get_gpu_metrics,
2531 	.od_edit_dpm_table = vangogh_od_edit_dpm_table,
2532 	.print_clk_levels = vangogh_common_print_clk_levels,
2533 	.set_default_dpm_table = vangogh_set_default_dpm_tables,
2534 	.set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,
2535 	.system_features_control = vangogh_system_features_control,
2536 	.feature_is_enabled = smu_cmn_feature_is_enabled,
2537 	.set_power_profile_mode = vangogh_set_power_profile_mode,
2538 	.get_power_profile_mode = vangogh_get_power_profile_mode,
2539 	.get_dpm_clock_table = vangogh_get_dpm_clock_table,
2540 	.force_clk_levels = vangogh_force_clk_levels,
2541 	.set_performance_level = vangogh_set_performance_level,
2542 	.post_init = vangogh_post_smu_init,
2543 	.mode2_reset = vangogh_mode2_reset,
2544 	.gfx_off_control = smu_v11_0_gfx_off_control,
2545 	.get_gfx_off_status = vangogh_get_gfxoff_status,
2546 	.get_gfx_off_entrycount = vangogh_get_gfxoff_entrycount,
2547 	.get_gfx_off_residency = vangogh_get_gfxoff_residency,
2548 	.set_gfx_off_residency = vangogh_set_gfxoff_residency,
2549 	.get_ppt_limit = vangogh_get_ppt_limit,
2550 	.get_power_limit = vangogh_get_power_limit,
2551 	.set_power_limit = vangogh_set_power_limit,
2552 	.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2553 };
2554 
2555 void vangogh_set_ppt_funcs(struct smu_context *smu)
2556 {
2557 	smu->ppt_funcs = &vangogh_ppt_funcs;
2558 	smu->message_map = vangogh_message_map;
2559 	smu->feature_map = vangogh_feature_mask_map;
2560 	smu->table_map = vangogh_table_map;
2561 	smu->workload_map = vangogh_workload_map;
2562 	smu->is_apu = true;
2563 	smu_v11_0_set_smu_mailbox_registers(smu);
2564 }
2565