1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v11_0.h" 29 #include "smu11_driver_if_vangogh.h" 30 #include "vangogh_ppt.h" 31 #include "smu_v11_5_ppsmc.h" 32 #include "smu_v11_5_pmfw.h" 33 #include "smu_cmn.h" 34 #include "soc15_common.h" 35 #include "asic_reg/gc/gc_10_3_0_offset.h" 36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h" 37 #include <asm/processor.h> 38 39 /* 40 * DO NOT use these for err/warn/info/debug messages. 41 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 42 * They are more MGPU friendly. 43 */ 44 #undef pr_err 45 #undef pr_warn 46 #undef pr_info 47 #undef pr_debug 48 49 // Registers related to GFXOFF 50 // addressBlock: smuio_smuio_SmuSmuioDec 51 // base address: 0x5a000 52 #define mmSMUIO_GFX_MISC_CNTL 0x00c5 53 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0 54 55 //SMUIO_GFX_MISC_CNTL 56 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0 57 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1 58 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L 59 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L 60 61 #define FEATURE_MASK(feature) (1ULL << feature) 62 #define SMC_DPM_FEATURE ( \ 63 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 64 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 65 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 66 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 67 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 68 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 69 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 70 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 71 FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 72 73 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { 74 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 75 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0), 76 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0), 77 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0), 78 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 79 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 80 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0), 81 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0), 82 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 83 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 84 MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0), 85 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0), 86 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0), 87 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0), 88 MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0), 89 MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0), 90 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0), 91 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0), 92 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0), 93 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 94 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0), 95 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0), 96 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0), 97 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0), 98 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0), 99 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0), 100 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0), 101 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0), 102 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0), 103 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0), 104 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0), 105 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0), 106 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0), 107 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0), 108 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 109 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 110 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0), 111 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0), 112 MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0), 113 MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0), 114 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 115 MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0), 116 MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0), 117 MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0), 118 MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0), 119 MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0), 120 MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0), 121 MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0), 122 MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0), 123 MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0), 124 MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0), 125 MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0), 126 MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0), 127 MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0), 128 MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0), 129 MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0), 130 MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0), 131 MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0), 132 MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0), 133 MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0), 134 MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0), 135 MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0), 136 MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0), 137 MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0), 138 MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0), 139 MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0), 140 MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0), 141 MSG_MAP(GetGfxOffStatus, PPSMC_MSG_GetGfxOffStatus, 0), 142 MSG_MAP(GetGfxOffEntryCount, PPSMC_MSG_GetGfxOffEntryCount, 0), 143 MSG_MAP(LogGfxOffResidency, PPSMC_MSG_LogGfxOffResidency, 0), 144 }; 145 146 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { 147 FEA_MAP(PPT), 148 FEA_MAP(TDC), 149 FEA_MAP(THERMAL), 150 FEA_MAP(DS_GFXCLK), 151 FEA_MAP(DS_SOCCLK), 152 FEA_MAP(DS_LCLK), 153 FEA_MAP(DS_FCLK), 154 FEA_MAP(DS_MP1CLK), 155 FEA_MAP(DS_MP0CLK), 156 FEA_MAP(ATHUB_PG), 157 FEA_MAP(CCLK_DPM), 158 FEA_MAP(FAN_CONTROLLER), 159 FEA_MAP(ULV), 160 FEA_MAP(VCN_DPM), 161 FEA_MAP(LCLK_DPM), 162 FEA_MAP(SHUBCLK_DPM), 163 FEA_MAP(DCFCLK_DPM), 164 FEA_MAP(DS_DCFCLK), 165 FEA_MAP(S0I2), 166 FEA_MAP(SMU_LOW_POWER), 167 FEA_MAP(GFX_DEM), 168 FEA_MAP(PSI), 169 FEA_MAP(PROCHOT), 170 FEA_MAP(CPUOFF), 171 FEA_MAP(STAPM), 172 FEA_MAP(S0I3), 173 FEA_MAP(DF_CSTATES), 174 FEA_MAP(PERF_LIMIT), 175 FEA_MAP(CORE_DLDO), 176 FEA_MAP(RSMU_LOW_POWER), 177 FEA_MAP(SMN_LOW_POWER), 178 FEA_MAP(THM_LOW_POWER), 179 FEA_MAP(SMUIO_LOW_POWER), 180 FEA_MAP(MP1_LOW_POWER), 181 FEA_MAP(DS_VCN), 182 FEA_MAP(CPPC), 183 FEA_MAP(OS_CSTATES), 184 FEA_MAP(ISP_DPM), 185 FEA_MAP(A55_DPM), 186 FEA_MAP(CVIP_DSP_DPM), 187 FEA_MAP(MSMU_LOW_POWER), 188 FEA_MAP_REVERSE(SOCCLK), 189 FEA_MAP_REVERSE(FCLK), 190 FEA_MAP_HALF_REVERSE(GFX), 191 }; 192 193 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = { 194 TAB_MAP_VALID(WATERMARKS), 195 TAB_MAP_VALID(SMU_METRICS), 196 TAB_MAP_VALID(CUSTOM_DPM), 197 TAB_MAP_VALID(DPMCLOCKS), 198 }; 199 200 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 201 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 202 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 203 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 204 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CAPPED, WORKLOAD_PPLIB_CAPPED_BIT), 207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_UNCAPPED, WORKLOAD_PPLIB_UNCAPPED_BIT), 208 }; 209 210 static const uint8_t vangogh_throttler_map[] = { 211 [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT), 212 [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT), 213 [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT), 214 [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT), 215 [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT), 216 [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT), 217 [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT), 218 [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT), 219 [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT), 220 [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT), 221 [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT), 222 }; 223 224 static int vangogh_tables_init(struct smu_context *smu) 225 { 226 struct smu_table_context *smu_table = &smu->smu_table; 227 struct smu_table *tables = smu_table->tables; 228 229 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 230 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 231 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 232 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 233 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 234 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 235 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t), 236 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 237 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, max(sizeof(SmuMetrics_t), sizeof(SmuMetrics_legacy_t)), 238 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 239 240 smu_table->metrics_table = kzalloc(max(sizeof(SmuMetrics_t), sizeof(SmuMetrics_legacy_t)), GFP_KERNEL); 241 if (!smu_table->metrics_table) 242 goto err0_out; 243 smu_table->metrics_time = 0; 244 245 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2); 246 smu_table->gpu_metrics_table_size = max(smu_table->gpu_metrics_table_size, sizeof(struct gpu_metrics_v2_3)); 247 smu_table->gpu_metrics_table_size = max(smu_table->gpu_metrics_table_size, sizeof(struct gpu_metrics_v2_4)); 248 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 249 if (!smu_table->gpu_metrics_table) 250 goto err1_out; 251 252 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 253 if (!smu_table->watermarks_table) 254 goto err2_out; 255 256 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 257 if (!smu_table->clocks_table) 258 goto err3_out; 259 260 return 0; 261 262 err3_out: 263 kfree(smu_table->watermarks_table); 264 err2_out: 265 kfree(smu_table->gpu_metrics_table); 266 err1_out: 267 kfree(smu_table->metrics_table); 268 err0_out: 269 return -ENOMEM; 270 } 271 272 static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu, 273 MetricsMember_t member, 274 uint32_t *value) 275 { 276 struct smu_table_context *smu_table = &smu->smu_table; 277 SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table; 278 int ret = 0; 279 280 ret = smu_cmn_get_metrics_table(smu, 281 NULL, 282 false); 283 if (ret) 284 return ret; 285 286 switch (member) { 287 case METRICS_CURR_GFXCLK: 288 *value = metrics->GfxclkFrequency; 289 break; 290 case METRICS_AVERAGE_SOCCLK: 291 *value = metrics->SocclkFrequency; 292 break; 293 case METRICS_AVERAGE_VCLK: 294 *value = metrics->VclkFrequency; 295 break; 296 case METRICS_AVERAGE_DCLK: 297 *value = metrics->DclkFrequency; 298 break; 299 case METRICS_CURR_UCLK: 300 *value = metrics->MemclkFrequency; 301 break; 302 case METRICS_AVERAGE_GFXACTIVITY: 303 *value = metrics->GfxActivity / 100; 304 break; 305 case METRICS_AVERAGE_VCNACTIVITY: 306 *value = metrics->UvdActivity / 100; 307 break; 308 case METRICS_AVERAGE_SOCKETPOWER: 309 *value = (metrics->CurrentSocketPower << 8) / 310 1000 ; 311 break; 312 case METRICS_TEMPERATURE_EDGE: 313 *value = metrics->GfxTemperature / 100 * 314 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 315 break; 316 case METRICS_TEMPERATURE_HOTSPOT: 317 *value = metrics->SocTemperature / 100 * 318 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 319 break; 320 case METRICS_THROTTLER_STATUS: 321 *value = metrics->ThrottlerStatus; 322 break; 323 case METRICS_VOLTAGE_VDDGFX: 324 *value = metrics->Voltage[2]; 325 break; 326 case METRICS_VOLTAGE_VDDSOC: 327 *value = metrics->Voltage[1]; 328 break; 329 case METRICS_AVERAGE_CPUCLK: 330 memcpy(value, &metrics->CoreFrequency[0], 331 smu->cpu_core_num * sizeof(uint16_t)); 332 break; 333 default: 334 *value = UINT_MAX; 335 break; 336 } 337 338 return ret; 339 } 340 341 static int vangogh_get_smu_metrics_data(struct smu_context *smu, 342 MetricsMember_t member, 343 uint32_t *value) 344 { 345 struct smu_table_context *smu_table = &smu->smu_table; 346 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 347 int ret = 0; 348 349 ret = smu_cmn_get_metrics_table(smu, 350 NULL, 351 false); 352 if (ret) 353 return ret; 354 355 switch (member) { 356 case METRICS_CURR_GFXCLK: 357 *value = metrics->Current.GfxclkFrequency; 358 break; 359 case METRICS_AVERAGE_SOCCLK: 360 *value = metrics->Current.SocclkFrequency; 361 break; 362 case METRICS_AVERAGE_VCLK: 363 *value = metrics->Current.VclkFrequency; 364 break; 365 case METRICS_AVERAGE_DCLK: 366 *value = metrics->Current.DclkFrequency; 367 break; 368 case METRICS_CURR_UCLK: 369 *value = metrics->Current.MemclkFrequency; 370 break; 371 case METRICS_AVERAGE_GFXACTIVITY: 372 *value = metrics->Current.GfxActivity; 373 break; 374 case METRICS_AVERAGE_VCNACTIVITY: 375 *value = metrics->Current.UvdActivity; 376 break; 377 case METRICS_AVERAGE_SOCKETPOWER: 378 *value = (metrics->Average.CurrentSocketPower << 8) / 379 1000; 380 break; 381 case METRICS_CURR_SOCKETPOWER: 382 *value = (metrics->Current.CurrentSocketPower << 8) / 383 1000; 384 break; 385 case METRICS_TEMPERATURE_EDGE: 386 *value = metrics->Current.GfxTemperature / 100 * 387 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 388 break; 389 case METRICS_TEMPERATURE_HOTSPOT: 390 *value = metrics->Current.SocTemperature / 100 * 391 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 392 break; 393 case METRICS_THROTTLER_STATUS: 394 *value = metrics->Current.ThrottlerStatus; 395 break; 396 case METRICS_VOLTAGE_VDDGFX: 397 *value = metrics->Current.Voltage[2]; 398 break; 399 case METRICS_VOLTAGE_VDDSOC: 400 *value = metrics->Current.Voltage[1]; 401 break; 402 case METRICS_AVERAGE_CPUCLK: 403 memcpy(value, &metrics->Current.CoreFrequency[0], 404 smu->cpu_core_num * sizeof(uint16_t)); 405 break; 406 default: 407 *value = UINT_MAX; 408 break; 409 } 410 411 return ret; 412 } 413 414 static int vangogh_common_get_smu_metrics_data(struct smu_context *smu, 415 MetricsMember_t member, 416 uint32_t *value) 417 { 418 int ret = 0; 419 420 if (smu->smc_fw_if_version < 0x3) 421 ret = vangogh_get_legacy_smu_metrics_data(smu, member, value); 422 else 423 ret = vangogh_get_smu_metrics_data(smu, member, value); 424 425 return ret; 426 } 427 428 static int vangogh_allocate_dpm_context(struct smu_context *smu) 429 { 430 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 431 432 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 433 GFP_KERNEL); 434 if (!smu_dpm->dpm_context) 435 return -ENOMEM; 436 437 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 438 439 return 0; 440 } 441 442 static int vangogh_init_smc_tables(struct smu_context *smu) 443 { 444 int ret = 0; 445 446 ret = vangogh_tables_init(smu); 447 if (ret) 448 return ret; 449 450 ret = vangogh_allocate_dpm_context(smu); 451 if (ret) 452 return ret; 453 454 #ifdef CONFIG_X86 455 /* AMD x86 APU only */ 456 smu->cpu_core_num = topology_num_cores_per_package(); 457 #else 458 smu->cpu_core_num = 4; 459 #endif 460 461 return smu_v11_0_init_smc_tables(smu); 462 } 463 464 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, 465 bool enable, 466 int inst) 467 { 468 int ret = 0; 469 470 if (enable) { 471 /* vcn dpm on is a prerequisite for vcn power gate messages */ 472 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 473 if (ret) 474 return ret; 475 } else { 476 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); 477 if (ret) 478 return ret; 479 } 480 481 return ret; 482 } 483 484 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 485 { 486 int ret = 0; 487 488 if (enable) { 489 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 490 if (ret) 491 return ret; 492 } else { 493 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 494 if (ret) 495 return ret; 496 } 497 498 return ret; 499 } 500 501 static bool vangogh_is_dpm_running(struct smu_context *smu) 502 { 503 struct amdgpu_device *adev = smu->adev; 504 int ret = 0; 505 uint64_t feature_enabled; 506 507 /* we need to re-init after suspend so return false */ 508 if (adev->in_suspend) 509 return false; 510 511 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 512 513 if (ret) 514 return false; 515 516 return !!(feature_enabled & SMC_DPM_FEATURE); 517 } 518 519 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 520 uint32_t dpm_level, uint32_t *freq) 521 { 522 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 523 524 if (!clk_table || clk_type >= SMU_CLK_COUNT) 525 return -EINVAL; 526 527 switch (clk_type) { 528 case SMU_SOCCLK: 529 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 530 return -EINVAL; 531 *freq = clk_table->SocClocks[dpm_level]; 532 break; 533 case SMU_VCLK: 534 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 535 return -EINVAL; 536 *freq = clk_table->VcnClocks[dpm_level].vclk; 537 break; 538 case SMU_DCLK: 539 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 540 return -EINVAL; 541 *freq = clk_table->VcnClocks[dpm_level].dclk; 542 break; 543 case SMU_UCLK: 544 case SMU_MCLK: 545 if (dpm_level >= clk_table->NumDfPstatesEnabled) 546 return -EINVAL; 547 *freq = clk_table->DfPstateTable[dpm_level].memclk; 548 549 break; 550 case SMU_FCLK: 551 if (dpm_level >= clk_table->NumDfPstatesEnabled) 552 return -EINVAL; 553 *freq = clk_table->DfPstateTable[dpm_level].fclk; 554 break; 555 default: 556 return -EINVAL; 557 } 558 559 return 0; 560 } 561 562 static int vangogh_print_legacy_clk_levels(struct smu_context *smu, 563 enum smu_clk_type clk_type, char *buf) 564 { 565 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 566 SmuMetrics_legacy_t metrics; 567 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 568 int i, idx, size = 0, ret = 0; 569 uint32_t cur_value = 0, value = 0, count = 0; 570 bool cur_value_match_level = false; 571 572 memset(&metrics, 0, sizeof(metrics)); 573 574 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 575 if (ret) 576 return ret; 577 578 smu_cmn_get_sysfs_buf(&buf, &size); 579 580 switch (clk_type) { 581 case SMU_OD_SCLK: 582 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 583 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 584 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 585 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 586 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 587 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 588 } 589 break; 590 case SMU_OD_CCLK: 591 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 592 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 593 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 594 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 595 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 596 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 597 } 598 break; 599 case SMU_OD_RANGE: 600 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 601 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 602 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 603 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 604 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", 605 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 606 } 607 break; 608 case SMU_SOCCLK: 609 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 610 count = clk_table->NumSocClkLevelsEnabled; 611 cur_value = metrics.SocclkFrequency; 612 break; 613 case SMU_VCLK: 614 count = clk_table->VcnClkLevelsEnabled; 615 cur_value = metrics.VclkFrequency; 616 break; 617 case SMU_DCLK: 618 count = clk_table->VcnClkLevelsEnabled; 619 cur_value = metrics.DclkFrequency; 620 break; 621 case SMU_MCLK: 622 count = clk_table->NumDfPstatesEnabled; 623 cur_value = metrics.MemclkFrequency; 624 break; 625 case SMU_FCLK: 626 count = clk_table->NumDfPstatesEnabled; 627 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 628 if (ret) 629 return ret; 630 break; 631 default: 632 break; 633 } 634 635 switch (clk_type) { 636 case SMU_SOCCLK: 637 case SMU_VCLK: 638 case SMU_DCLK: 639 case SMU_MCLK: 640 case SMU_FCLK: 641 for (i = 0; i < count; i++) { 642 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; 643 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value); 644 if (ret) 645 return ret; 646 if (!value) 647 continue; 648 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 649 cur_value == value ? "*" : ""); 650 if (cur_value == value) 651 cur_value_match_level = true; 652 } 653 654 if (!cur_value_match_level) 655 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value); 656 break; 657 default: 658 break; 659 } 660 661 return size; 662 } 663 664 static int vangogh_print_clk_levels(struct smu_context *smu, 665 enum smu_clk_type clk_type, char *buf) 666 { 667 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 668 SmuMetrics_t metrics; 669 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 670 int i, idx, size = 0, ret = 0; 671 uint32_t cur_value = 0, value = 0, count = 0; 672 bool cur_value_match_level = false; 673 uint32_t min, max; 674 675 memset(&metrics, 0, sizeof(metrics)); 676 677 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 678 if (ret) 679 return ret; 680 681 smu_cmn_get_sysfs_buf(&buf, &size); 682 683 switch (clk_type) { 684 case SMU_OD_SCLK: 685 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 686 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 687 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 688 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 689 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 690 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 691 } 692 break; 693 case SMU_OD_CCLK: 694 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 695 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 696 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 697 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 698 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 699 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 700 } 701 break; 702 case SMU_OD_RANGE: 703 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 704 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 705 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 706 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 707 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", 708 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 709 } 710 break; 711 case SMU_SOCCLK: 712 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 713 count = clk_table->NumSocClkLevelsEnabled; 714 cur_value = metrics.Current.SocclkFrequency; 715 break; 716 case SMU_VCLK: 717 count = clk_table->VcnClkLevelsEnabled; 718 cur_value = metrics.Current.VclkFrequency; 719 break; 720 case SMU_DCLK: 721 count = clk_table->VcnClkLevelsEnabled; 722 cur_value = metrics.Current.DclkFrequency; 723 break; 724 case SMU_MCLK: 725 count = clk_table->NumDfPstatesEnabled; 726 cur_value = metrics.Current.MemclkFrequency; 727 break; 728 case SMU_FCLK: 729 count = clk_table->NumDfPstatesEnabled; 730 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 731 if (ret) 732 return ret; 733 break; 734 case SMU_GFXCLK: 735 case SMU_SCLK: 736 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value); 737 if (ret) { 738 return ret; 739 } 740 break; 741 default: 742 break; 743 } 744 745 switch (clk_type) { 746 case SMU_SOCCLK: 747 case SMU_VCLK: 748 case SMU_DCLK: 749 case SMU_MCLK: 750 case SMU_FCLK: 751 for (i = 0; i < count; i++) { 752 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; 753 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value); 754 if (ret) 755 return ret; 756 if (!value) 757 continue; 758 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 759 cur_value == value ? "*" : ""); 760 if (cur_value == value) 761 cur_value_match_level = true; 762 } 763 764 if (!cur_value_match_level) 765 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value); 766 break; 767 case SMU_GFXCLK: 768 case SMU_SCLK: 769 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; 770 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; 771 if (cur_value == max) 772 i = 2; 773 else if (cur_value == min) 774 i = 0; 775 else 776 i = 1; 777 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min, 778 i == 0 ? "*" : ""); 779 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 780 i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, 781 i == 1 ? "*" : ""); 782 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, 783 i == 2 ? "*" : ""); 784 break; 785 default: 786 break; 787 } 788 789 return size; 790 } 791 792 static int vangogh_common_print_clk_levels(struct smu_context *smu, 793 enum smu_clk_type clk_type, char *buf) 794 { 795 int ret = 0; 796 797 if (smu->smc_fw_if_version < 0x3) 798 ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf); 799 else 800 ret = vangogh_print_clk_levels(smu, clk_type, buf); 801 802 return ret; 803 } 804 805 static int vangogh_get_profiling_clk_mask(struct smu_context *smu, 806 enum amd_dpm_forced_level level, 807 uint32_t *vclk_mask, 808 uint32_t *dclk_mask, 809 uint32_t *mclk_mask, 810 uint32_t *fclk_mask, 811 uint32_t *soc_mask) 812 { 813 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 814 815 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 816 if (mclk_mask) 817 *mclk_mask = clk_table->NumDfPstatesEnabled - 1; 818 819 if (fclk_mask) 820 *fclk_mask = clk_table->NumDfPstatesEnabled - 1; 821 822 if (soc_mask) 823 *soc_mask = 0; 824 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 825 if (mclk_mask) 826 *mclk_mask = 0; 827 828 if (fclk_mask) 829 *fclk_mask = 0; 830 831 if (soc_mask) 832 *soc_mask = 1; 833 834 if (vclk_mask) 835 *vclk_mask = 1; 836 837 if (dclk_mask) 838 *dclk_mask = 1; 839 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) { 840 if (mclk_mask) 841 *mclk_mask = 0; 842 843 if (fclk_mask) 844 *fclk_mask = 0; 845 846 if (soc_mask) 847 *soc_mask = 1; 848 849 if (vclk_mask) 850 *vclk_mask = 1; 851 852 if (dclk_mask) 853 *dclk_mask = 1; 854 } 855 856 return 0; 857 } 858 859 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu, 860 enum smu_clk_type clk_type) 861 { 862 enum smu_feature_mask feature_id = 0; 863 864 switch (clk_type) { 865 case SMU_MCLK: 866 case SMU_UCLK: 867 case SMU_FCLK: 868 feature_id = SMU_FEATURE_DPM_FCLK_BIT; 869 break; 870 case SMU_GFXCLK: 871 case SMU_SCLK: 872 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 873 break; 874 case SMU_SOCCLK: 875 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 876 break; 877 case SMU_VCLK: 878 case SMU_DCLK: 879 feature_id = SMU_FEATURE_VCN_DPM_BIT; 880 break; 881 default: 882 return true; 883 } 884 885 if (!smu_cmn_feature_is_enabled(smu, feature_id)) 886 return false; 887 888 return true; 889 } 890 891 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu, 892 enum smu_clk_type clk_type, 893 uint32_t *min, 894 uint32_t *max) 895 { 896 int ret = 0; 897 uint32_t soc_mask; 898 uint32_t vclk_mask; 899 uint32_t dclk_mask; 900 uint32_t mclk_mask; 901 uint32_t fclk_mask; 902 uint32_t clock_limit; 903 904 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) { 905 switch (clk_type) { 906 case SMU_MCLK: 907 case SMU_UCLK: 908 clock_limit = smu->smu_table.boot_values.uclk; 909 break; 910 case SMU_FCLK: 911 clock_limit = smu->smu_table.boot_values.fclk; 912 break; 913 case SMU_GFXCLK: 914 case SMU_SCLK: 915 clock_limit = smu->smu_table.boot_values.gfxclk; 916 break; 917 case SMU_SOCCLK: 918 clock_limit = smu->smu_table.boot_values.socclk; 919 break; 920 case SMU_VCLK: 921 clock_limit = smu->smu_table.boot_values.vclk; 922 break; 923 case SMU_DCLK: 924 clock_limit = smu->smu_table.boot_values.dclk; 925 break; 926 default: 927 clock_limit = 0; 928 break; 929 } 930 931 /* clock in Mhz unit */ 932 if (min) 933 *min = clock_limit / 100; 934 if (max) 935 *max = clock_limit / 100; 936 937 return 0; 938 } 939 if (max) { 940 ret = vangogh_get_profiling_clk_mask(smu, 941 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 942 &vclk_mask, 943 &dclk_mask, 944 &mclk_mask, 945 &fclk_mask, 946 &soc_mask); 947 if (ret) 948 goto failed; 949 950 switch (clk_type) { 951 case SMU_UCLK: 952 case SMU_MCLK: 953 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 954 if (ret) 955 goto failed; 956 break; 957 case SMU_SOCCLK: 958 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 959 if (ret) 960 goto failed; 961 break; 962 case SMU_FCLK: 963 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max); 964 if (ret) 965 goto failed; 966 break; 967 case SMU_VCLK: 968 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max); 969 if (ret) 970 goto failed; 971 break; 972 case SMU_DCLK: 973 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max); 974 if (ret) 975 goto failed; 976 break; 977 default: 978 ret = -EINVAL; 979 goto failed; 980 } 981 } 982 if (min) { 983 ret = vangogh_get_profiling_clk_mask(smu, 984 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK, 985 NULL, 986 NULL, 987 &mclk_mask, 988 &fclk_mask, 989 &soc_mask); 990 if (ret) 991 goto failed; 992 993 vclk_mask = dclk_mask = 0; 994 995 switch (clk_type) { 996 case SMU_UCLK: 997 case SMU_MCLK: 998 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min); 999 if (ret) 1000 goto failed; 1001 break; 1002 case SMU_SOCCLK: 1003 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min); 1004 if (ret) 1005 goto failed; 1006 break; 1007 case SMU_FCLK: 1008 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min); 1009 if (ret) 1010 goto failed; 1011 break; 1012 case SMU_VCLK: 1013 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min); 1014 if (ret) 1015 goto failed; 1016 break; 1017 case SMU_DCLK: 1018 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min); 1019 if (ret) 1020 goto failed; 1021 break; 1022 default: 1023 ret = -EINVAL; 1024 goto failed; 1025 } 1026 } 1027 failed: 1028 return ret; 1029 } 1030 1031 static int vangogh_get_power_profile_mode(struct smu_context *smu, 1032 char *buf) 1033 { 1034 uint32_t i, size = 0; 1035 int16_t workload_type = 0; 1036 1037 if (!buf) 1038 return -EINVAL; 1039 1040 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 1041 /* 1042 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1043 * Not all profile modes are supported on vangogh. 1044 */ 1045 workload_type = smu_cmn_to_asic_specific_index(smu, 1046 CMN2ASIC_MAPPING_WORKLOAD, 1047 i); 1048 1049 if (workload_type < 0) 1050 continue; 1051 1052 size += sysfs_emit_at(buf, size, "%2d %14s%s\n", 1053 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1054 } 1055 1056 return size; 1057 } 1058 1059 static int vangogh_set_power_profile_mode(struct smu_context *smu, 1060 u32 workload_mask, 1061 long *custom_params, 1062 u32 custom_params_max_idx) 1063 { 1064 u32 backend_workload_mask = 0; 1065 int ret; 1066 1067 smu_cmn_get_backend_workload_mask(smu, workload_mask, 1068 &backend_workload_mask); 1069 1070 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 1071 backend_workload_mask, 1072 NULL); 1073 if (ret) { 1074 dev_err_once(smu->adev->dev, "Fail to set workload mask 0x%08x\n", 1075 workload_mask); 1076 return ret; 1077 } 1078 1079 return ret; 1080 } 1081 1082 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu, 1083 enum smu_clk_type clk_type, 1084 uint32_t min, 1085 uint32_t max, 1086 bool automatic) 1087 { 1088 int ret = 0; 1089 1090 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) 1091 return 0; 1092 1093 switch (clk_type) { 1094 case SMU_GFXCLK: 1095 case SMU_SCLK: 1096 ret = smu_cmn_send_smc_msg_with_param(smu, 1097 SMU_MSG_SetHardMinGfxClk, 1098 min, NULL); 1099 if (ret) 1100 return ret; 1101 1102 ret = smu_cmn_send_smc_msg_with_param(smu, 1103 SMU_MSG_SetSoftMaxGfxClk, 1104 max, NULL); 1105 if (ret) 1106 return ret; 1107 break; 1108 case SMU_FCLK: 1109 ret = smu_cmn_send_smc_msg_with_param(smu, 1110 SMU_MSG_SetHardMinFclkByFreq, 1111 min, NULL); 1112 if (ret) 1113 return ret; 1114 1115 ret = smu_cmn_send_smc_msg_with_param(smu, 1116 SMU_MSG_SetSoftMaxFclkByFreq, 1117 max, NULL); 1118 if (ret) 1119 return ret; 1120 break; 1121 case SMU_SOCCLK: 1122 ret = smu_cmn_send_smc_msg_with_param(smu, 1123 SMU_MSG_SetHardMinSocclkByFreq, 1124 min, NULL); 1125 if (ret) 1126 return ret; 1127 1128 ret = smu_cmn_send_smc_msg_with_param(smu, 1129 SMU_MSG_SetSoftMaxSocclkByFreq, 1130 max, NULL); 1131 if (ret) 1132 return ret; 1133 break; 1134 case SMU_VCLK: 1135 ret = smu_cmn_send_smc_msg_with_param(smu, 1136 SMU_MSG_SetHardMinVcn, 1137 min << 16, NULL); 1138 if (ret) 1139 return ret; 1140 ret = smu_cmn_send_smc_msg_with_param(smu, 1141 SMU_MSG_SetSoftMaxVcn, 1142 max << 16, NULL); 1143 if (ret) 1144 return ret; 1145 break; 1146 case SMU_DCLK: 1147 ret = smu_cmn_send_smc_msg_with_param(smu, 1148 SMU_MSG_SetHardMinVcn, 1149 min, NULL); 1150 if (ret) 1151 return ret; 1152 ret = smu_cmn_send_smc_msg_with_param(smu, 1153 SMU_MSG_SetSoftMaxVcn, 1154 max, NULL); 1155 if (ret) 1156 return ret; 1157 break; 1158 default: 1159 return -EINVAL; 1160 } 1161 1162 return ret; 1163 } 1164 1165 static int vangogh_force_clk_levels(struct smu_context *smu, 1166 enum smu_clk_type clk_type, uint32_t mask) 1167 { 1168 uint32_t soft_min_level = 0, soft_max_level = 0; 1169 uint32_t min_freq = 0, max_freq = 0; 1170 int ret = 0 ; 1171 1172 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1173 soft_max_level = mask ? (fls(mask) - 1) : 0; 1174 1175 switch (clk_type) { 1176 case SMU_SOCCLK: 1177 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 1178 soft_min_level, &min_freq); 1179 if (ret) 1180 return ret; 1181 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 1182 soft_max_level, &max_freq); 1183 if (ret) 1184 return ret; 1185 ret = smu_cmn_send_smc_msg_with_param(smu, 1186 SMU_MSG_SetSoftMaxSocclkByFreq, 1187 max_freq, NULL); 1188 if (ret) 1189 return ret; 1190 ret = smu_cmn_send_smc_msg_with_param(smu, 1191 SMU_MSG_SetHardMinSocclkByFreq, 1192 min_freq, NULL); 1193 if (ret) 1194 return ret; 1195 break; 1196 case SMU_FCLK: 1197 ret = vangogh_get_dpm_clk_limited(smu, 1198 clk_type, soft_min_level, &min_freq); 1199 if (ret) 1200 return ret; 1201 ret = vangogh_get_dpm_clk_limited(smu, 1202 clk_type, soft_max_level, &max_freq); 1203 if (ret) 1204 return ret; 1205 ret = smu_cmn_send_smc_msg_with_param(smu, 1206 SMU_MSG_SetSoftMaxFclkByFreq, 1207 max_freq, NULL); 1208 if (ret) 1209 return ret; 1210 ret = smu_cmn_send_smc_msg_with_param(smu, 1211 SMU_MSG_SetHardMinFclkByFreq, 1212 min_freq, NULL); 1213 if (ret) 1214 return ret; 1215 break; 1216 case SMU_VCLK: 1217 ret = vangogh_get_dpm_clk_limited(smu, 1218 clk_type, soft_min_level, &min_freq); 1219 if (ret) 1220 return ret; 1221 1222 ret = vangogh_get_dpm_clk_limited(smu, 1223 clk_type, soft_max_level, &max_freq); 1224 if (ret) 1225 return ret; 1226 1227 1228 ret = smu_cmn_send_smc_msg_with_param(smu, 1229 SMU_MSG_SetHardMinVcn, 1230 min_freq << 16, NULL); 1231 if (ret) 1232 return ret; 1233 1234 ret = smu_cmn_send_smc_msg_with_param(smu, 1235 SMU_MSG_SetSoftMaxVcn, 1236 max_freq << 16, NULL); 1237 if (ret) 1238 return ret; 1239 1240 break; 1241 case SMU_DCLK: 1242 ret = vangogh_get_dpm_clk_limited(smu, 1243 clk_type, soft_min_level, &min_freq); 1244 if (ret) 1245 return ret; 1246 1247 ret = vangogh_get_dpm_clk_limited(smu, 1248 clk_type, soft_max_level, &max_freq); 1249 if (ret) 1250 return ret; 1251 1252 ret = smu_cmn_send_smc_msg_with_param(smu, 1253 SMU_MSG_SetHardMinVcn, 1254 min_freq, NULL); 1255 if (ret) 1256 return ret; 1257 1258 ret = smu_cmn_send_smc_msg_with_param(smu, 1259 SMU_MSG_SetSoftMaxVcn, 1260 max_freq, NULL); 1261 if (ret) 1262 return ret; 1263 1264 break; 1265 default: 1266 break; 1267 } 1268 1269 return ret; 1270 } 1271 1272 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest) 1273 { 1274 int ret = 0, i = 0; 1275 uint32_t min_freq, max_freq, force_freq; 1276 enum smu_clk_type clk_type; 1277 1278 enum smu_clk_type clks[] = { 1279 SMU_SOCCLK, 1280 SMU_VCLK, 1281 SMU_DCLK, 1282 SMU_FCLK, 1283 }; 1284 1285 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1286 clk_type = clks[i]; 1287 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1288 if (ret) 1289 return ret; 1290 1291 force_freq = highest ? max_freq : min_freq; 1292 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq, false); 1293 if (ret) 1294 return ret; 1295 } 1296 1297 return ret; 1298 } 1299 1300 static int vangogh_unforce_dpm_levels(struct smu_context *smu) 1301 { 1302 int ret = 0, i = 0; 1303 uint32_t min_freq, max_freq; 1304 enum smu_clk_type clk_type; 1305 1306 struct clk_feature_map { 1307 enum smu_clk_type clk_type; 1308 uint32_t feature; 1309 } clk_feature_map[] = { 1310 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT}, 1311 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 1312 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT}, 1313 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT}, 1314 }; 1315 1316 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 1317 1318 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 1319 continue; 1320 1321 clk_type = clk_feature_map[i].clk_type; 1322 1323 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1324 1325 if (ret) 1326 return ret; 1327 1328 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false); 1329 1330 if (ret) 1331 return ret; 1332 } 1333 1334 return ret; 1335 } 1336 1337 static int vangogh_set_peak_clock_by_device(struct smu_context *smu) 1338 { 1339 int ret = 0; 1340 uint32_t socclk_freq = 0, fclk_freq = 0; 1341 uint32_t vclk_freq = 0, dclk_freq = 0; 1342 1343 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq); 1344 if (ret) 1345 return ret; 1346 1347 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq, false); 1348 if (ret) 1349 return ret; 1350 1351 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq); 1352 if (ret) 1353 return ret; 1354 1355 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq, false); 1356 if (ret) 1357 return ret; 1358 1359 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq); 1360 if (ret) 1361 return ret; 1362 1363 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq, false); 1364 if (ret) 1365 return ret; 1366 1367 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq); 1368 if (ret) 1369 return ret; 1370 1371 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq, false); 1372 if (ret) 1373 return ret; 1374 1375 return ret; 1376 } 1377 1378 static int vangogh_set_performance_level(struct smu_context *smu, 1379 enum amd_dpm_forced_level level) 1380 { 1381 int ret = 0, i; 1382 uint32_t soc_mask, mclk_mask, fclk_mask; 1383 uint32_t vclk_mask = 0, dclk_mask = 0; 1384 1385 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1386 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1387 1388 switch (level) { 1389 case AMD_DPM_FORCED_LEVEL_HIGH: 1390 smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq; 1391 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1392 1393 1394 ret = vangogh_force_dpm_limit_value(smu, true); 1395 if (ret) 1396 return ret; 1397 break; 1398 case AMD_DPM_FORCED_LEVEL_LOW: 1399 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1400 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq; 1401 1402 ret = vangogh_force_dpm_limit_value(smu, false); 1403 if (ret) 1404 return ret; 1405 break; 1406 case AMD_DPM_FORCED_LEVEL_AUTO: 1407 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1408 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1409 1410 ret = vangogh_unforce_dpm_levels(smu); 1411 if (ret) 1412 return ret; 1413 break; 1414 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1415 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK; 1416 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK; 1417 1418 ret = vangogh_get_profiling_clk_mask(smu, level, 1419 &vclk_mask, 1420 &dclk_mask, 1421 &mclk_mask, 1422 &fclk_mask, 1423 &soc_mask); 1424 if (ret) 1425 return ret; 1426 1427 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1428 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 1429 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask); 1430 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask); 1431 break; 1432 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1433 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1434 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq; 1435 break; 1436 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1437 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1438 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1439 1440 ret = vangogh_get_profiling_clk_mask(smu, level, 1441 NULL, 1442 NULL, 1443 &mclk_mask, 1444 &fclk_mask, 1445 NULL); 1446 if (ret) 1447 return ret; 1448 1449 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1450 break; 1451 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1452 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK; 1453 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK; 1454 1455 ret = vangogh_set_peak_clock_by_device(smu); 1456 if (ret) 1457 return ret; 1458 break; 1459 case AMD_DPM_FORCED_LEVEL_MANUAL: 1460 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1461 default: 1462 return 0; 1463 } 1464 1465 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1466 smu->gfx_actual_hard_min_freq, NULL); 1467 if (ret) 1468 return ret; 1469 1470 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1471 smu->gfx_actual_soft_max_freq, NULL); 1472 if (ret) 1473 return ret; 1474 1475 if (smu->adev->pm.fw_version >= 0x43f1b00) { 1476 for (i = 0; i < smu->cpu_core_num; i++) { 1477 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 1478 ((i << 20) 1479 | smu->cpu_actual_soft_min_freq), 1480 NULL); 1481 if (ret) 1482 return ret; 1483 1484 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 1485 ((i << 20) 1486 | smu->cpu_actual_soft_max_freq), 1487 NULL); 1488 if (ret) 1489 return ret; 1490 } 1491 } 1492 1493 return ret; 1494 } 1495 1496 static int vangogh_read_sensor(struct smu_context *smu, 1497 enum amd_pp_sensors sensor, 1498 void *data, uint32_t *size) 1499 { 1500 int ret = 0; 1501 1502 if (!data || !size) 1503 return -EINVAL; 1504 1505 switch (sensor) { 1506 case AMDGPU_PP_SENSOR_GPU_LOAD: 1507 ret = vangogh_common_get_smu_metrics_data(smu, 1508 METRICS_AVERAGE_GFXACTIVITY, 1509 (uint32_t *)data); 1510 *size = 4; 1511 break; 1512 case AMDGPU_PP_SENSOR_VCN_LOAD: 1513 ret = vangogh_common_get_smu_metrics_data(smu, 1514 METRICS_AVERAGE_VCNACTIVITY, 1515 (uint32_t *)data); 1516 *size = 4; 1517 break; 1518 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 1519 ret = vangogh_common_get_smu_metrics_data(smu, 1520 METRICS_AVERAGE_SOCKETPOWER, 1521 (uint32_t *)data); 1522 *size = 4; 1523 break; 1524 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 1525 ret = vangogh_common_get_smu_metrics_data(smu, 1526 METRICS_CURR_SOCKETPOWER, 1527 (uint32_t *)data); 1528 *size = 4; 1529 break; 1530 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1531 ret = vangogh_common_get_smu_metrics_data(smu, 1532 METRICS_TEMPERATURE_EDGE, 1533 (uint32_t *)data); 1534 *size = 4; 1535 break; 1536 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1537 ret = vangogh_common_get_smu_metrics_data(smu, 1538 METRICS_TEMPERATURE_HOTSPOT, 1539 (uint32_t *)data); 1540 *size = 4; 1541 break; 1542 case AMDGPU_PP_SENSOR_GFX_MCLK: 1543 ret = vangogh_common_get_smu_metrics_data(smu, 1544 METRICS_CURR_UCLK, 1545 (uint32_t *)data); 1546 *(uint32_t *)data *= 100; 1547 *size = 4; 1548 break; 1549 case AMDGPU_PP_SENSOR_GFX_SCLK: 1550 ret = vangogh_common_get_smu_metrics_data(smu, 1551 METRICS_CURR_GFXCLK, 1552 (uint32_t *)data); 1553 *(uint32_t *)data *= 100; 1554 *size = 4; 1555 break; 1556 case AMDGPU_PP_SENSOR_VDDGFX: 1557 ret = vangogh_common_get_smu_metrics_data(smu, 1558 METRICS_VOLTAGE_VDDGFX, 1559 (uint32_t *)data); 1560 *size = 4; 1561 break; 1562 case AMDGPU_PP_SENSOR_VDDNB: 1563 ret = vangogh_common_get_smu_metrics_data(smu, 1564 METRICS_VOLTAGE_VDDSOC, 1565 (uint32_t *)data); 1566 *size = 4; 1567 break; 1568 case AMDGPU_PP_SENSOR_CPU_CLK: 1569 ret = vangogh_common_get_smu_metrics_data(smu, 1570 METRICS_AVERAGE_CPUCLK, 1571 (uint32_t *)data); 1572 *size = smu->cpu_core_num * sizeof(uint16_t); 1573 break; 1574 default: 1575 ret = -EOPNOTSUPP; 1576 break; 1577 } 1578 1579 return ret; 1580 } 1581 1582 static int vangogh_get_apu_thermal_limit(struct smu_context *smu, uint32_t *limit) 1583 { 1584 return smu_cmn_send_smc_msg_with_param(smu, 1585 SMU_MSG_GetThermalLimit, 1586 0, limit); 1587 } 1588 1589 static int vangogh_set_apu_thermal_limit(struct smu_context *smu, uint32_t limit) 1590 { 1591 return smu_cmn_send_smc_msg_with_param(smu, 1592 SMU_MSG_SetReducedThermalLimit, 1593 limit, NULL); 1594 } 1595 1596 1597 static int vangogh_set_watermarks_table(struct smu_context *smu, 1598 struct pp_smu_wm_range_sets *clock_ranges) 1599 { 1600 int i; 1601 int ret = 0; 1602 Watermarks_t *table = smu->smu_table.watermarks_table; 1603 1604 if (!table || !clock_ranges) 1605 return -EINVAL; 1606 1607 if (clock_ranges) { 1608 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1609 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1610 return -EINVAL; 1611 1612 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1613 table->WatermarkRow[WM_DCFCLK][i].MinClock = 1614 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1615 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1616 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1617 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1618 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1619 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1620 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1621 1622 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1623 clock_ranges->reader_wm_sets[i].wm_inst; 1624 } 1625 1626 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1627 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1628 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1629 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1630 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1631 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1632 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1633 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1634 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1635 1636 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1637 clock_ranges->writer_wm_sets[i].wm_inst; 1638 } 1639 1640 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1641 } 1642 1643 /* pass data to smu controller */ 1644 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1645 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1646 ret = smu_cmn_write_watermarks_table(smu); 1647 if (ret) { 1648 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1649 return ret; 1650 } 1651 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1652 } 1653 1654 return 0; 1655 } 1656 1657 static ssize_t vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context *smu, 1658 void **table) 1659 { 1660 struct smu_table_context *smu_table = &smu->smu_table; 1661 struct gpu_metrics_v2_3 *gpu_metrics = 1662 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table; 1663 SmuMetrics_legacy_t metrics; 1664 int ret = 0; 1665 1666 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1667 if (ret) 1668 return ret; 1669 1670 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3); 1671 1672 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1673 gpu_metrics->temperature_soc = metrics.SocTemperature; 1674 memcpy(&gpu_metrics->temperature_core[0], 1675 &metrics.CoreTemperature[0], 1676 sizeof(uint16_t) * 4); 1677 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1678 1679 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 1680 gpu_metrics->average_mm_activity = metrics.UvdActivity; 1681 1682 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1683 gpu_metrics->average_cpu_power = metrics.Power[0]; 1684 gpu_metrics->average_soc_power = metrics.Power[1]; 1685 gpu_metrics->average_gfx_power = metrics.Power[2]; 1686 memcpy(&gpu_metrics->average_core_power[0], 1687 &metrics.CorePower[0], 1688 sizeof(uint16_t) * 4); 1689 1690 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 1691 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 1692 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 1693 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 1694 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 1695 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 1696 1697 memcpy(&gpu_metrics->current_coreclk[0], 1698 &metrics.CoreFrequency[0], 1699 sizeof(uint16_t) * 4); 1700 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1701 1702 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1703 gpu_metrics->indep_throttle_status = 1704 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1705 vangogh_throttler_map); 1706 1707 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1708 1709 *table = (void *)gpu_metrics; 1710 1711 return sizeof(struct gpu_metrics_v2_3); 1712 } 1713 1714 static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu, 1715 void **table) 1716 { 1717 struct smu_table_context *smu_table = &smu->smu_table; 1718 struct gpu_metrics_v2_2 *gpu_metrics = 1719 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; 1720 SmuMetrics_legacy_t metrics; 1721 int ret = 0; 1722 1723 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1724 if (ret) 1725 return ret; 1726 1727 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); 1728 1729 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1730 gpu_metrics->temperature_soc = metrics.SocTemperature; 1731 memcpy(&gpu_metrics->temperature_core[0], 1732 &metrics.CoreTemperature[0], 1733 sizeof(uint16_t) * 4); 1734 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1735 1736 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 1737 gpu_metrics->average_mm_activity = metrics.UvdActivity; 1738 1739 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1740 gpu_metrics->average_cpu_power = metrics.Power[0]; 1741 gpu_metrics->average_soc_power = metrics.Power[1]; 1742 gpu_metrics->average_gfx_power = metrics.Power[2]; 1743 memcpy(&gpu_metrics->average_core_power[0], 1744 &metrics.CorePower[0], 1745 sizeof(uint16_t) * 4); 1746 1747 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 1748 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 1749 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 1750 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 1751 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 1752 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 1753 1754 memcpy(&gpu_metrics->current_coreclk[0], 1755 &metrics.CoreFrequency[0], 1756 sizeof(uint16_t) * 4); 1757 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1758 1759 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1760 gpu_metrics->indep_throttle_status = 1761 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1762 vangogh_throttler_map); 1763 1764 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1765 1766 *table = (void *)gpu_metrics; 1767 1768 return sizeof(struct gpu_metrics_v2_2); 1769 } 1770 1771 static ssize_t vangogh_get_gpu_metrics_v2_3(struct smu_context *smu, 1772 void **table) 1773 { 1774 struct smu_table_context *smu_table = &smu->smu_table; 1775 struct gpu_metrics_v2_3 *gpu_metrics = 1776 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table; 1777 SmuMetrics_t metrics; 1778 int ret = 0; 1779 1780 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1781 if (ret) 1782 return ret; 1783 1784 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3); 1785 1786 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 1787 gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1788 memcpy(&gpu_metrics->temperature_core[0], 1789 &metrics.Current.CoreTemperature[0], 1790 sizeof(uint16_t) * 4); 1791 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1792 1793 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature; 1794 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature; 1795 memcpy(&gpu_metrics->average_temperature_core[0], 1796 &metrics.Average.CoreTemperature[0], 1797 sizeof(uint16_t) * 4); 1798 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0]; 1799 1800 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity; 1801 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity; 1802 1803 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower; 1804 gpu_metrics->average_cpu_power = metrics.Current.Power[0]; 1805 gpu_metrics->average_soc_power = metrics.Current.Power[1]; 1806 gpu_metrics->average_gfx_power = metrics.Current.Power[2]; 1807 memcpy(&gpu_metrics->average_core_power[0], 1808 &metrics.Average.CorePower[0], 1809 sizeof(uint16_t) * 4); 1810 1811 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 1812 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 1813 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 1814 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 1815 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 1816 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 1817 1818 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 1819 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 1820 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 1821 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 1822 gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 1823 gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 1824 1825 memcpy(&gpu_metrics->current_coreclk[0], 1826 &metrics.Current.CoreFrequency[0], 1827 sizeof(uint16_t) * 4); 1828 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 1829 1830 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 1831 gpu_metrics->indep_throttle_status = 1832 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, 1833 vangogh_throttler_map); 1834 1835 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1836 1837 *table = (void *)gpu_metrics; 1838 1839 return sizeof(struct gpu_metrics_v2_3); 1840 } 1841 1842 static ssize_t vangogh_get_gpu_metrics_v2_4(struct smu_context *smu, 1843 void **table) 1844 { 1845 SmuMetrics_t metrics; 1846 struct smu_table_context *smu_table = &smu->smu_table; 1847 struct gpu_metrics_v2_4 *gpu_metrics = 1848 (struct gpu_metrics_v2_4 *)smu_table->gpu_metrics_table; 1849 int ret = 0; 1850 1851 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1852 if (ret) 1853 return ret; 1854 1855 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 4); 1856 1857 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 1858 gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1859 memcpy(&gpu_metrics->temperature_core[0], 1860 &metrics.Current.CoreTemperature[0], 1861 sizeof(uint16_t) * 4); 1862 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1863 1864 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature; 1865 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature; 1866 memcpy(&gpu_metrics->average_temperature_core[0], 1867 &metrics.Average.CoreTemperature[0], 1868 sizeof(uint16_t) * 4); 1869 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0]; 1870 1871 gpu_metrics->average_gfx_activity = metrics.Average.GfxActivity; 1872 gpu_metrics->average_mm_activity = metrics.Average.UvdActivity; 1873 1874 gpu_metrics->average_socket_power = metrics.Average.CurrentSocketPower; 1875 gpu_metrics->average_cpu_power = metrics.Average.Power[0]; 1876 gpu_metrics->average_soc_power = metrics.Average.Power[1]; 1877 gpu_metrics->average_gfx_power = metrics.Average.Power[2]; 1878 1879 gpu_metrics->average_cpu_voltage = metrics.Average.Voltage[0]; 1880 gpu_metrics->average_soc_voltage = metrics.Average.Voltage[1]; 1881 gpu_metrics->average_gfx_voltage = metrics.Average.Voltage[2]; 1882 1883 gpu_metrics->average_cpu_current = metrics.Average.Current[0]; 1884 gpu_metrics->average_soc_current = metrics.Average.Current[1]; 1885 gpu_metrics->average_gfx_current = metrics.Average.Current[2]; 1886 1887 memcpy(&gpu_metrics->average_core_power[0], 1888 &metrics.Average.CorePower[0], 1889 sizeof(uint16_t) * 4); 1890 1891 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 1892 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 1893 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 1894 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 1895 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 1896 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 1897 1898 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 1899 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 1900 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 1901 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 1902 gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 1903 gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 1904 1905 memcpy(&gpu_metrics->current_coreclk[0], 1906 &metrics.Current.CoreFrequency[0], 1907 sizeof(uint16_t) * 4); 1908 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 1909 1910 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 1911 gpu_metrics->indep_throttle_status = 1912 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, 1913 vangogh_throttler_map); 1914 1915 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1916 1917 *table = (void *)gpu_metrics; 1918 1919 return sizeof(struct gpu_metrics_v2_4); 1920 } 1921 1922 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, 1923 void **table) 1924 { 1925 struct smu_table_context *smu_table = &smu->smu_table; 1926 struct gpu_metrics_v2_2 *gpu_metrics = 1927 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; 1928 SmuMetrics_t metrics; 1929 int ret = 0; 1930 1931 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1932 if (ret) 1933 return ret; 1934 1935 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); 1936 1937 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 1938 gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1939 memcpy(&gpu_metrics->temperature_core[0], 1940 &metrics.Current.CoreTemperature[0], 1941 sizeof(uint16_t) * 4); 1942 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1943 1944 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity; 1945 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity; 1946 1947 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower; 1948 gpu_metrics->average_cpu_power = metrics.Current.Power[0]; 1949 gpu_metrics->average_soc_power = metrics.Current.Power[1]; 1950 gpu_metrics->average_gfx_power = metrics.Current.Power[2]; 1951 memcpy(&gpu_metrics->average_core_power[0], 1952 &metrics.Average.CorePower[0], 1953 sizeof(uint16_t) * 4); 1954 1955 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 1956 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 1957 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 1958 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 1959 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 1960 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 1961 1962 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 1963 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 1964 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 1965 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 1966 gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 1967 gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 1968 1969 memcpy(&gpu_metrics->current_coreclk[0], 1970 &metrics.Current.CoreFrequency[0], 1971 sizeof(uint16_t) * 4); 1972 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 1973 1974 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 1975 gpu_metrics->indep_throttle_status = 1976 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, 1977 vangogh_throttler_map); 1978 1979 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1980 1981 *table = (void *)gpu_metrics; 1982 1983 return sizeof(struct gpu_metrics_v2_2); 1984 } 1985 1986 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu, 1987 void **table) 1988 { 1989 uint32_t smu_program; 1990 uint32_t fw_version; 1991 int ret = 0; 1992 1993 smu_program = (smu->smc_fw_version >> 24) & 0xff; 1994 fw_version = smu->smc_fw_version & 0xffffff; 1995 if (smu_program == 6) { 1996 if (fw_version >= 0x3F0800) 1997 ret = vangogh_get_gpu_metrics_v2_4(smu, table); 1998 else 1999 ret = vangogh_get_gpu_metrics_v2_3(smu, table); 2000 2001 } else { 2002 if (smu->smc_fw_version >= 0x043F3E00) { 2003 if (smu->smc_fw_if_version < 0x3) 2004 ret = vangogh_get_legacy_gpu_metrics_v2_3(smu, table); 2005 else 2006 ret = vangogh_get_gpu_metrics_v2_3(smu, table); 2007 } else { 2008 if (smu->smc_fw_if_version < 0x3) 2009 ret = vangogh_get_legacy_gpu_metrics(smu, table); 2010 else 2011 ret = vangogh_get_gpu_metrics(smu, table); 2012 } 2013 } 2014 2015 return ret; 2016 } 2017 2018 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 2019 long input[], uint32_t size) 2020 { 2021 int ret = 0; 2022 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2023 2024 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { 2025 dev_warn(smu->adev->dev, 2026 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n"); 2027 return -EINVAL; 2028 } 2029 2030 switch (type) { 2031 case PP_OD_EDIT_CCLK_VDDC_TABLE: 2032 if (size != 3) { 2033 dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n"); 2034 return -EINVAL; 2035 } 2036 if (input[0] >= smu->cpu_core_num) { 2037 dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n", 2038 smu->cpu_core_num); 2039 } 2040 smu->cpu_core_id_select = input[0]; 2041 if (input[1] == 0) { 2042 if (input[2] < smu->cpu_default_soft_min_freq) { 2043 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 2044 input[2], smu->cpu_default_soft_min_freq); 2045 return -EINVAL; 2046 } 2047 smu->cpu_actual_soft_min_freq = input[2]; 2048 } else if (input[1] == 1) { 2049 if (input[2] > smu->cpu_default_soft_max_freq) { 2050 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 2051 input[2], smu->cpu_default_soft_max_freq); 2052 return -EINVAL; 2053 } 2054 smu->cpu_actual_soft_max_freq = input[2]; 2055 } else { 2056 return -EINVAL; 2057 } 2058 break; 2059 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2060 if (size != 2) { 2061 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2062 return -EINVAL; 2063 } 2064 2065 if (input[0] == 0) { 2066 if (input[1] < smu->gfx_default_hard_min_freq) { 2067 dev_warn(smu->adev->dev, 2068 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 2069 input[1], smu->gfx_default_hard_min_freq); 2070 return -EINVAL; 2071 } 2072 smu->gfx_actual_hard_min_freq = input[1]; 2073 } else if (input[0] == 1) { 2074 if (input[1] > smu->gfx_default_soft_max_freq) { 2075 dev_warn(smu->adev->dev, 2076 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 2077 input[1], smu->gfx_default_soft_max_freq); 2078 return -EINVAL; 2079 } 2080 smu->gfx_actual_soft_max_freq = input[1]; 2081 } else { 2082 return -EINVAL; 2083 } 2084 break; 2085 case PP_OD_RESTORE_DEFAULT_TABLE: 2086 if (size != 0) { 2087 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2088 return -EINVAL; 2089 } else { 2090 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 2091 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 2092 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 2093 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 2094 } 2095 break; 2096 case PP_OD_COMMIT_DPM_TABLE: 2097 if (size != 0) { 2098 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2099 return -EINVAL; 2100 } else { 2101 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 2102 dev_err(smu->adev->dev, 2103 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 2104 smu->gfx_actual_hard_min_freq, 2105 smu->gfx_actual_soft_max_freq); 2106 return -EINVAL; 2107 } 2108 2109 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 2110 smu->gfx_actual_hard_min_freq, NULL); 2111 if (ret) { 2112 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 2113 return ret; 2114 } 2115 2116 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 2117 smu->gfx_actual_soft_max_freq, NULL); 2118 if (ret) { 2119 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 2120 return ret; 2121 } 2122 2123 if (smu->adev->pm.fw_version < 0x43f1b00) { 2124 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n"); 2125 break; 2126 } 2127 2128 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 2129 ((smu->cpu_core_id_select << 20) 2130 | smu->cpu_actual_soft_min_freq), 2131 NULL); 2132 if (ret) { 2133 dev_err(smu->adev->dev, "Set hard min cclk failed!"); 2134 return ret; 2135 } 2136 2137 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 2138 ((smu->cpu_core_id_select << 20) 2139 | smu->cpu_actual_soft_max_freq), 2140 NULL); 2141 if (ret) { 2142 dev_err(smu->adev->dev, "Set soft max cclk failed!"); 2143 return ret; 2144 } 2145 } 2146 break; 2147 default: 2148 return -ENOSYS; 2149 } 2150 2151 return ret; 2152 } 2153 2154 static int vangogh_set_default_dpm_tables(struct smu_context *smu) 2155 { 2156 struct smu_table_context *smu_table = &smu->smu_table; 2157 2158 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); 2159 } 2160 2161 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 2162 { 2163 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 2164 2165 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 2166 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 2167 smu->gfx_actual_hard_min_freq = 0; 2168 smu->gfx_actual_soft_max_freq = 0; 2169 2170 smu->cpu_default_soft_min_freq = 1400; 2171 smu->cpu_default_soft_max_freq = 3500; 2172 smu->cpu_actual_soft_min_freq = 0; 2173 smu->cpu_actual_soft_max_freq = 0; 2174 2175 return 0; 2176 } 2177 2178 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 2179 { 2180 DpmClocks_t *table = smu->smu_table.clocks_table; 2181 int i; 2182 2183 if (!clock_table || !table) 2184 return -EINVAL; 2185 2186 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 2187 clock_table->SocClocks[i].Freq = table->SocClocks[i]; 2188 clock_table->SocClocks[i].Vol = table->SocVoltage[i]; 2189 } 2190 2191 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 2192 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk; 2193 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage; 2194 } 2195 2196 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 2197 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk; 2198 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage; 2199 } 2200 2201 return 0; 2202 } 2203 2204 static int vangogh_notify_rlc_state(struct smu_context *smu, bool en) 2205 { 2206 struct amdgpu_device *adev = smu->adev; 2207 int ret = 0; 2208 2209 if (adev->pm.fw_version >= 0x43f1700 && !en) 2210 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify, 2211 RLC_STATUS_OFF, NULL); 2212 2213 return ret; 2214 } 2215 2216 static int vangogh_post_smu_init(struct smu_context *smu) 2217 { 2218 struct amdgpu_device *adev = smu->adev; 2219 uint32_t tmp; 2220 int ret = 0; 2221 uint8_t aon_bits = 0; 2222 /* Two CUs in one WGP */ 2223 uint32_t req_active_wgps = adev->gfx.cu_info.number/2; 2224 uint32_t total_cu = adev->gfx.config.max_cu_per_sh * 2225 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 2226 2227 /* allow message will be sent after enable message on Vangogh*/ 2228 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 2229 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2230 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL); 2231 if (ret) { 2232 dev_err(adev->dev, "Failed to Enable GfxOff!\n"); 2233 return ret; 2234 } 2235 } else { 2236 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 2237 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n"); 2238 } 2239 2240 /* if all CUs are active, no need to power off any WGPs */ 2241 if (total_cu == adev->gfx.cu_info.number) 2242 return 0; 2243 2244 /* 2245 * Calculate the total bits number of always on WGPs for all SA/SEs in 2246 * RLC_PG_ALWAYS_ON_WGP_MASK. 2247 */ 2248 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK)); 2249 tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK; 2250 2251 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 2252 2253 /* Do not request any WGPs less than set in the AON_WGP_MASK */ 2254 if (aon_bits > req_active_wgps) { 2255 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n"); 2256 return 0; 2257 } else { 2258 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL); 2259 } 2260 } 2261 2262 static int vangogh_mode_reset(struct smu_context *smu, int type) 2263 { 2264 int ret = 0, index = 0; 2265 2266 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 2267 SMU_MSG_GfxDeviceDriverReset); 2268 if (index < 0) 2269 return index == -EACCES ? 0 : index; 2270 2271 mutex_lock(&smu->message_lock); 2272 2273 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type); 2274 2275 mutex_unlock(&smu->message_lock); 2276 2277 mdelay(10); 2278 2279 return ret; 2280 } 2281 2282 static int vangogh_mode2_reset(struct smu_context *smu) 2283 { 2284 return vangogh_mode_reset(smu, SMU_RESET_MODE_2); 2285 } 2286 2287 /** 2288 * vangogh_get_gfxoff_status - Get gfxoff status 2289 * 2290 * @smu: amdgpu_device pointer 2291 * 2292 * Get current gfxoff status 2293 * 2294 * Return: 2295 * * 0 - GFXOFF (default if enabled). 2296 * * 1 - Transition out of GFX State. 2297 * * 2 - Not in GFXOFF. 2298 * * 3 - Transition into GFXOFF. 2299 */ 2300 static u32 vangogh_get_gfxoff_status(struct smu_context *smu) 2301 { 2302 struct amdgpu_device *adev = smu->adev; 2303 u32 reg, gfxoff_status; 2304 2305 reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL); 2306 gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK) 2307 >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT; 2308 2309 return gfxoff_status; 2310 } 2311 2312 static int vangogh_get_power_limit(struct smu_context *smu, 2313 uint32_t *current_power_limit, 2314 uint32_t *default_power_limit, 2315 uint32_t *max_power_limit, 2316 uint32_t *min_power_limit) 2317 { 2318 struct smu_11_5_power_context *power_context = 2319 smu->smu_power.power_context; 2320 uint32_t ppt_limit; 2321 int ret = 0; 2322 2323 if (smu->adev->pm.fw_version < 0x43f1e00) 2324 return ret; 2325 2326 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit); 2327 if (ret) { 2328 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n"); 2329 return ret; 2330 } 2331 /* convert from milliwatt to watt */ 2332 if (current_power_limit) 2333 *current_power_limit = ppt_limit / 1000; 2334 if (default_power_limit) 2335 *default_power_limit = ppt_limit / 1000; 2336 if (max_power_limit) 2337 *max_power_limit = 29; 2338 if (min_power_limit) 2339 *min_power_limit = 0; 2340 2341 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit); 2342 if (ret) { 2343 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n"); 2344 return ret; 2345 } 2346 /* convert from milliwatt to watt */ 2347 power_context->current_fast_ppt_limit = 2348 power_context->default_fast_ppt_limit = ppt_limit / 1000; 2349 power_context->max_fast_ppt_limit = 30; 2350 2351 return ret; 2352 } 2353 2354 static int vangogh_get_ppt_limit(struct smu_context *smu, 2355 uint32_t *ppt_limit, 2356 enum smu_ppt_limit_type type, 2357 enum smu_ppt_limit_level level) 2358 { 2359 struct smu_11_5_power_context *power_context = 2360 smu->smu_power.power_context; 2361 2362 if (!power_context) 2363 return -EOPNOTSUPP; 2364 2365 if (type == SMU_FAST_PPT_LIMIT) { 2366 switch (level) { 2367 case SMU_PPT_LIMIT_MAX: 2368 *ppt_limit = power_context->max_fast_ppt_limit; 2369 break; 2370 case SMU_PPT_LIMIT_CURRENT: 2371 *ppt_limit = power_context->current_fast_ppt_limit; 2372 break; 2373 case SMU_PPT_LIMIT_DEFAULT: 2374 *ppt_limit = power_context->default_fast_ppt_limit; 2375 break; 2376 default: 2377 break; 2378 } 2379 } 2380 2381 return 0; 2382 } 2383 2384 static int vangogh_set_power_limit(struct smu_context *smu, 2385 enum smu_ppt_limit_type limit_type, 2386 uint32_t ppt_limit) 2387 { 2388 struct smu_11_5_power_context *power_context = 2389 smu->smu_power.power_context; 2390 int ret = 0; 2391 2392 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 2393 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 2394 return -EOPNOTSUPP; 2395 } 2396 2397 switch (limit_type) { 2398 case SMU_DEFAULT_PPT_LIMIT: 2399 ret = smu_cmn_send_smc_msg_with_param(smu, 2400 SMU_MSG_SetSlowPPTLimit, 2401 ppt_limit * 1000, /* convert from watt to milliwatt */ 2402 NULL); 2403 if (ret) 2404 return ret; 2405 2406 smu->current_power_limit = ppt_limit; 2407 break; 2408 case SMU_FAST_PPT_LIMIT: 2409 ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24); 2410 if (ppt_limit > power_context->max_fast_ppt_limit) { 2411 dev_err(smu->adev->dev, 2412 "New power limit (%d) is over the max allowed %d\n", 2413 ppt_limit, power_context->max_fast_ppt_limit); 2414 return ret; 2415 } 2416 2417 ret = smu_cmn_send_smc_msg_with_param(smu, 2418 SMU_MSG_SetFastPPTLimit, 2419 ppt_limit * 1000, /* convert from watt to milliwatt */ 2420 NULL); 2421 if (ret) 2422 return ret; 2423 2424 power_context->current_fast_ppt_limit = ppt_limit; 2425 break; 2426 default: 2427 return -EINVAL; 2428 } 2429 2430 return ret; 2431 } 2432 2433 /** 2434 * vangogh_set_gfxoff_residency 2435 * 2436 * @smu: amdgpu_device pointer 2437 * @start: start/stop residency log 2438 * 2439 * This function will be used to log gfxoff residency 2440 * 2441 * 2442 * Returns standard response codes. 2443 */ 2444 static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start) 2445 { 2446 int ret = 0; 2447 u32 residency; 2448 struct amdgpu_device *adev = smu->adev; 2449 2450 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 2451 return 0; 2452 2453 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency, 2454 start, &residency); 2455 if (ret) 2456 return ret; 2457 2458 if (!start) 2459 adev->gfx.gfx_off_residency = residency; 2460 2461 return ret; 2462 } 2463 2464 /** 2465 * vangogh_get_gfxoff_residency 2466 * 2467 * @smu: amdgpu_device pointer 2468 * @residency: placeholder for return value 2469 * 2470 * This function will be used to get gfxoff residency. 2471 * 2472 * Returns standard response codes. 2473 */ 2474 static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency) 2475 { 2476 struct amdgpu_device *adev = smu->adev; 2477 2478 *residency = adev->gfx.gfx_off_residency; 2479 2480 return 0; 2481 } 2482 2483 /** 2484 * vangogh_get_gfxoff_entrycount - get gfxoff entry count 2485 * 2486 * @smu: amdgpu_device pointer 2487 * @entrycount: placeholder for return value 2488 * 2489 * This function will be used to get gfxoff entry count 2490 * 2491 * Returns standard response codes. 2492 */ 2493 static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t *entrycount) 2494 { 2495 int ret = 0, value = 0; 2496 struct amdgpu_device *adev = smu->adev; 2497 2498 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 2499 return 0; 2500 2501 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryCount, &value); 2502 *entrycount = value + adev->gfx.gfx_off_entrycount; 2503 2504 return ret; 2505 } 2506 2507 static const struct pptable_funcs vangogh_ppt_funcs = { 2508 2509 .check_fw_status = smu_v11_0_check_fw_status, 2510 .check_fw_version = smu_v11_0_check_fw_version, 2511 .init_smc_tables = vangogh_init_smc_tables, 2512 .fini_smc_tables = smu_v11_0_fini_smc_tables, 2513 .init_power = smu_v11_0_init_power, 2514 .fini_power = smu_v11_0_fini_power, 2515 .register_irq_handler = smu_v11_0_register_irq_handler, 2516 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 2517 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2518 .send_smc_msg = smu_cmn_send_smc_msg, 2519 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable, 2520 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable, 2521 .is_dpm_running = vangogh_is_dpm_running, 2522 .read_sensor = vangogh_read_sensor, 2523 .get_apu_thermal_limit = vangogh_get_apu_thermal_limit, 2524 .set_apu_thermal_limit = vangogh_set_apu_thermal_limit, 2525 .get_enabled_mask = smu_cmn_get_enabled_mask, 2526 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2527 .set_watermarks_table = vangogh_set_watermarks_table, 2528 .set_driver_table_location = smu_v11_0_set_driver_table_location, 2529 .interrupt_work = smu_v11_0_interrupt_work, 2530 .get_gpu_metrics = vangogh_common_get_gpu_metrics, 2531 .od_edit_dpm_table = vangogh_od_edit_dpm_table, 2532 .print_clk_levels = vangogh_common_print_clk_levels, 2533 .set_default_dpm_table = vangogh_set_default_dpm_tables, 2534 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters, 2535 .notify_rlc_state = vangogh_notify_rlc_state, 2536 .feature_is_enabled = smu_cmn_feature_is_enabled, 2537 .set_power_profile_mode = vangogh_set_power_profile_mode, 2538 .get_power_profile_mode = vangogh_get_power_profile_mode, 2539 .get_dpm_clock_table = vangogh_get_dpm_clock_table, 2540 .force_clk_levels = vangogh_force_clk_levels, 2541 .set_performance_level = vangogh_set_performance_level, 2542 .post_init = vangogh_post_smu_init, 2543 .mode2_reset = vangogh_mode2_reset, 2544 .gfx_off_control = smu_v11_0_gfx_off_control, 2545 .get_gfx_off_status = vangogh_get_gfxoff_status, 2546 .get_gfx_off_entrycount = vangogh_get_gfxoff_entrycount, 2547 .get_gfx_off_residency = vangogh_get_gfxoff_residency, 2548 .set_gfx_off_residency = vangogh_set_gfxoff_residency, 2549 .get_ppt_limit = vangogh_get_ppt_limit, 2550 .get_power_limit = vangogh_get_power_limit, 2551 .set_power_limit = vangogh_set_power_limit, 2552 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 2553 }; 2554 2555 void vangogh_set_ppt_funcs(struct smu_context *smu) 2556 { 2557 smu->ppt_funcs = &vangogh_ppt_funcs; 2558 smu->message_map = vangogh_message_map; 2559 smu->feature_map = vangogh_feature_mask_map; 2560 smu->table_map = vangogh_table_map; 2561 smu->workload_map = vangogh_workload_map; 2562 smu->is_apu = true; 2563 smu_v11_0_set_smu_mailbox_registers(smu); 2564 } 2565