1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include "amdgpu.h" 27 #include "amdgpu_smu.h" 28 #include "smu_v11_0.h" 29 #include "smu11_driver_if_vangogh.h" 30 #include "vangogh_ppt.h" 31 #include "smu_v11_5_ppsmc.h" 32 #include "smu_v11_5_pmfw.h" 33 #include "smu_cmn.h" 34 #include "soc15_common.h" 35 #include "asic_reg/gc/gc_10_3_0_offset.h" 36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h" 37 #include <asm/processor.h> 38 39 /* 40 * DO NOT use these for err/warn/info/debug messages. 41 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 42 * They are more MGPU friendly. 43 */ 44 #undef pr_err 45 #undef pr_warn 46 #undef pr_info 47 #undef pr_debug 48 49 // Registers related to GFXOFF 50 // addressBlock: smuio_smuio_SmuSmuioDec 51 // base address: 0x5a000 52 #define mmSMUIO_GFX_MISC_CNTL 0x00c5 53 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0 54 55 //SMUIO_GFX_MISC_CNTL 56 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0 57 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1 58 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L 59 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L 60 61 #define FEATURE_MASK(feature) (1ULL << feature) 62 #define SMC_DPM_FEATURE ( \ 63 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 64 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 65 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 66 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 67 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 68 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 69 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 70 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 71 FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 72 73 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { 74 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 75 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0), 76 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0), 77 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0), 78 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 79 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 80 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0), 81 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0), 82 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 83 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 84 MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0), 85 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0), 86 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0), 87 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0), 88 MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0), 89 MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0), 90 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0), 91 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0), 92 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0), 93 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 94 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0), 95 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0), 96 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0), 97 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0), 98 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0), 99 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0), 100 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0), 101 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0), 102 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0), 103 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0), 104 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0), 105 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0), 106 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0), 107 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0), 108 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 109 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 110 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0), 111 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0), 112 MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0), 113 MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0), 114 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 115 MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0), 116 MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0), 117 MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0), 118 MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0), 119 MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0), 120 MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0), 121 MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0), 122 MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0), 123 MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0), 124 MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0), 125 MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0), 126 MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0), 127 MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0), 128 MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0), 129 MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0), 130 MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0), 131 MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0), 132 MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0), 133 MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0), 134 MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0), 135 MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0), 136 MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0), 137 MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0), 138 MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0), 139 MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0), 140 MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0), 141 MSG_MAP(GetGfxOffStatus, PPSMC_MSG_GetGfxOffStatus, 0), 142 MSG_MAP(GetGfxOffEntryCount, PPSMC_MSG_GetGfxOffEntryCount, 0), 143 MSG_MAP(LogGfxOffResidency, PPSMC_MSG_LogGfxOffResidency, 0), 144 }; 145 146 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { 147 FEA_MAP(PPT), 148 FEA_MAP(TDC), 149 FEA_MAP(THERMAL), 150 FEA_MAP(DS_GFXCLK), 151 FEA_MAP(DS_SOCCLK), 152 FEA_MAP(DS_LCLK), 153 FEA_MAP(DS_FCLK), 154 FEA_MAP(DS_MP1CLK), 155 FEA_MAP(DS_MP0CLK), 156 FEA_MAP(ATHUB_PG), 157 FEA_MAP(CCLK_DPM), 158 FEA_MAP(FAN_CONTROLLER), 159 FEA_MAP(ULV), 160 FEA_MAP(VCN_DPM), 161 FEA_MAP(LCLK_DPM), 162 FEA_MAP(SHUBCLK_DPM), 163 FEA_MAP(DCFCLK_DPM), 164 FEA_MAP(DS_DCFCLK), 165 FEA_MAP(S0I2), 166 FEA_MAP(SMU_LOW_POWER), 167 FEA_MAP(GFX_DEM), 168 FEA_MAP(PSI), 169 FEA_MAP(PROCHOT), 170 FEA_MAP(CPUOFF), 171 FEA_MAP(STAPM), 172 FEA_MAP(S0I3), 173 FEA_MAP(DF_CSTATES), 174 FEA_MAP(PERF_LIMIT), 175 FEA_MAP(CORE_DLDO), 176 FEA_MAP(RSMU_LOW_POWER), 177 FEA_MAP(SMN_LOW_POWER), 178 FEA_MAP(THM_LOW_POWER), 179 FEA_MAP(SMUIO_LOW_POWER), 180 FEA_MAP(MP1_LOW_POWER), 181 FEA_MAP(DS_VCN), 182 FEA_MAP(CPPC), 183 FEA_MAP(OS_CSTATES), 184 FEA_MAP(ISP_DPM), 185 FEA_MAP(A55_DPM), 186 FEA_MAP(CVIP_DSP_DPM), 187 FEA_MAP(MSMU_LOW_POWER), 188 FEA_MAP_REVERSE(SOCCLK), 189 FEA_MAP_REVERSE(FCLK), 190 FEA_MAP_HALF_REVERSE(GFX), 191 }; 192 193 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = { 194 TAB_MAP_VALID(WATERMARKS), 195 TAB_MAP_VALID(SMU_METRICS), 196 TAB_MAP_VALID(CUSTOM_DPM), 197 TAB_MAP_VALID(DPMCLOCKS), 198 }; 199 200 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 201 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 202 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 203 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 204 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CAPPED, WORKLOAD_PPLIB_CAPPED_BIT), 207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_UNCAPPED, WORKLOAD_PPLIB_UNCAPPED_BIT), 208 }; 209 210 static const uint8_t vangogh_throttler_map[] = { 211 [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT), 212 [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT), 213 [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT), 214 [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT), 215 [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT), 216 [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT), 217 [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT), 218 [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT), 219 [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT), 220 [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT), 221 [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT), 222 }; 223 224 static int vangogh_tables_init(struct smu_context *smu) 225 { 226 struct smu_table_context *smu_table = &smu->smu_table; 227 struct smu_table *tables = smu_table->tables; 228 229 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 230 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 231 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 232 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 233 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 234 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 235 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t), 236 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 237 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, max(sizeof(SmuMetrics_t), sizeof(SmuMetrics_legacy_t)), 238 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 239 240 smu_table->metrics_table = kzalloc(max(sizeof(SmuMetrics_t), sizeof(SmuMetrics_legacy_t)), GFP_KERNEL); 241 if (!smu_table->metrics_table) 242 goto err0_out; 243 smu_table->metrics_time = 0; 244 245 smu_table->gpu_metrics_table_size = max(sizeof(struct gpu_metrics_v2_3), sizeof(struct gpu_metrics_v2_2)); 246 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 247 if (!smu_table->gpu_metrics_table) 248 goto err1_out; 249 250 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 251 if (!smu_table->watermarks_table) 252 goto err2_out; 253 254 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 255 if (!smu_table->clocks_table) 256 goto err3_out; 257 258 return 0; 259 260 err3_out: 261 kfree(smu_table->watermarks_table); 262 err2_out: 263 kfree(smu_table->gpu_metrics_table); 264 err1_out: 265 kfree(smu_table->metrics_table); 266 err0_out: 267 return -ENOMEM; 268 } 269 270 static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu, 271 MetricsMember_t member, 272 uint32_t *value) 273 { 274 struct smu_table_context *smu_table = &smu->smu_table; 275 SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table; 276 int ret = 0; 277 278 ret = smu_cmn_get_metrics_table(smu, 279 NULL, 280 false); 281 if (ret) 282 return ret; 283 284 switch (member) { 285 case METRICS_CURR_GFXCLK: 286 *value = metrics->GfxclkFrequency; 287 break; 288 case METRICS_AVERAGE_SOCCLK: 289 *value = metrics->SocclkFrequency; 290 break; 291 case METRICS_AVERAGE_VCLK: 292 *value = metrics->VclkFrequency; 293 break; 294 case METRICS_AVERAGE_DCLK: 295 *value = metrics->DclkFrequency; 296 break; 297 case METRICS_CURR_UCLK: 298 *value = metrics->MemclkFrequency; 299 break; 300 case METRICS_AVERAGE_GFXACTIVITY: 301 *value = metrics->GfxActivity / 100; 302 break; 303 case METRICS_AVERAGE_VCNACTIVITY: 304 *value = metrics->UvdActivity / 100; 305 break; 306 case METRICS_AVERAGE_SOCKETPOWER: 307 *value = (metrics->CurrentSocketPower << 8) / 308 1000 ; 309 break; 310 case METRICS_TEMPERATURE_EDGE: 311 *value = metrics->GfxTemperature / 100 * 312 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 313 break; 314 case METRICS_TEMPERATURE_HOTSPOT: 315 *value = metrics->SocTemperature / 100 * 316 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 317 break; 318 case METRICS_THROTTLER_STATUS: 319 *value = metrics->ThrottlerStatus; 320 break; 321 case METRICS_VOLTAGE_VDDGFX: 322 *value = metrics->Voltage[2]; 323 break; 324 case METRICS_VOLTAGE_VDDSOC: 325 *value = metrics->Voltage[1]; 326 break; 327 case METRICS_AVERAGE_CPUCLK: 328 memcpy(value, &metrics->CoreFrequency[0], 329 smu->cpu_core_num * sizeof(uint16_t)); 330 break; 331 default: 332 *value = UINT_MAX; 333 break; 334 } 335 336 return ret; 337 } 338 339 static int vangogh_get_smu_metrics_data(struct smu_context *smu, 340 MetricsMember_t member, 341 uint32_t *value) 342 { 343 struct smu_table_context *smu_table = &smu->smu_table; 344 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 345 int ret = 0; 346 347 ret = smu_cmn_get_metrics_table(smu, 348 NULL, 349 false); 350 if (ret) 351 return ret; 352 353 switch (member) { 354 case METRICS_CURR_GFXCLK: 355 *value = metrics->Current.GfxclkFrequency; 356 break; 357 case METRICS_AVERAGE_SOCCLK: 358 *value = metrics->Current.SocclkFrequency; 359 break; 360 case METRICS_AVERAGE_VCLK: 361 *value = metrics->Current.VclkFrequency; 362 break; 363 case METRICS_AVERAGE_DCLK: 364 *value = metrics->Current.DclkFrequency; 365 break; 366 case METRICS_CURR_UCLK: 367 *value = metrics->Current.MemclkFrequency; 368 break; 369 case METRICS_AVERAGE_GFXACTIVITY: 370 *value = metrics->Current.GfxActivity; 371 break; 372 case METRICS_AVERAGE_VCNACTIVITY: 373 *value = metrics->Current.UvdActivity; 374 break; 375 case METRICS_AVERAGE_SOCKETPOWER: 376 *value = (metrics->Average.CurrentSocketPower << 8) / 377 1000; 378 break; 379 case METRICS_CURR_SOCKETPOWER: 380 *value = (metrics->Current.CurrentSocketPower << 8) / 381 1000; 382 break; 383 case METRICS_TEMPERATURE_EDGE: 384 *value = metrics->Current.GfxTemperature / 100 * 385 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 386 break; 387 case METRICS_TEMPERATURE_HOTSPOT: 388 *value = metrics->Current.SocTemperature / 100 * 389 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 390 break; 391 case METRICS_THROTTLER_STATUS: 392 *value = metrics->Current.ThrottlerStatus; 393 break; 394 case METRICS_VOLTAGE_VDDGFX: 395 *value = metrics->Current.Voltage[2]; 396 break; 397 case METRICS_VOLTAGE_VDDSOC: 398 *value = metrics->Current.Voltage[1]; 399 break; 400 case METRICS_AVERAGE_CPUCLK: 401 memcpy(value, &metrics->Current.CoreFrequency[0], 402 smu->cpu_core_num * sizeof(uint16_t)); 403 break; 404 default: 405 *value = UINT_MAX; 406 break; 407 } 408 409 return ret; 410 } 411 412 static int vangogh_common_get_smu_metrics_data(struct smu_context *smu, 413 MetricsMember_t member, 414 uint32_t *value) 415 { 416 int ret = 0; 417 418 if (smu->smc_fw_if_version < 0x3) 419 ret = vangogh_get_legacy_smu_metrics_data(smu, member, value); 420 else 421 ret = vangogh_get_smu_metrics_data(smu, member, value); 422 423 return ret; 424 } 425 426 static int vangogh_allocate_dpm_context(struct smu_context *smu) 427 { 428 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 429 430 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 431 GFP_KERNEL); 432 if (!smu_dpm->dpm_context) 433 return -ENOMEM; 434 435 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 436 437 return 0; 438 } 439 440 static int vangogh_init_smc_tables(struct smu_context *smu) 441 { 442 int ret = 0; 443 444 ret = vangogh_tables_init(smu); 445 if (ret) 446 return ret; 447 448 ret = vangogh_allocate_dpm_context(smu); 449 if (ret) 450 return ret; 451 452 #ifdef CONFIG_X86 453 /* AMD x86 APU only */ 454 smu->cpu_core_num = topology_num_cores_per_package(); 455 #else 456 smu->cpu_core_num = 4; 457 #endif 458 459 return smu_v11_0_init_smc_tables(smu); 460 } 461 462 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 463 { 464 int ret = 0; 465 466 if (enable) { 467 /* vcn dpm on is a prerequisite for vcn power gate messages */ 468 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 469 if (ret) 470 return ret; 471 } else { 472 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); 473 if (ret) 474 return ret; 475 } 476 477 return ret; 478 } 479 480 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 481 { 482 int ret = 0; 483 484 if (enable) { 485 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 486 if (ret) 487 return ret; 488 } else { 489 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 490 if (ret) 491 return ret; 492 } 493 494 return ret; 495 } 496 497 static bool vangogh_is_dpm_running(struct smu_context *smu) 498 { 499 struct amdgpu_device *adev = smu->adev; 500 int ret = 0; 501 uint64_t feature_enabled; 502 503 /* we need to re-init after suspend so return false */ 504 if (adev->in_suspend) 505 return false; 506 507 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 508 509 if (ret) 510 return false; 511 512 return !!(feature_enabled & SMC_DPM_FEATURE); 513 } 514 515 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 516 uint32_t dpm_level, uint32_t *freq) 517 { 518 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 519 520 if (!clk_table || clk_type >= SMU_CLK_COUNT) 521 return -EINVAL; 522 523 switch (clk_type) { 524 case SMU_SOCCLK: 525 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 526 return -EINVAL; 527 *freq = clk_table->SocClocks[dpm_level]; 528 break; 529 case SMU_VCLK: 530 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 531 return -EINVAL; 532 *freq = clk_table->VcnClocks[dpm_level].vclk; 533 break; 534 case SMU_DCLK: 535 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 536 return -EINVAL; 537 *freq = clk_table->VcnClocks[dpm_level].dclk; 538 break; 539 case SMU_UCLK: 540 case SMU_MCLK: 541 if (dpm_level >= clk_table->NumDfPstatesEnabled) 542 return -EINVAL; 543 *freq = clk_table->DfPstateTable[dpm_level].memclk; 544 545 break; 546 case SMU_FCLK: 547 if (dpm_level >= clk_table->NumDfPstatesEnabled) 548 return -EINVAL; 549 *freq = clk_table->DfPstateTable[dpm_level].fclk; 550 break; 551 default: 552 return -EINVAL; 553 } 554 555 return 0; 556 } 557 558 static int vangogh_print_legacy_clk_levels(struct smu_context *smu, 559 enum smu_clk_type clk_type, char *buf) 560 { 561 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 562 SmuMetrics_legacy_t metrics; 563 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 564 int i, idx, size = 0, ret = 0; 565 uint32_t cur_value = 0, value = 0, count = 0; 566 bool cur_value_match_level = false; 567 568 memset(&metrics, 0, sizeof(metrics)); 569 570 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 571 if (ret) 572 return ret; 573 574 smu_cmn_get_sysfs_buf(&buf, &size); 575 576 switch (clk_type) { 577 case SMU_OD_SCLK: 578 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 579 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 580 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 581 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 582 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 583 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 584 } 585 break; 586 case SMU_OD_CCLK: 587 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 588 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 589 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 590 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 591 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 592 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 593 } 594 break; 595 case SMU_OD_RANGE: 596 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 597 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 598 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 599 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 600 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", 601 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 602 } 603 break; 604 case SMU_SOCCLK: 605 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 606 count = clk_table->NumSocClkLevelsEnabled; 607 cur_value = metrics.SocclkFrequency; 608 break; 609 case SMU_VCLK: 610 count = clk_table->VcnClkLevelsEnabled; 611 cur_value = metrics.VclkFrequency; 612 break; 613 case SMU_DCLK: 614 count = clk_table->VcnClkLevelsEnabled; 615 cur_value = metrics.DclkFrequency; 616 break; 617 case SMU_MCLK: 618 count = clk_table->NumDfPstatesEnabled; 619 cur_value = metrics.MemclkFrequency; 620 break; 621 case SMU_FCLK: 622 count = clk_table->NumDfPstatesEnabled; 623 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 624 if (ret) 625 return ret; 626 break; 627 default: 628 break; 629 } 630 631 switch (clk_type) { 632 case SMU_SOCCLK: 633 case SMU_VCLK: 634 case SMU_DCLK: 635 case SMU_MCLK: 636 case SMU_FCLK: 637 for (i = 0; i < count; i++) { 638 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; 639 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value); 640 if (ret) 641 return ret; 642 if (!value) 643 continue; 644 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 645 cur_value == value ? "*" : ""); 646 if (cur_value == value) 647 cur_value_match_level = true; 648 } 649 650 if (!cur_value_match_level) 651 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value); 652 break; 653 default: 654 break; 655 } 656 657 return size; 658 } 659 660 static int vangogh_print_clk_levels(struct smu_context *smu, 661 enum smu_clk_type clk_type, char *buf) 662 { 663 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 664 SmuMetrics_t metrics; 665 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 666 int i, idx, size = 0, ret = 0; 667 uint32_t cur_value = 0, value = 0, count = 0; 668 bool cur_value_match_level = false; 669 uint32_t min, max; 670 671 memset(&metrics, 0, sizeof(metrics)); 672 673 ret = smu_cmn_get_metrics_table(smu, &metrics, false); 674 if (ret) 675 return ret; 676 677 smu_cmn_get_sysfs_buf(&buf, &size); 678 679 switch (clk_type) { 680 case SMU_OD_SCLK: 681 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 682 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 683 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 684 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 685 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 686 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 687 } 688 break; 689 case SMU_OD_CCLK: 690 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 691 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select); 692 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 693 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); 694 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 695 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); 696 } 697 break; 698 case SMU_OD_RANGE: 699 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 700 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 701 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 702 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 703 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", 704 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq); 705 } 706 break; 707 case SMU_SOCCLK: 708 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */ 709 count = clk_table->NumSocClkLevelsEnabled; 710 cur_value = metrics.Current.SocclkFrequency; 711 break; 712 case SMU_VCLK: 713 count = clk_table->VcnClkLevelsEnabled; 714 cur_value = metrics.Current.VclkFrequency; 715 break; 716 case SMU_DCLK: 717 count = clk_table->VcnClkLevelsEnabled; 718 cur_value = metrics.Current.DclkFrequency; 719 break; 720 case SMU_MCLK: 721 count = clk_table->NumDfPstatesEnabled; 722 cur_value = metrics.Current.MemclkFrequency; 723 break; 724 case SMU_FCLK: 725 count = clk_table->NumDfPstatesEnabled; 726 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value); 727 if (ret) 728 return ret; 729 break; 730 case SMU_GFXCLK: 731 case SMU_SCLK: 732 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value); 733 if (ret) { 734 return ret; 735 } 736 break; 737 default: 738 break; 739 } 740 741 switch (clk_type) { 742 case SMU_SOCCLK: 743 case SMU_VCLK: 744 case SMU_DCLK: 745 case SMU_MCLK: 746 case SMU_FCLK: 747 for (i = 0; i < count; i++) { 748 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; 749 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value); 750 if (ret) 751 return ret; 752 if (!value) 753 continue; 754 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 755 cur_value == value ? "*" : ""); 756 if (cur_value == value) 757 cur_value_match_level = true; 758 } 759 760 if (!cur_value_match_level) 761 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value); 762 break; 763 case SMU_GFXCLK: 764 case SMU_SCLK: 765 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; 766 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; 767 if (cur_value == max) 768 i = 2; 769 else if (cur_value == min) 770 i = 0; 771 else 772 i = 1; 773 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min, 774 i == 0 ? "*" : ""); 775 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 776 i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, 777 i == 1 ? "*" : ""); 778 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, 779 i == 2 ? "*" : ""); 780 break; 781 default: 782 break; 783 } 784 785 return size; 786 } 787 788 static int vangogh_common_print_clk_levels(struct smu_context *smu, 789 enum smu_clk_type clk_type, char *buf) 790 { 791 int ret = 0; 792 793 if (smu->smc_fw_if_version < 0x3) 794 ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf); 795 else 796 ret = vangogh_print_clk_levels(smu, clk_type, buf); 797 798 return ret; 799 } 800 801 static int vangogh_get_profiling_clk_mask(struct smu_context *smu, 802 enum amd_dpm_forced_level level, 803 uint32_t *vclk_mask, 804 uint32_t *dclk_mask, 805 uint32_t *mclk_mask, 806 uint32_t *fclk_mask, 807 uint32_t *soc_mask) 808 { 809 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 810 811 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 812 if (mclk_mask) 813 *mclk_mask = clk_table->NumDfPstatesEnabled - 1; 814 815 if (fclk_mask) 816 *fclk_mask = clk_table->NumDfPstatesEnabled - 1; 817 818 if (soc_mask) 819 *soc_mask = 0; 820 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 821 if (mclk_mask) 822 *mclk_mask = 0; 823 824 if (fclk_mask) 825 *fclk_mask = 0; 826 827 if (soc_mask) 828 *soc_mask = 1; 829 830 if (vclk_mask) 831 *vclk_mask = 1; 832 833 if (dclk_mask) 834 *dclk_mask = 1; 835 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) { 836 if (mclk_mask) 837 *mclk_mask = 0; 838 839 if (fclk_mask) 840 *fclk_mask = 0; 841 842 if (soc_mask) 843 *soc_mask = 1; 844 845 if (vclk_mask) 846 *vclk_mask = 1; 847 848 if (dclk_mask) 849 *dclk_mask = 1; 850 } 851 852 return 0; 853 } 854 855 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu, 856 enum smu_clk_type clk_type) 857 { 858 enum smu_feature_mask feature_id = 0; 859 860 switch (clk_type) { 861 case SMU_MCLK: 862 case SMU_UCLK: 863 case SMU_FCLK: 864 feature_id = SMU_FEATURE_DPM_FCLK_BIT; 865 break; 866 case SMU_GFXCLK: 867 case SMU_SCLK: 868 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 869 break; 870 case SMU_SOCCLK: 871 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 872 break; 873 case SMU_VCLK: 874 case SMU_DCLK: 875 feature_id = SMU_FEATURE_VCN_DPM_BIT; 876 break; 877 default: 878 return true; 879 } 880 881 if (!smu_cmn_feature_is_enabled(smu, feature_id)) 882 return false; 883 884 return true; 885 } 886 887 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu, 888 enum smu_clk_type clk_type, 889 uint32_t *min, 890 uint32_t *max) 891 { 892 int ret = 0; 893 uint32_t soc_mask; 894 uint32_t vclk_mask; 895 uint32_t dclk_mask; 896 uint32_t mclk_mask; 897 uint32_t fclk_mask; 898 uint32_t clock_limit; 899 900 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) { 901 switch (clk_type) { 902 case SMU_MCLK: 903 case SMU_UCLK: 904 clock_limit = smu->smu_table.boot_values.uclk; 905 break; 906 case SMU_FCLK: 907 clock_limit = smu->smu_table.boot_values.fclk; 908 break; 909 case SMU_GFXCLK: 910 case SMU_SCLK: 911 clock_limit = smu->smu_table.boot_values.gfxclk; 912 break; 913 case SMU_SOCCLK: 914 clock_limit = smu->smu_table.boot_values.socclk; 915 break; 916 case SMU_VCLK: 917 clock_limit = smu->smu_table.boot_values.vclk; 918 break; 919 case SMU_DCLK: 920 clock_limit = smu->smu_table.boot_values.dclk; 921 break; 922 default: 923 clock_limit = 0; 924 break; 925 } 926 927 /* clock in Mhz unit */ 928 if (min) 929 *min = clock_limit / 100; 930 if (max) 931 *max = clock_limit / 100; 932 933 return 0; 934 } 935 if (max) { 936 ret = vangogh_get_profiling_clk_mask(smu, 937 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK, 938 &vclk_mask, 939 &dclk_mask, 940 &mclk_mask, 941 &fclk_mask, 942 &soc_mask); 943 if (ret) 944 goto failed; 945 946 switch (clk_type) { 947 case SMU_UCLK: 948 case SMU_MCLK: 949 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); 950 if (ret) 951 goto failed; 952 break; 953 case SMU_SOCCLK: 954 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max); 955 if (ret) 956 goto failed; 957 break; 958 case SMU_FCLK: 959 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max); 960 if (ret) 961 goto failed; 962 break; 963 case SMU_VCLK: 964 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max); 965 if (ret) 966 goto failed; 967 break; 968 case SMU_DCLK: 969 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max); 970 if (ret) 971 goto failed; 972 break; 973 default: 974 ret = -EINVAL; 975 goto failed; 976 } 977 } 978 if (min) { 979 ret = vangogh_get_profiling_clk_mask(smu, 980 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK, 981 NULL, 982 NULL, 983 &mclk_mask, 984 &fclk_mask, 985 &soc_mask); 986 if (ret) 987 goto failed; 988 989 vclk_mask = dclk_mask = 0; 990 991 switch (clk_type) { 992 case SMU_UCLK: 993 case SMU_MCLK: 994 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min); 995 if (ret) 996 goto failed; 997 break; 998 case SMU_SOCCLK: 999 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min); 1000 if (ret) 1001 goto failed; 1002 break; 1003 case SMU_FCLK: 1004 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min); 1005 if (ret) 1006 goto failed; 1007 break; 1008 case SMU_VCLK: 1009 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min); 1010 if (ret) 1011 goto failed; 1012 break; 1013 case SMU_DCLK: 1014 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min); 1015 if (ret) 1016 goto failed; 1017 break; 1018 default: 1019 ret = -EINVAL; 1020 goto failed; 1021 } 1022 } 1023 failed: 1024 return ret; 1025 } 1026 1027 static int vangogh_get_power_profile_mode(struct smu_context *smu, 1028 char *buf) 1029 { 1030 uint32_t i, size = 0; 1031 int16_t workload_type = 0; 1032 1033 if (!buf) 1034 return -EINVAL; 1035 1036 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 1037 /* 1038 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1039 * Not all profile modes are supported on vangogh. 1040 */ 1041 workload_type = smu_cmn_to_asic_specific_index(smu, 1042 CMN2ASIC_MAPPING_WORKLOAD, 1043 i); 1044 1045 if (workload_type < 0) 1046 continue; 1047 1048 size += sysfs_emit_at(buf, size, "%2d %14s%s\n", 1049 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1050 } 1051 1052 return size; 1053 } 1054 1055 static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1056 { 1057 int workload_type, ret; 1058 uint32_t profile_mode = input[size]; 1059 1060 if (profile_mode >= PP_SMC_POWER_PROFILE_COUNT) { 1061 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 1062 return -EINVAL; 1063 } 1064 1065 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT || 1066 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) 1067 return 0; 1068 1069 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1070 workload_type = smu_cmn_to_asic_specific_index(smu, 1071 CMN2ASIC_MAPPING_WORKLOAD, 1072 profile_mode); 1073 if (workload_type < 0) { 1074 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n", 1075 profile_mode); 1076 return -EINVAL; 1077 } 1078 1079 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 1080 1 << workload_type, 1081 NULL); 1082 if (ret) { 1083 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", 1084 workload_type); 1085 return ret; 1086 } 1087 1088 smu->power_profile_mode = profile_mode; 1089 1090 return 0; 1091 } 1092 1093 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu, 1094 enum smu_clk_type clk_type, 1095 uint32_t min, 1096 uint32_t max) 1097 { 1098 int ret = 0; 1099 1100 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) 1101 return 0; 1102 1103 switch (clk_type) { 1104 case SMU_GFXCLK: 1105 case SMU_SCLK: 1106 ret = smu_cmn_send_smc_msg_with_param(smu, 1107 SMU_MSG_SetHardMinGfxClk, 1108 min, NULL); 1109 if (ret) 1110 return ret; 1111 1112 ret = smu_cmn_send_smc_msg_with_param(smu, 1113 SMU_MSG_SetSoftMaxGfxClk, 1114 max, NULL); 1115 if (ret) 1116 return ret; 1117 break; 1118 case SMU_FCLK: 1119 ret = smu_cmn_send_smc_msg_with_param(smu, 1120 SMU_MSG_SetHardMinFclkByFreq, 1121 min, NULL); 1122 if (ret) 1123 return ret; 1124 1125 ret = smu_cmn_send_smc_msg_with_param(smu, 1126 SMU_MSG_SetSoftMaxFclkByFreq, 1127 max, NULL); 1128 if (ret) 1129 return ret; 1130 break; 1131 case SMU_SOCCLK: 1132 ret = smu_cmn_send_smc_msg_with_param(smu, 1133 SMU_MSG_SetHardMinSocclkByFreq, 1134 min, NULL); 1135 if (ret) 1136 return ret; 1137 1138 ret = smu_cmn_send_smc_msg_with_param(smu, 1139 SMU_MSG_SetSoftMaxSocclkByFreq, 1140 max, NULL); 1141 if (ret) 1142 return ret; 1143 break; 1144 case SMU_VCLK: 1145 ret = smu_cmn_send_smc_msg_with_param(smu, 1146 SMU_MSG_SetHardMinVcn, 1147 min << 16, NULL); 1148 if (ret) 1149 return ret; 1150 ret = smu_cmn_send_smc_msg_with_param(smu, 1151 SMU_MSG_SetSoftMaxVcn, 1152 max << 16, NULL); 1153 if (ret) 1154 return ret; 1155 break; 1156 case SMU_DCLK: 1157 ret = smu_cmn_send_smc_msg_with_param(smu, 1158 SMU_MSG_SetHardMinVcn, 1159 min, NULL); 1160 if (ret) 1161 return ret; 1162 ret = smu_cmn_send_smc_msg_with_param(smu, 1163 SMU_MSG_SetSoftMaxVcn, 1164 max, NULL); 1165 if (ret) 1166 return ret; 1167 break; 1168 default: 1169 return -EINVAL; 1170 } 1171 1172 return ret; 1173 } 1174 1175 static int vangogh_force_clk_levels(struct smu_context *smu, 1176 enum smu_clk_type clk_type, uint32_t mask) 1177 { 1178 uint32_t soft_min_level = 0, soft_max_level = 0; 1179 uint32_t min_freq = 0, max_freq = 0; 1180 int ret = 0 ; 1181 1182 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1183 soft_max_level = mask ? (fls(mask) - 1) : 0; 1184 1185 switch (clk_type) { 1186 case SMU_SOCCLK: 1187 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 1188 soft_min_level, &min_freq); 1189 if (ret) 1190 return ret; 1191 ret = vangogh_get_dpm_clk_limited(smu, clk_type, 1192 soft_max_level, &max_freq); 1193 if (ret) 1194 return ret; 1195 ret = smu_cmn_send_smc_msg_with_param(smu, 1196 SMU_MSG_SetSoftMaxSocclkByFreq, 1197 max_freq, NULL); 1198 if (ret) 1199 return ret; 1200 ret = smu_cmn_send_smc_msg_with_param(smu, 1201 SMU_MSG_SetHardMinSocclkByFreq, 1202 min_freq, NULL); 1203 if (ret) 1204 return ret; 1205 break; 1206 case SMU_FCLK: 1207 ret = vangogh_get_dpm_clk_limited(smu, 1208 clk_type, soft_min_level, &min_freq); 1209 if (ret) 1210 return ret; 1211 ret = vangogh_get_dpm_clk_limited(smu, 1212 clk_type, soft_max_level, &max_freq); 1213 if (ret) 1214 return ret; 1215 ret = smu_cmn_send_smc_msg_with_param(smu, 1216 SMU_MSG_SetSoftMaxFclkByFreq, 1217 max_freq, NULL); 1218 if (ret) 1219 return ret; 1220 ret = smu_cmn_send_smc_msg_with_param(smu, 1221 SMU_MSG_SetHardMinFclkByFreq, 1222 min_freq, NULL); 1223 if (ret) 1224 return ret; 1225 break; 1226 case SMU_VCLK: 1227 ret = vangogh_get_dpm_clk_limited(smu, 1228 clk_type, soft_min_level, &min_freq); 1229 if (ret) 1230 return ret; 1231 1232 ret = vangogh_get_dpm_clk_limited(smu, 1233 clk_type, soft_max_level, &max_freq); 1234 if (ret) 1235 return ret; 1236 1237 1238 ret = smu_cmn_send_smc_msg_with_param(smu, 1239 SMU_MSG_SetHardMinVcn, 1240 min_freq << 16, NULL); 1241 if (ret) 1242 return ret; 1243 1244 ret = smu_cmn_send_smc_msg_with_param(smu, 1245 SMU_MSG_SetSoftMaxVcn, 1246 max_freq << 16, NULL); 1247 if (ret) 1248 return ret; 1249 1250 break; 1251 case SMU_DCLK: 1252 ret = vangogh_get_dpm_clk_limited(smu, 1253 clk_type, soft_min_level, &min_freq); 1254 if (ret) 1255 return ret; 1256 1257 ret = vangogh_get_dpm_clk_limited(smu, 1258 clk_type, soft_max_level, &max_freq); 1259 if (ret) 1260 return ret; 1261 1262 ret = smu_cmn_send_smc_msg_with_param(smu, 1263 SMU_MSG_SetHardMinVcn, 1264 min_freq, NULL); 1265 if (ret) 1266 return ret; 1267 1268 ret = smu_cmn_send_smc_msg_with_param(smu, 1269 SMU_MSG_SetSoftMaxVcn, 1270 max_freq, NULL); 1271 if (ret) 1272 return ret; 1273 1274 break; 1275 default: 1276 break; 1277 } 1278 1279 return ret; 1280 } 1281 1282 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest) 1283 { 1284 int ret = 0, i = 0; 1285 uint32_t min_freq, max_freq, force_freq; 1286 enum smu_clk_type clk_type; 1287 1288 enum smu_clk_type clks[] = { 1289 SMU_SOCCLK, 1290 SMU_VCLK, 1291 SMU_DCLK, 1292 SMU_FCLK, 1293 }; 1294 1295 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1296 clk_type = clks[i]; 1297 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1298 if (ret) 1299 return ret; 1300 1301 force_freq = highest ? max_freq : min_freq; 1302 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq); 1303 if (ret) 1304 return ret; 1305 } 1306 1307 return ret; 1308 } 1309 1310 static int vangogh_unforce_dpm_levels(struct smu_context *smu) 1311 { 1312 int ret = 0, i = 0; 1313 uint32_t min_freq, max_freq; 1314 enum smu_clk_type clk_type; 1315 1316 struct clk_feature_map { 1317 enum smu_clk_type clk_type; 1318 uint32_t feature; 1319 } clk_feature_map[] = { 1320 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT}, 1321 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, 1322 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT}, 1323 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT}, 1324 }; 1325 1326 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { 1327 1328 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature)) 1329 continue; 1330 1331 clk_type = clk_feature_map[i].clk_type; 1332 1333 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq); 1334 1335 if (ret) 1336 return ret; 1337 1338 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1339 1340 if (ret) 1341 return ret; 1342 } 1343 1344 return ret; 1345 } 1346 1347 static int vangogh_set_peak_clock_by_device(struct smu_context *smu) 1348 { 1349 int ret = 0; 1350 uint32_t socclk_freq = 0, fclk_freq = 0; 1351 uint32_t vclk_freq = 0, dclk_freq = 0; 1352 1353 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq); 1354 if (ret) 1355 return ret; 1356 1357 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq); 1358 if (ret) 1359 return ret; 1360 1361 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq); 1362 if (ret) 1363 return ret; 1364 1365 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq); 1366 if (ret) 1367 return ret; 1368 1369 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq); 1370 if (ret) 1371 return ret; 1372 1373 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq); 1374 if (ret) 1375 return ret; 1376 1377 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq); 1378 if (ret) 1379 return ret; 1380 1381 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq); 1382 if (ret) 1383 return ret; 1384 1385 return ret; 1386 } 1387 1388 static int vangogh_set_performance_level(struct smu_context *smu, 1389 enum amd_dpm_forced_level level) 1390 { 1391 int ret = 0, i; 1392 uint32_t soc_mask, mclk_mask, fclk_mask; 1393 uint32_t vclk_mask = 0, dclk_mask = 0; 1394 1395 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 1396 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 1397 1398 switch (level) { 1399 case AMD_DPM_FORCED_LEVEL_HIGH: 1400 smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq; 1401 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1402 1403 1404 ret = vangogh_force_dpm_limit_value(smu, true); 1405 if (ret) 1406 return ret; 1407 break; 1408 case AMD_DPM_FORCED_LEVEL_LOW: 1409 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1410 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq; 1411 1412 ret = vangogh_force_dpm_limit_value(smu, false); 1413 if (ret) 1414 return ret; 1415 break; 1416 case AMD_DPM_FORCED_LEVEL_AUTO: 1417 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1418 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1419 1420 ret = vangogh_unforce_dpm_levels(smu); 1421 if (ret) 1422 return ret; 1423 break; 1424 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1425 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK; 1426 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK; 1427 1428 ret = vangogh_get_profiling_clk_mask(smu, level, 1429 &vclk_mask, 1430 &dclk_mask, 1431 &mclk_mask, 1432 &fclk_mask, 1433 &soc_mask); 1434 if (ret) 1435 return ret; 1436 1437 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1438 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); 1439 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask); 1440 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask); 1441 break; 1442 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1443 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1444 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq; 1445 break; 1446 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1447 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1448 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1449 1450 ret = vangogh_get_profiling_clk_mask(smu, level, 1451 NULL, 1452 NULL, 1453 &mclk_mask, 1454 &fclk_mask, 1455 NULL); 1456 if (ret) 1457 return ret; 1458 1459 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask); 1460 break; 1461 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1462 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK; 1463 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK; 1464 1465 ret = vangogh_set_peak_clock_by_device(smu); 1466 if (ret) 1467 return ret; 1468 break; 1469 case AMD_DPM_FORCED_LEVEL_MANUAL: 1470 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1471 default: 1472 return 0; 1473 } 1474 1475 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1476 smu->gfx_actual_hard_min_freq, NULL); 1477 if (ret) 1478 return ret; 1479 1480 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1481 smu->gfx_actual_soft_max_freq, NULL); 1482 if (ret) 1483 return ret; 1484 1485 if (smu->adev->pm.fw_version >= 0x43f1b00) { 1486 for (i = 0; i < smu->cpu_core_num; i++) { 1487 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 1488 ((i << 20) 1489 | smu->cpu_actual_soft_min_freq), 1490 NULL); 1491 if (ret) 1492 return ret; 1493 1494 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 1495 ((i << 20) 1496 | smu->cpu_actual_soft_max_freq), 1497 NULL); 1498 if (ret) 1499 return ret; 1500 } 1501 } 1502 1503 return ret; 1504 } 1505 1506 static int vangogh_read_sensor(struct smu_context *smu, 1507 enum amd_pp_sensors sensor, 1508 void *data, uint32_t *size) 1509 { 1510 int ret = 0; 1511 1512 if (!data || !size) 1513 return -EINVAL; 1514 1515 switch (sensor) { 1516 case AMDGPU_PP_SENSOR_GPU_LOAD: 1517 ret = vangogh_common_get_smu_metrics_data(smu, 1518 METRICS_AVERAGE_GFXACTIVITY, 1519 (uint32_t *)data); 1520 *size = 4; 1521 break; 1522 case AMDGPU_PP_SENSOR_VCN_LOAD: 1523 ret = vangogh_common_get_smu_metrics_data(smu, 1524 METRICS_AVERAGE_VCNACTIVITY, 1525 (uint32_t *)data); 1526 *size = 4; 1527 break; 1528 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 1529 ret = vangogh_common_get_smu_metrics_data(smu, 1530 METRICS_AVERAGE_SOCKETPOWER, 1531 (uint32_t *)data); 1532 *size = 4; 1533 break; 1534 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 1535 ret = vangogh_common_get_smu_metrics_data(smu, 1536 METRICS_CURR_SOCKETPOWER, 1537 (uint32_t *)data); 1538 *size = 4; 1539 break; 1540 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1541 ret = vangogh_common_get_smu_metrics_data(smu, 1542 METRICS_TEMPERATURE_EDGE, 1543 (uint32_t *)data); 1544 *size = 4; 1545 break; 1546 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1547 ret = vangogh_common_get_smu_metrics_data(smu, 1548 METRICS_TEMPERATURE_HOTSPOT, 1549 (uint32_t *)data); 1550 *size = 4; 1551 break; 1552 case AMDGPU_PP_SENSOR_GFX_MCLK: 1553 ret = vangogh_common_get_smu_metrics_data(smu, 1554 METRICS_CURR_UCLK, 1555 (uint32_t *)data); 1556 *(uint32_t *)data *= 100; 1557 *size = 4; 1558 break; 1559 case AMDGPU_PP_SENSOR_GFX_SCLK: 1560 ret = vangogh_common_get_smu_metrics_data(smu, 1561 METRICS_CURR_GFXCLK, 1562 (uint32_t *)data); 1563 *(uint32_t *)data *= 100; 1564 *size = 4; 1565 break; 1566 case AMDGPU_PP_SENSOR_VDDGFX: 1567 ret = vangogh_common_get_smu_metrics_data(smu, 1568 METRICS_VOLTAGE_VDDGFX, 1569 (uint32_t *)data); 1570 *size = 4; 1571 break; 1572 case AMDGPU_PP_SENSOR_VDDNB: 1573 ret = vangogh_common_get_smu_metrics_data(smu, 1574 METRICS_VOLTAGE_VDDSOC, 1575 (uint32_t *)data); 1576 *size = 4; 1577 break; 1578 case AMDGPU_PP_SENSOR_CPU_CLK: 1579 ret = vangogh_common_get_smu_metrics_data(smu, 1580 METRICS_AVERAGE_CPUCLK, 1581 (uint32_t *)data); 1582 *size = smu->cpu_core_num * sizeof(uint16_t); 1583 break; 1584 default: 1585 ret = -EOPNOTSUPP; 1586 break; 1587 } 1588 1589 return ret; 1590 } 1591 1592 static int vangogh_get_apu_thermal_limit(struct smu_context *smu, uint32_t *limit) 1593 { 1594 return smu_cmn_send_smc_msg_with_param(smu, 1595 SMU_MSG_GetThermalLimit, 1596 0, limit); 1597 } 1598 1599 static int vangogh_set_apu_thermal_limit(struct smu_context *smu, uint32_t limit) 1600 { 1601 return smu_cmn_send_smc_msg_with_param(smu, 1602 SMU_MSG_SetReducedThermalLimit, 1603 limit, NULL); 1604 } 1605 1606 1607 static int vangogh_set_watermarks_table(struct smu_context *smu, 1608 struct pp_smu_wm_range_sets *clock_ranges) 1609 { 1610 int i; 1611 int ret = 0; 1612 Watermarks_t *table = smu->smu_table.watermarks_table; 1613 1614 if (!table || !clock_ranges) 1615 return -EINVAL; 1616 1617 if (clock_ranges) { 1618 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1619 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1620 return -EINVAL; 1621 1622 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1623 table->WatermarkRow[WM_DCFCLK][i].MinClock = 1624 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1625 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 1626 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1627 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 1628 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1629 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 1630 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1631 1632 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 1633 clock_ranges->reader_wm_sets[i].wm_inst; 1634 } 1635 1636 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1637 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1638 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1639 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1640 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1641 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 1642 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1643 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 1644 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1645 1646 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1647 clock_ranges->writer_wm_sets[i].wm_inst; 1648 } 1649 1650 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1651 } 1652 1653 /* pass data to smu controller */ 1654 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1655 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1656 ret = smu_cmn_write_watermarks_table(smu); 1657 if (ret) { 1658 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1659 return ret; 1660 } 1661 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1662 } 1663 1664 return 0; 1665 } 1666 1667 static ssize_t vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context *smu, 1668 void **table) 1669 { 1670 struct smu_table_context *smu_table = &smu->smu_table; 1671 struct gpu_metrics_v2_3 *gpu_metrics = 1672 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table; 1673 SmuMetrics_legacy_t metrics; 1674 int ret = 0; 1675 1676 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1677 if (ret) 1678 return ret; 1679 1680 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3); 1681 1682 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1683 gpu_metrics->temperature_soc = metrics.SocTemperature; 1684 memcpy(&gpu_metrics->temperature_core[0], 1685 &metrics.CoreTemperature[0], 1686 sizeof(uint16_t) * 4); 1687 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1688 1689 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 1690 gpu_metrics->average_mm_activity = metrics.UvdActivity; 1691 1692 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1693 gpu_metrics->average_cpu_power = metrics.Power[0]; 1694 gpu_metrics->average_soc_power = metrics.Power[1]; 1695 gpu_metrics->average_gfx_power = metrics.Power[2]; 1696 memcpy(&gpu_metrics->average_core_power[0], 1697 &metrics.CorePower[0], 1698 sizeof(uint16_t) * 4); 1699 1700 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 1701 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 1702 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 1703 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 1704 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 1705 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 1706 1707 memcpy(&gpu_metrics->current_coreclk[0], 1708 &metrics.CoreFrequency[0], 1709 sizeof(uint16_t) * 4); 1710 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1711 1712 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1713 gpu_metrics->indep_throttle_status = 1714 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1715 vangogh_throttler_map); 1716 1717 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1718 1719 *table = (void *)gpu_metrics; 1720 1721 return sizeof(struct gpu_metrics_v2_3); 1722 } 1723 1724 static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu, 1725 void **table) 1726 { 1727 struct smu_table_context *smu_table = &smu->smu_table; 1728 struct gpu_metrics_v2_2 *gpu_metrics = 1729 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; 1730 SmuMetrics_legacy_t metrics; 1731 int ret = 0; 1732 1733 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1734 if (ret) 1735 return ret; 1736 1737 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); 1738 1739 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 1740 gpu_metrics->temperature_soc = metrics.SocTemperature; 1741 memcpy(&gpu_metrics->temperature_core[0], 1742 &metrics.CoreTemperature[0], 1743 sizeof(uint16_t) * 4); 1744 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0]; 1745 1746 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 1747 gpu_metrics->average_mm_activity = metrics.UvdActivity; 1748 1749 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 1750 gpu_metrics->average_cpu_power = metrics.Power[0]; 1751 gpu_metrics->average_soc_power = metrics.Power[1]; 1752 gpu_metrics->average_gfx_power = metrics.Power[2]; 1753 memcpy(&gpu_metrics->average_core_power[0], 1754 &metrics.CorePower[0], 1755 sizeof(uint16_t) * 4); 1756 1757 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 1758 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 1759 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 1760 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 1761 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 1762 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 1763 1764 memcpy(&gpu_metrics->current_coreclk[0], 1765 &metrics.CoreFrequency[0], 1766 sizeof(uint16_t) * 4); 1767 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0]; 1768 1769 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 1770 gpu_metrics->indep_throttle_status = 1771 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 1772 vangogh_throttler_map); 1773 1774 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1775 1776 *table = (void *)gpu_metrics; 1777 1778 return sizeof(struct gpu_metrics_v2_2); 1779 } 1780 1781 static ssize_t vangogh_get_gpu_metrics_v2_3(struct smu_context *smu, 1782 void **table) 1783 { 1784 struct smu_table_context *smu_table = &smu->smu_table; 1785 struct gpu_metrics_v2_3 *gpu_metrics = 1786 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table; 1787 SmuMetrics_t metrics; 1788 int ret = 0; 1789 1790 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1791 if (ret) 1792 return ret; 1793 1794 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3); 1795 1796 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 1797 gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1798 memcpy(&gpu_metrics->temperature_core[0], 1799 &metrics.Current.CoreTemperature[0], 1800 sizeof(uint16_t) * 4); 1801 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1802 1803 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature; 1804 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature; 1805 memcpy(&gpu_metrics->average_temperature_core[0], 1806 &metrics.Average.CoreTemperature[0], 1807 sizeof(uint16_t) * 4); 1808 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0]; 1809 1810 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity; 1811 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity; 1812 1813 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower; 1814 gpu_metrics->average_cpu_power = metrics.Current.Power[0]; 1815 gpu_metrics->average_soc_power = metrics.Current.Power[1]; 1816 gpu_metrics->average_gfx_power = metrics.Current.Power[2]; 1817 memcpy(&gpu_metrics->average_core_power[0], 1818 &metrics.Average.CorePower[0], 1819 sizeof(uint16_t) * 4); 1820 1821 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 1822 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 1823 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 1824 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 1825 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 1826 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 1827 1828 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 1829 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 1830 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 1831 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 1832 gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 1833 gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 1834 1835 memcpy(&gpu_metrics->current_coreclk[0], 1836 &metrics.Current.CoreFrequency[0], 1837 sizeof(uint16_t) * 4); 1838 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 1839 1840 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 1841 gpu_metrics->indep_throttle_status = 1842 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, 1843 vangogh_throttler_map); 1844 1845 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1846 1847 *table = (void *)gpu_metrics; 1848 1849 return sizeof(struct gpu_metrics_v2_3); 1850 } 1851 1852 static ssize_t vangogh_get_gpu_metrics_v2_4(struct smu_context *smu, 1853 void **table) 1854 { 1855 SmuMetrics_t metrics; 1856 struct smu_table_context *smu_table = &smu->smu_table; 1857 struct gpu_metrics_v2_4 *gpu_metrics = 1858 (struct gpu_metrics_v2_4 *)smu_table->gpu_metrics_table; 1859 int ret = 0; 1860 1861 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1862 if (ret) 1863 return ret; 1864 1865 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 4); 1866 1867 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 1868 gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1869 memcpy(&gpu_metrics->temperature_core[0], 1870 &metrics.Current.CoreTemperature[0], 1871 sizeof(uint16_t) * 4); 1872 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1873 1874 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature; 1875 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature; 1876 memcpy(&gpu_metrics->average_temperature_core[0], 1877 &metrics.Average.CoreTemperature[0], 1878 sizeof(uint16_t) * 4); 1879 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0]; 1880 1881 gpu_metrics->average_gfx_activity = metrics.Average.GfxActivity; 1882 gpu_metrics->average_mm_activity = metrics.Average.UvdActivity; 1883 1884 gpu_metrics->average_socket_power = metrics.Average.CurrentSocketPower; 1885 gpu_metrics->average_cpu_power = metrics.Average.Power[0]; 1886 gpu_metrics->average_soc_power = metrics.Average.Power[1]; 1887 gpu_metrics->average_gfx_power = metrics.Average.Power[2]; 1888 1889 gpu_metrics->average_cpu_voltage = metrics.Average.Voltage[0]; 1890 gpu_metrics->average_soc_voltage = metrics.Average.Voltage[1]; 1891 gpu_metrics->average_gfx_voltage = metrics.Average.Voltage[2]; 1892 1893 gpu_metrics->average_cpu_current = metrics.Average.Current[0]; 1894 gpu_metrics->average_soc_current = metrics.Average.Current[1]; 1895 gpu_metrics->average_gfx_current = metrics.Average.Current[2]; 1896 1897 memcpy(&gpu_metrics->average_core_power[0], 1898 &metrics.Average.CorePower[0], 1899 sizeof(uint16_t) * 4); 1900 1901 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 1902 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 1903 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 1904 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 1905 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 1906 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 1907 1908 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 1909 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 1910 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 1911 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 1912 gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 1913 gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 1914 1915 memcpy(&gpu_metrics->current_coreclk[0], 1916 &metrics.Current.CoreFrequency[0], 1917 sizeof(uint16_t) * 4); 1918 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 1919 1920 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 1921 gpu_metrics->indep_throttle_status = 1922 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, 1923 vangogh_throttler_map); 1924 1925 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1926 1927 *table = (void *)gpu_metrics; 1928 1929 return sizeof(struct gpu_metrics_v2_4); 1930 } 1931 1932 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, 1933 void **table) 1934 { 1935 struct smu_table_context *smu_table = &smu->smu_table; 1936 struct gpu_metrics_v2_2 *gpu_metrics = 1937 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; 1938 SmuMetrics_t metrics; 1939 int ret = 0; 1940 1941 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 1942 if (ret) 1943 return ret; 1944 1945 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2); 1946 1947 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature; 1948 gpu_metrics->temperature_soc = metrics.Current.SocTemperature; 1949 memcpy(&gpu_metrics->temperature_core[0], 1950 &metrics.Current.CoreTemperature[0], 1951 sizeof(uint16_t) * 4); 1952 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0]; 1953 1954 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity; 1955 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity; 1956 1957 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower; 1958 gpu_metrics->average_cpu_power = metrics.Current.Power[0]; 1959 gpu_metrics->average_soc_power = metrics.Current.Power[1]; 1960 gpu_metrics->average_gfx_power = metrics.Current.Power[2]; 1961 memcpy(&gpu_metrics->average_core_power[0], 1962 &metrics.Average.CorePower[0], 1963 sizeof(uint16_t) * 4); 1964 1965 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency; 1966 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency; 1967 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency; 1968 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency; 1969 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency; 1970 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency; 1971 1972 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency; 1973 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency; 1974 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency; 1975 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency; 1976 gpu_metrics->current_vclk = metrics.Current.VclkFrequency; 1977 gpu_metrics->current_dclk = metrics.Current.DclkFrequency; 1978 1979 memcpy(&gpu_metrics->current_coreclk[0], 1980 &metrics.Current.CoreFrequency[0], 1981 sizeof(uint16_t) * 4); 1982 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0]; 1983 1984 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus; 1985 gpu_metrics->indep_throttle_status = 1986 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus, 1987 vangogh_throttler_map); 1988 1989 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1990 1991 *table = (void *)gpu_metrics; 1992 1993 return sizeof(struct gpu_metrics_v2_2); 1994 } 1995 1996 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu, 1997 void **table) 1998 { 1999 uint32_t smu_program; 2000 uint32_t fw_version; 2001 int ret = 0; 2002 2003 smu_program = (smu->smc_fw_version >> 24) & 0xff; 2004 fw_version = smu->smc_fw_version & 0xffffff; 2005 if (smu_program == 6) { 2006 if (fw_version >= 0x3F0800) 2007 ret = vangogh_get_gpu_metrics_v2_4(smu, table); 2008 else 2009 ret = vangogh_get_gpu_metrics_v2_3(smu, table); 2010 2011 } else { 2012 if (smu->smc_fw_version >= 0x043F3E00) { 2013 if (smu->smc_fw_if_version < 0x3) 2014 ret = vangogh_get_legacy_gpu_metrics_v2_3(smu, table); 2015 else 2016 ret = vangogh_get_gpu_metrics_v2_3(smu, table); 2017 } else { 2018 if (smu->smc_fw_if_version < 0x3) 2019 ret = vangogh_get_legacy_gpu_metrics(smu, table); 2020 else 2021 ret = vangogh_get_gpu_metrics(smu, table); 2022 } 2023 } 2024 2025 return ret; 2026 } 2027 2028 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 2029 long input[], uint32_t size) 2030 { 2031 int ret = 0; 2032 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2033 2034 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { 2035 dev_warn(smu->adev->dev, 2036 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n"); 2037 return -EINVAL; 2038 } 2039 2040 switch (type) { 2041 case PP_OD_EDIT_CCLK_VDDC_TABLE: 2042 if (size != 3) { 2043 dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n"); 2044 return -EINVAL; 2045 } 2046 if (input[0] >= smu->cpu_core_num) { 2047 dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n", 2048 smu->cpu_core_num); 2049 } 2050 smu->cpu_core_id_select = input[0]; 2051 if (input[1] == 0) { 2052 if (input[2] < smu->cpu_default_soft_min_freq) { 2053 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 2054 input[2], smu->cpu_default_soft_min_freq); 2055 return -EINVAL; 2056 } 2057 smu->cpu_actual_soft_min_freq = input[2]; 2058 } else if (input[1] == 1) { 2059 if (input[2] > smu->cpu_default_soft_max_freq) { 2060 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 2061 input[2], smu->cpu_default_soft_max_freq); 2062 return -EINVAL; 2063 } 2064 smu->cpu_actual_soft_max_freq = input[2]; 2065 } else { 2066 return -EINVAL; 2067 } 2068 break; 2069 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2070 if (size != 2) { 2071 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2072 return -EINVAL; 2073 } 2074 2075 if (input[0] == 0) { 2076 if (input[1] < smu->gfx_default_hard_min_freq) { 2077 dev_warn(smu->adev->dev, 2078 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 2079 input[1], smu->gfx_default_hard_min_freq); 2080 return -EINVAL; 2081 } 2082 smu->gfx_actual_hard_min_freq = input[1]; 2083 } else if (input[0] == 1) { 2084 if (input[1] > smu->gfx_default_soft_max_freq) { 2085 dev_warn(smu->adev->dev, 2086 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 2087 input[1], smu->gfx_default_soft_max_freq); 2088 return -EINVAL; 2089 } 2090 smu->gfx_actual_soft_max_freq = input[1]; 2091 } else { 2092 return -EINVAL; 2093 } 2094 break; 2095 case PP_OD_RESTORE_DEFAULT_TABLE: 2096 if (size != 0) { 2097 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2098 return -EINVAL; 2099 } else { 2100 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 2101 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 2102 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq; 2103 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq; 2104 } 2105 break; 2106 case PP_OD_COMMIT_DPM_TABLE: 2107 if (size != 0) { 2108 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 2109 return -EINVAL; 2110 } else { 2111 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 2112 dev_err(smu->adev->dev, 2113 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 2114 smu->gfx_actual_hard_min_freq, 2115 smu->gfx_actual_soft_max_freq); 2116 return -EINVAL; 2117 } 2118 2119 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 2120 smu->gfx_actual_hard_min_freq, NULL); 2121 if (ret) { 2122 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 2123 return ret; 2124 } 2125 2126 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 2127 smu->gfx_actual_soft_max_freq, NULL); 2128 if (ret) { 2129 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 2130 return ret; 2131 } 2132 2133 if (smu->adev->pm.fw_version < 0x43f1b00) { 2134 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n"); 2135 break; 2136 } 2137 2138 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk, 2139 ((smu->cpu_core_id_select << 20) 2140 | smu->cpu_actual_soft_min_freq), 2141 NULL); 2142 if (ret) { 2143 dev_err(smu->adev->dev, "Set hard min cclk failed!"); 2144 return ret; 2145 } 2146 2147 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk, 2148 ((smu->cpu_core_id_select << 20) 2149 | smu->cpu_actual_soft_max_freq), 2150 NULL); 2151 if (ret) { 2152 dev_err(smu->adev->dev, "Set soft max cclk failed!"); 2153 return ret; 2154 } 2155 } 2156 break; 2157 default: 2158 return -ENOSYS; 2159 } 2160 2161 return ret; 2162 } 2163 2164 static int vangogh_set_default_dpm_tables(struct smu_context *smu) 2165 { 2166 struct smu_table_context *smu_table = &smu->smu_table; 2167 2168 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); 2169 } 2170 2171 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 2172 { 2173 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 2174 2175 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 2176 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 2177 smu->gfx_actual_hard_min_freq = 0; 2178 smu->gfx_actual_soft_max_freq = 0; 2179 2180 smu->cpu_default_soft_min_freq = 1400; 2181 smu->cpu_default_soft_max_freq = 3500; 2182 smu->cpu_actual_soft_min_freq = 0; 2183 smu->cpu_actual_soft_max_freq = 0; 2184 2185 return 0; 2186 } 2187 2188 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) 2189 { 2190 DpmClocks_t *table = smu->smu_table.clocks_table; 2191 int i; 2192 2193 if (!clock_table || !table) 2194 return -EINVAL; 2195 2196 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { 2197 clock_table->SocClocks[i].Freq = table->SocClocks[i]; 2198 clock_table->SocClocks[i].Vol = table->SocVoltage[i]; 2199 } 2200 2201 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 2202 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk; 2203 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage; 2204 } 2205 2206 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { 2207 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk; 2208 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage; 2209 } 2210 2211 return 0; 2212 } 2213 2214 static int vangogh_notify_rlc_state(struct smu_context *smu, bool en) 2215 { 2216 struct amdgpu_device *adev = smu->adev; 2217 int ret = 0; 2218 2219 if (adev->pm.fw_version >= 0x43f1700 && !en) 2220 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify, 2221 RLC_STATUS_OFF, NULL); 2222 2223 return ret; 2224 } 2225 2226 static int vangogh_post_smu_init(struct smu_context *smu) 2227 { 2228 struct amdgpu_device *adev = smu->adev; 2229 uint32_t tmp; 2230 int ret = 0; 2231 uint8_t aon_bits = 0; 2232 /* Two CUs in one WGP */ 2233 uint32_t req_active_wgps = adev->gfx.cu_info.number/2; 2234 uint32_t total_cu = adev->gfx.config.max_cu_per_sh * 2235 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 2236 2237 /* allow message will be sent after enable message on Vangogh*/ 2238 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 2239 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2240 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL); 2241 if (ret) { 2242 dev_err(adev->dev, "Failed to Enable GfxOff!\n"); 2243 return ret; 2244 } 2245 } else { 2246 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 2247 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n"); 2248 } 2249 2250 /* if all CUs are active, no need to power off any WGPs */ 2251 if (total_cu == adev->gfx.cu_info.number) 2252 return 0; 2253 2254 /* 2255 * Calculate the total bits number of always on WGPs for all SA/SEs in 2256 * RLC_PG_ALWAYS_ON_WGP_MASK. 2257 */ 2258 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK)); 2259 tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK; 2260 2261 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 2262 2263 /* Do not request any WGPs less than set in the AON_WGP_MASK */ 2264 if (aon_bits > req_active_wgps) { 2265 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n"); 2266 return 0; 2267 } else { 2268 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL); 2269 } 2270 } 2271 2272 static int vangogh_mode_reset(struct smu_context *smu, int type) 2273 { 2274 int ret = 0, index = 0; 2275 2276 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 2277 SMU_MSG_GfxDeviceDriverReset); 2278 if (index < 0) 2279 return index == -EACCES ? 0 : index; 2280 2281 mutex_lock(&smu->message_lock); 2282 2283 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type); 2284 2285 mutex_unlock(&smu->message_lock); 2286 2287 mdelay(10); 2288 2289 return ret; 2290 } 2291 2292 static int vangogh_mode2_reset(struct smu_context *smu) 2293 { 2294 return vangogh_mode_reset(smu, SMU_RESET_MODE_2); 2295 } 2296 2297 /** 2298 * vangogh_get_gfxoff_status - Get gfxoff status 2299 * 2300 * @smu: amdgpu_device pointer 2301 * 2302 * Get current gfxoff status 2303 * 2304 * Return: 2305 * * 0 - GFXOFF (default if enabled). 2306 * * 1 - Transition out of GFX State. 2307 * * 2 - Not in GFXOFF. 2308 * * 3 - Transition into GFXOFF. 2309 */ 2310 static u32 vangogh_get_gfxoff_status(struct smu_context *smu) 2311 { 2312 struct amdgpu_device *adev = smu->adev; 2313 u32 reg, gfxoff_status; 2314 2315 reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL); 2316 gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK) 2317 >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT; 2318 2319 return gfxoff_status; 2320 } 2321 2322 static int vangogh_get_power_limit(struct smu_context *smu, 2323 uint32_t *current_power_limit, 2324 uint32_t *default_power_limit, 2325 uint32_t *max_power_limit, 2326 uint32_t *min_power_limit) 2327 { 2328 struct smu_11_5_power_context *power_context = 2329 smu->smu_power.power_context; 2330 uint32_t ppt_limit; 2331 int ret = 0; 2332 2333 if (smu->adev->pm.fw_version < 0x43f1e00) 2334 return ret; 2335 2336 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit); 2337 if (ret) { 2338 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n"); 2339 return ret; 2340 } 2341 /* convert from milliwatt to watt */ 2342 if (current_power_limit) 2343 *current_power_limit = ppt_limit / 1000; 2344 if (default_power_limit) 2345 *default_power_limit = ppt_limit / 1000; 2346 if (max_power_limit) 2347 *max_power_limit = 29; 2348 if (min_power_limit) 2349 *min_power_limit = 0; 2350 2351 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit); 2352 if (ret) { 2353 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n"); 2354 return ret; 2355 } 2356 /* convert from milliwatt to watt */ 2357 power_context->current_fast_ppt_limit = 2358 power_context->default_fast_ppt_limit = ppt_limit / 1000; 2359 power_context->max_fast_ppt_limit = 30; 2360 2361 return ret; 2362 } 2363 2364 static int vangogh_get_ppt_limit(struct smu_context *smu, 2365 uint32_t *ppt_limit, 2366 enum smu_ppt_limit_type type, 2367 enum smu_ppt_limit_level level) 2368 { 2369 struct smu_11_5_power_context *power_context = 2370 smu->smu_power.power_context; 2371 2372 if (!power_context) 2373 return -EOPNOTSUPP; 2374 2375 if (type == SMU_FAST_PPT_LIMIT) { 2376 switch (level) { 2377 case SMU_PPT_LIMIT_MAX: 2378 *ppt_limit = power_context->max_fast_ppt_limit; 2379 break; 2380 case SMU_PPT_LIMIT_CURRENT: 2381 *ppt_limit = power_context->current_fast_ppt_limit; 2382 break; 2383 case SMU_PPT_LIMIT_DEFAULT: 2384 *ppt_limit = power_context->default_fast_ppt_limit; 2385 break; 2386 default: 2387 break; 2388 } 2389 } 2390 2391 return 0; 2392 } 2393 2394 static int vangogh_set_power_limit(struct smu_context *smu, 2395 enum smu_ppt_limit_type limit_type, 2396 uint32_t ppt_limit) 2397 { 2398 struct smu_11_5_power_context *power_context = 2399 smu->smu_power.power_context; 2400 int ret = 0; 2401 2402 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 2403 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 2404 return -EOPNOTSUPP; 2405 } 2406 2407 switch (limit_type) { 2408 case SMU_DEFAULT_PPT_LIMIT: 2409 ret = smu_cmn_send_smc_msg_with_param(smu, 2410 SMU_MSG_SetSlowPPTLimit, 2411 ppt_limit * 1000, /* convert from watt to milliwatt */ 2412 NULL); 2413 if (ret) 2414 return ret; 2415 2416 smu->current_power_limit = ppt_limit; 2417 break; 2418 case SMU_FAST_PPT_LIMIT: 2419 ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24); 2420 if (ppt_limit > power_context->max_fast_ppt_limit) { 2421 dev_err(smu->adev->dev, 2422 "New power limit (%d) is over the max allowed %d\n", 2423 ppt_limit, power_context->max_fast_ppt_limit); 2424 return ret; 2425 } 2426 2427 ret = smu_cmn_send_smc_msg_with_param(smu, 2428 SMU_MSG_SetFastPPTLimit, 2429 ppt_limit * 1000, /* convert from watt to milliwatt */ 2430 NULL); 2431 if (ret) 2432 return ret; 2433 2434 power_context->current_fast_ppt_limit = ppt_limit; 2435 break; 2436 default: 2437 return -EINVAL; 2438 } 2439 2440 return ret; 2441 } 2442 2443 /** 2444 * vangogh_set_gfxoff_residency 2445 * 2446 * @smu: amdgpu_device pointer 2447 * @start: start/stop residency log 2448 * 2449 * This function will be used to log gfxoff residency 2450 * 2451 * 2452 * Returns standard response codes. 2453 */ 2454 static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start) 2455 { 2456 int ret = 0; 2457 u32 residency; 2458 struct amdgpu_device *adev = smu->adev; 2459 2460 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 2461 return 0; 2462 2463 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency, 2464 start, &residency); 2465 if (ret) 2466 return ret; 2467 2468 if (!start) 2469 adev->gfx.gfx_off_residency = residency; 2470 2471 return ret; 2472 } 2473 2474 /** 2475 * vangogh_get_gfxoff_residency 2476 * 2477 * @smu: amdgpu_device pointer 2478 * @residency: placeholder for return value 2479 * 2480 * This function will be used to get gfxoff residency. 2481 * 2482 * Returns standard response codes. 2483 */ 2484 static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency) 2485 { 2486 struct amdgpu_device *adev = smu->adev; 2487 2488 *residency = adev->gfx.gfx_off_residency; 2489 2490 return 0; 2491 } 2492 2493 /** 2494 * vangogh_get_gfxoff_entrycount - get gfxoff entry count 2495 * 2496 * @smu: amdgpu_device pointer 2497 * @entrycount: placeholder for return value 2498 * 2499 * This function will be used to get gfxoff entry count 2500 * 2501 * Returns standard response codes. 2502 */ 2503 static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t *entrycount) 2504 { 2505 int ret = 0, value = 0; 2506 struct amdgpu_device *adev = smu->adev; 2507 2508 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 2509 return 0; 2510 2511 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryCount, &value); 2512 *entrycount = value + adev->gfx.gfx_off_entrycount; 2513 2514 return ret; 2515 } 2516 2517 static const struct pptable_funcs vangogh_ppt_funcs = { 2518 2519 .check_fw_status = smu_v11_0_check_fw_status, 2520 .check_fw_version = smu_v11_0_check_fw_version, 2521 .init_smc_tables = vangogh_init_smc_tables, 2522 .fini_smc_tables = smu_v11_0_fini_smc_tables, 2523 .init_power = smu_v11_0_init_power, 2524 .fini_power = smu_v11_0_fini_power, 2525 .register_irq_handler = smu_v11_0_register_irq_handler, 2526 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 2527 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2528 .send_smc_msg = smu_cmn_send_smc_msg, 2529 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable, 2530 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable, 2531 .is_dpm_running = vangogh_is_dpm_running, 2532 .read_sensor = vangogh_read_sensor, 2533 .get_apu_thermal_limit = vangogh_get_apu_thermal_limit, 2534 .set_apu_thermal_limit = vangogh_set_apu_thermal_limit, 2535 .get_enabled_mask = smu_cmn_get_enabled_mask, 2536 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2537 .set_watermarks_table = vangogh_set_watermarks_table, 2538 .set_driver_table_location = smu_v11_0_set_driver_table_location, 2539 .interrupt_work = smu_v11_0_interrupt_work, 2540 .get_gpu_metrics = vangogh_common_get_gpu_metrics, 2541 .od_edit_dpm_table = vangogh_od_edit_dpm_table, 2542 .print_clk_levels = vangogh_common_print_clk_levels, 2543 .set_default_dpm_table = vangogh_set_default_dpm_tables, 2544 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters, 2545 .notify_rlc_state = vangogh_notify_rlc_state, 2546 .feature_is_enabled = smu_cmn_feature_is_enabled, 2547 .set_power_profile_mode = vangogh_set_power_profile_mode, 2548 .get_power_profile_mode = vangogh_get_power_profile_mode, 2549 .get_dpm_clock_table = vangogh_get_dpm_clock_table, 2550 .force_clk_levels = vangogh_force_clk_levels, 2551 .set_performance_level = vangogh_set_performance_level, 2552 .post_init = vangogh_post_smu_init, 2553 .mode2_reset = vangogh_mode2_reset, 2554 .gfx_off_control = smu_v11_0_gfx_off_control, 2555 .get_gfx_off_status = vangogh_get_gfxoff_status, 2556 .get_gfx_off_entrycount = vangogh_get_gfxoff_entrycount, 2557 .get_gfx_off_residency = vangogh_get_gfxoff_residency, 2558 .set_gfx_off_residency = vangogh_set_gfxoff_residency, 2559 .get_ppt_limit = vangogh_get_ppt_limit, 2560 .get_power_limit = vangogh_get_power_limit, 2561 .set_power_limit = vangogh_set_power_limit, 2562 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 2563 }; 2564 2565 void vangogh_set_ppt_funcs(struct smu_context *smu) 2566 { 2567 smu->ppt_funcs = &vangogh_ppt_funcs; 2568 smu->message_map = vangogh_message_map; 2569 smu->feature_map = vangogh_feature_mask_map; 2570 smu->table_map = vangogh_table_map; 2571 smu->workload_map = vangogh_workload_map; 2572 smu->is_apu = true; 2573 smu_v11_0_set_smu_mailbox_registers(smu); 2574 } 2575