1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_dpm.h" 31 #include "amdgpu_smu.h" 32 #include "atomfirmware.h" 33 #include "amdgpu_atomfirmware.h" 34 #include "amdgpu_atombios.h" 35 #include "soc15_common.h" 36 #include "smu_v11_0.h" 37 #include "smu11_driver_if_navi10.h" 38 #include "atom.h" 39 #include "navi10_ppt.h" 40 #include "smu_v11_0_pptable.h" 41 #include "smu_v11_0_ppsmc.h" 42 #include "nbio/nbio_2_3_offset.h" 43 #include "nbio/nbio_2_3_sh_mask.h" 44 #include "thm/thm_11_0_2_offset.h" 45 #include "thm/thm_11_0_2_sh_mask.h" 46 47 #include "asic_reg/mp/mp_11_0_sh_mask.h" 48 #include "smu_cmn.h" 49 #include "smu_11_0_cdr_table.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 #define FEATURE_MASK(feature) (1ULL << feature) 62 #define SMC_DPM_FEATURE ( \ 63 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) 71 72 #define SMU_11_0_GFX_BUSY_THRESHOLD 15 73 74 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = { 75 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 76 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 77 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 78 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 79 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 80 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 81 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 82 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 0), 83 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 0), 84 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0), 85 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0), 86 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 87 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 88 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 0), 89 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 90 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 91 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 92 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 93 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 94 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 95 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 96 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 97 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0), 98 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc, 0), 99 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 100 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 101 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 102 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 103 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 104 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 105 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 106 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 107 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig, 0), 108 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0), 109 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0), 110 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0), 111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 112 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk, 0), 113 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 114 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 115 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0), 116 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0), 117 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 118 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 119 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 120 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 121 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt, 0), 122 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays, 0), 123 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 124 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 125 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 126 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 127 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 128 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 129 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 130 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 131 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0), 132 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0), 133 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 134 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 135 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 136 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 137 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0), 138 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 139 MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALDisableDummyPstateChange, 0), 140 MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0), 141 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 142 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 143 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 144 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0), 145 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0), 146 MSG_MAP(GET_UMC_FW_WA, PPSMC_MSG_GetUMCFWWA, 0), 147 }; 148 149 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = { 150 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 151 CLK_MAP(SCLK, PPCLK_GFXCLK), 152 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 153 CLK_MAP(FCLK, PPCLK_SOCCLK), 154 CLK_MAP(UCLK, PPCLK_UCLK), 155 CLK_MAP(MCLK, PPCLK_UCLK), 156 CLK_MAP(DCLK, PPCLK_DCLK), 157 CLK_MAP(VCLK, PPCLK_VCLK), 158 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), 159 CLK_MAP(DISPCLK, PPCLK_DISPCLK), 160 CLK_MAP(PIXCLK, PPCLK_PIXCLK), 161 CLK_MAP(PHYCLK, PPCLK_PHYCLK), 162 }; 163 164 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = { 165 FEA_MAP(DPM_PREFETCHER), 166 FEA_MAP(DPM_GFXCLK), 167 FEA_MAP(DPM_GFX_PACE), 168 FEA_MAP(DPM_UCLK), 169 FEA_MAP(DPM_SOCCLK), 170 FEA_MAP(DPM_MP0CLK), 171 FEA_MAP(DPM_LINK), 172 FEA_MAP(DPM_DCEFCLK), 173 FEA_MAP(MEM_VDDCI_SCALING), 174 FEA_MAP(MEM_MVDD_SCALING), 175 FEA_MAP(DS_GFXCLK), 176 FEA_MAP(DS_SOCCLK), 177 FEA_MAP(DS_LCLK), 178 FEA_MAP(DS_DCEFCLK), 179 FEA_MAP(DS_UCLK), 180 FEA_MAP(GFX_ULV), 181 FEA_MAP(FW_DSTATE), 182 FEA_MAP(GFXOFF), 183 FEA_MAP(BACO), 184 FEA_MAP(VCN_PG), 185 FEA_MAP(JPEG_PG), 186 FEA_MAP(USB_PG), 187 FEA_MAP(RSMU_SMN_CG), 188 FEA_MAP(PPT), 189 FEA_MAP(TDC), 190 FEA_MAP(GFX_EDC), 191 FEA_MAP(APCC_PLUS), 192 FEA_MAP(GTHR), 193 FEA_MAP(ACDC), 194 FEA_MAP(VR0HOT), 195 FEA_MAP(VR1HOT), 196 FEA_MAP(FW_CTF), 197 FEA_MAP(FAN_CONTROL), 198 FEA_MAP(THERMAL), 199 FEA_MAP(GFX_DCS), 200 FEA_MAP(RM), 201 FEA_MAP(LED_DISPLAY), 202 FEA_MAP(GFX_SS), 203 FEA_MAP(OUT_OF_BAND_MONITOR), 204 FEA_MAP(TEMP_DEPENDENT_VMIN), 205 FEA_MAP(MMHUB_PG), 206 FEA_MAP(ATHUB_PG), 207 FEA_MAP(APCC_DFLL), 208 }; 209 210 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = { 211 TAB_MAP(PPTABLE), 212 TAB_MAP(WATERMARKS), 213 TAB_MAP(AVFS), 214 TAB_MAP(AVFS_PSM_DEBUG), 215 TAB_MAP(AVFS_FUSE_OVERRIDE), 216 TAB_MAP(PMSTATUSLOG), 217 TAB_MAP(SMU_METRICS), 218 TAB_MAP(DRIVER_SMU_CONFIG), 219 TAB_MAP(ACTIVITY_MONITOR_COEFF), 220 TAB_MAP(OVERDRIVE), 221 TAB_MAP(I2C_COMMANDS), 222 TAB_MAP(PACE), 223 }; 224 225 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 226 PWR_MAP(AC), 227 PWR_MAP(DC), 228 }; 229 230 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 231 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 232 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 238 }; 239 240 static const uint8_t navi1x_throttler_map[] = { 241 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 242 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 243 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 244 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 245 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 246 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 247 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 248 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 249 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 250 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 251 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 252 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 253 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 254 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 255 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 256 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 257 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), 258 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 259 }; 260 261 262 static bool is_asic_secure(struct smu_context *smu) 263 { 264 struct amdgpu_device *adev = smu->adev; 265 bool is_secure = true; 266 uint32_t mp0_fw_intf; 267 268 mp0_fw_intf = RREG32_PCIE(MP0_Public | 269 (smnMP0_FW_INTF & 0xffffffff)); 270 271 if (!(mp0_fw_intf & (1 << 19))) 272 is_secure = false; 273 274 return is_secure; 275 } 276 277 static int 278 navi10_get_allowed_feature_mask(struct smu_context *smu, 279 uint32_t *feature_mask, uint32_t num) 280 { 281 struct amdgpu_device *adev = smu->adev; 282 283 if (num > 2) 284 return -EINVAL; 285 286 memset(feature_mask, 0, sizeof(uint32_t) * num); 287 288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 289 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) 290 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) 291 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 292 | FEATURE_MASK(FEATURE_PPT_BIT) 293 | FEATURE_MASK(FEATURE_TDC_BIT) 294 | FEATURE_MASK(FEATURE_GFX_EDC_BIT) 295 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT) 296 | FEATURE_MASK(FEATURE_VR0HOT_BIT) 297 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) 298 | FEATURE_MASK(FEATURE_THERMAL_BIT) 299 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) 300 | FEATURE_MASK(FEATURE_DS_LCLK_BIT) 301 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) 302 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) 303 | FEATURE_MASK(FEATURE_BACO_BIT) 304 | FEATURE_MASK(FEATURE_GFX_SS_BIT) 305 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) 306 | FEATURE_MASK(FEATURE_FW_CTF_BIT) 307 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT) 308 | FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT); 309 310 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) 311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 312 313 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 315 316 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 318 319 if (adev->pm.pp_feature & PP_ULV_MASK) 320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 321 322 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 324 325 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 327 328 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); 330 331 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 333 334 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN) 335 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); 336 337 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 338 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT); 339 340 if (smu->dc_controlled_by_gpio) 341 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); 342 343 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 344 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 345 346 /* DPM UCLK enablement should be skipped for navi10 A0 secure board */ 347 if (!(is_asic_secure(smu) && 348 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && 349 (adev->rev_id == 0)) && 350 (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) 351 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 352 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) 353 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); 354 355 /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */ 356 if (is_asic_secure(smu) && 357 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && 358 (adev->rev_id == 0)) 359 *(uint64_t *)feature_mask &= 360 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); 361 362 return 0; 363 } 364 365 static void navi10_check_bxco_support(struct smu_context *smu) 366 { 367 struct smu_table_context *table_context = &smu->smu_table; 368 struct smu_11_0_powerplay_table *powerplay_table = 369 table_context->power_play_table; 370 struct smu_baco_context *smu_baco = &smu->smu_baco; 371 struct amdgpu_device *adev = smu->adev; 372 uint32_t val; 373 374 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || 375 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) { 376 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 377 smu_baco->platform_support = 378 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : 379 false; 380 } 381 } 382 383 static int navi10_check_powerplay_table(struct smu_context *smu) 384 { 385 struct smu_table_context *table_context = &smu->smu_table; 386 struct smu_11_0_powerplay_table *powerplay_table = 387 table_context->power_play_table; 388 389 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC) 390 smu->dc_controlled_by_gpio = true; 391 392 navi10_check_bxco_support(smu); 393 394 table_context->thermal_controller_type = 395 powerplay_table->thermal_controller_type; 396 397 /* 398 * Instead of having its own buffer space and get overdrive_table copied, 399 * smu->od_settings just points to the actual overdrive_table 400 */ 401 smu->od_settings = &powerplay_table->overdrive_table; 402 403 return 0; 404 } 405 406 static int navi10_append_powerplay_table(struct smu_context *smu) 407 { 408 struct amdgpu_device *adev = smu->adev; 409 struct smu_table_context *table_context = &smu->smu_table; 410 PPTable_t *smc_pptable = table_context->driver_pptable; 411 struct atom_smc_dpm_info_v4_5 *smc_dpm_table; 412 struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7; 413 int index, ret; 414 415 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 416 smc_dpm_info); 417 418 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL, 419 (uint8_t **)&smc_dpm_table); 420 if (ret) 421 return ret; 422 423 dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 424 smc_dpm_table->table_header.format_revision, 425 smc_dpm_table->table_header.content_revision); 426 427 if (smc_dpm_table->table_header.format_revision != 4) { 428 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n"); 429 return -EINVAL; 430 } 431 432 switch (smc_dpm_table->table_header.content_revision) { 433 case 5: /* nv10 and nv14 */ 434 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved, 435 smc_dpm_table, I2cControllers); 436 break; 437 case 7: /* nv12 */ 438 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL, 439 (uint8_t **)&smc_dpm_table_v4_7); 440 if (ret) 441 return ret; 442 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved, 443 smc_dpm_table_v4_7, I2cControllers); 444 break; 445 default: 446 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n", 447 smc_dpm_table->table_header.content_revision); 448 return -EINVAL; 449 } 450 451 if (adev->pm.pp_feature & PP_GFXOFF_MASK) { 452 /* TODO: remove it once SMU fw fix it */ 453 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN; 454 } 455 456 return 0; 457 } 458 459 static int navi10_store_powerplay_table(struct smu_context *smu) 460 { 461 struct smu_table_context *table_context = &smu->smu_table; 462 struct smu_11_0_powerplay_table *powerplay_table = 463 table_context->power_play_table; 464 465 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 466 sizeof(PPTable_t)); 467 468 return 0; 469 } 470 471 static int navi10_setup_pptable(struct smu_context *smu) 472 { 473 int ret = 0; 474 475 ret = smu_v11_0_setup_pptable(smu); 476 if (ret) 477 return ret; 478 479 ret = navi10_store_powerplay_table(smu); 480 if (ret) 481 return ret; 482 483 ret = navi10_append_powerplay_table(smu); 484 if (ret) 485 return ret; 486 487 ret = navi10_check_powerplay_table(smu); 488 if (ret) 489 return ret; 490 491 return ret; 492 } 493 494 static int navi10_tables_init(struct smu_context *smu) 495 { 496 struct smu_table_context *smu_table = &smu->smu_table; 497 struct smu_table *tables = smu_table->tables; 498 struct smu_table *dummy_read_1_table = 499 &smu_table->dummy_read_1_table; 500 501 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 502 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 503 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 504 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 505 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t), 506 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 507 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 508 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 509 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 510 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 511 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 512 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 513 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 514 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, 515 AMDGPU_GEM_DOMAIN_VRAM); 516 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfig_t), 517 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 518 519 dummy_read_1_table->size = 0x40000; 520 dummy_read_1_table->align = PAGE_SIZE; 521 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 522 523 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t), 524 GFP_KERNEL); 525 if (!smu_table->metrics_table) 526 goto err0_out; 527 smu_table->metrics_time = 0; 528 529 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 530 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 531 if (!smu_table->gpu_metrics_table) 532 goto err1_out; 533 534 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 535 if (!smu_table->watermarks_table) 536 goto err2_out; 537 538 smu_table->driver_smu_config_table = 539 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL); 540 if (!smu_table->driver_smu_config_table) 541 goto err3_out; 542 543 return 0; 544 545 err3_out: 546 kfree(smu_table->watermarks_table); 547 err2_out: 548 kfree(smu_table->gpu_metrics_table); 549 err1_out: 550 kfree(smu_table->metrics_table); 551 err0_out: 552 return -ENOMEM; 553 } 554 555 static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu, 556 MetricsMember_t member, 557 uint32_t *value) 558 { 559 struct smu_table_context *smu_table = &smu->smu_table; 560 SmuMetrics_legacy_t *metrics = 561 (SmuMetrics_legacy_t *)smu_table->metrics_table; 562 int ret = 0; 563 564 ret = smu_cmn_get_metrics_table(smu, 565 NULL, 566 false); 567 if (ret) 568 return ret; 569 570 switch (member) { 571 case METRICS_CURR_GFXCLK: 572 *value = metrics->CurrClock[PPCLK_GFXCLK]; 573 break; 574 case METRICS_CURR_SOCCLK: 575 *value = metrics->CurrClock[PPCLK_SOCCLK]; 576 break; 577 case METRICS_CURR_UCLK: 578 *value = metrics->CurrClock[PPCLK_UCLK]; 579 break; 580 case METRICS_CURR_VCLK: 581 *value = metrics->CurrClock[PPCLK_VCLK]; 582 break; 583 case METRICS_CURR_DCLK: 584 *value = metrics->CurrClock[PPCLK_DCLK]; 585 break; 586 case METRICS_CURR_DCEFCLK: 587 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 588 break; 589 case METRICS_AVERAGE_GFXCLK: 590 *value = metrics->AverageGfxclkFrequency; 591 break; 592 case METRICS_AVERAGE_SOCCLK: 593 *value = metrics->AverageSocclkFrequency; 594 break; 595 case METRICS_AVERAGE_UCLK: 596 *value = metrics->AverageUclkFrequency; 597 break; 598 case METRICS_AVERAGE_GFXACTIVITY: 599 *value = metrics->AverageGfxActivity; 600 break; 601 case METRICS_AVERAGE_MEMACTIVITY: 602 *value = metrics->AverageUclkActivity; 603 break; 604 case METRICS_AVERAGE_SOCKETPOWER: 605 *value = metrics->AverageSocketPower << 8; 606 break; 607 case METRICS_TEMPERATURE_EDGE: 608 *value = metrics->TemperatureEdge * 609 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 610 break; 611 case METRICS_TEMPERATURE_HOTSPOT: 612 *value = metrics->TemperatureHotspot * 613 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 614 break; 615 case METRICS_TEMPERATURE_MEM: 616 *value = metrics->TemperatureMem * 617 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 618 break; 619 case METRICS_TEMPERATURE_VRGFX: 620 *value = metrics->TemperatureVrGfx * 621 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 622 break; 623 case METRICS_TEMPERATURE_VRSOC: 624 *value = metrics->TemperatureVrSoc * 625 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 626 break; 627 case METRICS_THROTTLER_STATUS: 628 *value = metrics->ThrottlerStatus; 629 break; 630 case METRICS_CURR_FANSPEED: 631 *value = metrics->CurrFanSpeed; 632 break; 633 default: 634 *value = UINT_MAX; 635 break; 636 } 637 638 return ret; 639 } 640 641 static int navi10_get_smu_metrics_data(struct smu_context *smu, 642 MetricsMember_t member, 643 uint32_t *value) 644 { 645 struct smu_table_context *smu_table = &smu->smu_table; 646 SmuMetrics_t *metrics = 647 (SmuMetrics_t *)smu_table->metrics_table; 648 int ret = 0; 649 650 ret = smu_cmn_get_metrics_table(smu, 651 NULL, 652 false); 653 if (ret) 654 return ret; 655 656 switch (member) { 657 case METRICS_CURR_GFXCLK: 658 *value = metrics->CurrClock[PPCLK_GFXCLK]; 659 break; 660 case METRICS_CURR_SOCCLK: 661 *value = metrics->CurrClock[PPCLK_SOCCLK]; 662 break; 663 case METRICS_CURR_UCLK: 664 *value = metrics->CurrClock[PPCLK_UCLK]; 665 break; 666 case METRICS_CURR_VCLK: 667 *value = metrics->CurrClock[PPCLK_VCLK]; 668 break; 669 case METRICS_CURR_DCLK: 670 *value = metrics->CurrClock[PPCLK_DCLK]; 671 break; 672 case METRICS_CURR_DCEFCLK: 673 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 674 break; 675 case METRICS_AVERAGE_GFXCLK: 676 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 677 *value = metrics->AverageGfxclkFrequencyPreDs; 678 else 679 *value = metrics->AverageGfxclkFrequencyPostDs; 680 break; 681 case METRICS_AVERAGE_SOCCLK: 682 *value = metrics->AverageSocclkFrequency; 683 break; 684 case METRICS_AVERAGE_UCLK: 685 *value = metrics->AverageUclkFrequencyPostDs; 686 break; 687 case METRICS_AVERAGE_GFXACTIVITY: 688 *value = metrics->AverageGfxActivity; 689 break; 690 case METRICS_AVERAGE_MEMACTIVITY: 691 *value = metrics->AverageUclkActivity; 692 break; 693 case METRICS_AVERAGE_SOCKETPOWER: 694 *value = metrics->AverageSocketPower << 8; 695 break; 696 case METRICS_TEMPERATURE_EDGE: 697 *value = metrics->TemperatureEdge * 698 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 699 break; 700 case METRICS_TEMPERATURE_HOTSPOT: 701 *value = metrics->TemperatureHotspot * 702 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 703 break; 704 case METRICS_TEMPERATURE_MEM: 705 *value = metrics->TemperatureMem * 706 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 707 break; 708 case METRICS_TEMPERATURE_VRGFX: 709 *value = metrics->TemperatureVrGfx * 710 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 711 break; 712 case METRICS_TEMPERATURE_VRSOC: 713 *value = metrics->TemperatureVrSoc * 714 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 715 break; 716 case METRICS_THROTTLER_STATUS: 717 *value = metrics->ThrottlerStatus; 718 break; 719 case METRICS_CURR_FANSPEED: 720 *value = metrics->CurrFanSpeed; 721 break; 722 default: 723 *value = UINT_MAX; 724 break; 725 } 726 727 return ret; 728 } 729 730 static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu, 731 MetricsMember_t member, 732 uint32_t *value) 733 { 734 struct smu_table_context *smu_table = &smu->smu_table; 735 SmuMetrics_NV12_legacy_t *metrics = 736 (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table; 737 int ret = 0; 738 739 ret = smu_cmn_get_metrics_table(smu, 740 NULL, 741 false); 742 if (ret) 743 return ret; 744 745 switch (member) { 746 case METRICS_CURR_GFXCLK: 747 *value = metrics->CurrClock[PPCLK_GFXCLK]; 748 break; 749 case METRICS_CURR_SOCCLK: 750 *value = metrics->CurrClock[PPCLK_SOCCLK]; 751 break; 752 case METRICS_CURR_UCLK: 753 *value = metrics->CurrClock[PPCLK_UCLK]; 754 break; 755 case METRICS_CURR_VCLK: 756 *value = metrics->CurrClock[PPCLK_VCLK]; 757 break; 758 case METRICS_CURR_DCLK: 759 *value = metrics->CurrClock[PPCLK_DCLK]; 760 break; 761 case METRICS_CURR_DCEFCLK: 762 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 763 break; 764 case METRICS_AVERAGE_GFXCLK: 765 *value = metrics->AverageGfxclkFrequency; 766 break; 767 case METRICS_AVERAGE_SOCCLK: 768 *value = metrics->AverageSocclkFrequency; 769 break; 770 case METRICS_AVERAGE_UCLK: 771 *value = metrics->AverageUclkFrequency; 772 break; 773 case METRICS_AVERAGE_GFXACTIVITY: 774 *value = metrics->AverageGfxActivity; 775 break; 776 case METRICS_AVERAGE_MEMACTIVITY: 777 *value = metrics->AverageUclkActivity; 778 break; 779 case METRICS_AVERAGE_SOCKETPOWER: 780 *value = metrics->AverageSocketPower << 8; 781 break; 782 case METRICS_TEMPERATURE_EDGE: 783 *value = metrics->TemperatureEdge * 784 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 785 break; 786 case METRICS_TEMPERATURE_HOTSPOT: 787 *value = metrics->TemperatureHotspot * 788 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 789 break; 790 case METRICS_TEMPERATURE_MEM: 791 *value = metrics->TemperatureMem * 792 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 793 break; 794 case METRICS_TEMPERATURE_VRGFX: 795 *value = metrics->TemperatureVrGfx * 796 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 797 break; 798 case METRICS_TEMPERATURE_VRSOC: 799 *value = metrics->TemperatureVrSoc * 800 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 801 break; 802 case METRICS_THROTTLER_STATUS: 803 *value = metrics->ThrottlerStatus; 804 break; 805 case METRICS_CURR_FANSPEED: 806 *value = metrics->CurrFanSpeed; 807 break; 808 default: 809 *value = UINT_MAX; 810 break; 811 } 812 813 return ret; 814 } 815 816 static int navi12_get_smu_metrics_data(struct smu_context *smu, 817 MetricsMember_t member, 818 uint32_t *value) 819 { 820 struct smu_table_context *smu_table = &smu->smu_table; 821 SmuMetrics_NV12_t *metrics = 822 (SmuMetrics_NV12_t *)smu_table->metrics_table; 823 int ret = 0; 824 825 ret = smu_cmn_get_metrics_table(smu, 826 NULL, 827 false); 828 if (ret) 829 return ret; 830 831 switch (member) { 832 case METRICS_CURR_GFXCLK: 833 *value = metrics->CurrClock[PPCLK_GFXCLK]; 834 break; 835 case METRICS_CURR_SOCCLK: 836 *value = metrics->CurrClock[PPCLK_SOCCLK]; 837 break; 838 case METRICS_CURR_UCLK: 839 *value = metrics->CurrClock[PPCLK_UCLK]; 840 break; 841 case METRICS_CURR_VCLK: 842 *value = metrics->CurrClock[PPCLK_VCLK]; 843 break; 844 case METRICS_CURR_DCLK: 845 *value = metrics->CurrClock[PPCLK_DCLK]; 846 break; 847 case METRICS_CURR_DCEFCLK: 848 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 849 break; 850 case METRICS_AVERAGE_GFXCLK: 851 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 852 *value = metrics->AverageGfxclkFrequencyPreDs; 853 else 854 *value = metrics->AverageGfxclkFrequencyPostDs; 855 break; 856 case METRICS_AVERAGE_SOCCLK: 857 *value = metrics->AverageSocclkFrequency; 858 break; 859 case METRICS_AVERAGE_UCLK: 860 *value = metrics->AverageUclkFrequencyPostDs; 861 break; 862 case METRICS_AVERAGE_GFXACTIVITY: 863 *value = metrics->AverageGfxActivity; 864 break; 865 case METRICS_AVERAGE_MEMACTIVITY: 866 *value = metrics->AverageUclkActivity; 867 break; 868 case METRICS_AVERAGE_SOCKETPOWER: 869 *value = metrics->AverageSocketPower << 8; 870 break; 871 case METRICS_TEMPERATURE_EDGE: 872 *value = metrics->TemperatureEdge * 873 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 874 break; 875 case METRICS_TEMPERATURE_HOTSPOT: 876 *value = metrics->TemperatureHotspot * 877 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 878 break; 879 case METRICS_TEMPERATURE_MEM: 880 *value = metrics->TemperatureMem * 881 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 882 break; 883 case METRICS_TEMPERATURE_VRGFX: 884 *value = metrics->TemperatureVrGfx * 885 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 886 break; 887 case METRICS_TEMPERATURE_VRSOC: 888 *value = metrics->TemperatureVrSoc * 889 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 890 break; 891 case METRICS_THROTTLER_STATUS: 892 *value = metrics->ThrottlerStatus; 893 break; 894 case METRICS_CURR_FANSPEED: 895 *value = metrics->CurrFanSpeed; 896 break; 897 default: 898 *value = UINT_MAX; 899 break; 900 } 901 902 return ret; 903 } 904 905 static int navi1x_get_smu_metrics_data(struct smu_context *smu, 906 MetricsMember_t member, 907 uint32_t *value) 908 { 909 struct amdgpu_device *adev = smu->adev; 910 int ret = 0; 911 912 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 913 case IP_VERSION(11, 0, 9): 914 if (smu->smc_fw_version > 0x00341C00) 915 ret = navi12_get_smu_metrics_data(smu, member, value); 916 else 917 ret = navi12_get_legacy_smu_metrics_data(smu, member, value); 918 break; 919 case IP_VERSION(11, 0, 0): 920 case IP_VERSION(11, 0, 5): 921 default: 922 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == 923 IP_VERSION(11, 0, 5)) && 924 smu->smc_fw_version > 0x00351F00) || 925 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == 926 IP_VERSION(11, 0, 0)) && 927 smu->smc_fw_version > 0x002A3B00)) 928 ret = navi10_get_smu_metrics_data(smu, member, value); 929 else 930 ret = navi10_get_legacy_smu_metrics_data(smu, member, value); 931 break; 932 } 933 934 return ret; 935 } 936 937 static int navi10_allocate_dpm_context(struct smu_context *smu) 938 { 939 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 940 941 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 942 GFP_KERNEL); 943 if (!smu_dpm->dpm_context) 944 return -ENOMEM; 945 946 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 947 948 return 0; 949 } 950 951 static int navi10_init_smc_tables(struct smu_context *smu) 952 { 953 int ret = 0; 954 955 ret = navi10_tables_init(smu); 956 if (ret) 957 return ret; 958 959 ret = navi10_allocate_dpm_context(smu); 960 if (ret) 961 return ret; 962 963 return smu_v11_0_init_smc_tables(smu); 964 } 965 966 static int navi10_set_default_dpm_table(struct smu_context *smu) 967 { 968 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 969 PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 970 struct smu_11_0_dpm_table *dpm_table; 971 int ret = 0; 972 973 /* socclk dpm table setup */ 974 dpm_table = &dpm_context->dpm_tables.soc_table; 975 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 976 ret = smu_v11_0_set_single_dpm_table(smu, 977 SMU_SOCCLK, 978 dpm_table); 979 if (ret) 980 return ret; 981 dpm_table->is_fine_grained = 982 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete; 983 } else { 984 dpm_table->count = 1; 985 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 986 dpm_table->dpm_levels[0].enabled = true; 987 dpm_table->min = dpm_table->dpm_levels[0].value; 988 dpm_table->max = dpm_table->dpm_levels[0].value; 989 } 990 991 /* gfxclk dpm table setup */ 992 dpm_table = &dpm_context->dpm_tables.gfx_table; 993 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 994 ret = smu_v11_0_set_single_dpm_table(smu, 995 SMU_GFXCLK, 996 dpm_table); 997 if (ret) 998 return ret; 999 dpm_table->is_fine_grained = 1000 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete; 1001 } else { 1002 dpm_table->count = 1; 1003 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 1004 dpm_table->dpm_levels[0].enabled = true; 1005 dpm_table->min = dpm_table->dpm_levels[0].value; 1006 dpm_table->max = dpm_table->dpm_levels[0].value; 1007 } 1008 1009 /* uclk dpm table setup */ 1010 dpm_table = &dpm_context->dpm_tables.uclk_table; 1011 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1012 ret = smu_v11_0_set_single_dpm_table(smu, 1013 SMU_UCLK, 1014 dpm_table); 1015 if (ret) 1016 return ret; 1017 dpm_table->is_fine_grained = 1018 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete; 1019 } else { 1020 dpm_table->count = 1; 1021 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 1022 dpm_table->dpm_levels[0].enabled = true; 1023 dpm_table->min = dpm_table->dpm_levels[0].value; 1024 dpm_table->max = dpm_table->dpm_levels[0].value; 1025 } 1026 1027 /* vclk dpm table setup */ 1028 dpm_table = &dpm_context->dpm_tables.vclk_table; 1029 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1030 ret = smu_v11_0_set_single_dpm_table(smu, 1031 SMU_VCLK, 1032 dpm_table); 1033 if (ret) 1034 return ret; 1035 dpm_table->is_fine_grained = 1036 !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete; 1037 } else { 1038 dpm_table->count = 1; 1039 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 1040 dpm_table->dpm_levels[0].enabled = true; 1041 dpm_table->min = dpm_table->dpm_levels[0].value; 1042 dpm_table->max = dpm_table->dpm_levels[0].value; 1043 } 1044 1045 /* dclk dpm table setup */ 1046 dpm_table = &dpm_context->dpm_tables.dclk_table; 1047 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1048 ret = smu_v11_0_set_single_dpm_table(smu, 1049 SMU_DCLK, 1050 dpm_table); 1051 if (ret) 1052 return ret; 1053 dpm_table->is_fine_grained = 1054 !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete; 1055 } else { 1056 dpm_table->count = 1; 1057 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 1058 dpm_table->dpm_levels[0].enabled = true; 1059 dpm_table->min = dpm_table->dpm_levels[0].value; 1060 dpm_table->max = dpm_table->dpm_levels[0].value; 1061 } 1062 1063 /* dcefclk dpm table setup */ 1064 dpm_table = &dpm_context->dpm_tables.dcef_table; 1065 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1066 ret = smu_v11_0_set_single_dpm_table(smu, 1067 SMU_DCEFCLK, 1068 dpm_table); 1069 if (ret) 1070 return ret; 1071 dpm_table->is_fine_grained = 1072 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete; 1073 } else { 1074 dpm_table->count = 1; 1075 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1076 dpm_table->dpm_levels[0].enabled = true; 1077 dpm_table->min = dpm_table->dpm_levels[0].value; 1078 dpm_table->max = dpm_table->dpm_levels[0].value; 1079 } 1080 1081 /* pixelclk dpm table setup */ 1082 dpm_table = &dpm_context->dpm_tables.pixel_table; 1083 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1084 ret = smu_v11_0_set_single_dpm_table(smu, 1085 SMU_PIXCLK, 1086 dpm_table); 1087 if (ret) 1088 return ret; 1089 dpm_table->is_fine_grained = 1090 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete; 1091 } else { 1092 dpm_table->count = 1; 1093 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1094 dpm_table->dpm_levels[0].enabled = true; 1095 dpm_table->min = dpm_table->dpm_levels[0].value; 1096 dpm_table->max = dpm_table->dpm_levels[0].value; 1097 } 1098 1099 /* displayclk dpm table setup */ 1100 dpm_table = &dpm_context->dpm_tables.display_table; 1101 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1102 ret = smu_v11_0_set_single_dpm_table(smu, 1103 SMU_DISPCLK, 1104 dpm_table); 1105 if (ret) 1106 return ret; 1107 dpm_table->is_fine_grained = 1108 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete; 1109 } else { 1110 dpm_table->count = 1; 1111 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1112 dpm_table->dpm_levels[0].enabled = true; 1113 dpm_table->min = dpm_table->dpm_levels[0].value; 1114 dpm_table->max = dpm_table->dpm_levels[0].value; 1115 } 1116 1117 /* phyclk dpm table setup */ 1118 dpm_table = &dpm_context->dpm_tables.phy_table; 1119 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1120 ret = smu_v11_0_set_single_dpm_table(smu, 1121 SMU_PHYCLK, 1122 dpm_table); 1123 if (ret) 1124 return ret; 1125 dpm_table->is_fine_grained = 1126 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete; 1127 } else { 1128 dpm_table->count = 1; 1129 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1130 dpm_table->dpm_levels[0].enabled = true; 1131 dpm_table->min = dpm_table->dpm_levels[0].value; 1132 dpm_table->max = dpm_table->dpm_levels[0].value; 1133 } 1134 1135 return 0; 1136 } 1137 1138 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, 1139 bool enable, 1140 int inst) 1141 { 1142 int ret = 0; 1143 1144 if (enable) { 1145 /* vcn dpm on is a prerequisite for vcn power gate messages */ 1146 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1147 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL); 1148 if (ret) 1149 return ret; 1150 } 1151 } else { 1152 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1153 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); 1154 if (ret) 1155 return ret; 1156 } 1157 } 1158 1159 return ret; 1160 } 1161 1162 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 1163 { 1164 int ret = 0; 1165 1166 if (enable) { 1167 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 1168 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL); 1169 if (ret) 1170 return ret; 1171 } 1172 } else { 1173 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 1174 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL); 1175 if (ret) 1176 return ret; 1177 } 1178 } 1179 1180 return ret; 1181 } 1182 1183 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, 1184 enum smu_clk_type clk_type, 1185 uint32_t *value) 1186 { 1187 MetricsMember_t member_type; 1188 int clk_id = 0; 1189 1190 clk_id = smu_cmn_to_asic_specific_index(smu, 1191 CMN2ASIC_MAPPING_CLK, 1192 clk_type); 1193 if (clk_id < 0) 1194 return clk_id; 1195 1196 switch (clk_id) { 1197 case PPCLK_GFXCLK: 1198 member_type = METRICS_CURR_GFXCLK; 1199 break; 1200 case PPCLK_UCLK: 1201 member_type = METRICS_CURR_UCLK; 1202 break; 1203 case PPCLK_SOCCLK: 1204 member_type = METRICS_CURR_SOCCLK; 1205 break; 1206 case PPCLK_VCLK: 1207 member_type = METRICS_CURR_VCLK; 1208 break; 1209 case PPCLK_DCLK: 1210 member_type = METRICS_CURR_DCLK; 1211 break; 1212 case PPCLK_DCEFCLK: 1213 member_type = METRICS_CURR_DCEFCLK; 1214 break; 1215 default: 1216 return -EINVAL; 1217 } 1218 1219 return navi1x_get_smu_metrics_data(smu, 1220 member_type, 1221 value); 1222 } 1223 1224 static int navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 1225 { 1226 PPTable_t *pptable = smu->smu_table.driver_pptable; 1227 DpmDescriptor_t *dpm_desc = NULL; 1228 int clk_index = 0; 1229 1230 clk_index = smu_cmn_to_asic_specific_index(smu, 1231 CMN2ASIC_MAPPING_CLK, 1232 clk_type); 1233 if (clk_index < 0) 1234 return clk_index; 1235 1236 dpm_desc = &pptable->DpmDescriptor[clk_index]; 1237 1238 /* 0 - Fine grained DPM, 1 - Discrete DPM */ 1239 return dpm_desc->SnapToDiscrete == 0 ? 1 : 0; 1240 } 1241 1242 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap) 1243 { 1244 return od_table->cap[cap]; 1245 } 1246 1247 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table, 1248 enum SMU_11_0_ODSETTING_ID setting, 1249 uint32_t *min, uint32_t *max) 1250 { 1251 if (min) 1252 *min = od_table->min[setting]; 1253 if (max) 1254 *max = od_table->max[setting]; 1255 } 1256 1257 static int navi10_emit_clk_levels(struct smu_context *smu, 1258 enum smu_clk_type clk_type, 1259 char *buf, 1260 int *offset) 1261 { 1262 uint16_t *curve_settings; 1263 int ret = 0; 1264 uint32_t cur_value = 0, value = 0; 1265 uint32_t freq_values[3] = {0}; 1266 uint32_t i, levels, mark_index = 0, count = 0; 1267 struct smu_table_context *table_context = &smu->smu_table; 1268 uint32_t gen_speed, lane_width; 1269 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1270 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1271 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; 1272 OverDriveTable_t *od_table = 1273 (OverDriveTable_t *)table_context->overdrive_table; 1274 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 1275 uint32_t min_value, max_value; 1276 1277 switch (clk_type) { 1278 case SMU_GFXCLK: 1279 case SMU_SCLK: 1280 case SMU_SOCCLK: 1281 case SMU_MCLK: 1282 case SMU_UCLK: 1283 case SMU_FCLK: 1284 case SMU_VCLK: 1285 case SMU_DCLK: 1286 case SMU_DCEFCLK: 1287 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1288 if (ret) 1289 return ret; 1290 1291 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1292 if (ret) 1293 return ret; 1294 1295 ret = navi10_is_support_fine_grained_dpm(smu, clk_type); 1296 if (ret < 0) 1297 return ret; 1298 1299 if (!ret) { 1300 for (i = 0; i < count; i++) { 1301 ret = smu_v11_0_get_dpm_freq_by_index(smu, 1302 clk_type, i, &value); 1303 if (ret) 1304 return ret; 1305 1306 *offset += sysfs_emit_at(buf, *offset, 1307 "%d: %uMhz %s\n", 1308 i, value, 1309 cur_value == value ? "*" : ""); 1310 } 1311 } else { 1312 ret = smu_v11_0_get_dpm_freq_by_index(smu, 1313 clk_type, 0, &freq_values[0]); 1314 if (ret) 1315 return ret; 1316 ret = smu_v11_0_get_dpm_freq_by_index(smu, 1317 clk_type, 1318 count - 1, 1319 &freq_values[2]); 1320 if (ret) 1321 return ret; 1322 1323 freq_values[1] = cur_value; 1324 mark_index = cur_value == freq_values[0] ? 0 : 1325 cur_value == freq_values[2] ? 2 : 1; 1326 1327 levels = 3; 1328 if (mark_index != 1) { 1329 levels = 2; 1330 freq_values[1] = freq_values[2]; 1331 } 1332 1333 for (i = 0; i < levels; i++) { 1334 *offset += sysfs_emit_at(buf, *offset, 1335 "%d: %uMhz %s\n", 1336 i, freq_values[i], 1337 i == mark_index ? "*" : ""); 1338 } 1339 } 1340 break; 1341 case SMU_PCIE: 1342 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1343 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1344 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1345 *offset += sysfs_emit_at(buf, *offset, "%d: %s %s %dMhz %s\n", i, 1346 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1347 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1348 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1349 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1350 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1351 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1352 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1353 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1354 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1355 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1356 pptable->LclkFreq[i], 1357 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1358 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1359 "*" : ""); 1360 } 1361 break; 1362 case SMU_OD_SCLK: 1363 if (!smu->od_enabled || !od_table || !od_settings) 1364 return -EOPNOTSUPP; 1365 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) 1366 break; 1367 *offset += sysfs_emit_at(buf, *offset, "OD_SCLK:\n0: %uMhz\n1: %uMhz\n", 1368 od_table->GfxclkFmin, od_table->GfxclkFmax); 1369 break; 1370 case SMU_OD_MCLK: 1371 if (!smu->od_enabled || !od_table || !od_settings) 1372 return -EOPNOTSUPP; 1373 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) 1374 break; 1375 *offset += sysfs_emit_at(buf, *offset, "OD_MCLK:\n1: %uMHz\n", od_table->UclkFmax); 1376 break; 1377 case SMU_OD_VDDC_CURVE: 1378 if (!smu->od_enabled || !od_table || !od_settings) 1379 return -EOPNOTSUPP; 1380 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) 1381 break; 1382 *offset += sysfs_emit_at(buf, *offset, "OD_VDDC_CURVE:\n"); 1383 for (i = 0; i < 3; i++) { 1384 switch (i) { 1385 case 0: 1386 curve_settings = &od_table->GfxclkFreq1; 1387 break; 1388 case 1: 1389 curve_settings = &od_table->GfxclkFreq2; 1390 break; 1391 case 2: 1392 curve_settings = &od_table->GfxclkFreq3; 1393 break; 1394 } 1395 *offset += sysfs_emit_at(buf, *offset, "%d: %uMHz %umV\n", 1396 i, curve_settings[0], 1397 curve_settings[1] / NAVI10_VOLTAGE_SCALE); 1398 } 1399 break; 1400 case SMU_OD_RANGE: 1401 if (!smu->od_enabled || !od_table || !od_settings) 1402 return -EOPNOTSUPP; 1403 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE"); 1404 1405 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 1406 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, 1407 &min_value, NULL); 1408 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, 1409 NULL, &max_value); 1410 *offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMhz %10uMhz\n", 1411 min_value, max_value); 1412 } 1413 1414 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 1415 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, 1416 &min_value, &max_value); 1417 *offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMhz %10uMhz\n", 1418 min_value, max_value); 1419 } 1420 1421 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 1422 navi10_od_setting_get_range(od_settings, 1423 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, 1424 &min_value, &max_value); 1425 *offset += sysfs_emit_at(buf, *offset, 1426 "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", 1427 min_value, max_value); 1428 navi10_od_setting_get_range(od_settings, 1429 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, 1430 &min_value, &max_value); 1431 *offset += sysfs_emit_at(buf, *offset, 1432 "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", 1433 min_value, max_value); 1434 navi10_od_setting_get_range(od_settings, 1435 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, 1436 &min_value, &max_value); 1437 *offset += sysfs_emit_at(buf, *offset, 1438 "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", 1439 min_value, max_value); 1440 navi10_od_setting_get_range(od_settings, 1441 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, 1442 &min_value, &max_value); 1443 *offset += sysfs_emit_at(buf, *offset, 1444 "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", 1445 min_value, max_value); 1446 navi10_od_setting_get_range(od_settings, 1447 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, 1448 &min_value, &max_value); 1449 *offset += sysfs_emit_at(buf, *offset, 1450 "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", 1451 min_value, max_value); 1452 navi10_od_setting_get_range(od_settings, 1453 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, 1454 &min_value, &max_value); 1455 *offset += sysfs_emit_at(buf, *offset, 1456 "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", 1457 min_value, max_value); 1458 } 1459 1460 break; 1461 default: 1462 break; 1463 } 1464 1465 return 0; 1466 } 1467 1468 static int navi10_print_clk_levels(struct smu_context *smu, 1469 enum smu_clk_type clk_type, char *buf) 1470 { 1471 uint16_t *curve_settings; 1472 int i, levels, size = 0, ret = 0; 1473 uint32_t cur_value = 0, value = 0, count = 0; 1474 uint32_t freq_values[3] = {0}; 1475 uint32_t mark_index = 0; 1476 struct smu_table_context *table_context = &smu->smu_table; 1477 uint32_t gen_speed, lane_width; 1478 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1479 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1480 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; 1481 OverDriveTable_t *od_table = 1482 (OverDriveTable_t *)table_context->overdrive_table; 1483 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 1484 uint32_t min_value, max_value; 1485 1486 smu_cmn_get_sysfs_buf(&buf, &size); 1487 1488 switch (clk_type) { 1489 case SMU_GFXCLK: 1490 case SMU_SCLK: 1491 case SMU_SOCCLK: 1492 case SMU_MCLK: 1493 case SMU_UCLK: 1494 case SMU_FCLK: 1495 case SMU_VCLK: 1496 case SMU_DCLK: 1497 case SMU_DCEFCLK: 1498 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1499 if (ret) 1500 return size; 1501 1502 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1503 if (ret) 1504 return size; 1505 1506 ret = navi10_is_support_fine_grained_dpm(smu, clk_type); 1507 if (ret < 0) 1508 return ret; 1509 1510 if (!ret) { 1511 for (i = 0; i < count; i++) { 1512 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); 1513 if (ret) 1514 return size; 1515 1516 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 1517 cur_value == value ? "*" : ""); 1518 } 1519 } else { 1520 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); 1521 if (ret) 1522 return size; 1523 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); 1524 if (ret) 1525 return size; 1526 1527 freq_values[1] = cur_value; 1528 mark_index = cur_value == freq_values[0] ? 0 : 1529 cur_value == freq_values[2] ? 2 : 1; 1530 1531 levels = 3; 1532 if (mark_index != 1) { 1533 levels = 2; 1534 freq_values[1] = freq_values[2]; 1535 } 1536 1537 for (i = 0; i < levels; i++) { 1538 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i], 1539 i == mark_index ? "*" : ""); 1540 } 1541 } 1542 break; 1543 case SMU_PCIE: 1544 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1545 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1546 for (i = 0; i < NUM_LINK_LEVELS; i++) 1547 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1548 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1549 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1550 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1551 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1552 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1553 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1554 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1555 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1556 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1557 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1558 pptable->LclkFreq[i], 1559 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1560 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1561 "*" : ""); 1562 break; 1563 case SMU_OD_SCLK: 1564 if (!smu->od_enabled || !od_table || !od_settings) 1565 break; 1566 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) 1567 break; 1568 size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); 1569 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", 1570 od_table->GfxclkFmin, od_table->GfxclkFmax); 1571 break; 1572 case SMU_OD_MCLK: 1573 if (!smu->od_enabled || !od_table || !od_settings) 1574 break; 1575 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) 1576 break; 1577 size += sysfs_emit_at(buf, size, "OD_MCLK:\n"); 1578 size += sysfs_emit_at(buf, size, "1: %uMHz\n", od_table->UclkFmax); 1579 break; 1580 case SMU_OD_VDDC_CURVE: 1581 if (!smu->od_enabled || !od_table || !od_settings) 1582 break; 1583 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) 1584 break; 1585 size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n"); 1586 for (i = 0; i < 3; i++) { 1587 switch (i) { 1588 case 0: 1589 curve_settings = &od_table->GfxclkFreq1; 1590 break; 1591 case 1: 1592 curve_settings = &od_table->GfxclkFreq2; 1593 break; 1594 case 2: 1595 curve_settings = &od_table->GfxclkFreq3; 1596 break; 1597 } 1598 size += sysfs_emit_at(buf, size, "%d: %uMHz %umV\n", 1599 i, curve_settings[0], 1600 curve_settings[1] / NAVI10_VOLTAGE_SCALE); 1601 } 1602 break; 1603 case SMU_OD_RANGE: 1604 if (!smu->od_enabled || !od_table || !od_settings) 1605 break; 1606 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1607 1608 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 1609 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, 1610 &min_value, NULL); 1611 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, 1612 NULL, &max_value); 1613 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 1614 min_value, max_value); 1615 } 1616 1617 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 1618 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, 1619 &min_value, &max_value); 1620 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n", 1621 min_value, max_value); 1622 } 1623 1624 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 1625 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, 1626 &min_value, &max_value); 1627 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", 1628 min_value, max_value); 1629 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, 1630 &min_value, &max_value); 1631 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", 1632 min_value, max_value); 1633 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, 1634 &min_value, &max_value); 1635 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", 1636 min_value, max_value); 1637 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, 1638 &min_value, &max_value); 1639 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", 1640 min_value, max_value); 1641 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, 1642 &min_value, &max_value); 1643 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", 1644 min_value, max_value); 1645 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, 1646 &min_value, &max_value); 1647 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", 1648 min_value, max_value); 1649 } 1650 1651 break; 1652 default: 1653 break; 1654 } 1655 1656 return size; 1657 } 1658 1659 static int navi10_force_clk_levels(struct smu_context *smu, 1660 enum smu_clk_type clk_type, uint32_t mask) 1661 { 1662 1663 int ret = 0; 1664 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 1665 1666 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1667 soft_max_level = mask ? (fls(mask) - 1) : 0; 1668 1669 switch (clk_type) { 1670 case SMU_GFXCLK: 1671 case SMU_SCLK: 1672 case SMU_SOCCLK: 1673 case SMU_MCLK: 1674 case SMU_UCLK: 1675 case SMU_FCLK: 1676 /* There is only 2 levels for fine grained DPM */ 1677 ret = navi10_is_support_fine_grained_dpm(smu, clk_type); 1678 if (ret < 0) 1679 return ret; 1680 1681 if (ret) { 1682 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1683 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1684 } 1685 1686 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 1687 if (ret) 1688 return 0; 1689 1690 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 1691 if (ret) 1692 return 0; 1693 1694 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false); 1695 if (ret) 1696 return 0; 1697 break; 1698 case SMU_DCEFCLK: 1699 dev_info(smu->adev->dev, "Setting DCEFCLK min/max dpm level is not supported!\n"); 1700 break; 1701 1702 default: 1703 break; 1704 } 1705 1706 return 0; 1707 } 1708 1709 static int navi10_populate_umd_state_clk(struct smu_context *smu) 1710 { 1711 struct smu_11_0_dpm_context *dpm_context = 1712 smu->smu_dpm.dpm_context; 1713 struct smu_11_0_dpm_table *gfx_table = 1714 &dpm_context->dpm_tables.gfx_table; 1715 struct smu_11_0_dpm_table *mem_table = 1716 &dpm_context->dpm_tables.uclk_table; 1717 struct smu_11_0_dpm_table *soc_table = 1718 &dpm_context->dpm_tables.soc_table; 1719 struct smu_umd_pstate_table *pstate_table = 1720 &smu->pstate_table; 1721 struct amdgpu_device *adev = smu->adev; 1722 uint32_t sclk_freq; 1723 1724 pstate_table->gfxclk_pstate.min = gfx_table->min; 1725 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1726 case IP_VERSION(11, 0, 0): 1727 switch (adev->pdev->revision) { 1728 case 0xf0: /* XTX */ 1729 case 0xc0: 1730 sclk_freq = NAVI10_PEAK_SCLK_XTX; 1731 break; 1732 case 0xf1: /* XT */ 1733 case 0xc1: 1734 sclk_freq = NAVI10_PEAK_SCLK_XT; 1735 break; 1736 default: /* XL */ 1737 sclk_freq = NAVI10_PEAK_SCLK_XL; 1738 break; 1739 } 1740 break; 1741 case IP_VERSION(11, 0, 5): 1742 switch (adev->pdev->revision) { 1743 case 0xc7: /* XT */ 1744 case 0xf4: 1745 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK; 1746 break; 1747 case 0xc1: /* XTM */ 1748 case 0xf2: 1749 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK; 1750 break; 1751 case 0xc3: /* XLM */ 1752 case 0xf3: 1753 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK; 1754 break; 1755 case 0xc5: /* XTX */ 1756 case 0xf6: 1757 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK; 1758 break; 1759 default: /* XL */ 1760 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK; 1761 break; 1762 } 1763 break; 1764 case IP_VERSION(11, 0, 9): 1765 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK; 1766 break; 1767 default: 1768 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value; 1769 break; 1770 } 1771 pstate_table->gfxclk_pstate.peak = sclk_freq; 1772 1773 pstate_table->uclk_pstate.min = mem_table->min; 1774 pstate_table->uclk_pstate.peak = mem_table->max; 1775 1776 pstate_table->socclk_pstate.min = soc_table->min; 1777 pstate_table->socclk_pstate.peak = soc_table->max; 1778 1779 if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK && 1780 mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK && 1781 soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) { 1782 pstate_table->gfxclk_pstate.standard = 1783 NAVI10_UMD_PSTATE_PROFILING_GFXCLK; 1784 pstate_table->uclk_pstate.standard = 1785 NAVI10_UMD_PSTATE_PROFILING_MEMCLK; 1786 pstate_table->socclk_pstate.standard = 1787 NAVI10_UMD_PSTATE_PROFILING_SOCCLK; 1788 } else { 1789 pstate_table->gfxclk_pstate.standard = 1790 pstate_table->gfxclk_pstate.min; 1791 pstate_table->uclk_pstate.standard = 1792 pstate_table->uclk_pstate.min; 1793 pstate_table->socclk_pstate.standard = 1794 pstate_table->socclk_pstate.min; 1795 } 1796 1797 return 0; 1798 } 1799 1800 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu, 1801 enum smu_clk_type clk_type, 1802 struct pp_clock_levels_with_latency *clocks) 1803 { 1804 int ret = 0, i = 0; 1805 uint32_t level_count = 0, freq = 0; 1806 1807 switch (clk_type) { 1808 case SMU_GFXCLK: 1809 case SMU_DCEFCLK: 1810 case SMU_SOCCLK: 1811 case SMU_MCLK: 1812 case SMU_UCLK: 1813 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count); 1814 if (ret) 1815 return ret; 1816 1817 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS); 1818 clocks->num_levels = level_count; 1819 1820 for (i = 0; i < level_count; i++) { 1821 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq); 1822 if (ret) 1823 return ret; 1824 1825 clocks->data[i].clocks_in_khz = freq * 1000; 1826 clocks->data[i].latency_in_us = 0; 1827 } 1828 break; 1829 default: 1830 break; 1831 } 1832 1833 return ret; 1834 } 1835 1836 static int navi10_pre_display_config_changed(struct smu_context *smu) 1837 { 1838 int ret = 0; 1839 uint32_t max_freq = 0; 1840 1841 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); 1842 if (ret) 1843 return ret; 1844 1845 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1846 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); 1847 if (ret) 1848 return ret; 1849 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); 1850 if (ret) 1851 return ret; 1852 } 1853 1854 return ret; 1855 } 1856 1857 static int navi10_display_config_changed(struct smu_context *smu) 1858 { 1859 int ret = 0; 1860 1861 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1862 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && 1863 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 1864 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 1865 smu->display_config->num_display, 1866 NULL); 1867 if (ret) 1868 return ret; 1869 } 1870 1871 return ret; 1872 } 1873 1874 static bool navi10_is_dpm_running(struct smu_context *smu) 1875 { 1876 int ret = 0; 1877 uint64_t feature_enabled; 1878 1879 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1880 if (ret) 1881 return false; 1882 1883 return !!(feature_enabled & SMC_DPM_FEATURE); 1884 } 1885 1886 static int navi10_get_fan_speed_rpm(struct smu_context *smu, 1887 uint32_t *speed) 1888 { 1889 int ret = 0; 1890 1891 if (!speed) 1892 return -EINVAL; 1893 1894 switch (smu_v11_0_get_fan_control_mode(smu)) { 1895 case AMD_FAN_CTRL_AUTO: 1896 ret = navi10_get_smu_metrics_data(smu, 1897 METRICS_CURR_FANSPEED, 1898 speed); 1899 break; 1900 default: 1901 ret = smu_v11_0_get_fan_speed_rpm(smu, 1902 speed); 1903 break; 1904 } 1905 1906 return ret; 1907 } 1908 1909 static int navi10_get_fan_parameters(struct smu_context *smu) 1910 { 1911 PPTable_t *pptable = smu->smu_table.driver_pptable; 1912 1913 smu->fan_max_rpm = pptable->FanMaximumRpm; 1914 1915 return 0; 1916 } 1917 1918 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf) 1919 { 1920 DpmActivityMonitorCoeffInt_t activity_monitor; 1921 uint32_t i, size = 0; 1922 int16_t workload_type = 0; 1923 static const char *title[] = { 1924 "PROFILE_INDEX(NAME)", 1925 "CLOCK_TYPE(NAME)", 1926 "FPS", 1927 "MinFreqType", 1928 "MinActiveFreqType", 1929 "MinActiveFreq", 1930 "BoosterFreqType", 1931 "BoosterFreq", 1932 "PD_Data_limit_c", 1933 "PD_Data_error_coeff", 1934 "PD_Data_error_rate_coeff"}; 1935 int result = 0; 1936 1937 if (!buf) 1938 return -EINVAL; 1939 1940 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1941 title[0], title[1], title[2], title[3], title[4], title[5], 1942 title[6], title[7], title[8], title[9], title[10]); 1943 1944 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1945 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1946 workload_type = smu_cmn_to_asic_specific_index(smu, 1947 CMN2ASIC_MAPPING_WORKLOAD, 1948 i); 1949 if (workload_type < 0) 1950 return -EINVAL; 1951 1952 result = smu_cmn_update_table(smu, 1953 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1954 (void *)(&activity_monitor), false); 1955 if (result) { 1956 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1957 return result; 1958 } 1959 1960 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 1961 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1962 1963 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1964 " ", 1965 0, 1966 "GFXCLK", 1967 activity_monitor.Gfx_FPS, 1968 activity_monitor.Gfx_MinFreqStep, 1969 activity_monitor.Gfx_MinActiveFreqType, 1970 activity_monitor.Gfx_MinActiveFreq, 1971 activity_monitor.Gfx_BoosterFreqType, 1972 activity_monitor.Gfx_BoosterFreq, 1973 activity_monitor.Gfx_PD_Data_limit_c, 1974 activity_monitor.Gfx_PD_Data_error_coeff, 1975 activity_monitor.Gfx_PD_Data_error_rate_coeff); 1976 1977 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1978 " ", 1979 1, 1980 "SOCCLK", 1981 activity_monitor.Soc_FPS, 1982 activity_monitor.Soc_MinFreqStep, 1983 activity_monitor.Soc_MinActiveFreqType, 1984 activity_monitor.Soc_MinActiveFreq, 1985 activity_monitor.Soc_BoosterFreqType, 1986 activity_monitor.Soc_BoosterFreq, 1987 activity_monitor.Soc_PD_Data_limit_c, 1988 activity_monitor.Soc_PD_Data_error_coeff, 1989 activity_monitor.Soc_PD_Data_error_rate_coeff); 1990 1991 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1992 " ", 1993 2, 1994 "MEMCLK", 1995 activity_monitor.Mem_FPS, 1996 activity_monitor.Mem_MinFreqStep, 1997 activity_monitor.Mem_MinActiveFreqType, 1998 activity_monitor.Mem_MinActiveFreq, 1999 activity_monitor.Mem_BoosterFreqType, 2000 activity_monitor.Mem_BoosterFreq, 2001 activity_monitor.Mem_PD_Data_limit_c, 2002 activity_monitor.Mem_PD_Data_error_coeff, 2003 activity_monitor.Mem_PD_Data_error_rate_coeff); 2004 } 2005 2006 return size; 2007 } 2008 2009 #define NAVI10_CUSTOM_PARAMS_COUNT 10 2010 #define NAVI10_CUSTOM_PARAMS_CLOCKS_COUNT 3 2011 #define NAVI10_CUSTOM_PARAMS_SIZE (NAVI10_CUSTOM_PARAMS_CLOCKS_COUNT * NAVI10_CUSTOM_PARAMS_COUNT * sizeof(long)) 2012 2013 static int navi10_set_power_profile_mode_coeff(struct smu_context *smu, 2014 long *input) 2015 { 2016 DpmActivityMonitorCoeffInt_t activity_monitor; 2017 int ret, idx; 2018 2019 ret = smu_cmn_update_table(smu, 2020 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 2021 (void *)(&activity_monitor), false); 2022 if (ret) { 2023 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 2024 return ret; 2025 } 2026 2027 idx = 0 * NAVI10_CUSTOM_PARAMS_COUNT; 2028 if (input[idx]) { 2029 /* Gfxclk */ 2030 activity_monitor.Gfx_FPS = input[idx + 1]; 2031 activity_monitor.Gfx_MinFreqStep = input[idx + 2]; 2032 activity_monitor.Gfx_MinActiveFreqType = input[idx + 3]; 2033 activity_monitor.Gfx_MinActiveFreq = input[idx + 4]; 2034 activity_monitor.Gfx_BoosterFreqType = input[idx + 5]; 2035 activity_monitor.Gfx_BoosterFreq = input[idx + 6]; 2036 activity_monitor.Gfx_PD_Data_limit_c = input[idx + 7]; 2037 activity_monitor.Gfx_PD_Data_error_coeff = input[idx + 8]; 2038 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[idx + 9]; 2039 } 2040 idx = 1 * NAVI10_CUSTOM_PARAMS_COUNT; 2041 if (input[idx]) { 2042 /* Socclk */ 2043 activity_monitor.Soc_FPS = input[idx + 1]; 2044 activity_monitor.Soc_MinFreqStep = input[idx + 2]; 2045 activity_monitor.Soc_MinActiveFreqType = input[idx + 3]; 2046 activity_monitor.Soc_MinActiveFreq = input[idx + 4]; 2047 activity_monitor.Soc_BoosterFreqType = input[idx + 5]; 2048 activity_monitor.Soc_BoosterFreq = input[idx + 6]; 2049 activity_monitor.Soc_PD_Data_limit_c = input[idx + 7]; 2050 activity_monitor.Soc_PD_Data_error_coeff = input[idx + 8]; 2051 activity_monitor.Soc_PD_Data_error_rate_coeff = input[idx + 9]; 2052 } 2053 idx = 2 * NAVI10_CUSTOM_PARAMS_COUNT; 2054 if (input[idx]) { 2055 /* Memclk */ 2056 activity_monitor.Mem_FPS = input[idx + 1]; 2057 activity_monitor.Mem_MinFreqStep = input[idx + 2]; 2058 activity_monitor.Mem_MinActiveFreqType = input[idx + 3]; 2059 activity_monitor.Mem_MinActiveFreq = input[idx + 4]; 2060 activity_monitor.Mem_BoosterFreqType = input[idx + 5]; 2061 activity_monitor.Mem_BoosterFreq = input[idx + 6]; 2062 activity_monitor.Mem_PD_Data_limit_c = input[idx + 7]; 2063 activity_monitor.Mem_PD_Data_error_coeff = input[idx + 8]; 2064 activity_monitor.Mem_PD_Data_error_rate_coeff = input[idx + 9]; 2065 } 2066 2067 ret = smu_cmn_update_table(smu, 2068 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 2069 (void *)(&activity_monitor), true); 2070 if (ret) { 2071 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 2072 return ret; 2073 } 2074 2075 return ret; 2076 } 2077 2078 static int navi10_set_power_profile_mode(struct smu_context *smu, 2079 u32 workload_mask, 2080 long *custom_params, 2081 u32 custom_params_max_idx) 2082 { 2083 u32 backend_workload_mask = 0; 2084 int ret, idx = -1, i; 2085 2086 smu_cmn_get_backend_workload_mask(smu, workload_mask, 2087 &backend_workload_mask); 2088 2089 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) { 2090 if (!smu->custom_profile_params) { 2091 smu->custom_profile_params = kzalloc(NAVI10_CUSTOM_PARAMS_SIZE, GFP_KERNEL); 2092 if (!smu->custom_profile_params) 2093 return -ENOMEM; 2094 } 2095 if (custom_params && custom_params_max_idx) { 2096 if (custom_params_max_idx != NAVI10_CUSTOM_PARAMS_COUNT) 2097 return -EINVAL; 2098 if (custom_params[0] >= NAVI10_CUSTOM_PARAMS_CLOCKS_COUNT) 2099 return -EINVAL; 2100 idx = custom_params[0] * NAVI10_CUSTOM_PARAMS_COUNT; 2101 smu->custom_profile_params[idx] = 1; 2102 for (i = 1; i < custom_params_max_idx; i++) 2103 smu->custom_profile_params[idx + i] = custom_params[i]; 2104 } 2105 ret = navi10_set_power_profile_mode_coeff(smu, 2106 smu->custom_profile_params); 2107 if (ret) { 2108 if (idx != -1) 2109 smu->custom_profile_params[idx] = 0; 2110 return ret; 2111 } 2112 } else if (smu->custom_profile_params) { 2113 memset(smu->custom_profile_params, 0, NAVI10_CUSTOM_PARAMS_SIZE); 2114 } 2115 2116 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 2117 backend_workload_mask, NULL); 2118 if (ret) { 2119 dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n", 2120 workload_mask); 2121 if (idx != -1) 2122 smu->custom_profile_params[idx] = 0; 2123 return ret; 2124 } 2125 2126 return ret; 2127 } 2128 2129 static int navi10_notify_smc_display_config(struct smu_context *smu) 2130 { 2131 struct smu_clocks min_clocks = {0}; 2132 struct pp_display_clock_request clock_req; 2133 int ret = 0; 2134 2135 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; 2136 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; 2137 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 2138 2139 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 2140 clock_req.clock_type = amd_pp_dcef_clock; 2141 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; 2142 2143 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); 2144 if (!ret) { 2145 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { 2146 ret = smu_cmn_send_smc_msg_with_param(smu, 2147 SMU_MSG_SetMinDeepSleepDcefclk, 2148 min_clocks.dcef_clock_in_sr/100, 2149 NULL); 2150 if (ret) { 2151 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); 2152 return ret; 2153 } 2154 } 2155 } else { 2156 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); 2157 } 2158 } 2159 2160 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 2161 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); 2162 if (ret) { 2163 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); 2164 return ret; 2165 } 2166 } 2167 2168 return 0; 2169 } 2170 2171 static int navi10_set_watermarks_table(struct smu_context *smu, 2172 struct pp_smu_wm_range_sets *clock_ranges) 2173 { 2174 Watermarks_t *table = smu->smu_table.watermarks_table; 2175 int ret = 0; 2176 int i; 2177 2178 if (clock_ranges) { 2179 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 2180 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 2181 return -EINVAL; 2182 2183 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 2184 table->WatermarkRow[WM_DCEFCLK][i].MinClock = 2185 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 2186 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = 2187 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 2188 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = 2189 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 2190 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = 2191 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 2192 2193 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = 2194 clock_ranges->reader_wm_sets[i].wm_inst; 2195 } 2196 2197 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 2198 table->WatermarkRow[WM_SOCCLK][i].MinClock = 2199 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 2200 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 2201 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 2202 table->WatermarkRow[WM_SOCCLK][i].MinUclk = 2203 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 2204 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = 2205 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 2206 2207 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 2208 clock_ranges->writer_wm_sets[i].wm_inst; 2209 } 2210 2211 smu->watermarks_bitmap |= WATERMARKS_EXIST; 2212 } 2213 2214 /* pass data to smu controller */ 2215 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 2216 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 2217 ret = smu_cmn_write_watermarks_table(smu); 2218 if (ret) { 2219 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 2220 return ret; 2221 } 2222 smu->watermarks_bitmap |= WATERMARKS_LOADED; 2223 } 2224 2225 return 0; 2226 } 2227 2228 static int navi10_read_sensor(struct smu_context *smu, 2229 enum amd_pp_sensors sensor, 2230 void *data, uint32_t *size) 2231 { 2232 int ret = 0; 2233 struct smu_table_context *table_context = &smu->smu_table; 2234 PPTable_t *pptable = table_context->driver_pptable; 2235 2236 if (!data || !size) 2237 return -EINVAL; 2238 2239 switch (sensor) { 2240 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 2241 *(uint32_t *)data = pptable->FanMaximumRpm; 2242 *size = 4; 2243 break; 2244 case AMDGPU_PP_SENSOR_MEM_LOAD: 2245 ret = navi1x_get_smu_metrics_data(smu, 2246 METRICS_AVERAGE_MEMACTIVITY, 2247 (uint32_t *)data); 2248 *size = 4; 2249 break; 2250 case AMDGPU_PP_SENSOR_GPU_LOAD: 2251 ret = navi1x_get_smu_metrics_data(smu, 2252 METRICS_AVERAGE_GFXACTIVITY, 2253 (uint32_t *)data); 2254 *size = 4; 2255 break; 2256 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 2257 ret = navi1x_get_smu_metrics_data(smu, 2258 METRICS_AVERAGE_SOCKETPOWER, 2259 (uint32_t *)data); 2260 *size = 4; 2261 break; 2262 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 2263 ret = navi1x_get_smu_metrics_data(smu, 2264 METRICS_TEMPERATURE_HOTSPOT, 2265 (uint32_t *)data); 2266 *size = 4; 2267 break; 2268 case AMDGPU_PP_SENSOR_EDGE_TEMP: 2269 ret = navi1x_get_smu_metrics_data(smu, 2270 METRICS_TEMPERATURE_EDGE, 2271 (uint32_t *)data); 2272 *size = 4; 2273 break; 2274 case AMDGPU_PP_SENSOR_MEM_TEMP: 2275 ret = navi1x_get_smu_metrics_data(smu, 2276 METRICS_TEMPERATURE_MEM, 2277 (uint32_t *)data); 2278 *size = 4; 2279 break; 2280 case AMDGPU_PP_SENSOR_GFX_MCLK: 2281 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 2282 *(uint32_t *)data *= 100; 2283 *size = 4; 2284 break; 2285 case AMDGPU_PP_SENSOR_GFX_SCLK: 2286 ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data); 2287 *(uint32_t *)data *= 100; 2288 *size = 4; 2289 break; 2290 case AMDGPU_PP_SENSOR_VDDGFX: 2291 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 2292 *size = 4; 2293 break; 2294 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 2295 default: 2296 ret = -EOPNOTSUPP; 2297 break; 2298 } 2299 2300 return ret; 2301 } 2302 2303 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) 2304 { 2305 uint32_t num_discrete_levels = 0; 2306 uint16_t *dpm_levels = NULL; 2307 uint16_t i = 0; 2308 struct smu_table_context *table_context = &smu->smu_table; 2309 PPTable_t *driver_ppt = NULL; 2310 2311 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) 2312 return -EINVAL; 2313 2314 driver_ppt = table_context->driver_pptable; 2315 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels; 2316 dpm_levels = driver_ppt->FreqTableUclk; 2317 2318 if (num_discrete_levels == 0 || dpm_levels == NULL) 2319 return -EINVAL; 2320 2321 *num_states = num_discrete_levels; 2322 for (i = 0; i < num_discrete_levels; i++) { 2323 /* convert to khz */ 2324 *clocks_in_khz = (*dpm_levels) * 1000; 2325 clocks_in_khz++; 2326 dpm_levels++; 2327 } 2328 2329 return 0; 2330 } 2331 2332 static int navi10_get_thermal_temperature_range(struct smu_context *smu, 2333 struct smu_temperature_range *range) 2334 { 2335 struct smu_table_context *table_context = &smu->smu_table; 2336 struct smu_11_0_powerplay_table *powerplay_table = 2337 table_context->power_play_table; 2338 PPTable_t *pptable = smu->smu_table.driver_pptable; 2339 2340 if (!range) 2341 return -EINVAL; 2342 2343 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 2344 2345 range->max = pptable->TedgeLimit * 2346 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2347 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) * 2348 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2349 range->hotspot_crit_max = pptable->ThotspotLimit * 2350 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2351 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 2352 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2353 range->mem_crit_max = pptable->TmemLimit * 2354 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2355 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 2356 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2357 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 2358 2359 return 0; 2360 } 2361 2362 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu, 2363 bool disable_memory_clock_switch) 2364 { 2365 int ret = 0; 2366 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 2367 (struct smu_11_0_max_sustainable_clocks *) 2368 smu->smu_table.max_sustainable_clocks; 2369 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; 2370 uint32_t max_memory_clock = max_sustainable_clocks->uclock; 2371 2372 if (smu->disable_uclk_switch == disable_memory_clock_switch) 2373 return 0; 2374 2375 if (disable_memory_clock_switch) 2376 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); 2377 else 2378 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); 2379 2380 if (!ret) 2381 smu->disable_uclk_switch = disable_memory_clock_switch; 2382 2383 return ret; 2384 } 2385 2386 static int navi10_get_power_limit(struct smu_context *smu, 2387 uint32_t *current_power_limit, 2388 uint32_t *default_power_limit, 2389 uint32_t *max_power_limit, 2390 uint32_t *min_power_limit) 2391 { 2392 struct smu_11_0_powerplay_table *powerplay_table = 2393 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table; 2394 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 2395 PPTable_t *pptable = smu->smu_table.driver_pptable; 2396 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0; 2397 2398 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 2399 /* the last hope to figure out the ppt limit */ 2400 if (!pptable) { 2401 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); 2402 return -EINVAL; 2403 } 2404 power_limit = 2405 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; 2406 } 2407 2408 if (current_power_limit) 2409 *current_power_limit = power_limit; 2410 if (default_power_limit) 2411 *default_power_limit = power_limit; 2412 2413 if (powerplay_table) { 2414 if (smu->od_enabled && 2415 navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) { 2416 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 2417 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 2418 } else if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) { 2419 od_percent_upper = 0; 2420 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 2421 } 2422 } 2423 2424 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n", 2425 od_percent_upper, od_percent_lower, power_limit); 2426 2427 if (max_power_limit) { 2428 *max_power_limit = power_limit * (100 + od_percent_upper); 2429 *max_power_limit /= 100; 2430 } 2431 2432 if (min_power_limit) { 2433 *min_power_limit = power_limit * (100 - od_percent_lower); 2434 *min_power_limit /= 100; 2435 } 2436 2437 return 0; 2438 } 2439 2440 static int navi10_update_pcie_parameters(struct smu_context *smu, 2441 uint8_t pcie_gen_cap, 2442 uint8_t pcie_width_cap) 2443 { 2444 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 2445 PPTable_t *pptable = smu->smu_table.driver_pptable; 2446 uint32_t smu_pcie_arg; 2447 int ret = 0; 2448 int i; 2449 2450 /* lclk dpm table setup */ 2451 for (i = 0; i < MAX_PCIE_CONF; i++) { 2452 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i]; 2453 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; 2454 } 2455 2456 for (i = 0; i < NUM_LINK_LEVELS; i++) { 2457 if (pptable->PcieGenSpeed[i] > pcie_gen_cap || 2458 pptable->PcieLaneCount[i] > pcie_width_cap) { 2459 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; 2460 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; 2461 smu_pcie_arg = i << 16; 2462 smu_pcie_arg |= pcie_gen_cap << 8; 2463 smu_pcie_arg |= pcie_width_cap; 2464 ret = smu_cmn_send_smc_msg_with_param(smu, 2465 SMU_MSG_OverridePcieParameters, 2466 smu_pcie_arg, 2467 NULL); 2468 if (ret) 2469 break; 2470 } 2471 } 2472 2473 return ret; 2474 } 2475 2476 static inline void navi10_dump_od_table(struct smu_context *smu, 2477 OverDriveTable_t *od_table) 2478 { 2479 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 2480 dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1); 2481 dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2); 2482 dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3); 2483 dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax); 2484 dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct); 2485 } 2486 2487 static int navi10_od_setting_check_range(struct smu_context *smu, 2488 struct smu_11_0_overdrive_table *od_table, 2489 enum SMU_11_0_ODSETTING_ID setting, 2490 uint32_t value) 2491 { 2492 if (value < od_table->min[setting]) { 2493 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]); 2494 return -EINVAL; 2495 } 2496 if (value > od_table->max[setting]) { 2497 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]); 2498 return -EINVAL; 2499 } 2500 return 0; 2501 } 2502 2503 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu, 2504 uint16_t *voltage, 2505 uint32_t freq) 2506 { 2507 uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16); 2508 uint32_t value = 0; 2509 int ret; 2510 2511 ret = smu_cmn_send_smc_msg_with_param(smu, 2512 SMU_MSG_GetVoltageByDpm, 2513 param, 2514 &value); 2515 if (ret) { 2516 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!"); 2517 return ret; 2518 } 2519 2520 *voltage = (uint16_t)value; 2521 2522 return 0; 2523 } 2524 2525 static int navi10_baco_enter(struct smu_context *smu) 2526 { 2527 struct amdgpu_device *adev = smu->adev; 2528 2529 /* 2530 * This aims the case below: 2531 * amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded 2532 * 2533 * For NAVI10 and later ASICs, we rely on PMFW to handle the runpm. To 2534 * make that possible, PMFW needs to acknowledge the dstate transition 2535 * process for both gfx(function 0) and audio(function 1) function of 2536 * the ASIC. 2537 * 2538 * The PCI device's initial runpm status is RUNPM_SUSPENDED. So as the 2539 * device representing the audio function of the ASIC. And that means 2540 * even if the sound driver(snd_hda_intel) was not loaded yet, it's still 2541 * possible runpm suspend kicked on the ASIC. However without the dstate 2542 * transition notification from audio function, pmfw cannot handle the 2543 * BACO in/exit correctly. And that will cause driver hang on runpm 2544 * resuming. 2545 * 2546 * To address this, we revert to legacy message way(driver masters the 2547 * timing for BACO in/exit) on sound driver missing. 2548 */ 2549 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) 2550 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); 2551 else 2552 return smu_v11_0_baco_enter(smu); 2553 } 2554 2555 static int navi10_baco_exit(struct smu_context *smu) 2556 { 2557 struct amdgpu_device *adev = smu->adev; 2558 2559 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { 2560 /* Wait for PMFW handling for the Dstate change */ 2561 msleep(10); 2562 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); 2563 } else { 2564 return smu_v11_0_baco_exit(smu); 2565 } 2566 } 2567 2568 static int navi10_set_default_od_settings(struct smu_context *smu) 2569 { 2570 OverDriveTable_t *od_table = 2571 (OverDriveTable_t *)smu->smu_table.overdrive_table; 2572 OverDriveTable_t *boot_od_table = 2573 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table; 2574 OverDriveTable_t *user_od_table = 2575 (OverDriveTable_t *)smu->smu_table.user_overdrive_table; 2576 int ret = 0; 2577 2578 /* 2579 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as 2580 * - either they already have the default OD settings got during cold bootup 2581 * - or they have some user customized OD settings which cannot be overwritten 2582 */ 2583 if (smu->adev->in_suspend) 2584 return 0; 2585 2586 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)boot_od_table, false); 2587 if (ret) { 2588 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 2589 return ret; 2590 } 2591 2592 if (!boot_od_table->GfxclkVolt1) { 2593 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2594 &boot_od_table->GfxclkVolt1, 2595 boot_od_table->GfxclkFreq1); 2596 if (ret) 2597 return ret; 2598 } 2599 2600 if (!boot_od_table->GfxclkVolt2) { 2601 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2602 &boot_od_table->GfxclkVolt2, 2603 boot_od_table->GfxclkFreq2); 2604 if (ret) 2605 return ret; 2606 } 2607 2608 if (!boot_od_table->GfxclkVolt3) { 2609 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2610 &boot_od_table->GfxclkVolt3, 2611 boot_od_table->GfxclkFreq3); 2612 if (ret) 2613 return ret; 2614 } 2615 2616 navi10_dump_od_table(smu, boot_od_table); 2617 2618 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t)); 2619 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t)); 2620 2621 return 0; 2622 } 2623 2624 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) 2625 { 2626 int i; 2627 int ret = 0; 2628 struct smu_table_context *table_context = &smu->smu_table; 2629 OverDriveTable_t *od_table; 2630 struct smu_11_0_overdrive_table *od_settings; 2631 enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting; 2632 uint16_t *freq_ptr, *voltage_ptr; 2633 od_table = (OverDriveTable_t *)table_context->overdrive_table; 2634 2635 if (!smu->od_enabled) { 2636 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n"); 2637 return -EINVAL; 2638 } 2639 2640 if (!smu->od_settings) { 2641 dev_err(smu->adev->dev, "OD board limits are not set!\n"); 2642 return -ENOENT; 2643 } 2644 2645 od_settings = smu->od_settings; 2646 2647 switch (type) { 2648 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2649 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 2650 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n"); 2651 return -ENOTSUPP; 2652 } 2653 if (!table_context->overdrive_table) { 2654 dev_err(smu->adev->dev, "Overdrive is not initialized\n"); 2655 return -EINVAL; 2656 } 2657 for (i = 0; i < size; i += 2) { 2658 if (i + 2 > size) { 2659 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2660 return -EINVAL; 2661 } 2662 switch (input[i]) { 2663 case 0: 2664 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN; 2665 freq_ptr = &od_table->GfxclkFmin; 2666 if (input[i + 1] > od_table->GfxclkFmax) { 2667 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n", 2668 input[i + 1], 2669 od_table->GfxclkFmin); 2670 return -EINVAL; 2671 } 2672 break; 2673 case 1: 2674 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX; 2675 freq_ptr = &od_table->GfxclkFmax; 2676 if (input[i + 1] < od_table->GfxclkFmin) { 2677 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n", 2678 input[i + 1], 2679 od_table->GfxclkFmax); 2680 return -EINVAL; 2681 } 2682 break; 2683 default: 2684 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 2685 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2686 return -EINVAL; 2687 } 2688 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]); 2689 if (ret) 2690 return ret; 2691 *freq_ptr = input[i + 1]; 2692 } 2693 break; 2694 case PP_OD_EDIT_MCLK_VDDC_TABLE: 2695 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 2696 dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n"); 2697 return -ENOTSUPP; 2698 } 2699 if (size < 2) { 2700 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2701 return -EINVAL; 2702 } 2703 if (input[0] != 1) { 2704 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]); 2705 dev_info(smu->adev->dev, "Supported indices: [1:max]\n"); 2706 return -EINVAL; 2707 } 2708 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]); 2709 if (ret) 2710 return ret; 2711 od_table->UclkFmax = input[1]; 2712 break; 2713 case PP_OD_RESTORE_DEFAULT_TABLE: 2714 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { 2715 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n"); 2716 return -EINVAL; 2717 } 2718 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t)); 2719 break; 2720 case PP_OD_COMMIT_DPM_TABLE: 2721 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) { 2722 navi10_dump_od_table(smu, od_table); 2723 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true); 2724 if (ret) { 2725 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2726 return ret; 2727 } 2728 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t)); 2729 smu->user_dpm_profile.user_od = true; 2730 2731 if (!memcmp(table_context->user_overdrive_table, 2732 table_context->boot_overdrive_table, 2733 sizeof(OverDriveTable_t))) 2734 smu->user_dpm_profile.user_od = false; 2735 } 2736 break; 2737 case PP_OD_EDIT_VDDC_CURVE: 2738 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 2739 dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n"); 2740 return -ENOTSUPP; 2741 } 2742 if (size < 3) { 2743 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2744 return -EINVAL; 2745 } 2746 if (!od_table) { 2747 dev_info(smu->adev->dev, "Overdrive is not initialized\n"); 2748 return -EINVAL; 2749 } 2750 2751 switch (input[0]) { 2752 case 0: 2753 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1; 2754 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1; 2755 freq_ptr = &od_table->GfxclkFreq1; 2756 voltage_ptr = &od_table->GfxclkVolt1; 2757 break; 2758 case 1: 2759 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2; 2760 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2; 2761 freq_ptr = &od_table->GfxclkFreq2; 2762 voltage_ptr = &od_table->GfxclkVolt2; 2763 break; 2764 case 2: 2765 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3; 2766 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3; 2767 freq_ptr = &od_table->GfxclkFreq3; 2768 voltage_ptr = &od_table->GfxclkVolt3; 2769 break; 2770 default: 2771 dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]); 2772 dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n"); 2773 return -EINVAL; 2774 } 2775 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]); 2776 if (ret) 2777 return ret; 2778 // Allow setting zero to disable the OverDrive VDDC curve 2779 if (input[2] != 0) { 2780 ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]); 2781 if (ret) 2782 return ret; 2783 *freq_ptr = input[1]; 2784 *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE; 2785 dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr); 2786 } else { 2787 // If setting 0, disable all voltage curve settings 2788 od_table->GfxclkVolt1 = 0; 2789 od_table->GfxclkVolt2 = 0; 2790 od_table->GfxclkVolt3 = 0; 2791 } 2792 navi10_dump_od_table(smu, od_table); 2793 break; 2794 default: 2795 return -ENOSYS; 2796 } 2797 return ret; 2798 } 2799 2800 static int navi10_run_btc(struct smu_context *smu) 2801 { 2802 int ret = 0; 2803 2804 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL); 2805 if (ret) 2806 dev_err(smu->adev->dev, "RunBtc failed!\n"); 2807 2808 return ret; 2809 } 2810 2811 static bool navi10_need_umc_cdr_workaround(struct smu_context *smu) 2812 { 2813 struct amdgpu_device *adev = smu->adev; 2814 2815 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 2816 return false; 2817 2818 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0) || 2819 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 5)) 2820 return true; 2821 2822 return false; 2823 } 2824 2825 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu) 2826 { 2827 uint32_t uclk_count, uclk_min, uclk_max; 2828 int ret = 0; 2829 2830 /* This workaround can be applied only with uclk dpm enabled */ 2831 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 2832 return 0; 2833 2834 ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count); 2835 if (ret) 2836 return ret; 2837 2838 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max); 2839 if (ret) 2840 return ret; 2841 2842 /* 2843 * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz. 2844 * This workaround is needed only when the max uclk frequency 2845 * not greater than that. 2846 */ 2847 if (uclk_max > 0x2EE) 2848 return 0; 2849 2850 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min); 2851 if (ret) 2852 return ret; 2853 2854 /* Force UCLK out of the highest DPM */ 2855 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min); 2856 if (ret) 2857 return ret; 2858 2859 /* Revert the UCLK Hardmax */ 2860 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max); 2861 if (ret) 2862 return ret; 2863 2864 /* 2865 * In this case, SMU already disabled dummy pstate during enablement 2866 * of UCLK DPM, we have to re-enabled it. 2867 */ 2868 return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL); 2869 } 2870 2871 static int navi10_set_dummy_pstates_table_location(struct smu_context *smu) 2872 { 2873 struct smu_table_context *smu_table = &smu->smu_table; 2874 struct smu_table *dummy_read_table = 2875 &smu_table->dummy_read_1_table; 2876 char *dummy_table = dummy_read_table->cpu_addr; 2877 int ret = 0; 2878 uint32_t i; 2879 2880 for (i = 0; i < 0x40000; i += 0x1000 * 2) { 2881 memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000); 2882 dummy_table += 0x1000; 2883 memcpy(dummy_table, &DbiPrbs7[0], 0x1000); 2884 dummy_table += 0x1000; 2885 } 2886 2887 amdgpu_asic_flush_hdp(smu->adev, NULL); 2888 2889 ret = smu_cmn_send_smc_msg_with_param(smu, 2890 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, 2891 upper_32_bits(dummy_read_table->mc_address), 2892 NULL); 2893 if (ret) 2894 return ret; 2895 2896 return smu_cmn_send_smc_msg_with_param(smu, 2897 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, 2898 lower_32_bits(dummy_read_table->mc_address), 2899 NULL); 2900 } 2901 2902 static int navi10_run_umc_cdr_workaround(struct smu_context *smu) 2903 { 2904 struct amdgpu_device *adev = smu->adev; 2905 uint8_t umc_fw_greater_than_v136 = false; 2906 uint8_t umc_fw_disable_cdr = false; 2907 uint32_t param; 2908 int ret = 0; 2909 2910 if (!navi10_need_umc_cdr_workaround(smu)) 2911 return 0; 2912 2913 /* 2914 * The messages below are only supported by Navi10 42.53.0 and later 2915 * PMFWs and Navi14 53.29.0 and later PMFWs. 2916 * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh 2917 * - PPSMC_MSG_SetDriverDummyTableDramAddrLow 2918 * - PPSMC_MSG_GetUMCFWWA 2919 */ 2920 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && 2921 (smu->smc_fw_version >= 0x2a3500)) || 2922 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 5)) && 2923 (smu->smc_fw_version >= 0x351D00))) { 2924 ret = smu_cmn_send_smc_msg_with_param(smu, 2925 SMU_MSG_GET_UMC_FW_WA, 2926 0, 2927 ¶m); 2928 if (ret) 2929 return ret; 2930 2931 /* First bit indicates if the UMC f/w is above v137 */ 2932 umc_fw_greater_than_v136 = param & 0x1; 2933 2934 /* Second bit indicates if hybrid-cdr is disabled */ 2935 umc_fw_disable_cdr = param & 0x2; 2936 2937 /* w/a only allowed if UMC f/w is <= 136 */ 2938 if (umc_fw_greater_than_v136) 2939 return 0; 2940 2941 if (umc_fw_disable_cdr) { 2942 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == 2943 IP_VERSION(11, 0, 0)) 2944 return navi10_umc_hybrid_cdr_workaround(smu); 2945 } else { 2946 return navi10_set_dummy_pstates_table_location(smu); 2947 } 2948 } else { 2949 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == 2950 IP_VERSION(11, 0, 0)) 2951 return navi10_umc_hybrid_cdr_workaround(smu); 2952 } 2953 2954 return 0; 2955 } 2956 2957 static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu, 2958 void **table) 2959 { 2960 struct smu_table_context *smu_table = &smu->smu_table; 2961 struct gpu_metrics_v1_3 *gpu_metrics = 2962 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 2963 SmuMetrics_legacy_t metrics; 2964 int ret = 0; 2965 2966 ret = smu_cmn_get_metrics_table(smu, 2967 NULL, 2968 true); 2969 if (ret) 2970 return ret; 2971 2972 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t)); 2973 2974 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 2975 2976 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2977 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2978 gpu_metrics->temperature_mem = metrics.TemperatureMem; 2979 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2980 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2981 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 2982 2983 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2984 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2985 2986 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 2987 2988 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 2989 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2990 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 2991 2992 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2993 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2994 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2995 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2996 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2997 2998 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2999 gpu_metrics->indep_throttle_status = 3000 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3001 navi1x_throttler_map); 3002 3003 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3004 3005 gpu_metrics->pcie_link_width = 3006 smu_v11_0_get_current_pcie_link_width(smu); 3007 gpu_metrics->pcie_link_speed = 3008 smu_v11_0_get_current_pcie_link_speed(smu); 3009 3010 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3011 3012 if (metrics.CurrGfxVoltageOffset) 3013 gpu_metrics->voltage_gfx = 3014 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3015 if (metrics.CurrMemVidOffset) 3016 gpu_metrics->voltage_mem = 3017 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3018 if (metrics.CurrSocVoltageOffset) 3019 gpu_metrics->voltage_soc = 3020 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3021 3022 *table = (void *)gpu_metrics; 3023 3024 return sizeof(struct gpu_metrics_v1_3); 3025 } 3026 3027 static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap, 3028 struct i2c_msg *msg, int num_msgs) 3029 { 3030 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 3031 struct amdgpu_device *adev = smu_i2c->adev; 3032 struct smu_context *smu = adev->powerplay.pp_handle; 3033 struct smu_table_context *smu_table = &smu->smu_table; 3034 struct smu_table *table = &smu_table->driver_table; 3035 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 3036 int i, j, r, c; 3037 u16 dir; 3038 3039 if (!adev->pm.dpm_enabled) 3040 return -EBUSY; 3041 3042 req = kzalloc(sizeof(*req), GFP_KERNEL); 3043 if (!req) 3044 return -ENOMEM; 3045 3046 req->I2CcontrollerPort = smu_i2c->port; 3047 req->I2CSpeed = I2C_SPEED_FAST_400K; 3048 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 3049 dir = msg[0].flags & I2C_M_RD; 3050 3051 for (c = i = 0; i < num_msgs; i++) { 3052 for (j = 0; j < msg[i].len; j++, c++) { 3053 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 3054 3055 if (!(msg[i].flags & I2C_M_RD)) { 3056 /* write */ 3057 cmd->Cmd = I2C_CMD_WRITE; 3058 cmd->RegisterAddr = msg[i].buf[j]; 3059 } 3060 3061 if ((dir ^ msg[i].flags) & I2C_M_RD) { 3062 /* The direction changes. 3063 */ 3064 dir = msg[i].flags & I2C_M_RD; 3065 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 3066 } 3067 3068 req->NumCmds++; 3069 3070 /* 3071 * Insert STOP if we are at the last byte of either last 3072 * message for the transaction or the client explicitly 3073 * requires a STOP at this particular message. 3074 */ 3075 if ((j == msg[i].len - 1) && 3076 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 3077 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 3078 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 3079 } 3080 } 3081 } 3082 mutex_lock(&adev->pm.mutex); 3083 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 3084 if (r) 3085 goto fail; 3086 3087 for (c = i = 0; i < num_msgs; i++) { 3088 if (!(msg[i].flags & I2C_M_RD)) { 3089 c += msg[i].len; 3090 continue; 3091 } 3092 for (j = 0; j < msg[i].len; j++, c++) { 3093 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 3094 3095 msg[i].buf[j] = cmd->Data; 3096 } 3097 } 3098 r = num_msgs; 3099 fail: 3100 mutex_unlock(&adev->pm.mutex); 3101 kfree(req); 3102 return r; 3103 } 3104 3105 static u32 navi10_i2c_func(struct i2c_adapter *adap) 3106 { 3107 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 3108 } 3109 3110 3111 static const struct i2c_algorithm navi10_i2c_algo = { 3112 .master_xfer = navi10_i2c_xfer, 3113 .functionality = navi10_i2c_func, 3114 }; 3115 3116 static const struct i2c_adapter_quirks navi10_i2c_control_quirks = { 3117 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 3118 .max_read_len = MAX_SW_I2C_COMMANDS, 3119 .max_write_len = MAX_SW_I2C_COMMANDS, 3120 .max_comb_1st_msg_len = 2, 3121 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 3122 }; 3123 3124 static int navi10_i2c_control_init(struct smu_context *smu) 3125 { 3126 struct amdgpu_device *adev = smu->adev; 3127 int res, i; 3128 3129 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3130 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3131 struct i2c_adapter *control = &smu_i2c->adapter; 3132 3133 smu_i2c->adev = adev; 3134 smu_i2c->port = i; 3135 mutex_init(&smu_i2c->mutex); 3136 control->owner = THIS_MODULE; 3137 control->class = I2C_CLASS_HWMON; 3138 control->dev.parent = &adev->pdev->dev; 3139 control->algo = &navi10_i2c_algo; 3140 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 3141 control->quirks = &navi10_i2c_control_quirks; 3142 i2c_set_adapdata(control, smu_i2c); 3143 3144 res = i2c_add_adapter(control); 3145 if (res) { 3146 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 3147 goto Out_err; 3148 } 3149 } 3150 3151 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 3152 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 3153 3154 return 0; 3155 Out_err: 3156 for ( ; i >= 0; i--) { 3157 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3158 struct i2c_adapter *control = &smu_i2c->adapter; 3159 3160 i2c_del_adapter(control); 3161 } 3162 return res; 3163 } 3164 3165 static void navi10_i2c_control_fini(struct smu_context *smu) 3166 { 3167 struct amdgpu_device *adev = smu->adev; 3168 int i; 3169 3170 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3171 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3172 struct i2c_adapter *control = &smu_i2c->adapter; 3173 3174 i2c_del_adapter(control); 3175 } 3176 adev->pm.ras_eeprom_i2c_bus = NULL; 3177 adev->pm.fru_eeprom_i2c_bus = NULL; 3178 } 3179 3180 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, 3181 void **table) 3182 { 3183 struct smu_table_context *smu_table = &smu->smu_table; 3184 struct gpu_metrics_v1_3 *gpu_metrics = 3185 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3186 SmuMetrics_t metrics; 3187 int ret = 0; 3188 3189 ret = smu_cmn_get_metrics_table(smu, 3190 NULL, 3191 true); 3192 if (ret) 3193 return ret; 3194 3195 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t)); 3196 3197 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3198 3199 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 3200 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 3201 gpu_metrics->temperature_mem = metrics.TemperatureMem; 3202 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 3203 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 3204 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 3205 3206 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 3207 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 3208 3209 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 3210 3211 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 3212 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; 3213 else 3214 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; 3215 3216 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 3217 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; 3218 3219 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 3220 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 3221 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 3222 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 3223 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 3224 3225 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 3226 gpu_metrics->indep_throttle_status = 3227 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3228 navi1x_throttler_map); 3229 3230 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3231 3232 gpu_metrics->pcie_link_width = metrics.PcieWidth; 3233 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate]; 3234 3235 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3236 3237 if (metrics.CurrGfxVoltageOffset) 3238 gpu_metrics->voltage_gfx = 3239 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3240 if (metrics.CurrMemVidOffset) 3241 gpu_metrics->voltage_mem = 3242 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3243 if (metrics.CurrSocVoltageOffset) 3244 gpu_metrics->voltage_soc = 3245 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3246 3247 *table = (void *)gpu_metrics; 3248 3249 return sizeof(struct gpu_metrics_v1_3); 3250 } 3251 3252 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, 3253 void **table) 3254 { 3255 struct smu_table_context *smu_table = &smu->smu_table; 3256 struct gpu_metrics_v1_3 *gpu_metrics = 3257 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3258 SmuMetrics_NV12_legacy_t metrics; 3259 int ret = 0; 3260 3261 ret = smu_cmn_get_metrics_table(smu, 3262 NULL, 3263 true); 3264 if (ret) 3265 return ret; 3266 3267 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t)); 3268 3269 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3270 3271 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 3272 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 3273 gpu_metrics->temperature_mem = metrics.TemperatureMem; 3274 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 3275 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 3276 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 3277 3278 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 3279 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 3280 3281 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 3282 3283 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 3284 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 3285 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 3286 3287 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 3288 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 3289 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 3290 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 3291 3292 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 3293 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 3294 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 3295 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 3296 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 3297 3298 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 3299 gpu_metrics->indep_throttle_status = 3300 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3301 navi1x_throttler_map); 3302 3303 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3304 3305 gpu_metrics->pcie_link_width = 3306 smu_v11_0_get_current_pcie_link_width(smu); 3307 gpu_metrics->pcie_link_speed = 3308 smu_v11_0_get_current_pcie_link_speed(smu); 3309 3310 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3311 3312 if (metrics.CurrGfxVoltageOffset) 3313 gpu_metrics->voltage_gfx = 3314 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3315 if (metrics.CurrMemVidOffset) 3316 gpu_metrics->voltage_mem = 3317 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3318 if (metrics.CurrSocVoltageOffset) 3319 gpu_metrics->voltage_soc = 3320 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3321 3322 *table = (void *)gpu_metrics; 3323 3324 return sizeof(struct gpu_metrics_v1_3); 3325 } 3326 3327 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, 3328 void **table) 3329 { 3330 struct smu_table_context *smu_table = &smu->smu_table; 3331 struct gpu_metrics_v1_3 *gpu_metrics = 3332 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3333 SmuMetrics_NV12_t metrics; 3334 int ret = 0; 3335 3336 ret = smu_cmn_get_metrics_table(smu, 3337 NULL, 3338 true); 3339 if (ret) 3340 return ret; 3341 3342 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t)); 3343 3344 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3345 3346 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 3347 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 3348 gpu_metrics->temperature_mem = metrics.TemperatureMem; 3349 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 3350 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 3351 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 3352 3353 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 3354 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 3355 3356 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 3357 3358 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 3359 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; 3360 else 3361 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; 3362 3363 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 3364 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; 3365 3366 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 3367 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 3368 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 3369 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 3370 3371 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 3372 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 3373 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 3374 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 3375 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 3376 3377 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 3378 gpu_metrics->indep_throttle_status = 3379 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3380 navi1x_throttler_map); 3381 3382 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3383 3384 gpu_metrics->pcie_link_width = metrics.PcieWidth; 3385 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate]; 3386 3387 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3388 3389 if (metrics.CurrGfxVoltageOffset) 3390 gpu_metrics->voltage_gfx = 3391 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3392 if (metrics.CurrMemVidOffset) 3393 gpu_metrics->voltage_mem = 3394 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3395 if (metrics.CurrSocVoltageOffset) 3396 gpu_metrics->voltage_soc = 3397 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3398 3399 *table = (void *)gpu_metrics; 3400 3401 return sizeof(struct gpu_metrics_v1_3); 3402 } 3403 3404 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu, 3405 void **table) 3406 { 3407 struct amdgpu_device *adev = smu->adev; 3408 int ret = 0; 3409 3410 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 3411 case IP_VERSION(11, 0, 9): 3412 if (smu->smc_fw_version > 0x00341C00) 3413 ret = navi12_get_gpu_metrics(smu, table); 3414 else 3415 ret = navi12_get_legacy_gpu_metrics(smu, table); 3416 break; 3417 case IP_VERSION(11, 0, 0): 3418 case IP_VERSION(11, 0, 5): 3419 default: 3420 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == 3421 IP_VERSION(11, 0, 5)) && 3422 smu->smc_fw_version > 0x00351F00) || 3423 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == 3424 IP_VERSION(11, 0, 0)) && 3425 smu->smc_fw_version > 0x002A3B00)) 3426 ret = navi10_get_gpu_metrics(smu, table); 3427 else 3428 ret = navi10_get_legacy_gpu_metrics(smu, table); 3429 break; 3430 } 3431 3432 return ret; 3433 } 3434 3435 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu) 3436 { 3437 struct smu_table_context *table_context = &smu->smu_table; 3438 PPTable_t *smc_pptable = table_context->driver_pptable; 3439 struct amdgpu_device *adev = smu->adev; 3440 uint32_t param = 0; 3441 3442 /* Navi12 does not support this */ 3443 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 9)) 3444 return 0; 3445 3446 /* 3447 * Skip the MGpuFanBoost setting for those ASICs 3448 * which do not support it 3449 */ 3450 if (!smc_pptable->MGpuFanBoostLimitRpm) 3451 return 0; 3452 3453 /* Workaround for WS SKU */ 3454 if (adev->pdev->device == 0x7312 && 3455 adev->pdev->revision == 0) 3456 param = 0xD188; 3457 3458 return smu_cmn_send_smc_msg_with_param(smu, 3459 SMU_MSG_SetMGpuFanBoostLimitRpm, 3460 param, 3461 NULL); 3462 } 3463 3464 static int navi10_post_smu_init(struct smu_context *smu) 3465 { 3466 struct amdgpu_device *adev = smu->adev; 3467 int ret = 0; 3468 3469 if (amdgpu_sriov_vf(adev)) 3470 return 0; 3471 3472 ret = navi10_run_umc_cdr_workaround(smu); 3473 if (ret) 3474 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n"); 3475 3476 return ret; 3477 } 3478 3479 static int navi10_get_default_config_table_settings(struct smu_context *smu, 3480 struct config_table_setting *table) 3481 { 3482 if (!table) 3483 return -EINVAL; 3484 3485 table->gfxclk_average_tau = 10; 3486 table->socclk_average_tau = 10; 3487 table->uclk_average_tau = 10; 3488 table->gfx_activity_average_tau = 10; 3489 table->mem_activity_average_tau = 10; 3490 table->socket_power_average_tau = 10; 3491 3492 return 0; 3493 } 3494 3495 static int navi10_set_config_table(struct smu_context *smu, 3496 struct config_table_setting *table) 3497 { 3498 DriverSmuConfig_t driver_smu_config_table; 3499 3500 if (!table) 3501 return -EINVAL; 3502 3503 memset(&driver_smu_config_table, 3504 0, 3505 sizeof(driver_smu_config_table)); 3506 3507 driver_smu_config_table.GfxclkAverageLpfTau = 3508 table->gfxclk_average_tau; 3509 driver_smu_config_table.SocclkAverageLpfTau = 3510 table->socclk_average_tau; 3511 driver_smu_config_table.UclkAverageLpfTau = 3512 table->uclk_average_tau; 3513 driver_smu_config_table.GfxActivityLpfTau = 3514 table->gfx_activity_average_tau; 3515 driver_smu_config_table.UclkActivityLpfTau = 3516 table->mem_activity_average_tau; 3517 driver_smu_config_table.SocketPowerLpfTau = 3518 table->socket_power_average_tau; 3519 3520 return smu_cmn_update_table(smu, 3521 SMU_TABLE_DRIVER_SMU_CONFIG, 3522 0, 3523 (void *)&driver_smu_config_table, 3524 true); 3525 } 3526 3527 static const struct pptable_funcs navi10_ppt_funcs = { 3528 .get_allowed_feature_mask = navi10_get_allowed_feature_mask, 3529 .set_default_dpm_table = navi10_set_default_dpm_table, 3530 .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable, 3531 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable, 3532 .i2c_init = navi10_i2c_control_init, 3533 .i2c_fini = navi10_i2c_control_fini, 3534 .print_clk_levels = navi10_print_clk_levels, 3535 .emit_clk_levels = navi10_emit_clk_levels, 3536 .force_clk_levels = navi10_force_clk_levels, 3537 .populate_umd_state_clk = navi10_populate_umd_state_clk, 3538 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency, 3539 .pre_display_config_changed = navi10_pre_display_config_changed, 3540 .display_config_changed = navi10_display_config_changed, 3541 .notify_smc_display_config = navi10_notify_smc_display_config, 3542 .is_dpm_running = navi10_is_dpm_running, 3543 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm, 3544 .get_fan_speed_rpm = navi10_get_fan_speed_rpm, 3545 .get_power_profile_mode = navi10_get_power_profile_mode, 3546 .set_power_profile_mode = navi10_set_power_profile_mode, 3547 .set_watermarks_table = navi10_set_watermarks_table, 3548 .read_sensor = navi10_read_sensor, 3549 .get_uclk_dpm_states = navi10_get_uclk_dpm_states, 3550 .set_performance_level = smu_v11_0_set_performance_level, 3551 .get_thermal_temperature_range = navi10_get_thermal_temperature_range, 3552 .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch, 3553 .get_power_limit = navi10_get_power_limit, 3554 .update_pcie_parameters = navi10_update_pcie_parameters, 3555 .init_microcode = smu_v11_0_init_microcode, 3556 .load_microcode = smu_v11_0_load_microcode, 3557 .fini_microcode = smu_v11_0_fini_microcode, 3558 .init_smc_tables = navi10_init_smc_tables, 3559 .fini_smc_tables = smu_v11_0_fini_smc_tables, 3560 .init_power = smu_v11_0_init_power, 3561 .fini_power = smu_v11_0_fini_power, 3562 .check_fw_status = smu_v11_0_check_fw_status, 3563 .setup_pptable = navi10_setup_pptable, 3564 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 3565 .check_fw_version = smu_v11_0_check_fw_version, 3566 .write_pptable = smu_cmn_write_pptable, 3567 .set_driver_table_location = smu_v11_0_set_driver_table_location, 3568 .set_tool_table_location = smu_v11_0_set_tool_table_location, 3569 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 3570 .system_features_control = smu_v11_0_system_features_control, 3571 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 3572 .send_smc_msg = smu_cmn_send_smc_msg, 3573 .init_display_count = smu_v11_0_init_display_count, 3574 .set_allowed_mask = smu_v11_0_set_allowed_mask, 3575 .get_enabled_mask = smu_cmn_get_enabled_mask, 3576 .feature_is_enabled = smu_cmn_feature_is_enabled, 3577 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 3578 .notify_display_change = smu_v11_0_notify_display_change, 3579 .set_power_limit = smu_v11_0_set_power_limit, 3580 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 3581 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 3582 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 3583 .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk, 3584 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 3585 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 3586 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 3587 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm, 3588 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, 3589 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 3590 .gfx_off_control = smu_v11_0_gfx_off_control, 3591 .register_irq_handler = smu_v11_0_register_irq_handler, 3592 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 3593 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 3594 .get_bamaco_support = smu_v11_0_get_bamaco_support, 3595 .baco_enter = navi10_baco_enter, 3596 .baco_exit = navi10_baco_exit, 3597 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq, 3598 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 3599 .set_default_od_settings = navi10_set_default_od_settings, 3600 .od_edit_dpm_table = navi10_od_edit_dpm_table, 3601 .restore_user_od_settings = smu_v11_0_restore_user_od_settings, 3602 .run_btc = navi10_run_btc, 3603 .set_power_source = smu_v11_0_set_power_source, 3604 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 3605 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 3606 .get_gpu_metrics = navi1x_get_gpu_metrics, 3607 .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost, 3608 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 3609 .deep_sleep_control = smu_v11_0_deep_sleep_control, 3610 .get_fan_parameters = navi10_get_fan_parameters, 3611 .post_init = navi10_post_smu_init, 3612 .interrupt_work = smu_v11_0_interrupt_work, 3613 .set_mp1_state = smu_cmn_set_mp1_state, 3614 .get_default_config_table_settings = navi10_get_default_config_table_settings, 3615 .set_config_table = navi10_set_config_table, 3616 }; 3617 3618 void navi10_set_ppt_funcs(struct smu_context *smu) 3619 { 3620 smu->ppt_funcs = &navi10_ppt_funcs; 3621 smu->message_map = navi10_message_map; 3622 smu->clock_map = navi10_clk_map; 3623 smu->feature_map = navi10_feature_mask_map; 3624 smu->table_map = navi10_table_map; 3625 smu->pwr_src_map = navi10_pwr_src_map; 3626 smu->workload_map = navi10_workload_map; 3627 smu_v11_0_set_smu_mailbox_registers(smu); 3628 } 3629