1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_dpm.h" 31 #include "amdgpu_smu.h" 32 #include "atomfirmware.h" 33 #include "amdgpu_atomfirmware.h" 34 #include "amdgpu_atombios.h" 35 #include "soc15_common.h" 36 #include "smu_v11_0.h" 37 #include "smu11_driver_if_navi10.h" 38 #include "atom.h" 39 #include "navi10_ppt.h" 40 #include "smu_v11_0_pptable.h" 41 #include "smu_v11_0_ppsmc.h" 42 #include "nbio/nbio_2_3_offset.h" 43 #include "nbio/nbio_2_3_sh_mask.h" 44 #include "thm/thm_11_0_2_offset.h" 45 #include "thm/thm_11_0_2_sh_mask.h" 46 47 #include "asic_reg/mp/mp_11_0_sh_mask.h" 48 #include "smu_cmn.h" 49 #include "smu_11_0_cdr_table.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 #define FEATURE_MASK(feature) (1ULL << feature) 62 #define SMC_DPM_FEATURE ( \ 63 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) 71 72 #define SMU_11_0_GFX_BUSY_THRESHOLD 15 73 74 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = { 75 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 76 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 77 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 78 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 79 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 80 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 81 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 82 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 0), 83 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 0), 84 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0), 85 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0), 86 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 87 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 88 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 0), 89 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 90 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 91 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 92 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 93 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 94 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 95 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 96 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 97 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0), 98 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc, 0), 99 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 100 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 101 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 102 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 103 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 104 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 105 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 106 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 107 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig, 0), 108 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0), 109 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0), 110 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0), 111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 112 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk, 0), 113 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 114 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 115 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0), 116 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0), 117 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 118 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 119 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 120 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 121 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt, 0), 122 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays, 0), 123 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 124 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 125 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 126 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 127 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 128 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 129 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 130 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 131 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0), 132 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0), 133 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 134 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 135 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 136 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 137 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0), 138 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 139 MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALDisableDummyPstateChange, 0), 140 MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0), 141 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 142 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 143 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 144 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0), 145 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0), 146 MSG_MAP(GET_UMC_FW_WA, PPSMC_MSG_GetUMCFWWA, 0), 147 }; 148 149 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = { 150 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 151 CLK_MAP(SCLK, PPCLK_GFXCLK), 152 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 153 CLK_MAP(FCLK, PPCLK_SOCCLK), 154 CLK_MAP(UCLK, PPCLK_UCLK), 155 CLK_MAP(MCLK, PPCLK_UCLK), 156 CLK_MAP(DCLK, PPCLK_DCLK), 157 CLK_MAP(VCLK, PPCLK_VCLK), 158 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), 159 CLK_MAP(DISPCLK, PPCLK_DISPCLK), 160 CLK_MAP(PIXCLK, PPCLK_PIXCLK), 161 CLK_MAP(PHYCLK, PPCLK_PHYCLK), 162 }; 163 164 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = { 165 FEA_MAP(DPM_PREFETCHER), 166 FEA_MAP(DPM_GFXCLK), 167 FEA_MAP(DPM_GFX_PACE), 168 FEA_MAP(DPM_UCLK), 169 FEA_MAP(DPM_SOCCLK), 170 FEA_MAP(DPM_MP0CLK), 171 FEA_MAP(DPM_LINK), 172 FEA_MAP(DPM_DCEFCLK), 173 FEA_MAP(MEM_VDDCI_SCALING), 174 FEA_MAP(MEM_MVDD_SCALING), 175 FEA_MAP(DS_GFXCLK), 176 FEA_MAP(DS_SOCCLK), 177 FEA_MAP(DS_LCLK), 178 FEA_MAP(DS_DCEFCLK), 179 FEA_MAP(DS_UCLK), 180 FEA_MAP(GFX_ULV), 181 FEA_MAP(FW_DSTATE), 182 FEA_MAP(GFXOFF), 183 FEA_MAP(BACO), 184 FEA_MAP(VCN_PG), 185 FEA_MAP(JPEG_PG), 186 FEA_MAP(USB_PG), 187 FEA_MAP(RSMU_SMN_CG), 188 FEA_MAP(PPT), 189 FEA_MAP(TDC), 190 FEA_MAP(GFX_EDC), 191 FEA_MAP(APCC_PLUS), 192 FEA_MAP(GTHR), 193 FEA_MAP(ACDC), 194 FEA_MAP(VR0HOT), 195 FEA_MAP(VR1HOT), 196 FEA_MAP(FW_CTF), 197 FEA_MAP(FAN_CONTROL), 198 FEA_MAP(THERMAL), 199 FEA_MAP(GFX_DCS), 200 FEA_MAP(RM), 201 FEA_MAP(LED_DISPLAY), 202 FEA_MAP(GFX_SS), 203 FEA_MAP(OUT_OF_BAND_MONITOR), 204 FEA_MAP(TEMP_DEPENDENT_VMIN), 205 FEA_MAP(MMHUB_PG), 206 FEA_MAP(ATHUB_PG), 207 FEA_MAP(APCC_DFLL), 208 }; 209 210 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = { 211 TAB_MAP(PPTABLE), 212 TAB_MAP(WATERMARKS), 213 TAB_MAP(AVFS), 214 TAB_MAP(AVFS_PSM_DEBUG), 215 TAB_MAP(AVFS_FUSE_OVERRIDE), 216 TAB_MAP(PMSTATUSLOG), 217 TAB_MAP(SMU_METRICS), 218 TAB_MAP(DRIVER_SMU_CONFIG), 219 TAB_MAP(ACTIVITY_MONITOR_COEFF), 220 TAB_MAP(OVERDRIVE), 221 TAB_MAP(I2C_COMMANDS), 222 TAB_MAP(PACE), 223 }; 224 225 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 226 PWR_MAP(AC), 227 PWR_MAP(DC), 228 }; 229 230 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 231 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 232 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 238 }; 239 240 static const uint8_t navi1x_throttler_map[] = { 241 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 242 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 243 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 244 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 245 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 246 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 247 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 248 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 249 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 250 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 251 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 252 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 253 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 254 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 255 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 256 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 257 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), 258 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 259 }; 260 261 262 static bool is_asic_secure(struct smu_context *smu) 263 { 264 struct amdgpu_device *adev = smu->adev; 265 bool is_secure = true; 266 uint32_t mp0_fw_intf; 267 268 mp0_fw_intf = RREG32_PCIE(MP0_Public | 269 (smnMP0_FW_INTF & 0xffffffff)); 270 271 if (!(mp0_fw_intf & (1 << 19))) 272 is_secure = false; 273 274 return is_secure; 275 } 276 277 static int 278 navi10_get_allowed_feature_mask(struct smu_context *smu, 279 uint32_t *feature_mask, uint32_t num) 280 { 281 struct amdgpu_device *adev = smu->adev; 282 283 if (num > 2) 284 return -EINVAL; 285 286 memset(feature_mask, 0, sizeof(uint32_t) * num); 287 288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 289 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) 290 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) 291 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 292 | FEATURE_MASK(FEATURE_PPT_BIT) 293 | FEATURE_MASK(FEATURE_TDC_BIT) 294 | FEATURE_MASK(FEATURE_GFX_EDC_BIT) 295 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT) 296 | FEATURE_MASK(FEATURE_VR0HOT_BIT) 297 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) 298 | FEATURE_MASK(FEATURE_THERMAL_BIT) 299 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) 300 | FEATURE_MASK(FEATURE_DS_LCLK_BIT) 301 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) 302 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) 303 | FEATURE_MASK(FEATURE_BACO_BIT) 304 | FEATURE_MASK(FEATURE_GFX_SS_BIT) 305 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) 306 | FEATURE_MASK(FEATURE_FW_CTF_BIT) 307 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT) 308 | FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT); 309 310 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) 311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 312 313 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 315 316 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 318 319 if (adev->pm.pp_feature & PP_ULV_MASK) 320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 321 322 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 324 325 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 327 328 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); 330 331 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 333 334 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN) 335 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); 336 337 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 338 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT); 339 340 if (smu->dc_controlled_by_gpio) 341 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); 342 343 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 344 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 345 346 /* DPM UCLK enablement should be skipped for navi10 A0 secure board */ 347 if (!(is_asic_secure(smu) && 348 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && 349 (adev->rev_id == 0)) && 350 (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) 351 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 352 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) 353 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); 354 355 /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */ 356 if (is_asic_secure(smu) && 357 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && 358 (adev->rev_id == 0)) 359 *(uint64_t *)feature_mask &= 360 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); 361 362 return 0; 363 } 364 365 static void navi10_check_bxco_support(struct smu_context *smu) 366 { 367 struct smu_table_context *table_context = &smu->smu_table; 368 struct smu_11_0_powerplay_table *powerplay_table = 369 table_context->power_play_table; 370 struct smu_baco_context *smu_baco = &smu->smu_baco; 371 struct amdgpu_device *adev = smu->adev; 372 uint32_t val; 373 374 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || 375 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) { 376 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 377 smu_baco->platform_support = 378 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : 379 false; 380 } 381 } 382 383 static int navi10_check_powerplay_table(struct smu_context *smu) 384 { 385 struct smu_table_context *table_context = &smu->smu_table; 386 struct smu_11_0_powerplay_table *powerplay_table = 387 table_context->power_play_table; 388 389 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC) 390 smu->dc_controlled_by_gpio = true; 391 392 navi10_check_bxco_support(smu); 393 394 table_context->thermal_controller_type = 395 powerplay_table->thermal_controller_type; 396 397 /* 398 * Instead of having its own buffer space and get overdrive_table copied, 399 * smu->od_settings just points to the actual overdrive_table 400 */ 401 smu->od_settings = &powerplay_table->overdrive_table; 402 403 return 0; 404 } 405 406 static int navi10_append_powerplay_table(struct smu_context *smu) 407 { 408 struct amdgpu_device *adev = smu->adev; 409 struct smu_table_context *table_context = &smu->smu_table; 410 PPTable_t *smc_pptable = table_context->driver_pptable; 411 struct atom_smc_dpm_info_v4_5 *smc_dpm_table; 412 struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7; 413 int index, ret; 414 415 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 416 smc_dpm_info); 417 418 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL, 419 (uint8_t **)&smc_dpm_table); 420 if (ret) 421 return ret; 422 423 dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 424 smc_dpm_table->table_header.format_revision, 425 smc_dpm_table->table_header.content_revision); 426 427 if (smc_dpm_table->table_header.format_revision != 4) { 428 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n"); 429 return -EINVAL; 430 } 431 432 switch (smc_dpm_table->table_header.content_revision) { 433 case 5: /* nv10 and nv14 */ 434 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved, 435 smc_dpm_table, I2cControllers); 436 break; 437 case 7: /* nv12 */ 438 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL, 439 (uint8_t **)&smc_dpm_table_v4_7); 440 if (ret) 441 return ret; 442 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved, 443 smc_dpm_table_v4_7, I2cControllers); 444 break; 445 default: 446 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n", 447 smc_dpm_table->table_header.content_revision); 448 return -EINVAL; 449 } 450 451 if (adev->pm.pp_feature & PP_GFXOFF_MASK) { 452 /* TODO: remove it once SMU fw fix it */ 453 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN; 454 } 455 456 return 0; 457 } 458 459 static int navi10_store_powerplay_table(struct smu_context *smu) 460 { 461 struct smu_table_context *table_context = &smu->smu_table; 462 struct smu_11_0_powerplay_table *powerplay_table = 463 table_context->power_play_table; 464 465 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 466 sizeof(PPTable_t)); 467 468 return 0; 469 } 470 471 static int navi10_setup_pptable(struct smu_context *smu) 472 { 473 int ret = 0; 474 475 ret = smu_v11_0_setup_pptable(smu); 476 if (ret) 477 return ret; 478 479 ret = navi10_store_powerplay_table(smu); 480 if (ret) 481 return ret; 482 483 ret = navi10_append_powerplay_table(smu); 484 if (ret) 485 return ret; 486 487 ret = navi10_check_powerplay_table(smu); 488 if (ret) 489 return ret; 490 491 return ret; 492 } 493 494 static int navi10_tables_init(struct smu_context *smu) 495 { 496 struct smu_table_context *smu_table = &smu->smu_table; 497 struct smu_table *tables = smu_table->tables; 498 struct smu_table *dummy_read_1_table = 499 &smu_table->dummy_read_1_table; 500 501 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 502 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 503 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 504 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 505 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t), 506 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 507 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 508 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 509 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 510 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 511 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 512 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 513 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 514 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, 515 AMDGPU_GEM_DOMAIN_VRAM); 516 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfig_t), 517 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 518 519 dummy_read_1_table->size = 0x40000; 520 dummy_read_1_table->align = PAGE_SIZE; 521 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 522 523 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t), 524 GFP_KERNEL); 525 if (!smu_table->metrics_table) 526 goto err0_out; 527 smu_table->metrics_time = 0; 528 529 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 530 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 531 if (!smu_table->gpu_metrics_table) 532 goto err1_out; 533 534 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 535 if (!smu_table->watermarks_table) 536 goto err2_out; 537 538 smu_table->driver_smu_config_table = 539 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL); 540 if (!smu_table->driver_smu_config_table) 541 goto err3_out; 542 543 return 0; 544 545 err3_out: 546 kfree(smu_table->watermarks_table); 547 err2_out: 548 kfree(smu_table->gpu_metrics_table); 549 err1_out: 550 kfree(smu_table->metrics_table); 551 err0_out: 552 return -ENOMEM; 553 } 554 555 static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu, 556 MetricsMember_t member, 557 uint32_t *value) 558 { 559 struct smu_table_context *smu_table = &smu->smu_table; 560 SmuMetrics_legacy_t *metrics = 561 (SmuMetrics_legacy_t *)smu_table->metrics_table; 562 int ret = 0; 563 564 ret = smu_cmn_get_metrics_table(smu, 565 NULL, 566 false); 567 if (ret) 568 return ret; 569 570 switch (member) { 571 case METRICS_CURR_GFXCLK: 572 *value = metrics->CurrClock[PPCLK_GFXCLK]; 573 break; 574 case METRICS_CURR_SOCCLK: 575 *value = metrics->CurrClock[PPCLK_SOCCLK]; 576 break; 577 case METRICS_CURR_UCLK: 578 *value = metrics->CurrClock[PPCLK_UCLK]; 579 break; 580 case METRICS_CURR_VCLK: 581 *value = metrics->CurrClock[PPCLK_VCLK]; 582 break; 583 case METRICS_CURR_DCLK: 584 *value = metrics->CurrClock[PPCLK_DCLK]; 585 break; 586 case METRICS_CURR_DCEFCLK: 587 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 588 break; 589 case METRICS_AVERAGE_GFXCLK: 590 *value = metrics->AverageGfxclkFrequency; 591 break; 592 case METRICS_AVERAGE_SOCCLK: 593 *value = metrics->AverageSocclkFrequency; 594 break; 595 case METRICS_AVERAGE_UCLK: 596 *value = metrics->AverageUclkFrequency; 597 break; 598 case METRICS_AVERAGE_GFXACTIVITY: 599 *value = metrics->AverageGfxActivity; 600 break; 601 case METRICS_AVERAGE_MEMACTIVITY: 602 *value = metrics->AverageUclkActivity; 603 break; 604 case METRICS_AVERAGE_SOCKETPOWER: 605 *value = metrics->AverageSocketPower << 8; 606 break; 607 case METRICS_TEMPERATURE_EDGE: 608 *value = metrics->TemperatureEdge * 609 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 610 break; 611 case METRICS_TEMPERATURE_HOTSPOT: 612 *value = metrics->TemperatureHotspot * 613 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 614 break; 615 case METRICS_TEMPERATURE_MEM: 616 *value = metrics->TemperatureMem * 617 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 618 break; 619 case METRICS_TEMPERATURE_VRGFX: 620 *value = metrics->TemperatureVrGfx * 621 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 622 break; 623 case METRICS_TEMPERATURE_VRSOC: 624 *value = metrics->TemperatureVrSoc * 625 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 626 break; 627 case METRICS_THROTTLER_STATUS: 628 *value = metrics->ThrottlerStatus; 629 break; 630 case METRICS_CURR_FANSPEED: 631 *value = metrics->CurrFanSpeed; 632 break; 633 default: 634 *value = UINT_MAX; 635 break; 636 } 637 638 return ret; 639 } 640 641 static int navi10_get_smu_metrics_data(struct smu_context *smu, 642 MetricsMember_t member, 643 uint32_t *value) 644 { 645 struct smu_table_context *smu_table = &smu->smu_table; 646 SmuMetrics_t *metrics = 647 (SmuMetrics_t *)smu_table->metrics_table; 648 int ret = 0; 649 650 ret = smu_cmn_get_metrics_table(smu, 651 NULL, 652 false); 653 if (ret) 654 return ret; 655 656 switch (member) { 657 case METRICS_CURR_GFXCLK: 658 *value = metrics->CurrClock[PPCLK_GFXCLK]; 659 break; 660 case METRICS_CURR_SOCCLK: 661 *value = metrics->CurrClock[PPCLK_SOCCLK]; 662 break; 663 case METRICS_CURR_UCLK: 664 *value = metrics->CurrClock[PPCLK_UCLK]; 665 break; 666 case METRICS_CURR_VCLK: 667 *value = metrics->CurrClock[PPCLK_VCLK]; 668 break; 669 case METRICS_CURR_DCLK: 670 *value = metrics->CurrClock[PPCLK_DCLK]; 671 break; 672 case METRICS_CURR_DCEFCLK: 673 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 674 break; 675 case METRICS_AVERAGE_GFXCLK: 676 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 677 *value = metrics->AverageGfxclkFrequencyPreDs; 678 else 679 *value = metrics->AverageGfxclkFrequencyPostDs; 680 break; 681 case METRICS_AVERAGE_SOCCLK: 682 *value = metrics->AverageSocclkFrequency; 683 break; 684 case METRICS_AVERAGE_UCLK: 685 *value = metrics->AverageUclkFrequencyPostDs; 686 break; 687 case METRICS_AVERAGE_GFXACTIVITY: 688 *value = metrics->AverageGfxActivity; 689 break; 690 case METRICS_AVERAGE_MEMACTIVITY: 691 *value = metrics->AverageUclkActivity; 692 break; 693 case METRICS_AVERAGE_SOCKETPOWER: 694 *value = metrics->AverageSocketPower << 8; 695 break; 696 case METRICS_TEMPERATURE_EDGE: 697 *value = metrics->TemperatureEdge * 698 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 699 break; 700 case METRICS_TEMPERATURE_HOTSPOT: 701 *value = metrics->TemperatureHotspot * 702 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 703 break; 704 case METRICS_TEMPERATURE_MEM: 705 *value = metrics->TemperatureMem * 706 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 707 break; 708 case METRICS_TEMPERATURE_VRGFX: 709 *value = metrics->TemperatureVrGfx * 710 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 711 break; 712 case METRICS_TEMPERATURE_VRSOC: 713 *value = metrics->TemperatureVrSoc * 714 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 715 break; 716 case METRICS_THROTTLER_STATUS: 717 *value = metrics->ThrottlerStatus; 718 break; 719 case METRICS_CURR_FANSPEED: 720 *value = metrics->CurrFanSpeed; 721 break; 722 default: 723 *value = UINT_MAX; 724 break; 725 } 726 727 return ret; 728 } 729 730 static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu, 731 MetricsMember_t member, 732 uint32_t *value) 733 { 734 struct smu_table_context *smu_table = &smu->smu_table; 735 SmuMetrics_NV12_legacy_t *metrics = 736 (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table; 737 int ret = 0; 738 739 ret = smu_cmn_get_metrics_table(smu, 740 NULL, 741 false); 742 if (ret) 743 return ret; 744 745 switch (member) { 746 case METRICS_CURR_GFXCLK: 747 *value = metrics->CurrClock[PPCLK_GFXCLK]; 748 break; 749 case METRICS_CURR_SOCCLK: 750 *value = metrics->CurrClock[PPCLK_SOCCLK]; 751 break; 752 case METRICS_CURR_UCLK: 753 *value = metrics->CurrClock[PPCLK_UCLK]; 754 break; 755 case METRICS_CURR_VCLK: 756 *value = metrics->CurrClock[PPCLK_VCLK]; 757 break; 758 case METRICS_CURR_DCLK: 759 *value = metrics->CurrClock[PPCLK_DCLK]; 760 break; 761 case METRICS_CURR_DCEFCLK: 762 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 763 break; 764 case METRICS_AVERAGE_GFXCLK: 765 *value = metrics->AverageGfxclkFrequency; 766 break; 767 case METRICS_AVERAGE_SOCCLK: 768 *value = metrics->AverageSocclkFrequency; 769 break; 770 case METRICS_AVERAGE_UCLK: 771 *value = metrics->AverageUclkFrequency; 772 break; 773 case METRICS_AVERAGE_GFXACTIVITY: 774 *value = metrics->AverageGfxActivity; 775 break; 776 case METRICS_AVERAGE_MEMACTIVITY: 777 *value = metrics->AverageUclkActivity; 778 break; 779 case METRICS_AVERAGE_SOCKETPOWER: 780 *value = metrics->AverageSocketPower << 8; 781 break; 782 case METRICS_TEMPERATURE_EDGE: 783 *value = metrics->TemperatureEdge * 784 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 785 break; 786 case METRICS_TEMPERATURE_HOTSPOT: 787 *value = metrics->TemperatureHotspot * 788 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 789 break; 790 case METRICS_TEMPERATURE_MEM: 791 *value = metrics->TemperatureMem * 792 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 793 break; 794 case METRICS_TEMPERATURE_VRGFX: 795 *value = metrics->TemperatureVrGfx * 796 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 797 break; 798 case METRICS_TEMPERATURE_VRSOC: 799 *value = metrics->TemperatureVrSoc * 800 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 801 break; 802 case METRICS_THROTTLER_STATUS: 803 *value = metrics->ThrottlerStatus; 804 break; 805 case METRICS_CURR_FANSPEED: 806 *value = metrics->CurrFanSpeed; 807 break; 808 default: 809 *value = UINT_MAX; 810 break; 811 } 812 813 return ret; 814 } 815 816 static int navi12_get_smu_metrics_data(struct smu_context *smu, 817 MetricsMember_t member, 818 uint32_t *value) 819 { 820 struct smu_table_context *smu_table = &smu->smu_table; 821 SmuMetrics_NV12_t *metrics = 822 (SmuMetrics_NV12_t *)smu_table->metrics_table; 823 int ret = 0; 824 825 ret = smu_cmn_get_metrics_table(smu, 826 NULL, 827 false); 828 if (ret) 829 return ret; 830 831 switch (member) { 832 case METRICS_CURR_GFXCLK: 833 *value = metrics->CurrClock[PPCLK_GFXCLK]; 834 break; 835 case METRICS_CURR_SOCCLK: 836 *value = metrics->CurrClock[PPCLK_SOCCLK]; 837 break; 838 case METRICS_CURR_UCLK: 839 *value = metrics->CurrClock[PPCLK_UCLK]; 840 break; 841 case METRICS_CURR_VCLK: 842 *value = metrics->CurrClock[PPCLK_VCLK]; 843 break; 844 case METRICS_CURR_DCLK: 845 *value = metrics->CurrClock[PPCLK_DCLK]; 846 break; 847 case METRICS_CURR_DCEFCLK: 848 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 849 break; 850 case METRICS_AVERAGE_GFXCLK: 851 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 852 *value = metrics->AverageGfxclkFrequencyPreDs; 853 else 854 *value = metrics->AverageGfxclkFrequencyPostDs; 855 break; 856 case METRICS_AVERAGE_SOCCLK: 857 *value = metrics->AverageSocclkFrequency; 858 break; 859 case METRICS_AVERAGE_UCLK: 860 *value = metrics->AverageUclkFrequencyPostDs; 861 break; 862 case METRICS_AVERAGE_GFXACTIVITY: 863 *value = metrics->AverageGfxActivity; 864 break; 865 case METRICS_AVERAGE_MEMACTIVITY: 866 *value = metrics->AverageUclkActivity; 867 break; 868 case METRICS_AVERAGE_SOCKETPOWER: 869 *value = metrics->AverageSocketPower << 8; 870 break; 871 case METRICS_TEMPERATURE_EDGE: 872 *value = metrics->TemperatureEdge * 873 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 874 break; 875 case METRICS_TEMPERATURE_HOTSPOT: 876 *value = metrics->TemperatureHotspot * 877 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 878 break; 879 case METRICS_TEMPERATURE_MEM: 880 *value = metrics->TemperatureMem * 881 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 882 break; 883 case METRICS_TEMPERATURE_VRGFX: 884 *value = metrics->TemperatureVrGfx * 885 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 886 break; 887 case METRICS_TEMPERATURE_VRSOC: 888 *value = metrics->TemperatureVrSoc * 889 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 890 break; 891 case METRICS_THROTTLER_STATUS: 892 *value = metrics->ThrottlerStatus; 893 break; 894 case METRICS_CURR_FANSPEED: 895 *value = metrics->CurrFanSpeed; 896 break; 897 default: 898 *value = UINT_MAX; 899 break; 900 } 901 902 return ret; 903 } 904 905 static int navi1x_get_smu_metrics_data(struct smu_context *smu, 906 MetricsMember_t member, 907 uint32_t *value) 908 { 909 struct amdgpu_device *adev = smu->adev; 910 int ret = 0; 911 912 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 913 case IP_VERSION(11, 0, 9): 914 if (smu->smc_fw_version > 0x00341C00) 915 ret = navi12_get_smu_metrics_data(smu, member, value); 916 else 917 ret = navi12_get_legacy_smu_metrics_data(smu, member, value); 918 break; 919 case IP_VERSION(11, 0, 0): 920 case IP_VERSION(11, 0, 5): 921 default: 922 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == 923 IP_VERSION(11, 0, 5)) && 924 smu->smc_fw_version > 0x00351F00) || 925 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == 926 IP_VERSION(11, 0, 0)) && 927 smu->smc_fw_version > 0x002A3B00)) 928 ret = navi10_get_smu_metrics_data(smu, member, value); 929 else 930 ret = navi10_get_legacy_smu_metrics_data(smu, member, value); 931 break; 932 } 933 934 return ret; 935 } 936 937 static int navi10_allocate_dpm_context(struct smu_context *smu) 938 { 939 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 940 941 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 942 GFP_KERNEL); 943 if (!smu_dpm->dpm_context) 944 return -ENOMEM; 945 946 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 947 948 return 0; 949 } 950 951 static int navi10_init_smc_tables(struct smu_context *smu) 952 { 953 int ret = 0; 954 955 ret = navi10_tables_init(smu); 956 if (ret) 957 return ret; 958 959 ret = navi10_allocate_dpm_context(smu); 960 if (ret) 961 return ret; 962 963 return smu_v11_0_init_smc_tables(smu); 964 } 965 966 static int navi10_set_default_dpm_table(struct smu_context *smu) 967 { 968 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 969 PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 970 struct smu_11_0_dpm_table *dpm_table; 971 int ret = 0; 972 973 /* socclk dpm table setup */ 974 dpm_table = &dpm_context->dpm_tables.soc_table; 975 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 976 ret = smu_v11_0_set_single_dpm_table(smu, 977 SMU_SOCCLK, 978 dpm_table); 979 if (ret) 980 return ret; 981 dpm_table->is_fine_grained = 982 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete; 983 } else { 984 dpm_table->count = 1; 985 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 986 dpm_table->dpm_levels[0].enabled = true; 987 dpm_table->min = dpm_table->dpm_levels[0].value; 988 dpm_table->max = dpm_table->dpm_levels[0].value; 989 } 990 991 /* gfxclk dpm table setup */ 992 dpm_table = &dpm_context->dpm_tables.gfx_table; 993 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 994 ret = smu_v11_0_set_single_dpm_table(smu, 995 SMU_GFXCLK, 996 dpm_table); 997 if (ret) 998 return ret; 999 dpm_table->is_fine_grained = 1000 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete; 1001 } else { 1002 dpm_table->count = 1; 1003 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 1004 dpm_table->dpm_levels[0].enabled = true; 1005 dpm_table->min = dpm_table->dpm_levels[0].value; 1006 dpm_table->max = dpm_table->dpm_levels[0].value; 1007 } 1008 1009 /* uclk dpm table setup */ 1010 dpm_table = &dpm_context->dpm_tables.uclk_table; 1011 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1012 ret = smu_v11_0_set_single_dpm_table(smu, 1013 SMU_UCLK, 1014 dpm_table); 1015 if (ret) 1016 return ret; 1017 dpm_table->is_fine_grained = 1018 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete; 1019 } else { 1020 dpm_table->count = 1; 1021 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 1022 dpm_table->dpm_levels[0].enabled = true; 1023 dpm_table->min = dpm_table->dpm_levels[0].value; 1024 dpm_table->max = dpm_table->dpm_levels[0].value; 1025 } 1026 1027 /* vclk dpm table setup */ 1028 dpm_table = &dpm_context->dpm_tables.vclk_table; 1029 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1030 ret = smu_v11_0_set_single_dpm_table(smu, 1031 SMU_VCLK, 1032 dpm_table); 1033 if (ret) 1034 return ret; 1035 dpm_table->is_fine_grained = 1036 !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete; 1037 } else { 1038 dpm_table->count = 1; 1039 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 1040 dpm_table->dpm_levels[0].enabled = true; 1041 dpm_table->min = dpm_table->dpm_levels[0].value; 1042 dpm_table->max = dpm_table->dpm_levels[0].value; 1043 } 1044 1045 /* dclk dpm table setup */ 1046 dpm_table = &dpm_context->dpm_tables.dclk_table; 1047 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1048 ret = smu_v11_0_set_single_dpm_table(smu, 1049 SMU_DCLK, 1050 dpm_table); 1051 if (ret) 1052 return ret; 1053 dpm_table->is_fine_grained = 1054 !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete; 1055 } else { 1056 dpm_table->count = 1; 1057 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 1058 dpm_table->dpm_levels[0].enabled = true; 1059 dpm_table->min = dpm_table->dpm_levels[0].value; 1060 dpm_table->max = dpm_table->dpm_levels[0].value; 1061 } 1062 1063 /* dcefclk dpm table setup */ 1064 dpm_table = &dpm_context->dpm_tables.dcef_table; 1065 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1066 ret = smu_v11_0_set_single_dpm_table(smu, 1067 SMU_DCEFCLK, 1068 dpm_table); 1069 if (ret) 1070 return ret; 1071 dpm_table->is_fine_grained = 1072 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete; 1073 } else { 1074 dpm_table->count = 1; 1075 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1076 dpm_table->dpm_levels[0].enabled = true; 1077 dpm_table->min = dpm_table->dpm_levels[0].value; 1078 dpm_table->max = dpm_table->dpm_levels[0].value; 1079 } 1080 1081 /* pixelclk dpm table setup */ 1082 dpm_table = &dpm_context->dpm_tables.pixel_table; 1083 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1084 ret = smu_v11_0_set_single_dpm_table(smu, 1085 SMU_PIXCLK, 1086 dpm_table); 1087 if (ret) 1088 return ret; 1089 dpm_table->is_fine_grained = 1090 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete; 1091 } else { 1092 dpm_table->count = 1; 1093 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1094 dpm_table->dpm_levels[0].enabled = true; 1095 dpm_table->min = dpm_table->dpm_levels[0].value; 1096 dpm_table->max = dpm_table->dpm_levels[0].value; 1097 } 1098 1099 /* displayclk dpm table setup */ 1100 dpm_table = &dpm_context->dpm_tables.display_table; 1101 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1102 ret = smu_v11_0_set_single_dpm_table(smu, 1103 SMU_DISPCLK, 1104 dpm_table); 1105 if (ret) 1106 return ret; 1107 dpm_table->is_fine_grained = 1108 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete; 1109 } else { 1110 dpm_table->count = 1; 1111 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1112 dpm_table->dpm_levels[0].enabled = true; 1113 dpm_table->min = dpm_table->dpm_levels[0].value; 1114 dpm_table->max = dpm_table->dpm_levels[0].value; 1115 } 1116 1117 /* phyclk dpm table setup */ 1118 dpm_table = &dpm_context->dpm_tables.phy_table; 1119 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1120 ret = smu_v11_0_set_single_dpm_table(smu, 1121 SMU_PHYCLK, 1122 dpm_table); 1123 if (ret) 1124 return ret; 1125 dpm_table->is_fine_grained = 1126 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete; 1127 } else { 1128 dpm_table->count = 1; 1129 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1130 dpm_table->dpm_levels[0].enabled = true; 1131 dpm_table->min = dpm_table->dpm_levels[0].value; 1132 dpm_table->max = dpm_table->dpm_levels[0].value; 1133 } 1134 1135 return 0; 1136 } 1137 1138 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, 1139 bool enable, 1140 int inst) 1141 { 1142 int ret = 0; 1143 1144 if (enable) { 1145 /* vcn dpm on is a prerequisite for vcn power gate messages */ 1146 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1147 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL); 1148 if (ret) 1149 return ret; 1150 } 1151 } else { 1152 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1153 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); 1154 if (ret) 1155 return ret; 1156 } 1157 } 1158 1159 return ret; 1160 } 1161 1162 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 1163 { 1164 int ret = 0; 1165 1166 if (enable) { 1167 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 1168 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL); 1169 if (ret) 1170 return ret; 1171 } 1172 } else { 1173 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 1174 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL); 1175 if (ret) 1176 return ret; 1177 } 1178 } 1179 1180 return ret; 1181 } 1182 1183 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, 1184 enum smu_clk_type clk_type, 1185 uint32_t *value) 1186 { 1187 MetricsMember_t member_type; 1188 int clk_id = 0; 1189 1190 clk_id = smu_cmn_to_asic_specific_index(smu, 1191 CMN2ASIC_MAPPING_CLK, 1192 clk_type); 1193 if (clk_id < 0) 1194 return clk_id; 1195 1196 switch (clk_id) { 1197 case PPCLK_GFXCLK: 1198 member_type = METRICS_CURR_GFXCLK; 1199 break; 1200 case PPCLK_UCLK: 1201 member_type = METRICS_CURR_UCLK; 1202 break; 1203 case PPCLK_SOCCLK: 1204 member_type = METRICS_CURR_SOCCLK; 1205 break; 1206 case PPCLK_VCLK: 1207 member_type = METRICS_CURR_VCLK; 1208 break; 1209 case PPCLK_DCLK: 1210 member_type = METRICS_CURR_DCLK; 1211 break; 1212 case PPCLK_DCEFCLK: 1213 member_type = METRICS_CURR_DCEFCLK; 1214 break; 1215 default: 1216 return -EINVAL; 1217 } 1218 1219 return navi1x_get_smu_metrics_data(smu, 1220 member_type, 1221 value); 1222 } 1223 1224 static int navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 1225 { 1226 PPTable_t *pptable = smu->smu_table.driver_pptable; 1227 DpmDescriptor_t *dpm_desc = NULL; 1228 int clk_index = 0; 1229 1230 clk_index = smu_cmn_to_asic_specific_index(smu, 1231 CMN2ASIC_MAPPING_CLK, 1232 clk_type); 1233 if (clk_index < 0) 1234 return clk_index; 1235 1236 dpm_desc = &pptable->DpmDescriptor[clk_index]; 1237 1238 /* 0 - Fine grained DPM, 1 - Discrete DPM */ 1239 return dpm_desc->SnapToDiscrete == 0 ? 1 : 0; 1240 } 1241 1242 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap) 1243 { 1244 return od_table->cap[cap]; 1245 } 1246 1247 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table, 1248 enum SMU_11_0_ODSETTING_ID setting, 1249 uint32_t *min, uint32_t *max) 1250 { 1251 if (min) 1252 *min = od_table->min[setting]; 1253 if (max) 1254 *max = od_table->max[setting]; 1255 } 1256 1257 static int navi10_emit_clk_levels(struct smu_context *smu, 1258 enum smu_clk_type clk_type, 1259 char *buf, 1260 int *offset) 1261 { 1262 uint16_t *curve_settings; 1263 int ret = 0; 1264 uint32_t cur_value = 0, value = 0; 1265 uint32_t freq_values[3] = {0}; 1266 uint32_t i, levels, mark_index = 0, count = 0; 1267 struct smu_table_context *table_context = &smu->smu_table; 1268 uint32_t gen_speed, lane_width; 1269 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1270 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1271 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; 1272 OverDriveTable_t *od_table = 1273 (OverDriveTable_t *)table_context->overdrive_table; 1274 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 1275 uint32_t min_value, max_value; 1276 1277 switch (clk_type) { 1278 case SMU_GFXCLK: 1279 case SMU_SCLK: 1280 case SMU_SOCCLK: 1281 case SMU_MCLK: 1282 case SMU_UCLK: 1283 case SMU_FCLK: 1284 case SMU_VCLK: 1285 case SMU_DCLK: 1286 case SMU_DCEFCLK: 1287 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1288 if (ret) 1289 return ret; 1290 1291 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1292 if (ret) 1293 return ret; 1294 1295 ret = navi10_is_support_fine_grained_dpm(smu, clk_type); 1296 if (ret < 0) 1297 return ret; 1298 1299 if (!ret) { 1300 for (i = 0; i < count; i++) { 1301 ret = smu_v11_0_get_dpm_freq_by_index(smu, 1302 clk_type, i, &value); 1303 if (ret) 1304 return ret; 1305 1306 *offset += sysfs_emit_at(buf, *offset, 1307 "%d: %uMhz %s\n", 1308 i, value, 1309 cur_value == value ? "*" : ""); 1310 } 1311 } else { 1312 ret = smu_v11_0_get_dpm_freq_by_index(smu, 1313 clk_type, 0, &freq_values[0]); 1314 if (ret) 1315 return ret; 1316 ret = smu_v11_0_get_dpm_freq_by_index(smu, 1317 clk_type, 1318 count - 1, 1319 &freq_values[2]); 1320 if (ret) 1321 return ret; 1322 1323 freq_values[1] = cur_value; 1324 mark_index = cur_value == freq_values[0] ? 0 : 1325 cur_value == freq_values[2] ? 2 : 1; 1326 1327 levels = 3; 1328 if (mark_index != 1) { 1329 levels = 2; 1330 freq_values[1] = freq_values[2]; 1331 } 1332 1333 for (i = 0; i < levels; i++) { 1334 *offset += sysfs_emit_at(buf, *offset, 1335 "%d: %uMhz %s\n", 1336 i, freq_values[i], 1337 i == mark_index ? "*" : ""); 1338 } 1339 } 1340 break; 1341 case SMU_PCIE: 1342 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1343 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1344 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1345 *offset += sysfs_emit_at(buf, *offset, "%d: %s %s %dMhz %s\n", i, 1346 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1347 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1348 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1349 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1350 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1351 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1352 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1353 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1354 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1355 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1356 pptable->LclkFreq[i], 1357 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1358 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1359 "*" : ""); 1360 } 1361 break; 1362 case SMU_OD_SCLK: 1363 if (!smu->od_enabled || !od_table || !od_settings) 1364 return -EOPNOTSUPP; 1365 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) 1366 break; 1367 *offset += sysfs_emit_at(buf, *offset, "OD_SCLK:\n0: %uMhz\n1: %uMhz\n", 1368 od_table->GfxclkFmin, od_table->GfxclkFmax); 1369 break; 1370 case SMU_OD_MCLK: 1371 if (!smu->od_enabled || !od_table || !od_settings) 1372 return -EOPNOTSUPP; 1373 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) 1374 break; 1375 *offset += sysfs_emit_at(buf, *offset, "OD_MCLK:\n1: %uMHz\n", od_table->UclkFmax); 1376 break; 1377 case SMU_OD_VDDC_CURVE: 1378 if (!smu->od_enabled || !od_table || !od_settings) 1379 return -EOPNOTSUPP; 1380 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) 1381 break; 1382 *offset += sysfs_emit_at(buf, *offset, "OD_VDDC_CURVE:\n"); 1383 for (i = 0; i < 3; i++) { 1384 switch (i) { 1385 case 0: 1386 curve_settings = &od_table->GfxclkFreq1; 1387 break; 1388 case 1: 1389 curve_settings = &od_table->GfxclkFreq2; 1390 break; 1391 case 2: 1392 curve_settings = &od_table->GfxclkFreq3; 1393 break; 1394 } 1395 *offset += sysfs_emit_at(buf, *offset, "%d: %uMHz %umV\n", 1396 i, curve_settings[0], 1397 curve_settings[1] / NAVI10_VOLTAGE_SCALE); 1398 } 1399 break; 1400 case SMU_OD_RANGE: 1401 if (!smu->od_enabled || !od_table || !od_settings) 1402 return -EOPNOTSUPP; 1403 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE"); 1404 1405 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 1406 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, 1407 &min_value, NULL); 1408 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, 1409 NULL, &max_value); 1410 *offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMhz %10uMhz\n", 1411 min_value, max_value); 1412 } 1413 1414 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 1415 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, 1416 &min_value, &max_value); 1417 *offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMhz %10uMhz\n", 1418 min_value, max_value); 1419 } 1420 1421 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 1422 navi10_od_setting_get_range(od_settings, 1423 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, 1424 &min_value, &max_value); 1425 *offset += sysfs_emit_at(buf, *offset, 1426 "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", 1427 min_value, max_value); 1428 navi10_od_setting_get_range(od_settings, 1429 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, 1430 &min_value, &max_value); 1431 *offset += sysfs_emit_at(buf, *offset, 1432 "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", 1433 min_value, max_value); 1434 navi10_od_setting_get_range(od_settings, 1435 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, 1436 &min_value, &max_value); 1437 *offset += sysfs_emit_at(buf, *offset, 1438 "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", 1439 min_value, max_value); 1440 navi10_od_setting_get_range(od_settings, 1441 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, 1442 &min_value, &max_value); 1443 *offset += sysfs_emit_at(buf, *offset, 1444 "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", 1445 min_value, max_value); 1446 navi10_od_setting_get_range(od_settings, 1447 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, 1448 &min_value, &max_value); 1449 *offset += sysfs_emit_at(buf, *offset, 1450 "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", 1451 min_value, max_value); 1452 navi10_od_setting_get_range(od_settings, 1453 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, 1454 &min_value, &max_value); 1455 *offset += sysfs_emit_at(buf, *offset, 1456 "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", 1457 min_value, max_value); 1458 } 1459 1460 break; 1461 default: 1462 break; 1463 } 1464 1465 return 0; 1466 } 1467 1468 static int navi10_print_clk_levels(struct smu_context *smu, 1469 enum smu_clk_type clk_type, char *buf) 1470 { 1471 uint16_t *curve_settings; 1472 int i, levels, size = 0, ret = 0; 1473 uint32_t cur_value = 0, value = 0, count = 0; 1474 uint32_t freq_values[3] = {0}; 1475 uint32_t mark_index = 0; 1476 struct smu_table_context *table_context = &smu->smu_table; 1477 uint32_t gen_speed, lane_width; 1478 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1479 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1480 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; 1481 OverDriveTable_t *od_table = 1482 (OverDriveTable_t *)table_context->overdrive_table; 1483 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 1484 uint32_t min_value, max_value; 1485 1486 smu_cmn_get_sysfs_buf(&buf, &size); 1487 1488 switch (clk_type) { 1489 case SMU_GFXCLK: 1490 case SMU_SCLK: 1491 case SMU_SOCCLK: 1492 case SMU_MCLK: 1493 case SMU_UCLK: 1494 case SMU_FCLK: 1495 case SMU_VCLK: 1496 case SMU_DCLK: 1497 case SMU_DCEFCLK: 1498 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1499 if (ret) 1500 return size; 1501 1502 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1503 if (ret) 1504 return size; 1505 1506 ret = navi10_is_support_fine_grained_dpm(smu, clk_type); 1507 if (ret < 0) 1508 return ret; 1509 1510 if (!ret) { 1511 for (i = 0; i < count; i++) { 1512 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); 1513 if (ret) 1514 return size; 1515 1516 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 1517 cur_value == value ? "*" : ""); 1518 } 1519 } else { 1520 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); 1521 if (ret) 1522 return size; 1523 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); 1524 if (ret) 1525 return size; 1526 1527 freq_values[1] = cur_value; 1528 mark_index = cur_value == freq_values[0] ? 0 : 1529 cur_value == freq_values[2] ? 2 : 1; 1530 1531 levels = 3; 1532 if (mark_index != 1) { 1533 levels = 2; 1534 freq_values[1] = freq_values[2]; 1535 } 1536 1537 for (i = 0; i < levels; i++) { 1538 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i], 1539 i == mark_index ? "*" : ""); 1540 } 1541 } 1542 break; 1543 case SMU_PCIE: 1544 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1545 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1546 for (i = 0; i < NUM_LINK_LEVELS; i++) 1547 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1548 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1549 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1550 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1551 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1552 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1553 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1554 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1555 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1556 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1557 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1558 pptable->LclkFreq[i], 1559 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1560 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1561 "*" : ""); 1562 break; 1563 case SMU_OD_SCLK: 1564 if (!smu->od_enabled || !od_table || !od_settings) 1565 break; 1566 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) 1567 break; 1568 size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); 1569 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", 1570 od_table->GfxclkFmin, od_table->GfxclkFmax); 1571 break; 1572 case SMU_OD_MCLK: 1573 if (!smu->od_enabled || !od_table || !od_settings) 1574 break; 1575 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) 1576 break; 1577 size += sysfs_emit_at(buf, size, "OD_MCLK:\n"); 1578 size += sysfs_emit_at(buf, size, "1: %uMHz\n", od_table->UclkFmax); 1579 break; 1580 case SMU_OD_VDDC_CURVE: 1581 if (!smu->od_enabled || !od_table || !od_settings) 1582 break; 1583 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) 1584 break; 1585 size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n"); 1586 for (i = 0; i < 3; i++) { 1587 switch (i) { 1588 case 0: 1589 curve_settings = &od_table->GfxclkFreq1; 1590 break; 1591 case 1: 1592 curve_settings = &od_table->GfxclkFreq2; 1593 break; 1594 case 2: 1595 curve_settings = &od_table->GfxclkFreq3; 1596 break; 1597 } 1598 size += sysfs_emit_at(buf, size, "%d: %uMHz %umV\n", 1599 i, curve_settings[0], 1600 curve_settings[1] / NAVI10_VOLTAGE_SCALE); 1601 } 1602 break; 1603 case SMU_OD_RANGE: 1604 if (!smu->od_enabled || !od_table || !od_settings) 1605 break; 1606 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1607 1608 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 1609 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, 1610 &min_value, NULL); 1611 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, 1612 NULL, &max_value); 1613 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 1614 min_value, max_value); 1615 } 1616 1617 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 1618 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, 1619 &min_value, &max_value); 1620 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n", 1621 min_value, max_value); 1622 } 1623 1624 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 1625 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, 1626 &min_value, &max_value); 1627 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", 1628 min_value, max_value); 1629 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, 1630 &min_value, &max_value); 1631 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", 1632 min_value, max_value); 1633 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, 1634 &min_value, &max_value); 1635 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", 1636 min_value, max_value); 1637 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, 1638 &min_value, &max_value); 1639 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", 1640 min_value, max_value); 1641 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, 1642 &min_value, &max_value); 1643 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", 1644 min_value, max_value); 1645 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, 1646 &min_value, &max_value); 1647 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", 1648 min_value, max_value); 1649 } 1650 1651 break; 1652 default: 1653 break; 1654 } 1655 1656 return size; 1657 } 1658 1659 static int navi10_force_clk_levels(struct smu_context *smu, 1660 enum smu_clk_type clk_type, uint32_t mask) 1661 { 1662 1663 int ret = 0; 1664 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 1665 1666 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1667 soft_max_level = mask ? (fls(mask) - 1) : 0; 1668 1669 switch (clk_type) { 1670 case SMU_GFXCLK: 1671 case SMU_SCLK: 1672 case SMU_SOCCLK: 1673 case SMU_MCLK: 1674 case SMU_UCLK: 1675 case SMU_FCLK: 1676 /* There is only 2 levels for fine grained DPM */ 1677 ret = navi10_is_support_fine_grained_dpm(smu, clk_type); 1678 if (ret < 0) 1679 return ret; 1680 1681 if (ret) { 1682 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1683 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1684 } 1685 1686 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 1687 if (ret) 1688 return 0; 1689 1690 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 1691 if (ret) 1692 return 0; 1693 1694 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false); 1695 if (ret) 1696 return 0; 1697 break; 1698 case SMU_DCEFCLK: 1699 dev_info(smu->adev->dev, "Setting DCEFCLK min/max dpm level is not supported!\n"); 1700 break; 1701 1702 default: 1703 break; 1704 } 1705 1706 return 0; 1707 } 1708 1709 static int navi10_populate_umd_state_clk(struct smu_context *smu) 1710 { 1711 struct smu_11_0_dpm_context *dpm_context = 1712 smu->smu_dpm.dpm_context; 1713 struct smu_11_0_dpm_table *gfx_table = 1714 &dpm_context->dpm_tables.gfx_table; 1715 struct smu_11_0_dpm_table *mem_table = 1716 &dpm_context->dpm_tables.uclk_table; 1717 struct smu_11_0_dpm_table *soc_table = 1718 &dpm_context->dpm_tables.soc_table; 1719 struct smu_umd_pstate_table *pstate_table = 1720 &smu->pstate_table; 1721 struct amdgpu_device *adev = smu->adev; 1722 uint32_t sclk_freq; 1723 1724 pstate_table->gfxclk_pstate.min = gfx_table->min; 1725 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1726 case IP_VERSION(11, 0, 0): 1727 switch (adev->pdev->revision) { 1728 case 0xf0: /* XTX */ 1729 case 0xc0: 1730 sclk_freq = NAVI10_PEAK_SCLK_XTX; 1731 break; 1732 case 0xf1: /* XT */ 1733 case 0xc1: 1734 sclk_freq = NAVI10_PEAK_SCLK_XT; 1735 break; 1736 default: /* XL */ 1737 sclk_freq = NAVI10_PEAK_SCLK_XL; 1738 break; 1739 } 1740 break; 1741 case IP_VERSION(11, 0, 5): 1742 switch (adev->pdev->revision) { 1743 case 0xc7: /* XT */ 1744 case 0xf4: 1745 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK; 1746 break; 1747 case 0xc1: /* XTM */ 1748 case 0xf2: 1749 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK; 1750 break; 1751 case 0xc3: /* XLM */ 1752 case 0xf3: 1753 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK; 1754 break; 1755 case 0xc5: /* XTX */ 1756 case 0xf6: 1757 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK; 1758 break; 1759 default: /* XL */ 1760 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK; 1761 break; 1762 } 1763 break; 1764 case IP_VERSION(11, 0, 9): 1765 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK; 1766 break; 1767 default: 1768 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value; 1769 break; 1770 } 1771 pstate_table->gfxclk_pstate.peak = sclk_freq; 1772 1773 pstate_table->uclk_pstate.min = mem_table->min; 1774 pstate_table->uclk_pstate.peak = mem_table->max; 1775 1776 pstate_table->socclk_pstate.min = soc_table->min; 1777 pstate_table->socclk_pstate.peak = soc_table->max; 1778 1779 if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK && 1780 mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK && 1781 soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) { 1782 pstate_table->gfxclk_pstate.standard = 1783 NAVI10_UMD_PSTATE_PROFILING_GFXCLK; 1784 pstate_table->uclk_pstate.standard = 1785 NAVI10_UMD_PSTATE_PROFILING_MEMCLK; 1786 pstate_table->socclk_pstate.standard = 1787 NAVI10_UMD_PSTATE_PROFILING_SOCCLK; 1788 } else { 1789 pstate_table->gfxclk_pstate.standard = 1790 pstate_table->gfxclk_pstate.min; 1791 pstate_table->uclk_pstate.standard = 1792 pstate_table->uclk_pstate.min; 1793 pstate_table->socclk_pstate.standard = 1794 pstate_table->socclk_pstate.min; 1795 } 1796 1797 return 0; 1798 } 1799 1800 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu, 1801 enum smu_clk_type clk_type, 1802 struct pp_clock_levels_with_latency *clocks) 1803 { 1804 int ret = 0, i = 0; 1805 uint32_t level_count = 0, freq = 0; 1806 1807 switch (clk_type) { 1808 case SMU_GFXCLK: 1809 case SMU_DCEFCLK: 1810 case SMU_SOCCLK: 1811 case SMU_MCLK: 1812 case SMU_UCLK: 1813 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count); 1814 if (ret) 1815 return ret; 1816 1817 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS); 1818 clocks->num_levels = level_count; 1819 1820 for (i = 0; i < level_count; i++) { 1821 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq); 1822 if (ret) 1823 return ret; 1824 1825 clocks->data[i].clocks_in_khz = freq * 1000; 1826 clocks->data[i].latency_in_us = 0; 1827 } 1828 break; 1829 default: 1830 break; 1831 } 1832 1833 return ret; 1834 } 1835 1836 static int navi10_pre_display_config_changed(struct smu_context *smu) 1837 { 1838 int ret = 0; 1839 uint32_t max_freq = 0; 1840 1841 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); 1842 if (ret) 1843 return ret; 1844 1845 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1846 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); 1847 if (ret) 1848 return ret; 1849 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); 1850 if (ret) 1851 return ret; 1852 } 1853 1854 return ret; 1855 } 1856 1857 static int navi10_display_config_changed(struct smu_context *smu) 1858 { 1859 int ret = 0; 1860 1861 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1862 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && 1863 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 1864 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 1865 smu->display_config->num_display, 1866 NULL); 1867 if (ret) 1868 return ret; 1869 } 1870 1871 return ret; 1872 } 1873 1874 static bool navi10_is_dpm_running(struct smu_context *smu) 1875 { 1876 int ret = 0; 1877 uint64_t feature_enabled; 1878 1879 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1880 if (ret) 1881 return false; 1882 1883 return !!(feature_enabled & SMC_DPM_FEATURE); 1884 } 1885 1886 static int navi10_get_fan_speed_rpm(struct smu_context *smu, 1887 uint32_t *speed) 1888 { 1889 int ret = 0; 1890 1891 if (!speed) 1892 return -EINVAL; 1893 1894 switch (smu_v11_0_get_fan_control_mode(smu)) { 1895 case AMD_FAN_CTRL_AUTO: 1896 ret = navi10_get_smu_metrics_data(smu, 1897 METRICS_CURR_FANSPEED, 1898 speed); 1899 break; 1900 default: 1901 ret = smu_v11_0_get_fan_speed_rpm(smu, 1902 speed); 1903 break; 1904 } 1905 1906 return ret; 1907 } 1908 1909 static int navi10_get_fan_parameters(struct smu_context *smu) 1910 { 1911 PPTable_t *pptable = smu->smu_table.driver_pptable; 1912 1913 smu->fan_max_rpm = pptable->FanMaximumRpm; 1914 1915 return 0; 1916 } 1917 1918 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf) 1919 { 1920 DpmActivityMonitorCoeffInt_t activity_monitor; 1921 uint32_t i, size = 0; 1922 int16_t workload_type = 0; 1923 static const char *title[] = { 1924 "PROFILE_INDEX(NAME)", 1925 "CLOCK_TYPE(NAME)", 1926 "FPS", 1927 "MinFreqType", 1928 "MinActiveFreqType", 1929 "MinActiveFreq", 1930 "BoosterFreqType", 1931 "BoosterFreq", 1932 "PD_Data_limit_c", 1933 "PD_Data_error_coeff", 1934 "PD_Data_error_rate_coeff"}; 1935 int result = 0; 1936 1937 if (!buf) 1938 return -EINVAL; 1939 1940 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1941 title[0], title[1], title[2], title[3], title[4], title[5], 1942 title[6], title[7], title[8], title[9], title[10]); 1943 1944 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1945 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1946 workload_type = smu_cmn_to_asic_specific_index(smu, 1947 CMN2ASIC_MAPPING_WORKLOAD, 1948 i); 1949 if (workload_type < 0) 1950 return -EINVAL; 1951 1952 result = smu_cmn_update_table(smu, 1953 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1954 (void *)(&activity_monitor), false); 1955 if (result) { 1956 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1957 return result; 1958 } 1959 1960 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 1961 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1962 1963 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1964 " ", 1965 0, 1966 "GFXCLK", 1967 activity_monitor.Gfx_FPS, 1968 activity_monitor.Gfx_MinFreqStep, 1969 activity_monitor.Gfx_MinActiveFreqType, 1970 activity_monitor.Gfx_MinActiveFreq, 1971 activity_monitor.Gfx_BoosterFreqType, 1972 activity_monitor.Gfx_BoosterFreq, 1973 activity_monitor.Gfx_PD_Data_limit_c, 1974 activity_monitor.Gfx_PD_Data_error_coeff, 1975 activity_monitor.Gfx_PD_Data_error_rate_coeff); 1976 1977 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1978 " ", 1979 1, 1980 "SOCCLK", 1981 activity_monitor.Soc_FPS, 1982 activity_monitor.Soc_MinFreqStep, 1983 activity_monitor.Soc_MinActiveFreqType, 1984 activity_monitor.Soc_MinActiveFreq, 1985 activity_monitor.Soc_BoosterFreqType, 1986 activity_monitor.Soc_BoosterFreq, 1987 activity_monitor.Soc_PD_Data_limit_c, 1988 activity_monitor.Soc_PD_Data_error_coeff, 1989 activity_monitor.Soc_PD_Data_error_rate_coeff); 1990 1991 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1992 " ", 1993 2, 1994 "MEMCLK", 1995 activity_monitor.Mem_FPS, 1996 activity_monitor.Mem_MinFreqStep, 1997 activity_monitor.Mem_MinActiveFreqType, 1998 activity_monitor.Mem_MinActiveFreq, 1999 activity_monitor.Mem_BoosterFreqType, 2000 activity_monitor.Mem_BoosterFreq, 2001 activity_monitor.Mem_PD_Data_limit_c, 2002 activity_monitor.Mem_PD_Data_error_coeff, 2003 activity_monitor.Mem_PD_Data_error_rate_coeff); 2004 } 2005 2006 return size; 2007 } 2008 2009 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 2010 { 2011 DpmActivityMonitorCoeffInt_t activity_monitor; 2012 int workload_type, ret = 0; 2013 2014 smu->power_profile_mode = input[size]; 2015 2016 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 2017 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 2018 return -EINVAL; 2019 } 2020 2021 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 2022 if (size != 10) 2023 return -EINVAL; 2024 2025 ret = smu_cmn_update_table(smu, 2026 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 2027 (void *)(&activity_monitor), false); 2028 if (ret) { 2029 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 2030 return ret; 2031 } 2032 2033 switch (input[0]) { 2034 case 0: /* Gfxclk */ 2035 activity_monitor.Gfx_FPS = input[1]; 2036 activity_monitor.Gfx_MinFreqStep = input[2]; 2037 activity_monitor.Gfx_MinActiveFreqType = input[3]; 2038 activity_monitor.Gfx_MinActiveFreq = input[4]; 2039 activity_monitor.Gfx_BoosterFreqType = input[5]; 2040 activity_monitor.Gfx_BoosterFreq = input[6]; 2041 activity_monitor.Gfx_PD_Data_limit_c = input[7]; 2042 activity_monitor.Gfx_PD_Data_error_coeff = input[8]; 2043 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9]; 2044 break; 2045 case 1: /* Socclk */ 2046 activity_monitor.Soc_FPS = input[1]; 2047 activity_monitor.Soc_MinFreqStep = input[2]; 2048 activity_monitor.Soc_MinActiveFreqType = input[3]; 2049 activity_monitor.Soc_MinActiveFreq = input[4]; 2050 activity_monitor.Soc_BoosterFreqType = input[5]; 2051 activity_monitor.Soc_BoosterFreq = input[6]; 2052 activity_monitor.Soc_PD_Data_limit_c = input[7]; 2053 activity_monitor.Soc_PD_Data_error_coeff = input[8]; 2054 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9]; 2055 break; 2056 case 2: /* Memclk */ 2057 activity_monitor.Mem_FPS = input[1]; 2058 activity_monitor.Mem_MinFreqStep = input[2]; 2059 activity_monitor.Mem_MinActiveFreqType = input[3]; 2060 activity_monitor.Mem_MinActiveFreq = input[4]; 2061 activity_monitor.Mem_BoosterFreqType = input[5]; 2062 activity_monitor.Mem_BoosterFreq = input[6]; 2063 activity_monitor.Mem_PD_Data_limit_c = input[7]; 2064 activity_monitor.Mem_PD_Data_error_coeff = input[8]; 2065 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; 2066 break; 2067 default: 2068 return -EINVAL; 2069 } 2070 2071 ret = smu_cmn_update_table(smu, 2072 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 2073 (void *)(&activity_monitor), true); 2074 if (ret) { 2075 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 2076 return ret; 2077 } 2078 } 2079 2080 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 2081 workload_type = smu_cmn_to_asic_specific_index(smu, 2082 CMN2ASIC_MAPPING_WORKLOAD, 2083 smu->power_profile_mode); 2084 if (workload_type < 0) 2085 return -EINVAL; 2086 2087 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 2088 smu->workload_mask, NULL); 2089 if (ret) 2090 dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__); 2091 else 2092 smu_cmn_assign_power_profile(smu); 2093 2094 return ret; 2095 } 2096 2097 static int navi10_notify_smc_display_config(struct smu_context *smu) 2098 { 2099 struct smu_clocks min_clocks = {0}; 2100 struct pp_display_clock_request clock_req; 2101 int ret = 0; 2102 2103 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; 2104 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; 2105 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 2106 2107 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 2108 clock_req.clock_type = amd_pp_dcef_clock; 2109 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; 2110 2111 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); 2112 if (!ret) { 2113 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { 2114 ret = smu_cmn_send_smc_msg_with_param(smu, 2115 SMU_MSG_SetMinDeepSleepDcefclk, 2116 min_clocks.dcef_clock_in_sr/100, 2117 NULL); 2118 if (ret) { 2119 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); 2120 return ret; 2121 } 2122 } 2123 } else { 2124 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); 2125 } 2126 } 2127 2128 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 2129 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); 2130 if (ret) { 2131 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); 2132 return ret; 2133 } 2134 } 2135 2136 return 0; 2137 } 2138 2139 static int navi10_set_watermarks_table(struct smu_context *smu, 2140 struct pp_smu_wm_range_sets *clock_ranges) 2141 { 2142 Watermarks_t *table = smu->smu_table.watermarks_table; 2143 int ret = 0; 2144 int i; 2145 2146 if (clock_ranges) { 2147 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 2148 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 2149 return -EINVAL; 2150 2151 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 2152 table->WatermarkRow[WM_DCEFCLK][i].MinClock = 2153 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 2154 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = 2155 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 2156 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = 2157 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 2158 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = 2159 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 2160 2161 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = 2162 clock_ranges->reader_wm_sets[i].wm_inst; 2163 } 2164 2165 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 2166 table->WatermarkRow[WM_SOCCLK][i].MinClock = 2167 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 2168 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 2169 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 2170 table->WatermarkRow[WM_SOCCLK][i].MinUclk = 2171 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 2172 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = 2173 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 2174 2175 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 2176 clock_ranges->writer_wm_sets[i].wm_inst; 2177 } 2178 2179 smu->watermarks_bitmap |= WATERMARKS_EXIST; 2180 } 2181 2182 /* pass data to smu controller */ 2183 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 2184 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 2185 ret = smu_cmn_write_watermarks_table(smu); 2186 if (ret) { 2187 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 2188 return ret; 2189 } 2190 smu->watermarks_bitmap |= WATERMARKS_LOADED; 2191 } 2192 2193 return 0; 2194 } 2195 2196 static int navi10_read_sensor(struct smu_context *smu, 2197 enum amd_pp_sensors sensor, 2198 void *data, uint32_t *size) 2199 { 2200 int ret = 0; 2201 struct smu_table_context *table_context = &smu->smu_table; 2202 PPTable_t *pptable = table_context->driver_pptable; 2203 2204 if (!data || !size) 2205 return -EINVAL; 2206 2207 switch (sensor) { 2208 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 2209 *(uint32_t *)data = pptable->FanMaximumRpm; 2210 *size = 4; 2211 break; 2212 case AMDGPU_PP_SENSOR_MEM_LOAD: 2213 ret = navi1x_get_smu_metrics_data(smu, 2214 METRICS_AVERAGE_MEMACTIVITY, 2215 (uint32_t *)data); 2216 *size = 4; 2217 break; 2218 case AMDGPU_PP_SENSOR_GPU_LOAD: 2219 ret = navi1x_get_smu_metrics_data(smu, 2220 METRICS_AVERAGE_GFXACTIVITY, 2221 (uint32_t *)data); 2222 *size = 4; 2223 break; 2224 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 2225 ret = navi1x_get_smu_metrics_data(smu, 2226 METRICS_AVERAGE_SOCKETPOWER, 2227 (uint32_t *)data); 2228 *size = 4; 2229 break; 2230 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 2231 ret = navi1x_get_smu_metrics_data(smu, 2232 METRICS_TEMPERATURE_HOTSPOT, 2233 (uint32_t *)data); 2234 *size = 4; 2235 break; 2236 case AMDGPU_PP_SENSOR_EDGE_TEMP: 2237 ret = navi1x_get_smu_metrics_data(smu, 2238 METRICS_TEMPERATURE_EDGE, 2239 (uint32_t *)data); 2240 *size = 4; 2241 break; 2242 case AMDGPU_PP_SENSOR_MEM_TEMP: 2243 ret = navi1x_get_smu_metrics_data(smu, 2244 METRICS_TEMPERATURE_MEM, 2245 (uint32_t *)data); 2246 *size = 4; 2247 break; 2248 case AMDGPU_PP_SENSOR_GFX_MCLK: 2249 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 2250 *(uint32_t *)data *= 100; 2251 *size = 4; 2252 break; 2253 case AMDGPU_PP_SENSOR_GFX_SCLK: 2254 ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data); 2255 *(uint32_t *)data *= 100; 2256 *size = 4; 2257 break; 2258 case AMDGPU_PP_SENSOR_VDDGFX: 2259 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 2260 *size = 4; 2261 break; 2262 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 2263 default: 2264 ret = -EOPNOTSUPP; 2265 break; 2266 } 2267 2268 return ret; 2269 } 2270 2271 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) 2272 { 2273 uint32_t num_discrete_levels = 0; 2274 uint16_t *dpm_levels = NULL; 2275 uint16_t i = 0; 2276 struct smu_table_context *table_context = &smu->smu_table; 2277 PPTable_t *driver_ppt = NULL; 2278 2279 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) 2280 return -EINVAL; 2281 2282 driver_ppt = table_context->driver_pptable; 2283 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels; 2284 dpm_levels = driver_ppt->FreqTableUclk; 2285 2286 if (num_discrete_levels == 0 || dpm_levels == NULL) 2287 return -EINVAL; 2288 2289 *num_states = num_discrete_levels; 2290 for (i = 0; i < num_discrete_levels; i++) { 2291 /* convert to khz */ 2292 *clocks_in_khz = (*dpm_levels) * 1000; 2293 clocks_in_khz++; 2294 dpm_levels++; 2295 } 2296 2297 return 0; 2298 } 2299 2300 static int navi10_get_thermal_temperature_range(struct smu_context *smu, 2301 struct smu_temperature_range *range) 2302 { 2303 struct smu_table_context *table_context = &smu->smu_table; 2304 struct smu_11_0_powerplay_table *powerplay_table = 2305 table_context->power_play_table; 2306 PPTable_t *pptable = smu->smu_table.driver_pptable; 2307 2308 if (!range) 2309 return -EINVAL; 2310 2311 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 2312 2313 range->max = pptable->TedgeLimit * 2314 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2315 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) * 2316 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2317 range->hotspot_crit_max = pptable->ThotspotLimit * 2318 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2319 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 2320 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2321 range->mem_crit_max = pptable->TmemLimit * 2322 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2323 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 2324 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2325 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 2326 2327 return 0; 2328 } 2329 2330 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu, 2331 bool disable_memory_clock_switch) 2332 { 2333 int ret = 0; 2334 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 2335 (struct smu_11_0_max_sustainable_clocks *) 2336 smu->smu_table.max_sustainable_clocks; 2337 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; 2338 uint32_t max_memory_clock = max_sustainable_clocks->uclock; 2339 2340 if (smu->disable_uclk_switch == disable_memory_clock_switch) 2341 return 0; 2342 2343 if (disable_memory_clock_switch) 2344 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); 2345 else 2346 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); 2347 2348 if (!ret) 2349 smu->disable_uclk_switch = disable_memory_clock_switch; 2350 2351 return ret; 2352 } 2353 2354 static int navi10_get_power_limit(struct smu_context *smu, 2355 uint32_t *current_power_limit, 2356 uint32_t *default_power_limit, 2357 uint32_t *max_power_limit, 2358 uint32_t *min_power_limit) 2359 { 2360 struct smu_11_0_powerplay_table *powerplay_table = 2361 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table; 2362 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 2363 PPTable_t *pptable = smu->smu_table.driver_pptable; 2364 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0; 2365 2366 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 2367 /* the last hope to figure out the ppt limit */ 2368 if (!pptable) { 2369 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); 2370 return -EINVAL; 2371 } 2372 power_limit = 2373 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; 2374 } 2375 2376 if (current_power_limit) 2377 *current_power_limit = power_limit; 2378 if (default_power_limit) 2379 *default_power_limit = power_limit; 2380 2381 if (powerplay_table) { 2382 if (smu->od_enabled && 2383 navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) { 2384 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 2385 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 2386 } else if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) { 2387 od_percent_upper = 0; 2388 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 2389 } 2390 } 2391 2392 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n", 2393 od_percent_upper, od_percent_lower, power_limit); 2394 2395 if (max_power_limit) { 2396 *max_power_limit = power_limit * (100 + od_percent_upper); 2397 *max_power_limit /= 100; 2398 } 2399 2400 if (min_power_limit) { 2401 *min_power_limit = power_limit * (100 - od_percent_lower); 2402 *min_power_limit /= 100; 2403 } 2404 2405 return 0; 2406 } 2407 2408 static int navi10_update_pcie_parameters(struct smu_context *smu, 2409 uint8_t pcie_gen_cap, 2410 uint8_t pcie_width_cap) 2411 { 2412 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 2413 PPTable_t *pptable = smu->smu_table.driver_pptable; 2414 uint32_t smu_pcie_arg; 2415 int ret, i; 2416 2417 /* lclk dpm table setup */ 2418 for (i = 0; i < MAX_PCIE_CONF; i++) { 2419 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i]; 2420 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; 2421 } 2422 2423 for (i = 0; i < NUM_LINK_LEVELS; i++) { 2424 smu_pcie_arg = (i << 16) | 2425 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) : 2426 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? 2427 pptable->PcieLaneCount[i] : pcie_width_cap); 2428 ret = smu_cmn_send_smc_msg_with_param(smu, 2429 SMU_MSG_OverridePcieParameters, 2430 smu_pcie_arg, 2431 NULL); 2432 2433 if (ret) 2434 return ret; 2435 2436 if (pptable->PcieGenSpeed[i] > pcie_gen_cap) 2437 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; 2438 if (pptable->PcieLaneCount[i] > pcie_width_cap) 2439 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; 2440 } 2441 2442 return 0; 2443 } 2444 2445 static inline void navi10_dump_od_table(struct smu_context *smu, 2446 OverDriveTable_t *od_table) 2447 { 2448 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 2449 dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1); 2450 dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2); 2451 dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3); 2452 dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax); 2453 dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct); 2454 } 2455 2456 static int navi10_od_setting_check_range(struct smu_context *smu, 2457 struct smu_11_0_overdrive_table *od_table, 2458 enum SMU_11_0_ODSETTING_ID setting, 2459 uint32_t value) 2460 { 2461 if (value < od_table->min[setting]) { 2462 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]); 2463 return -EINVAL; 2464 } 2465 if (value > od_table->max[setting]) { 2466 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]); 2467 return -EINVAL; 2468 } 2469 return 0; 2470 } 2471 2472 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu, 2473 uint16_t *voltage, 2474 uint32_t freq) 2475 { 2476 uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16); 2477 uint32_t value = 0; 2478 int ret; 2479 2480 ret = smu_cmn_send_smc_msg_with_param(smu, 2481 SMU_MSG_GetVoltageByDpm, 2482 param, 2483 &value); 2484 if (ret) { 2485 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!"); 2486 return ret; 2487 } 2488 2489 *voltage = (uint16_t)value; 2490 2491 return 0; 2492 } 2493 2494 static int navi10_baco_enter(struct smu_context *smu) 2495 { 2496 struct amdgpu_device *adev = smu->adev; 2497 2498 /* 2499 * This aims the case below: 2500 * amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded 2501 * 2502 * For NAVI10 and later ASICs, we rely on PMFW to handle the runpm. To 2503 * make that possible, PMFW needs to acknowledge the dstate transition 2504 * process for both gfx(function 0) and audio(function 1) function of 2505 * the ASIC. 2506 * 2507 * The PCI device's initial runpm status is RUNPM_SUSPENDED. So as the 2508 * device representing the audio function of the ASIC. And that means 2509 * even if the sound driver(snd_hda_intel) was not loaded yet, it's still 2510 * possible runpm suspend kicked on the ASIC. However without the dstate 2511 * transition notification from audio function, pmfw cannot handle the 2512 * BACO in/exit correctly. And that will cause driver hang on runpm 2513 * resuming. 2514 * 2515 * To address this, we revert to legacy message way(driver masters the 2516 * timing for BACO in/exit) on sound driver missing. 2517 */ 2518 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) 2519 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); 2520 else 2521 return smu_v11_0_baco_enter(smu); 2522 } 2523 2524 static int navi10_baco_exit(struct smu_context *smu) 2525 { 2526 struct amdgpu_device *adev = smu->adev; 2527 2528 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { 2529 /* Wait for PMFW handling for the Dstate change */ 2530 msleep(10); 2531 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); 2532 } else { 2533 return smu_v11_0_baco_exit(smu); 2534 } 2535 } 2536 2537 static int navi10_set_default_od_settings(struct smu_context *smu) 2538 { 2539 OverDriveTable_t *od_table = 2540 (OverDriveTable_t *)smu->smu_table.overdrive_table; 2541 OverDriveTable_t *boot_od_table = 2542 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table; 2543 OverDriveTable_t *user_od_table = 2544 (OverDriveTable_t *)smu->smu_table.user_overdrive_table; 2545 int ret = 0; 2546 2547 /* 2548 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as 2549 * - either they already have the default OD settings got during cold bootup 2550 * - or they have some user customized OD settings which cannot be overwritten 2551 */ 2552 if (smu->adev->in_suspend) 2553 return 0; 2554 2555 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)boot_od_table, false); 2556 if (ret) { 2557 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 2558 return ret; 2559 } 2560 2561 if (!boot_od_table->GfxclkVolt1) { 2562 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2563 &boot_od_table->GfxclkVolt1, 2564 boot_od_table->GfxclkFreq1); 2565 if (ret) 2566 return ret; 2567 } 2568 2569 if (!boot_od_table->GfxclkVolt2) { 2570 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2571 &boot_od_table->GfxclkVolt2, 2572 boot_od_table->GfxclkFreq2); 2573 if (ret) 2574 return ret; 2575 } 2576 2577 if (!boot_od_table->GfxclkVolt3) { 2578 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2579 &boot_od_table->GfxclkVolt3, 2580 boot_od_table->GfxclkFreq3); 2581 if (ret) 2582 return ret; 2583 } 2584 2585 navi10_dump_od_table(smu, boot_od_table); 2586 2587 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t)); 2588 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t)); 2589 2590 return 0; 2591 } 2592 2593 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) 2594 { 2595 int i; 2596 int ret = 0; 2597 struct smu_table_context *table_context = &smu->smu_table; 2598 OverDriveTable_t *od_table; 2599 struct smu_11_0_overdrive_table *od_settings; 2600 enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting; 2601 uint16_t *freq_ptr, *voltage_ptr; 2602 od_table = (OverDriveTable_t *)table_context->overdrive_table; 2603 2604 if (!smu->od_enabled) { 2605 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n"); 2606 return -EINVAL; 2607 } 2608 2609 if (!smu->od_settings) { 2610 dev_err(smu->adev->dev, "OD board limits are not set!\n"); 2611 return -ENOENT; 2612 } 2613 2614 od_settings = smu->od_settings; 2615 2616 switch (type) { 2617 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2618 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 2619 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n"); 2620 return -ENOTSUPP; 2621 } 2622 if (!table_context->overdrive_table) { 2623 dev_err(smu->adev->dev, "Overdrive is not initialized\n"); 2624 return -EINVAL; 2625 } 2626 for (i = 0; i < size; i += 2) { 2627 if (i + 2 > size) { 2628 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2629 return -EINVAL; 2630 } 2631 switch (input[i]) { 2632 case 0: 2633 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN; 2634 freq_ptr = &od_table->GfxclkFmin; 2635 if (input[i + 1] > od_table->GfxclkFmax) { 2636 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n", 2637 input[i + 1], 2638 od_table->GfxclkFmin); 2639 return -EINVAL; 2640 } 2641 break; 2642 case 1: 2643 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX; 2644 freq_ptr = &od_table->GfxclkFmax; 2645 if (input[i + 1] < od_table->GfxclkFmin) { 2646 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n", 2647 input[i + 1], 2648 od_table->GfxclkFmax); 2649 return -EINVAL; 2650 } 2651 break; 2652 default: 2653 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 2654 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2655 return -EINVAL; 2656 } 2657 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]); 2658 if (ret) 2659 return ret; 2660 *freq_ptr = input[i + 1]; 2661 } 2662 break; 2663 case PP_OD_EDIT_MCLK_VDDC_TABLE: 2664 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 2665 dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n"); 2666 return -ENOTSUPP; 2667 } 2668 if (size < 2) { 2669 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2670 return -EINVAL; 2671 } 2672 if (input[0] != 1) { 2673 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]); 2674 dev_info(smu->adev->dev, "Supported indices: [1:max]\n"); 2675 return -EINVAL; 2676 } 2677 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]); 2678 if (ret) 2679 return ret; 2680 od_table->UclkFmax = input[1]; 2681 break; 2682 case PP_OD_RESTORE_DEFAULT_TABLE: 2683 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { 2684 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n"); 2685 return -EINVAL; 2686 } 2687 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t)); 2688 break; 2689 case PP_OD_COMMIT_DPM_TABLE: 2690 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) { 2691 navi10_dump_od_table(smu, od_table); 2692 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true); 2693 if (ret) { 2694 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2695 return ret; 2696 } 2697 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t)); 2698 smu->user_dpm_profile.user_od = true; 2699 2700 if (!memcmp(table_context->user_overdrive_table, 2701 table_context->boot_overdrive_table, 2702 sizeof(OverDriveTable_t))) 2703 smu->user_dpm_profile.user_od = false; 2704 } 2705 break; 2706 case PP_OD_EDIT_VDDC_CURVE: 2707 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 2708 dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n"); 2709 return -ENOTSUPP; 2710 } 2711 if (size < 3) { 2712 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2713 return -EINVAL; 2714 } 2715 if (!od_table) { 2716 dev_info(smu->adev->dev, "Overdrive is not initialized\n"); 2717 return -EINVAL; 2718 } 2719 2720 switch (input[0]) { 2721 case 0: 2722 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1; 2723 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1; 2724 freq_ptr = &od_table->GfxclkFreq1; 2725 voltage_ptr = &od_table->GfxclkVolt1; 2726 break; 2727 case 1: 2728 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2; 2729 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2; 2730 freq_ptr = &od_table->GfxclkFreq2; 2731 voltage_ptr = &od_table->GfxclkVolt2; 2732 break; 2733 case 2: 2734 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3; 2735 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3; 2736 freq_ptr = &od_table->GfxclkFreq3; 2737 voltage_ptr = &od_table->GfxclkVolt3; 2738 break; 2739 default: 2740 dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]); 2741 dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n"); 2742 return -EINVAL; 2743 } 2744 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]); 2745 if (ret) 2746 return ret; 2747 // Allow setting zero to disable the OverDrive VDDC curve 2748 if (input[2] != 0) { 2749 ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]); 2750 if (ret) 2751 return ret; 2752 *freq_ptr = input[1]; 2753 *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE; 2754 dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr); 2755 } else { 2756 // If setting 0, disable all voltage curve settings 2757 od_table->GfxclkVolt1 = 0; 2758 od_table->GfxclkVolt2 = 0; 2759 od_table->GfxclkVolt3 = 0; 2760 } 2761 navi10_dump_od_table(smu, od_table); 2762 break; 2763 default: 2764 return -ENOSYS; 2765 } 2766 return ret; 2767 } 2768 2769 static int navi10_run_btc(struct smu_context *smu) 2770 { 2771 int ret = 0; 2772 2773 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL); 2774 if (ret) 2775 dev_err(smu->adev->dev, "RunBtc failed!\n"); 2776 2777 return ret; 2778 } 2779 2780 static bool navi10_need_umc_cdr_workaround(struct smu_context *smu) 2781 { 2782 struct amdgpu_device *adev = smu->adev; 2783 2784 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 2785 return false; 2786 2787 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0) || 2788 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 5)) 2789 return true; 2790 2791 return false; 2792 } 2793 2794 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu) 2795 { 2796 uint32_t uclk_count, uclk_min, uclk_max; 2797 int ret = 0; 2798 2799 /* This workaround can be applied only with uclk dpm enabled */ 2800 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 2801 return 0; 2802 2803 ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count); 2804 if (ret) 2805 return ret; 2806 2807 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max); 2808 if (ret) 2809 return ret; 2810 2811 /* 2812 * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz. 2813 * This workaround is needed only when the max uclk frequency 2814 * not greater than that. 2815 */ 2816 if (uclk_max > 0x2EE) 2817 return 0; 2818 2819 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min); 2820 if (ret) 2821 return ret; 2822 2823 /* Force UCLK out of the highest DPM */ 2824 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min); 2825 if (ret) 2826 return ret; 2827 2828 /* Revert the UCLK Hardmax */ 2829 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max); 2830 if (ret) 2831 return ret; 2832 2833 /* 2834 * In this case, SMU already disabled dummy pstate during enablement 2835 * of UCLK DPM, we have to re-enabled it. 2836 */ 2837 return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL); 2838 } 2839 2840 static int navi10_set_dummy_pstates_table_location(struct smu_context *smu) 2841 { 2842 struct smu_table_context *smu_table = &smu->smu_table; 2843 struct smu_table *dummy_read_table = 2844 &smu_table->dummy_read_1_table; 2845 char *dummy_table = dummy_read_table->cpu_addr; 2846 int ret = 0; 2847 uint32_t i; 2848 2849 for (i = 0; i < 0x40000; i += 0x1000 * 2) { 2850 memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000); 2851 dummy_table += 0x1000; 2852 memcpy(dummy_table, &DbiPrbs7[0], 0x1000); 2853 dummy_table += 0x1000; 2854 } 2855 2856 amdgpu_asic_flush_hdp(smu->adev, NULL); 2857 2858 ret = smu_cmn_send_smc_msg_with_param(smu, 2859 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, 2860 upper_32_bits(dummy_read_table->mc_address), 2861 NULL); 2862 if (ret) 2863 return ret; 2864 2865 return smu_cmn_send_smc_msg_with_param(smu, 2866 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, 2867 lower_32_bits(dummy_read_table->mc_address), 2868 NULL); 2869 } 2870 2871 static int navi10_run_umc_cdr_workaround(struct smu_context *smu) 2872 { 2873 struct amdgpu_device *adev = smu->adev; 2874 uint8_t umc_fw_greater_than_v136 = false; 2875 uint8_t umc_fw_disable_cdr = false; 2876 uint32_t param; 2877 int ret = 0; 2878 2879 if (!navi10_need_umc_cdr_workaround(smu)) 2880 return 0; 2881 2882 /* 2883 * The messages below are only supported by Navi10 42.53.0 and later 2884 * PMFWs and Navi14 53.29.0 and later PMFWs. 2885 * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh 2886 * - PPSMC_MSG_SetDriverDummyTableDramAddrLow 2887 * - PPSMC_MSG_GetUMCFWWA 2888 */ 2889 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && 2890 (smu->smc_fw_version >= 0x2a3500)) || 2891 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 5)) && 2892 (smu->smc_fw_version >= 0x351D00))) { 2893 ret = smu_cmn_send_smc_msg_with_param(smu, 2894 SMU_MSG_GET_UMC_FW_WA, 2895 0, 2896 ¶m); 2897 if (ret) 2898 return ret; 2899 2900 /* First bit indicates if the UMC f/w is above v137 */ 2901 umc_fw_greater_than_v136 = param & 0x1; 2902 2903 /* Second bit indicates if hybrid-cdr is disabled */ 2904 umc_fw_disable_cdr = param & 0x2; 2905 2906 /* w/a only allowed if UMC f/w is <= 136 */ 2907 if (umc_fw_greater_than_v136) 2908 return 0; 2909 2910 if (umc_fw_disable_cdr) { 2911 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == 2912 IP_VERSION(11, 0, 0)) 2913 return navi10_umc_hybrid_cdr_workaround(smu); 2914 } else { 2915 return navi10_set_dummy_pstates_table_location(smu); 2916 } 2917 } else { 2918 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == 2919 IP_VERSION(11, 0, 0)) 2920 return navi10_umc_hybrid_cdr_workaround(smu); 2921 } 2922 2923 return 0; 2924 } 2925 2926 static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu, 2927 void **table) 2928 { 2929 struct smu_table_context *smu_table = &smu->smu_table; 2930 struct gpu_metrics_v1_3 *gpu_metrics = 2931 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 2932 SmuMetrics_legacy_t metrics; 2933 int ret = 0; 2934 2935 ret = smu_cmn_get_metrics_table(smu, 2936 NULL, 2937 true); 2938 if (ret) 2939 return ret; 2940 2941 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t)); 2942 2943 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 2944 2945 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2946 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2947 gpu_metrics->temperature_mem = metrics.TemperatureMem; 2948 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2949 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2950 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 2951 2952 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2953 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2954 2955 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 2956 2957 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 2958 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2959 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 2960 2961 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2962 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2963 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2964 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2965 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2966 2967 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2968 gpu_metrics->indep_throttle_status = 2969 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 2970 navi1x_throttler_map); 2971 2972 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 2973 2974 gpu_metrics->pcie_link_width = 2975 smu_v11_0_get_current_pcie_link_width(smu); 2976 gpu_metrics->pcie_link_speed = 2977 smu_v11_0_get_current_pcie_link_speed(smu); 2978 2979 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2980 2981 if (metrics.CurrGfxVoltageOffset) 2982 gpu_metrics->voltage_gfx = 2983 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 2984 if (metrics.CurrMemVidOffset) 2985 gpu_metrics->voltage_mem = 2986 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 2987 if (metrics.CurrSocVoltageOffset) 2988 gpu_metrics->voltage_soc = 2989 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 2990 2991 *table = (void *)gpu_metrics; 2992 2993 return sizeof(struct gpu_metrics_v1_3); 2994 } 2995 2996 static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap, 2997 struct i2c_msg *msg, int num_msgs) 2998 { 2999 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 3000 struct amdgpu_device *adev = smu_i2c->adev; 3001 struct smu_context *smu = adev->powerplay.pp_handle; 3002 struct smu_table_context *smu_table = &smu->smu_table; 3003 struct smu_table *table = &smu_table->driver_table; 3004 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 3005 int i, j, r, c; 3006 u16 dir; 3007 3008 if (!adev->pm.dpm_enabled) 3009 return -EBUSY; 3010 3011 req = kzalloc(sizeof(*req), GFP_KERNEL); 3012 if (!req) 3013 return -ENOMEM; 3014 3015 req->I2CcontrollerPort = smu_i2c->port; 3016 req->I2CSpeed = I2C_SPEED_FAST_400K; 3017 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 3018 dir = msg[0].flags & I2C_M_RD; 3019 3020 for (c = i = 0; i < num_msgs; i++) { 3021 for (j = 0; j < msg[i].len; j++, c++) { 3022 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 3023 3024 if (!(msg[i].flags & I2C_M_RD)) { 3025 /* write */ 3026 cmd->Cmd = I2C_CMD_WRITE; 3027 cmd->RegisterAddr = msg[i].buf[j]; 3028 } 3029 3030 if ((dir ^ msg[i].flags) & I2C_M_RD) { 3031 /* The direction changes. 3032 */ 3033 dir = msg[i].flags & I2C_M_RD; 3034 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 3035 } 3036 3037 req->NumCmds++; 3038 3039 /* 3040 * Insert STOP if we are at the last byte of either last 3041 * message for the transaction or the client explicitly 3042 * requires a STOP at this particular message. 3043 */ 3044 if ((j == msg[i].len - 1) && 3045 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 3046 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 3047 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 3048 } 3049 } 3050 } 3051 mutex_lock(&adev->pm.mutex); 3052 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 3053 if (r) 3054 goto fail; 3055 3056 for (c = i = 0; i < num_msgs; i++) { 3057 if (!(msg[i].flags & I2C_M_RD)) { 3058 c += msg[i].len; 3059 continue; 3060 } 3061 for (j = 0; j < msg[i].len; j++, c++) { 3062 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 3063 3064 msg[i].buf[j] = cmd->Data; 3065 } 3066 } 3067 r = num_msgs; 3068 fail: 3069 mutex_unlock(&adev->pm.mutex); 3070 kfree(req); 3071 return r; 3072 } 3073 3074 static u32 navi10_i2c_func(struct i2c_adapter *adap) 3075 { 3076 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 3077 } 3078 3079 3080 static const struct i2c_algorithm navi10_i2c_algo = { 3081 .master_xfer = navi10_i2c_xfer, 3082 .functionality = navi10_i2c_func, 3083 }; 3084 3085 static const struct i2c_adapter_quirks navi10_i2c_control_quirks = { 3086 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 3087 .max_read_len = MAX_SW_I2C_COMMANDS, 3088 .max_write_len = MAX_SW_I2C_COMMANDS, 3089 .max_comb_1st_msg_len = 2, 3090 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 3091 }; 3092 3093 static int navi10_i2c_control_init(struct smu_context *smu) 3094 { 3095 struct amdgpu_device *adev = smu->adev; 3096 int res, i; 3097 3098 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3099 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3100 struct i2c_adapter *control = &smu_i2c->adapter; 3101 3102 smu_i2c->adev = adev; 3103 smu_i2c->port = i; 3104 mutex_init(&smu_i2c->mutex); 3105 control->owner = THIS_MODULE; 3106 control->class = I2C_CLASS_HWMON; 3107 control->dev.parent = &adev->pdev->dev; 3108 control->algo = &navi10_i2c_algo; 3109 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 3110 control->quirks = &navi10_i2c_control_quirks; 3111 i2c_set_adapdata(control, smu_i2c); 3112 3113 res = i2c_add_adapter(control); 3114 if (res) { 3115 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 3116 goto Out_err; 3117 } 3118 } 3119 3120 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 3121 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 3122 3123 return 0; 3124 Out_err: 3125 for ( ; i >= 0; i--) { 3126 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3127 struct i2c_adapter *control = &smu_i2c->adapter; 3128 3129 i2c_del_adapter(control); 3130 } 3131 return res; 3132 } 3133 3134 static void navi10_i2c_control_fini(struct smu_context *smu) 3135 { 3136 struct amdgpu_device *adev = smu->adev; 3137 int i; 3138 3139 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3140 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3141 struct i2c_adapter *control = &smu_i2c->adapter; 3142 3143 i2c_del_adapter(control); 3144 } 3145 adev->pm.ras_eeprom_i2c_bus = NULL; 3146 adev->pm.fru_eeprom_i2c_bus = NULL; 3147 } 3148 3149 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, 3150 void **table) 3151 { 3152 struct smu_table_context *smu_table = &smu->smu_table; 3153 struct gpu_metrics_v1_3 *gpu_metrics = 3154 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3155 SmuMetrics_t metrics; 3156 int ret = 0; 3157 3158 ret = smu_cmn_get_metrics_table(smu, 3159 NULL, 3160 true); 3161 if (ret) 3162 return ret; 3163 3164 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t)); 3165 3166 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3167 3168 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 3169 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 3170 gpu_metrics->temperature_mem = metrics.TemperatureMem; 3171 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 3172 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 3173 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 3174 3175 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 3176 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 3177 3178 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 3179 3180 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 3181 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; 3182 else 3183 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; 3184 3185 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 3186 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; 3187 3188 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 3189 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 3190 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 3191 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 3192 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 3193 3194 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 3195 gpu_metrics->indep_throttle_status = 3196 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3197 navi1x_throttler_map); 3198 3199 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3200 3201 gpu_metrics->pcie_link_width = metrics.PcieWidth; 3202 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate]; 3203 3204 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3205 3206 if (metrics.CurrGfxVoltageOffset) 3207 gpu_metrics->voltage_gfx = 3208 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3209 if (metrics.CurrMemVidOffset) 3210 gpu_metrics->voltage_mem = 3211 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3212 if (metrics.CurrSocVoltageOffset) 3213 gpu_metrics->voltage_soc = 3214 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3215 3216 *table = (void *)gpu_metrics; 3217 3218 return sizeof(struct gpu_metrics_v1_3); 3219 } 3220 3221 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, 3222 void **table) 3223 { 3224 struct smu_table_context *smu_table = &smu->smu_table; 3225 struct gpu_metrics_v1_3 *gpu_metrics = 3226 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3227 SmuMetrics_NV12_legacy_t metrics; 3228 int ret = 0; 3229 3230 ret = smu_cmn_get_metrics_table(smu, 3231 NULL, 3232 true); 3233 if (ret) 3234 return ret; 3235 3236 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t)); 3237 3238 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3239 3240 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 3241 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 3242 gpu_metrics->temperature_mem = metrics.TemperatureMem; 3243 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 3244 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 3245 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 3246 3247 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 3248 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 3249 3250 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 3251 3252 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 3253 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 3254 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 3255 3256 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 3257 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 3258 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 3259 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 3260 3261 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 3262 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 3263 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 3264 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 3265 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 3266 3267 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 3268 gpu_metrics->indep_throttle_status = 3269 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3270 navi1x_throttler_map); 3271 3272 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3273 3274 gpu_metrics->pcie_link_width = 3275 smu_v11_0_get_current_pcie_link_width(smu); 3276 gpu_metrics->pcie_link_speed = 3277 smu_v11_0_get_current_pcie_link_speed(smu); 3278 3279 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3280 3281 if (metrics.CurrGfxVoltageOffset) 3282 gpu_metrics->voltage_gfx = 3283 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3284 if (metrics.CurrMemVidOffset) 3285 gpu_metrics->voltage_mem = 3286 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3287 if (metrics.CurrSocVoltageOffset) 3288 gpu_metrics->voltage_soc = 3289 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3290 3291 *table = (void *)gpu_metrics; 3292 3293 return sizeof(struct gpu_metrics_v1_3); 3294 } 3295 3296 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, 3297 void **table) 3298 { 3299 struct smu_table_context *smu_table = &smu->smu_table; 3300 struct gpu_metrics_v1_3 *gpu_metrics = 3301 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3302 SmuMetrics_NV12_t metrics; 3303 int ret = 0; 3304 3305 ret = smu_cmn_get_metrics_table(smu, 3306 NULL, 3307 true); 3308 if (ret) 3309 return ret; 3310 3311 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t)); 3312 3313 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3314 3315 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 3316 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 3317 gpu_metrics->temperature_mem = metrics.TemperatureMem; 3318 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 3319 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 3320 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 3321 3322 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 3323 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 3324 3325 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 3326 3327 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 3328 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; 3329 else 3330 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; 3331 3332 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 3333 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; 3334 3335 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 3336 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 3337 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 3338 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 3339 3340 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 3341 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 3342 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 3343 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 3344 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 3345 3346 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 3347 gpu_metrics->indep_throttle_status = 3348 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3349 navi1x_throttler_map); 3350 3351 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3352 3353 gpu_metrics->pcie_link_width = metrics.PcieWidth; 3354 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate]; 3355 3356 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3357 3358 if (metrics.CurrGfxVoltageOffset) 3359 gpu_metrics->voltage_gfx = 3360 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3361 if (metrics.CurrMemVidOffset) 3362 gpu_metrics->voltage_mem = 3363 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3364 if (metrics.CurrSocVoltageOffset) 3365 gpu_metrics->voltage_soc = 3366 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3367 3368 *table = (void *)gpu_metrics; 3369 3370 return sizeof(struct gpu_metrics_v1_3); 3371 } 3372 3373 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu, 3374 void **table) 3375 { 3376 struct amdgpu_device *adev = smu->adev; 3377 int ret = 0; 3378 3379 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 3380 case IP_VERSION(11, 0, 9): 3381 if (smu->smc_fw_version > 0x00341C00) 3382 ret = navi12_get_gpu_metrics(smu, table); 3383 else 3384 ret = navi12_get_legacy_gpu_metrics(smu, table); 3385 break; 3386 case IP_VERSION(11, 0, 0): 3387 case IP_VERSION(11, 0, 5): 3388 default: 3389 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == 3390 IP_VERSION(11, 0, 5)) && 3391 smu->smc_fw_version > 0x00351F00) || 3392 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == 3393 IP_VERSION(11, 0, 0)) && 3394 smu->smc_fw_version > 0x002A3B00)) 3395 ret = navi10_get_gpu_metrics(smu, table); 3396 else 3397 ret = navi10_get_legacy_gpu_metrics(smu, table); 3398 break; 3399 } 3400 3401 return ret; 3402 } 3403 3404 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu) 3405 { 3406 struct smu_table_context *table_context = &smu->smu_table; 3407 PPTable_t *smc_pptable = table_context->driver_pptable; 3408 struct amdgpu_device *adev = smu->adev; 3409 uint32_t param = 0; 3410 3411 /* Navi12 does not support this */ 3412 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 9)) 3413 return 0; 3414 3415 /* 3416 * Skip the MGpuFanBoost setting for those ASICs 3417 * which do not support it 3418 */ 3419 if (!smc_pptable->MGpuFanBoostLimitRpm) 3420 return 0; 3421 3422 /* Workaround for WS SKU */ 3423 if (adev->pdev->device == 0x7312 && 3424 adev->pdev->revision == 0) 3425 param = 0xD188; 3426 3427 return smu_cmn_send_smc_msg_with_param(smu, 3428 SMU_MSG_SetMGpuFanBoostLimitRpm, 3429 param, 3430 NULL); 3431 } 3432 3433 static int navi10_post_smu_init(struct smu_context *smu) 3434 { 3435 struct amdgpu_device *adev = smu->adev; 3436 int ret = 0; 3437 3438 if (amdgpu_sriov_vf(adev)) 3439 return 0; 3440 3441 ret = navi10_run_umc_cdr_workaround(smu); 3442 if (ret) 3443 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n"); 3444 3445 return ret; 3446 } 3447 3448 static int navi10_get_default_config_table_settings(struct smu_context *smu, 3449 struct config_table_setting *table) 3450 { 3451 if (!table) 3452 return -EINVAL; 3453 3454 table->gfxclk_average_tau = 10; 3455 table->socclk_average_tau = 10; 3456 table->uclk_average_tau = 10; 3457 table->gfx_activity_average_tau = 10; 3458 table->mem_activity_average_tau = 10; 3459 table->socket_power_average_tau = 10; 3460 3461 return 0; 3462 } 3463 3464 static int navi10_set_config_table(struct smu_context *smu, 3465 struct config_table_setting *table) 3466 { 3467 DriverSmuConfig_t driver_smu_config_table; 3468 3469 if (!table) 3470 return -EINVAL; 3471 3472 memset(&driver_smu_config_table, 3473 0, 3474 sizeof(driver_smu_config_table)); 3475 3476 driver_smu_config_table.GfxclkAverageLpfTau = 3477 table->gfxclk_average_tau; 3478 driver_smu_config_table.SocclkAverageLpfTau = 3479 table->socclk_average_tau; 3480 driver_smu_config_table.UclkAverageLpfTau = 3481 table->uclk_average_tau; 3482 driver_smu_config_table.GfxActivityLpfTau = 3483 table->gfx_activity_average_tau; 3484 driver_smu_config_table.UclkActivityLpfTau = 3485 table->mem_activity_average_tau; 3486 driver_smu_config_table.SocketPowerLpfTau = 3487 table->socket_power_average_tau; 3488 3489 return smu_cmn_update_table(smu, 3490 SMU_TABLE_DRIVER_SMU_CONFIG, 3491 0, 3492 (void *)&driver_smu_config_table, 3493 true); 3494 } 3495 3496 static const struct pptable_funcs navi10_ppt_funcs = { 3497 .get_allowed_feature_mask = navi10_get_allowed_feature_mask, 3498 .set_default_dpm_table = navi10_set_default_dpm_table, 3499 .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable, 3500 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable, 3501 .i2c_init = navi10_i2c_control_init, 3502 .i2c_fini = navi10_i2c_control_fini, 3503 .print_clk_levels = navi10_print_clk_levels, 3504 .emit_clk_levels = navi10_emit_clk_levels, 3505 .force_clk_levels = navi10_force_clk_levels, 3506 .populate_umd_state_clk = navi10_populate_umd_state_clk, 3507 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency, 3508 .pre_display_config_changed = navi10_pre_display_config_changed, 3509 .display_config_changed = navi10_display_config_changed, 3510 .notify_smc_display_config = navi10_notify_smc_display_config, 3511 .is_dpm_running = navi10_is_dpm_running, 3512 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm, 3513 .get_fan_speed_rpm = navi10_get_fan_speed_rpm, 3514 .get_power_profile_mode = navi10_get_power_profile_mode, 3515 .set_power_profile_mode = navi10_set_power_profile_mode, 3516 .set_watermarks_table = navi10_set_watermarks_table, 3517 .read_sensor = navi10_read_sensor, 3518 .get_uclk_dpm_states = navi10_get_uclk_dpm_states, 3519 .set_performance_level = smu_v11_0_set_performance_level, 3520 .get_thermal_temperature_range = navi10_get_thermal_temperature_range, 3521 .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch, 3522 .get_power_limit = navi10_get_power_limit, 3523 .update_pcie_parameters = navi10_update_pcie_parameters, 3524 .init_microcode = smu_v11_0_init_microcode, 3525 .load_microcode = smu_v11_0_load_microcode, 3526 .fini_microcode = smu_v11_0_fini_microcode, 3527 .init_smc_tables = navi10_init_smc_tables, 3528 .fini_smc_tables = smu_v11_0_fini_smc_tables, 3529 .init_power = smu_v11_0_init_power, 3530 .fini_power = smu_v11_0_fini_power, 3531 .check_fw_status = smu_v11_0_check_fw_status, 3532 .setup_pptable = navi10_setup_pptable, 3533 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 3534 .check_fw_version = smu_v11_0_check_fw_version, 3535 .write_pptable = smu_cmn_write_pptable, 3536 .set_driver_table_location = smu_v11_0_set_driver_table_location, 3537 .set_tool_table_location = smu_v11_0_set_tool_table_location, 3538 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 3539 .system_features_control = smu_v11_0_system_features_control, 3540 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 3541 .send_smc_msg = smu_cmn_send_smc_msg, 3542 .init_display_count = smu_v11_0_init_display_count, 3543 .set_allowed_mask = smu_v11_0_set_allowed_mask, 3544 .get_enabled_mask = smu_cmn_get_enabled_mask, 3545 .feature_is_enabled = smu_cmn_feature_is_enabled, 3546 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 3547 .notify_display_change = smu_v11_0_notify_display_change, 3548 .set_power_limit = smu_v11_0_set_power_limit, 3549 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 3550 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 3551 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 3552 .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk, 3553 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 3554 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 3555 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 3556 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm, 3557 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, 3558 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 3559 .gfx_off_control = smu_v11_0_gfx_off_control, 3560 .register_irq_handler = smu_v11_0_register_irq_handler, 3561 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 3562 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 3563 .get_bamaco_support = smu_v11_0_get_bamaco_support, 3564 .baco_enter = navi10_baco_enter, 3565 .baco_exit = navi10_baco_exit, 3566 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq, 3567 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 3568 .set_default_od_settings = navi10_set_default_od_settings, 3569 .od_edit_dpm_table = navi10_od_edit_dpm_table, 3570 .restore_user_od_settings = smu_v11_0_restore_user_od_settings, 3571 .run_btc = navi10_run_btc, 3572 .set_power_source = smu_v11_0_set_power_source, 3573 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 3574 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 3575 .get_gpu_metrics = navi1x_get_gpu_metrics, 3576 .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost, 3577 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 3578 .deep_sleep_control = smu_v11_0_deep_sleep_control, 3579 .get_fan_parameters = navi10_get_fan_parameters, 3580 .post_init = navi10_post_smu_init, 3581 .interrupt_work = smu_v11_0_interrupt_work, 3582 .set_mp1_state = smu_cmn_set_mp1_state, 3583 .get_default_config_table_settings = navi10_get_default_config_table_settings, 3584 .set_config_table = navi10_set_config_table, 3585 }; 3586 3587 void navi10_set_ppt_funcs(struct smu_context *smu) 3588 { 3589 smu->ppt_funcs = &navi10_ppt_funcs; 3590 smu->message_map = navi10_message_map; 3591 smu->clock_map = navi10_clk_map; 3592 smu->feature_map = navi10_feature_mask_map; 3593 smu->table_map = navi10_table_map; 3594 smu->pwr_src_map = navi10_pwr_src_map; 3595 smu->workload_map = navi10_workload_map; 3596 smu_v11_0_set_smu_mailbox_registers(smu); 3597 } 3598