1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "amd_pcie.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 static const struct amd_pm_funcs swsmu_pm_funcs; 61 static int smu_force_smuclk_levels(struct smu_context *smu, 62 enum smu_clk_type clk_type, 63 uint32_t mask); 64 static int smu_handle_task(struct smu_context *smu, 65 enum amd_dpm_forced_level level, 66 enum amd_pp_task task_id); 67 static int smu_reset(struct smu_context *smu); 68 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 69 static int smu_set_fan_control_mode(void *handle, u32 value); 70 static int smu_set_power_limit(void *handle, uint32_t limit); 71 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 72 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 73 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 74 75 static int smu_sys_get_pp_feature_mask(void *handle, 76 char *buf) 77 { 78 struct smu_context *smu = handle; 79 80 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 81 return -EOPNOTSUPP; 82 83 return smu_get_pp_feature_mask(smu, buf); 84 } 85 86 static int smu_sys_set_pp_feature_mask(void *handle, 87 uint64_t new_mask) 88 { 89 struct smu_context *smu = handle; 90 91 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 92 return -EOPNOTSUPP; 93 94 return smu_set_pp_feature_mask(smu, new_mask); 95 } 96 97 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 98 { 99 if (!smu->ppt_funcs->set_gfx_off_residency) 100 return -EINVAL; 101 102 return smu_set_gfx_off_residency(smu, value); 103 } 104 105 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 106 { 107 if (!smu->ppt_funcs->get_gfx_off_residency) 108 return -EINVAL; 109 110 return smu_get_gfx_off_residency(smu, value); 111 } 112 113 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 114 { 115 if (!smu->ppt_funcs->get_gfx_off_entrycount) 116 return -EINVAL; 117 118 return smu_get_gfx_off_entrycount(smu, value); 119 } 120 121 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 122 { 123 if (!smu->ppt_funcs->get_gfx_off_status) 124 return -EINVAL; 125 126 *value = smu_get_gfx_off_status(smu); 127 128 return 0; 129 } 130 131 int smu_set_soft_freq_range(struct smu_context *smu, 132 enum smu_clk_type clk_type, 133 uint32_t min, 134 uint32_t max) 135 { 136 int ret = 0; 137 138 if (smu->ppt_funcs->set_soft_freq_limited_range) 139 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 140 clk_type, 141 min, 142 max); 143 144 return ret; 145 } 146 147 int smu_get_dpm_freq_range(struct smu_context *smu, 148 enum smu_clk_type clk_type, 149 uint32_t *min, 150 uint32_t *max) 151 { 152 int ret = -ENOTSUPP; 153 154 if (!min && !max) 155 return -EINVAL; 156 157 if (smu->ppt_funcs->get_dpm_ultimate_freq) 158 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 159 clk_type, 160 min, 161 max); 162 163 return ret; 164 } 165 166 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 167 { 168 int ret = 0; 169 struct amdgpu_device *adev = smu->adev; 170 171 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 172 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 173 if (ret) 174 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 175 } 176 return ret; 177 } 178 179 static u32 smu_get_mclk(void *handle, bool low) 180 { 181 struct smu_context *smu = handle; 182 uint32_t clk_freq; 183 int ret = 0; 184 185 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 186 low ? &clk_freq : NULL, 187 !low ? &clk_freq : NULL); 188 if (ret) 189 return 0; 190 return clk_freq * 100; 191 } 192 193 static u32 smu_get_sclk(void *handle, bool low) 194 { 195 struct smu_context *smu = handle; 196 uint32_t clk_freq; 197 int ret = 0; 198 199 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 200 low ? &clk_freq : NULL, 201 !low ? &clk_freq : NULL); 202 if (ret) 203 return 0; 204 return clk_freq * 100; 205 } 206 207 static int smu_set_gfx_imu_enable(struct smu_context *smu) 208 { 209 struct amdgpu_device *adev = smu->adev; 210 211 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 212 return 0; 213 214 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 215 return 0; 216 217 return smu_set_gfx_power_up_by_imu(smu); 218 } 219 220 static bool is_vcn_enabled(struct amdgpu_device *adev) 221 { 222 int i; 223 224 for (i = 0; i < adev->num_ip_blocks; i++) { 225 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 226 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 227 !adev->ip_blocks[i].status.valid) 228 return false; 229 } 230 231 return true; 232 } 233 234 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 235 bool enable) 236 { 237 struct smu_power_context *smu_power = &smu->smu_power; 238 struct smu_power_gate *power_gate = &smu_power->power_gate; 239 int ret = 0; 240 241 /* 242 * don't poweron vcn/jpeg when they are skipped. 243 */ 244 if (!is_vcn_enabled(smu->adev)) 245 return 0; 246 247 if (!smu->ppt_funcs->dpm_set_vcn_enable) 248 return 0; 249 250 if (atomic_read(&power_gate->vcn_gated) ^ enable) 251 return 0; 252 253 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 254 if (!ret) 255 atomic_set(&power_gate->vcn_gated, !enable); 256 257 return ret; 258 } 259 260 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 261 bool enable) 262 { 263 struct smu_power_context *smu_power = &smu->smu_power; 264 struct smu_power_gate *power_gate = &smu_power->power_gate; 265 int ret = 0; 266 267 if (!is_vcn_enabled(smu->adev)) 268 return 0; 269 270 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 271 return 0; 272 273 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 274 return 0; 275 276 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 277 if (!ret) 278 atomic_set(&power_gate->jpeg_gated, !enable); 279 280 return ret; 281 } 282 283 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 284 bool enable) 285 { 286 struct smu_power_context *smu_power = &smu->smu_power; 287 struct smu_power_gate *power_gate = &smu_power->power_gate; 288 int ret = 0; 289 290 if (!smu->ppt_funcs->dpm_set_vpe_enable) 291 return 0; 292 293 if (atomic_read(&power_gate->vpe_gated) ^ enable) 294 return 0; 295 296 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 297 if (!ret) 298 atomic_set(&power_gate->vpe_gated, !enable); 299 300 return ret; 301 } 302 303 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 304 bool enable) 305 { 306 struct smu_power_context *smu_power = &smu->smu_power; 307 struct smu_power_gate *power_gate = &smu_power->power_gate; 308 int ret = 0; 309 310 if (!smu->adev->enable_umsch_mm) 311 return 0; 312 313 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 314 return 0; 315 316 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 317 return 0; 318 319 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 320 if (!ret) 321 atomic_set(&power_gate->umsch_mm_gated, !enable); 322 323 return ret; 324 } 325 326 /** 327 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 328 * 329 * @handle: smu_context pointer 330 * @block_type: the IP block to power gate/ungate 331 * @gate: to power gate if true, ungate otherwise 332 * 333 * This API uses no smu->mutex lock protection due to: 334 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 335 * This is guarded to be race condition free by the caller. 336 * 2. Or get called on user setting request of power_dpm_force_performance_level. 337 * Under this case, the smu->mutex lock protection is already enforced on 338 * the parent API smu_force_performance_level of the call path. 339 */ 340 static int smu_dpm_set_power_gate(void *handle, 341 uint32_t block_type, 342 bool gate) 343 { 344 struct smu_context *smu = handle; 345 int ret = 0; 346 347 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 348 dev_WARN(smu->adev->dev, 349 "SMU uninitialized but power %s requested for %u!\n", 350 gate ? "gate" : "ungate", block_type); 351 return -EOPNOTSUPP; 352 } 353 354 switch (block_type) { 355 /* 356 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 357 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 358 */ 359 case AMD_IP_BLOCK_TYPE_UVD: 360 case AMD_IP_BLOCK_TYPE_VCN: 361 ret = smu_dpm_set_vcn_enable(smu, !gate); 362 if (ret) 363 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 364 gate ? "gate" : "ungate"); 365 break; 366 case AMD_IP_BLOCK_TYPE_GFX: 367 ret = smu_gfx_off_control(smu, gate); 368 if (ret) 369 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 370 gate ? "enable" : "disable"); 371 break; 372 case AMD_IP_BLOCK_TYPE_SDMA: 373 ret = smu_powergate_sdma(smu, gate); 374 if (ret) 375 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 376 gate ? "gate" : "ungate"); 377 break; 378 case AMD_IP_BLOCK_TYPE_JPEG: 379 ret = smu_dpm_set_jpeg_enable(smu, !gate); 380 if (ret) 381 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 382 gate ? "gate" : "ungate"); 383 break; 384 case AMD_IP_BLOCK_TYPE_VPE: 385 ret = smu_dpm_set_vpe_enable(smu, !gate); 386 if (ret) 387 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 388 gate ? "gate" : "ungate"); 389 break; 390 default: 391 dev_err(smu->adev->dev, "Unsupported block type!\n"); 392 return -EINVAL; 393 } 394 395 return ret; 396 } 397 398 /** 399 * smu_set_user_clk_dependencies - set user profile clock dependencies 400 * 401 * @smu: smu_context pointer 402 * @clk: enum smu_clk_type type 403 * 404 * Enable/Disable the clock dependency for the @clk type. 405 */ 406 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 407 { 408 if (smu->adev->in_suspend) 409 return; 410 411 if (clk == SMU_MCLK) { 412 smu->user_dpm_profile.clk_dependency = 0; 413 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 414 } else if (clk == SMU_FCLK) { 415 /* MCLK takes precedence over FCLK */ 416 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 417 return; 418 419 smu->user_dpm_profile.clk_dependency = 0; 420 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 421 } else if (clk == SMU_SOCCLK) { 422 /* MCLK takes precedence over SOCCLK */ 423 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 424 return; 425 426 smu->user_dpm_profile.clk_dependency = 0; 427 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 428 } else 429 /* Add clk dependencies here, if any */ 430 return; 431 } 432 433 /** 434 * smu_restore_dpm_user_profile - reinstate user dpm profile 435 * 436 * @smu: smu_context pointer 437 * 438 * Restore the saved user power configurations include power limit, 439 * clock frequencies, fan control mode and fan speed. 440 */ 441 static void smu_restore_dpm_user_profile(struct smu_context *smu) 442 { 443 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 444 int ret = 0; 445 446 if (!smu->adev->in_suspend) 447 return; 448 449 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 450 return; 451 452 /* Enable restore flag */ 453 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 454 455 /* set the user dpm power limit */ 456 if (smu->user_dpm_profile.power_limit) { 457 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 458 if (ret) 459 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 460 } 461 462 /* set the user dpm clock configurations */ 463 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 464 enum smu_clk_type clk_type; 465 466 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 467 /* 468 * Iterate over smu clk type and force the saved user clk 469 * configs, skip if clock dependency is enabled 470 */ 471 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 472 smu->user_dpm_profile.clk_mask[clk_type]) { 473 ret = smu_force_smuclk_levels(smu, clk_type, 474 smu->user_dpm_profile.clk_mask[clk_type]); 475 if (ret) 476 dev_err(smu->adev->dev, 477 "Failed to set clock type = %d\n", clk_type); 478 } 479 } 480 } 481 482 /* set the user dpm fan configurations */ 483 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 484 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 485 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 486 if (ret != -EOPNOTSUPP) { 487 smu->user_dpm_profile.fan_speed_pwm = 0; 488 smu->user_dpm_profile.fan_speed_rpm = 0; 489 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 490 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 491 } 492 493 if (smu->user_dpm_profile.fan_speed_pwm) { 494 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 495 if (ret != -EOPNOTSUPP) 496 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 497 } 498 499 if (smu->user_dpm_profile.fan_speed_rpm) { 500 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 501 if (ret != -EOPNOTSUPP) 502 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 503 } 504 } 505 506 /* Restore user customized OD settings */ 507 if (smu->user_dpm_profile.user_od) { 508 if (smu->ppt_funcs->restore_user_od_settings) { 509 ret = smu->ppt_funcs->restore_user_od_settings(smu); 510 if (ret) 511 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 512 } 513 } 514 515 /* Disable restore flag */ 516 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 517 } 518 519 static int smu_get_power_num_states(void *handle, 520 struct pp_states_info *state_info) 521 { 522 if (!state_info) 523 return -EINVAL; 524 525 /* not support power state */ 526 memset(state_info, 0, sizeof(struct pp_states_info)); 527 state_info->nums = 1; 528 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 529 530 return 0; 531 } 532 533 bool is_support_sw_smu(struct amdgpu_device *adev) 534 { 535 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 536 if (adev->asic_type == CHIP_VEGA20) 537 return false; 538 539 if (amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) 540 return true; 541 542 return false; 543 } 544 545 bool is_support_cclk_dpm(struct amdgpu_device *adev) 546 { 547 struct smu_context *smu = adev->powerplay.pp_handle; 548 549 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 550 return false; 551 552 return true; 553 } 554 555 556 static int smu_sys_get_pp_table(void *handle, 557 char **table) 558 { 559 struct smu_context *smu = handle; 560 struct smu_table_context *smu_table = &smu->smu_table; 561 562 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 563 return -EOPNOTSUPP; 564 565 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 566 return -EINVAL; 567 568 if (smu_table->hardcode_pptable) 569 *table = smu_table->hardcode_pptable; 570 else 571 *table = smu_table->power_play_table; 572 573 return smu_table->power_play_table_size; 574 } 575 576 static int smu_sys_set_pp_table(void *handle, 577 const char *buf, 578 size_t size) 579 { 580 struct smu_context *smu = handle; 581 struct smu_table_context *smu_table = &smu->smu_table; 582 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 583 int ret = 0; 584 585 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 586 return -EOPNOTSUPP; 587 588 if (header->usStructureSize != size) { 589 dev_err(smu->adev->dev, "pp table size not matched !\n"); 590 return -EIO; 591 } 592 593 if (!smu_table->hardcode_pptable) { 594 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 595 if (!smu_table->hardcode_pptable) 596 return -ENOMEM; 597 } 598 599 memcpy(smu_table->hardcode_pptable, buf, size); 600 smu_table->power_play_table = smu_table->hardcode_pptable; 601 smu_table->power_play_table_size = size; 602 603 /* 604 * Special hw_fini action(for Navi1x, the DPMs disablement will be 605 * skipped) may be needed for custom pptable uploading. 606 */ 607 smu->uploading_custom_pp_table = true; 608 609 ret = smu_reset(smu); 610 if (ret) 611 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 612 613 smu->uploading_custom_pp_table = false; 614 615 return ret; 616 } 617 618 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 619 { 620 struct smu_feature *feature = &smu->smu_feature; 621 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 622 int ret = 0; 623 624 /* 625 * With SCPM enabled, the allowed featuremasks setting(via 626 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 627 * That means there is no way to let PMFW knows the settings below. 628 * Thus, we just assume all the features are allowed under 629 * such scenario. 630 */ 631 if (smu->adev->scpm_enabled) { 632 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 633 return 0; 634 } 635 636 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 637 638 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 639 SMU_FEATURE_MAX/32); 640 if (ret) 641 return ret; 642 643 bitmap_or(feature->allowed, feature->allowed, 644 (unsigned long *)allowed_feature_mask, 645 feature->feature_num); 646 647 return ret; 648 } 649 650 static int smu_set_funcs(struct amdgpu_device *adev) 651 { 652 struct smu_context *smu = adev->powerplay.pp_handle; 653 654 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 655 smu->od_enabled = true; 656 657 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 658 case IP_VERSION(11, 0, 0): 659 case IP_VERSION(11, 0, 5): 660 case IP_VERSION(11, 0, 9): 661 navi10_set_ppt_funcs(smu); 662 break; 663 case IP_VERSION(11, 0, 7): 664 case IP_VERSION(11, 0, 11): 665 case IP_VERSION(11, 0, 12): 666 case IP_VERSION(11, 0, 13): 667 sienna_cichlid_set_ppt_funcs(smu); 668 break; 669 case IP_VERSION(12, 0, 0): 670 case IP_VERSION(12, 0, 1): 671 renoir_set_ppt_funcs(smu); 672 break; 673 case IP_VERSION(11, 5, 0): 674 vangogh_set_ppt_funcs(smu); 675 break; 676 case IP_VERSION(13, 0, 1): 677 case IP_VERSION(13, 0, 3): 678 case IP_VERSION(13, 0, 8): 679 yellow_carp_set_ppt_funcs(smu); 680 break; 681 case IP_VERSION(13, 0, 4): 682 case IP_VERSION(13, 0, 11): 683 smu_v13_0_4_set_ppt_funcs(smu); 684 break; 685 case IP_VERSION(13, 0, 5): 686 smu_v13_0_5_set_ppt_funcs(smu); 687 break; 688 case IP_VERSION(11, 0, 8): 689 cyan_skillfish_set_ppt_funcs(smu); 690 break; 691 case IP_VERSION(11, 0, 2): 692 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 693 arcturus_set_ppt_funcs(smu); 694 /* OD is not supported on Arcturus */ 695 smu->od_enabled = false; 696 break; 697 case IP_VERSION(13, 0, 2): 698 aldebaran_set_ppt_funcs(smu); 699 /* Enable pp_od_clk_voltage node */ 700 smu->od_enabled = true; 701 break; 702 case IP_VERSION(13, 0, 0): 703 case IP_VERSION(13, 0, 10): 704 smu_v13_0_0_set_ppt_funcs(smu); 705 break; 706 case IP_VERSION(13, 0, 6): 707 smu_v13_0_6_set_ppt_funcs(smu); 708 /* Enable pp_od_clk_voltage node */ 709 smu->od_enabled = true; 710 break; 711 case IP_VERSION(13, 0, 7): 712 smu_v13_0_7_set_ppt_funcs(smu); 713 break; 714 case IP_VERSION(14, 0, 0): 715 smu_v14_0_0_set_ppt_funcs(smu); 716 break; 717 default: 718 return -EINVAL; 719 } 720 721 return 0; 722 } 723 724 static int smu_early_init(void *handle) 725 { 726 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 727 struct smu_context *smu; 728 int r; 729 730 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 731 if (!smu) 732 return -ENOMEM; 733 734 smu->adev = adev; 735 smu->pm_enabled = !!amdgpu_dpm; 736 smu->is_apu = false; 737 smu->smu_baco.state = SMU_BACO_STATE_NONE; 738 smu->smu_baco.platform_support = false; 739 smu->user_dpm_profile.fan_mode = -1; 740 741 mutex_init(&smu->message_lock); 742 743 adev->powerplay.pp_handle = smu; 744 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 745 746 r = smu_set_funcs(adev); 747 if (r) 748 return r; 749 return smu_init_microcode(smu); 750 } 751 752 static int smu_set_default_dpm_table(struct smu_context *smu) 753 { 754 struct smu_power_context *smu_power = &smu->smu_power; 755 struct smu_power_gate *power_gate = &smu_power->power_gate; 756 int vcn_gate, jpeg_gate; 757 int ret = 0; 758 759 if (!smu->ppt_funcs->set_default_dpm_table) 760 return 0; 761 762 vcn_gate = atomic_read(&power_gate->vcn_gated); 763 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 764 765 ret = smu_dpm_set_vcn_enable(smu, true); 766 if (ret) 767 return ret; 768 769 ret = smu_dpm_set_jpeg_enable(smu, true); 770 if (ret) 771 goto err_out; 772 773 ret = smu->ppt_funcs->set_default_dpm_table(smu); 774 if (ret) 775 dev_err(smu->adev->dev, 776 "Failed to setup default dpm clock tables!\n"); 777 778 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 779 err_out: 780 smu_dpm_set_vcn_enable(smu, !vcn_gate); 781 return ret; 782 } 783 784 static int smu_apply_default_config_table_settings(struct smu_context *smu) 785 { 786 struct amdgpu_device *adev = smu->adev; 787 int ret = 0; 788 789 ret = smu_get_default_config_table_settings(smu, 790 &adev->pm.config_table); 791 if (ret) 792 return ret; 793 794 return smu_set_config_table(smu, &adev->pm.config_table); 795 } 796 797 static int smu_late_init(void *handle) 798 { 799 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 800 struct smu_context *smu = adev->powerplay.pp_handle; 801 int ret = 0; 802 803 smu_set_fine_grain_gfx_freq_parameters(smu); 804 805 if (!smu->pm_enabled) 806 return 0; 807 808 ret = smu_post_init(smu); 809 if (ret) { 810 dev_err(adev->dev, "Failed to post smu init!\n"); 811 return ret; 812 } 813 814 /* 815 * Explicitly notify PMFW the power mode the system in. Since 816 * the PMFW may boot the ASIC with a different mode. 817 * For those supporting ACDC switch via gpio, PMFW will 818 * handle the switch automatically. Driver involvement 819 * is unnecessary. 820 */ 821 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 822 smu_set_ac_dc(smu); 823 824 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 825 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 826 return 0; 827 828 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 829 ret = smu_set_default_od_settings(smu); 830 if (ret) { 831 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 832 return ret; 833 } 834 } 835 836 ret = smu_populate_umd_state_clk(smu); 837 if (ret) { 838 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 839 return ret; 840 } 841 842 ret = smu_get_asic_power_limits(smu, 843 &smu->current_power_limit, 844 &smu->default_power_limit, 845 &smu->max_power_limit, 846 &smu->min_power_limit); 847 if (ret) { 848 dev_err(adev->dev, "Failed to get asic power limits!\n"); 849 return ret; 850 } 851 852 if (!amdgpu_sriov_vf(adev)) 853 smu_get_unique_id(smu); 854 855 smu_get_fan_parameters(smu); 856 857 smu_handle_task(smu, 858 smu->smu_dpm.dpm_level, 859 AMD_PP_TASK_COMPLETE_INIT); 860 861 ret = smu_apply_default_config_table_settings(smu); 862 if (ret && (ret != -EOPNOTSUPP)) { 863 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 864 return ret; 865 } 866 867 smu_restore_dpm_user_profile(smu); 868 869 return 0; 870 } 871 872 static int smu_init_fb_allocations(struct smu_context *smu) 873 { 874 struct amdgpu_device *adev = smu->adev; 875 struct smu_table_context *smu_table = &smu->smu_table; 876 struct smu_table *tables = smu_table->tables; 877 struct smu_table *driver_table = &(smu_table->driver_table); 878 uint32_t max_table_size = 0; 879 int ret, i; 880 881 /* VRAM allocation for tool table */ 882 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 883 ret = amdgpu_bo_create_kernel(adev, 884 tables[SMU_TABLE_PMSTATUSLOG].size, 885 tables[SMU_TABLE_PMSTATUSLOG].align, 886 tables[SMU_TABLE_PMSTATUSLOG].domain, 887 &tables[SMU_TABLE_PMSTATUSLOG].bo, 888 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 889 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 890 if (ret) { 891 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 892 return ret; 893 } 894 } 895 896 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 897 /* VRAM allocation for driver table */ 898 for (i = 0; i < SMU_TABLE_COUNT; i++) { 899 if (tables[i].size == 0) 900 continue; 901 902 /* If one of the tables has VRAM domain restriction, keep it in 903 * VRAM 904 */ 905 if ((tables[i].domain & 906 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 907 AMDGPU_GEM_DOMAIN_VRAM) 908 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 909 910 if (i == SMU_TABLE_PMSTATUSLOG) 911 continue; 912 913 if (max_table_size < tables[i].size) 914 max_table_size = tables[i].size; 915 } 916 917 driver_table->size = max_table_size; 918 driver_table->align = PAGE_SIZE; 919 920 ret = amdgpu_bo_create_kernel(adev, 921 driver_table->size, 922 driver_table->align, 923 driver_table->domain, 924 &driver_table->bo, 925 &driver_table->mc_address, 926 &driver_table->cpu_addr); 927 if (ret) { 928 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 929 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 930 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 931 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 932 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 933 } 934 935 return ret; 936 } 937 938 static int smu_fini_fb_allocations(struct smu_context *smu) 939 { 940 struct smu_table_context *smu_table = &smu->smu_table; 941 struct smu_table *tables = smu_table->tables; 942 struct smu_table *driver_table = &(smu_table->driver_table); 943 944 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 945 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 946 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 947 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 948 949 amdgpu_bo_free_kernel(&driver_table->bo, 950 &driver_table->mc_address, 951 &driver_table->cpu_addr); 952 953 return 0; 954 } 955 956 /** 957 * smu_alloc_memory_pool - allocate memory pool in the system memory 958 * 959 * @smu: amdgpu_device pointer 960 * 961 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 962 * and DramLogSetDramAddr can notify it changed. 963 * 964 * Returns 0 on success, error on failure. 965 */ 966 static int smu_alloc_memory_pool(struct smu_context *smu) 967 { 968 struct amdgpu_device *adev = smu->adev; 969 struct smu_table_context *smu_table = &smu->smu_table; 970 struct smu_table *memory_pool = &smu_table->memory_pool; 971 uint64_t pool_size = smu->pool_size; 972 int ret = 0; 973 974 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 975 return ret; 976 977 memory_pool->size = pool_size; 978 memory_pool->align = PAGE_SIZE; 979 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 980 981 switch (pool_size) { 982 case SMU_MEMORY_POOL_SIZE_256_MB: 983 case SMU_MEMORY_POOL_SIZE_512_MB: 984 case SMU_MEMORY_POOL_SIZE_1_GB: 985 case SMU_MEMORY_POOL_SIZE_2_GB: 986 ret = amdgpu_bo_create_kernel(adev, 987 memory_pool->size, 988 memory_pool->align, 989 memory_pool->domain, 990 &memory_pool->bo, 991 &memory_pool->mc_address, 992 &memory_pool->cpu_addr); 993 if (ret) 994 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 995 break; 996 default: 997 break; 998 } 999 1000 return ret; 1001 } 1002 1003 static int smu_free_memory_pool(struct smu_context *smu) 1004 { 1005 struct smu_table_context *smu_table = &smu->smu_table; 1006 struct smu_table *memory_pool = &smu_table->memory_pool; 1007 1008 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1009 return 0; 1010 1011 amdgpu_bo_free_kernel(&memory_pool->bo, 1012 &memory_pool->mc_address, 1013 &memory_pool->cpu_addr); 1014 1015 memset(memory_pool, 0, sizeof(struct smu_table)); 1016 1017 return 0; 1018 } 1019 1020 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1021 { 1022 struct smu_table_context *smu_table = &smu->smu_table; 1023 struct smu_table *dummy_read_1_table = 1024 &smu_table->dummy_read_1_table; 1025 struct amdgpu_device *adev = smu->adev; 1026 int ret = 0; 1027 1028 if (!dummy_read_1_table->size) 1029 return 0; 1030 1031 ret = amdgpu_bo_create_kernel(adev, 1032 dummy_read_1_table->size, 1033 dummy_read_1_table->align, 1034 dummy_read_1_table->domain, 1035 &dummy_read_1_table->bo, 1036 &dummy_read_1_table->mc_address, 1037 &dummy_read_1_table->cpu_addr); 1038 if (ret) 1039 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1040 1041 return ret; 1042 } 1043 1044 static void smu_free_dummy_read_table(struct smu_context *smu) 1045 { 1046 struct smu_table_context *smu_table = &smu->smu_table; 1047 struct smu_table *dummy_read_1_table = 1048 &smu_table->dummy_read_1_table; 1049 1050 1051 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1052 &dummy_read_1_table->mc_address, 1053 &dummy_read_1_table->cpu_addr); 1054 1055 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1056 } 1057 1058 static int smu_smc_table_sw_init(struct smu_context *smu) 1059 { 1060 int ret; 1061 1062 /** 1063 * Create smu_table structure, and init smc tables such as 1064 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1065 */ 1066 ret = smu_init_smc_tables(smu); 1067 if (ret) { 1068 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1069 return ret; 1070 } 1071 1072 /** 1073 * Create smu_power_context structure, and allocate smu_dpm_context and 1074 * context size to fill the smu_power_context data. 1075 */ 1076 ret = smu_init_power(smu); 1077 if (ret) { 1078 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1079 return ret; 1080 } 1081 1082 /* 1083 * allocate vram bos to store smc table contents. 1084 */ 1085 ret = smu_init_fb_allocations(smu); 1086 if (ret) 1087 return ret; 1088 1089 ret = smu_alloc_memory_pool(smu); 1090 if (ret) 1091 return ret; 1092 1093 ret = smu_alloc_dummy_read_table(smu); 1094 if (ret) 1095 return ret; 1096 1097 ret = smu_i2c_init(smu); 1098 if (ret) 1099 return ret; 1100 1101 return 0; 1102 } 1103 1104 static int smu_smc_table_sw_fini(struct smu_context *smu) 1105 { 1106 int ret; 1107 1108 smu_i2c_fini(smu); 1109 1110 smu_free_dummy_read_table(smu); 1111 1112 ret = smu_free_memory_pool(smu); 1113 if (ret) 1114 return ret; 1115 1116 ret = smu_fini_fb_allocations(smu); 1117 if (ret) 1118 return ret; 1119 1120 ret = smu_fini_power(smu); 1121 if (ret) { 1122 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1123 return ret; 1124 } 1125 1126 ret = smu_fini_smc_tables(smu); 1127 if (ret) { 1128 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1129 return ret; 1130 } 1131 1132 return 0; 1133 } 1134 1135 static void smu_throttling_logging_work_fn(struct work_struct *work) 1136 { 1137 struct smu_context *smu = container_of(work, struct smu_context, 1138 throttling_logging_work); 1139 1140 smu_log_thermal_throttling(smu); 1141 } 1142 1143 static void smu_interrupt_work_fn(struct work_struct *work) 1144 { 1145 struct smu_context *smu = container_of(work, struct smu_context, 1146 interrupt_work); 1147 1148 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1149 smu->ppt_funcs->interrupt_work(smu); 1150 } 1151 1152 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1153 { 1154 struct smu_context *smu = 1155 container_of(work, struct smu_context, swctf_delayed_work.work); 1156 struct smu_temperature_range *range = 1157 &smu->thermal_range; 1158 struct amdgpu_device *adev = smu->adev; 1159 uint32_t hotspot_tmp, size; 1160 1161 /* 1162 * If the hotspot temperature is confirmed as below SW CTF setting point 1163 * after the delay enforced, nothing will be done. 1164 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1165 */ 1166 if (range->software_shutdown_temp && 1167 smu->ppt_funcs->read_sensor && 1168 !smu->ppt_funcs->read_sensor(smu, 1169 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1170 &hotspot_tmp, 1171 &size) && 1172 hotspot_tmp / 1000 < range->software_shutdown_temp) 1173 return; 1174 1175 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1176 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1177 orderly_poweroff(true); 1178 } 1179 1180 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1181 { 1182 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1183 smu->plpd_mode = XGMI_PLPD_DEFAULT; 1184 return; 1185 } 1186 1187 /* PMFW put PLPD into default policy after enabling the feature */ 1188 if (smu_feature_is_enabled(smu, 1189 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) 1190 smu->plpd_mode = XGMI_PLPD_DEFAULT; 1191 else 1192 smu->plpd_mode = XGMI_PLPD_NONE; 1193 } 1194 1195 static int smu_sw_init(void *handle) 1196 { 1197 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1198 struct smu_context *smu = adev->powerplay.pp_handle; 1199 int ret; 1200 1201 smu->pool_size = adev->pm.smu_prv_buffer_size; 1202 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1203 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1204 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1205 1206 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1207 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1208 atomic64_set(&smu->throttle_int_counter, 0); 1209 smu->watermarks_bitmap = 0; 1210 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1211 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1212 1213 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1214 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1215 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1216 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1217 1218 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1219 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1220 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1221 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1222 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1223 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1224 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1225 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1226 1227 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1228 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1229 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1230 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1231 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1232 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1233 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1234 smu->display_config = &adev->pm.pm_display_cfg; 1235 1236 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1237 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1238 1239 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1240 smu_swctf_delayed_work_handler); 1241 1242 ret = smu_smc_table_sw_init(smu); 1243 if (ret) { 1244 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1245 return ret; 1246 } 1247 1248 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1249 ret = smu_get_vbios_bootup_values(smu); 1250 if (ret) { 1251 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1252 return ret; 1253 } 1254 1255 ret = smu_init_pptable_microcode(smu); 1256 if (ret) { 1257 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1258 return ret; 1259 } 1260 1261 ret = smu_register_irq_handler(smu); 1262 if (ret) { 1263 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1264 return ret; 1265 } 1266 1267 /* If there is no way to query fan control mode, fan control is not supported */ 1268 if (!smu->ppt_funcs->get_fan_control_mode) 1269 smu->adev->pm.no_fan = true; 1270 1271 return 0; 1272 } 1273 1274 static int smu_sw_fini(void *handle) 1275 { 1276 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1277 struct smu_context *smu = adev->powerplay.pp_handle; 1278 int ret; 1279 1280 ret = smu_smc_table_sw_fini(smu); 1281 if (ret) { 1282 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1283 return ret; 1284 } 1285 1286 smu_fini_microcode(smu); 1287 1288 return 0; 1289 } 1290 1291 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1292 { 1293 struct amdgpu_device *adev = smu->adev; 1294 struct smu_temperature_range *range = 1295 &smu->thermal_range; 1296 int ret = 0; 1297 1298 if (!smu->ppt_funcs->get_thermal_temperature_range) 1299 return 0; 1300 1301 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1302 if (ret) 1303 return ret; 1304 1305 adev->pm.dpm.thermal.min_temp = range->min; 1306 adev->pm.dpm.thermal.max_temp = range->max; 1307 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1308 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1309 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1310 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1311 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1312 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1313 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1314 1315 return ret; 1316 } 1317 1318 /** 1319 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1320 * 1321 * @smu: smu_context pointer 1322 * 1323 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1324 * Returns 0 on success, error on failure. 1325 */ 1326 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1327 { 1328 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1329 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1330 struct amdgpu_device *adev = smu->adev; 1331 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1332 uint64_t start, end; 1333 int ret, i, j; 1334 1335 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1336 if (ret) { 1337 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1338 return ret; 1339 } 1340 1341 /* 1342 * The exclusion ranges array we got might be filled with holes and duplicate 1343 * entries. For example: 1344 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1345 * We need to do some sortups to eliminate those holes and duplicate entries. 1346 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1347 */ 1348 for (i = 0; i < num_of_wbrf_ranges; i++) { 1349 start = wifi_bands[i].start; 1350 end = wifi_bands[i].end; 1351 1352 /* get the last valid entry to fill the intermediate hole */ 1353 if (!start && !end) { 1354 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1355 if (wifi_bands[j].start && wifi_bands[j].end) 1356 break; 1357 1358 /* no valid entry left */ 1359 if (j <= i) 1360 break; 1361 1362 start = wifi_bands[i].start = wifi_bands[j].start; 1363 end = wifi_bands[i].end = wifi_bands[j].end; 1364 wifi_bands[j].start = 0; 1365 wifi_bands[j].end = 0; 1366 num_of_wbrf_ranges = j; 1367 } 1368 1369 /* eliminate duplicate entries */ 1370 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1371 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1372 wifi_bands[j].start = 0; 1373 wifi_bands[j].end = 0; 1374 } 1375 } 1376 } 1377 1378 /* Send the sorted wifi_bands to PMFW */ 1379 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1380 /* Try to set the wifi_bands again */ 1381 if (unlikely(ret == -EBUSY)) { 1382 mdelay(5); 1383 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1384 } 1385 1386 return ret; 1387 } 1388 1389 /** 1390 * smu_wbrf_event_handler - handle notify events 1391 * 1392 * @nb: notifier block 1393 * @action: event type 1394 * @_arg: event data 1395 * 1396 * Calls relevant amdgpu function in response to wbrf event 1397 * notification from kernel. 1398 */ 1399 static int smu_wbrf_event_handler(struct notifier_block *nb, 1400 unsigned long action, void *_arg) 1401 { 1402 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1403 1404 switch (action) { 1405 case WBRF_CHANGED: 1406 schedule_delayed_work(&smu->wbrf_delayed_work, 1407 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1408 break; 1409 default: 1410 return NOTIFY_DONE; 1411 } 1412 1413 return NOTIFY_OK; 1414 } 1415 1416 /** 1417 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1418 * 1419 * @work: struct work_struct pointer 1420 * 1421 * Flood is over and driver will consume the latest exclusion ranges. 1422 */ 1423 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1424 { 1425 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1426 1427 smu_wbrf_handle_exclusion_ranges(smu); 1428 } 1429 1430 /** 1431 * smu_wbrf_support_check - check wbrf support 1432 * 1433 * @smu: smu_context pointer 1434 * 1435 * Verifies the ACPI interface whether wbrf is supported. 1436 */ 1437 static void smu_wbrf_support_check(struct smu_context *smu) 1438 { 1439 struct amdgpu_device *adev = smu->adev; 1440 1441 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1442 acpi_amd_wbrf_supported_consumer(adev->dev); 1443 1444 if (smu->wbrf_supported) 1445 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1446 } 1447 1448 /** 1449 * smu_wbrf_init - init driver wbrf support 1450 * 1451 * @smu: smu_context pointer 1452 * 1453 * Verifies the AMD ACPI interfaces and registers with the wbrf 1454 * notifier chain if wbrf feature is supported. 1455 * Returns 0 on success, error on failure. 1456 */ 1457 static int smu_wbrf_init(struct smu_context *smu) 1458 { 1459 int ret; 1460 1461 if (!smu->wbrf_supported) 1462 return 0; 1463 1464 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1465 1466 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1467 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1468 if (ret) 1469 return ret; 1470 1471 /* 1472 * Some wifiband exclusion ranges may be already there 1473 * before our driver loaded. To make sure our driver 1474 * is awared of those exclusion ranges. 1475 */ 1476 schedule_delayed_work(&smu->wbrf_delayed_work, 1477 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1478 1479 return 0; 1480 } 1481 1482 /** 1483 * smu_wbrf_fini - tear down driver wbrf support 1484 * 1485 * @smu: smu_context pointer 1486 * 1487 * Unregisters with the wbrf notifier chain. 1488 */ 1489 static void smu_wbrf_fini(struct smu_context *smu) 1490 { 1491 if (!smu->wbrf_supported) 1492 return; 1493 1494 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1495 1496 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1497 } 1498 1499 static int smu_smc_hw_setup(struct smu_context *smu) 1500 { 1501 struct smu_feature *feature = &smu->smu_feature; 1502 struct amdgpu_device *adev = smu->adev; 1503 uint8_t pcie_gen = 0, pcie_width = 0; 1504 uint64_t features_supported; 1505 int ret = 0; 1506 1507 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1508 case IP_VERSION(11, 0, 7): 1509 case IP_VERSION(11, 0, 11): 1510 case IP_VERSION(11, 5, 0): 1511 case IP_VERSION(11, 0, 12): 1512 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1513 dev_info(adev->dev, "dpm has been enabled\n"); 1514 ret = smu_system_features_control(smu, true); 1515 if (ret) 1516 dev_err(adev->dev, "Failed system features control!\n"); 1517 return ret; 1518 } 1519 break; 1520 default: 1521 break; 1522 } 1523 1524 ret = smu_init_display_count(smu, 0); 1525 if (ret) { 1526 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1527 return ret; 1528 } 1529 1530 ret = smu_set_driver_table_location(smu); 1531 if (ret) { 1532 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1533 return ret; 1534 } 1535 1536 /* 1537 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1538 */ 1539 ret = smu_set_tool_table_location(smu); 1540 if (ret) { 1541 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1542 return ret; 1543 } 1544 1545 /* 1546 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1547 * pool location. 1548 */ 1549 ret = smu_notify_memory_pool_location(smu); 1550 if (ret) { 1551 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1552 return ret; 1553 } 1554 1555 /* 1556 * It is assumed the pptable used before runpm is same as 1557 * the one used afterwards. Thus, we can reuse the stored 1558 * copy and do not need to resetup the pptable again. 1559 */ 1560 if (!adev->in_runpm) { 1561 ret = smu_setup_pptable(smu); 1562 if (ret) { 1563 dev_err(adev->dev, "Failed to setup pptable!\n"); 1564 return ret; 1565 } 1566 } 1567 1568 /* smu_dump_pptable(smu); */ 1569 1570 /* 1571 * With SCPM enabled, PSP is responsible for the PPTable transferring 1572 * (to SMU). Driver involvement is not needed and permitted. 1573 */ 1574 if (!adev->scpm_enabled) { 1575 /* 1576 * Copy pptable bo in the vram to smc with SMU MSGs such as 1577 * SetDriverDramAddr and TransferTableDram2Smu. 1578 */ 1579 ret = smu_write_pptable(smu); 1580 if (ret) { 1581 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1582 return ret; 1583 } 1584 } 1585 1586 /* issue Run*Btc msg */ 1587 ret = smu_run_btc(smu); 1588 if (ret) 1589 return ret; 1590 1591 /* Enable UclkShadow on wbrf supported */ 1592 if (smu->wbrf_supported) { 1593 ret = smu_enable_uclk_shadow(smu, true); 1594 if (ret) { 1595 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1596 return ret; 1597 } 1598 } 1599 1600 /* 1601 * With SCPM enabled, these actions(and relevant messages) are 1602 * not needed and permitted. 1603 */ 1604 if (!adev->scpm_enabled) { 1605 ret = smu_feature_set_allowed_mask(smu); 1606 if (ret) { 1607 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1608 return ret; 1609 } 1610 } 1611 1612 ret = smu_system_features_control(smu, true); 1613 if (ret) { 1614 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1615 return ret; 1616 } 1617 1618 smu_init_xgmi_plpd_mode(smu); 1619 1620 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1621 if (ret) { 1622 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1623 return ret; 1624 } 1625 bitmap_copy(feature->supported, 1626 (unsigned long *)&features_supported, 1627 feature->feature_num); 1628 1629 if (!smu_is_dpm_running(smu)) 1630 dev_info(adev->dev, "dpm has been disabled\n"); 1631 1632 /* 1633 * Set initialized values (get from vbios) to dpm tables context such as 1634 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1635 * type of clks. 1636 */ 1637 ret = smu_set_default_dpm_table(smu); 1638 if (ret) { 1639 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1640 return ret; 1641 } 1642 1643 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1644 pcie_gen = 3; 1645 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1646 pcie_gen = 2; 1647 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1648 pcie_gen = 1; 1649 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1650 pcie_gen = 0; 1651 1652 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1653 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1654 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1655 */ 1656 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1657 pcie_width = 6; 1658 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1659 pcie_width = 5; 1660 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1661 pcie_width = 4; 1662 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1663 pcie_width = 3; 1664 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1665 pcie_width = 2; 1666 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1667 pcie_width = 1; 1668 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1669 if (ret) { 1670 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1671 return ret; 1672 } 1673 1674 ret = smu_get_thermal_temperature_range(smu); 1675 if (ret) { 1676 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1677 return ret; 1678 } 1679 1680 ret = smu_enable_thermal_alert(smu); 1681 if (ret) { 1682 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1683 return ret; 1684 } 1685 1686 ret = smu_notify_display_change(smu); 1687 if (ret) { 1688 dev_err(adev->dev, "Failed to notify display change!\n"); 1689 return ret; 1690 } 1691 1692 /* 1693 * Set min deep sleep dce fclk with bootup value from vbios via 1694 * SetMinDeepSleepDcefclk MSG. 1695 */ 1696 ret = smu_set_min_dcef_deep_sleep(smu, 1697 smu->smu_table.boot_values.dcefclk / 100); 1698 if (ret) { 1699 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1700 return ret; 1701 } 1702 1703 /* Init wbrf support. Properly setup the notifier */ 1704 ret = smu_wbrf_init(smu); 1705 if (ret) 1706 dev_err(adev->dev, "Error during wbrf init call\n"); 1707 1708 return ret; 1709 } 1710 1711 static int smu_start_smc_engine(struct smu_context *smu) 1712 { 1713 struct amdgpu_device *adev = smu->adev; 1714 int ret = 0; 1715 1716 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1717 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1718 if (smu->ppt_funcs->load_microcode) { 1719 ret = smu->ppt_funcs->load_microcode(smu); 1720 if (ret) 1721 return ret; 1722 } 1723 } 1724 } 1725 1726 if (smu->ppt_funcs->check_fw_status) { 1727 ret = smu->ppt_funcs->check_fw_status(smu); 1728 if (ret) { 1729 dev_err(adev->dev, "SMC is not ready\n"); 1730 return ret; 1731 } 1732 } 1733 1734 /* 1735 * Send msg GetDriverIfVersion to check if the return value is equal 1736 * with DRIVER_IF_VERSION of smc header. 1737 */ 1738 ret = smu_check_fw_version(smu); 1739 if (ret) 1740 return ret; 1741 1742 return ret; 1743 } 1744 1745 static int smu_hw_init(void *handle) 1746 { 1747 int ret; 1748 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1749 struct smu_context *smu = adev->powerplay.pp_handle; 1750 1751 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1752 smu->pm_enabled = false; 1753 return 0; 1754 } 1755 1756 ret = smu_start_smc_engine(smu); 1757 if (ret) { 1758 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1759 return ret; 1760 } 1761 1762 /* 1763 * Check whether wbrf is supported. This needs to be done 1764 * before SMU setup starts since part of SMU configuration 1765 * relies on this. 1766 */ 1767 smu_wbrf_support_check(smu); 1768 1769 if (smu->is_apu) { 1770 ret = smu_set_gfx_imu_enable(smu); 1771 if (ret) 1772 return ret; 1773 smu_dpm_set_vcn_enable(smu, true); 1774 smu_dpm_set_jpeg_enable(smu, true); 1775 smu_dpm_set_vpe_enable(smu, true); 1776 smu_dpm_set_umsch_mm_enable(smu, true); 1777 smu_set_gfx_cgpg(smu, true); 1778 } 1779 1780 if (!smu->pm_enabled) 1781 return 0; 1782 1783 ret = smu_get_driver_allowed_feature_mask(smu); 1784 if (ret) 1785 return ret; 1786 1787 ret = smu_smc_hw_setup(smu); 1788 if (ret) { 1789 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1790 return ret; 1791 } 1792 1793 /* 1794 * Move maximum sustainable clock retrieving here considering 1795 * 1. It is not needed on resume(from S3). 1796 * 2. DAL settings come between .hw_init and .late_init of SMU. 1797 * And DAL needs to know the maximum sustainable clocks. Thus 1798 * it cannot be put in .late_init(). 1799 */ 1800 ret = smu_init_max_sustainable_clocks(smu); 1801 if (ret) { 1802 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1803 return ret; 1804 } 1805 1806 adev->pm.dpm_enabled = true; 1807 1808 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1809 1810 return 0; 1811 } 1812 1813 static int smu_disable_dpms(struct smu_context *smu) 1814 { 1815 struct amdgpu_device *adev = smu->adev; 1816 int ret = 0; 1817 bool use_baco = !smu->is_apu && 1818 ((amdgpu_in_reset(adev) && 1819 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1820 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1821 1822 /* 1823 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1824 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1825 */ 1826 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1827 case IP_VERSION(13, 0, 0): 1828 case IP_VERSION(13, 0, 7): 1829 case IP_VERSION(13, 0, 10): 1830 return 0; 1831 default: 1832 break; 1833 } 1834 1835 /* 1836 * For custom pptable uploading, skip the DPM features 1837 * disable process on Navi1x ASICs. 1838 * - As the gfx related features are under control of 1839 * RLC on those ASICs. RLC reinitialization will be 1840 * needed to reenable them. That will cost much more 1841 * efforts. 1842 * 1843 * - SMU firmware can handle the DPM reenablement 1844 * properly. 1845 */ 1846 if (smu->uploading_custom_pp_table) { 1847 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1848 case IP_VERSION(11, 0, 0): 1849 case IP_VERSION(11, 0, 5): 1850 case IP_VERSION(11, 0, 9): 1851 case IP_VERSION(11, 0, 7): 1852 case IP_VERSION(11, 0, 11): 1853 case IP_VERSION(11, 5, 0): 1854 case IP_VERSION(11, 0, 12): 1855 case IP_VERSION(11, 0, 13): 1856 return 0; 1857 default: 1858 break; 1859 } 1860 } 1861 1862 /* 1863 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1864 * on BACO in. Driver involvement is unnecessary. 1865 */ 1866 if (use_baco) { 1867 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1868 case IP_VERSION(11, 0, 7): 1869 case IP_VERSION(11, 0, 0): 1870 case IP_VERSION(11, 0, 5): 1871 case IP_VERSION(11, 0, 9): 1872 case IP_VERSION(13, 0, 7): 1873 return 0; 1874 default: 1875 break; 1876 } 1877 } 1878 1879 /* 1880 * For SMU 13.0.4/11 and 14.0.0, PMFW will handle the features disablement properly 1881 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1882 */ 1883 if (amdgpu_in_reset(adev) || adev->in_s0ix) { 1884 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1885 case IP_VERSION(13, 0, 4): 1886 case IP_VERSION(13, 0, 11): 1887 case IP_VERSION(14, 0, 0): 1888 return 0; 1889 default: 1890 break; 1891 } 1892 } 1893 1894 /* 1895 * For gpu reset, runpm and hibernation through BACO, 1896 * BACO feature has to be kept enabled. 1897 */ 1898 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1899 ret = smu_disable_all_features_with_exception(smu, 1900 SMU_FEATURE_BACO_BIT); 1901 if (ret) 1902 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1903 } else { 1904 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1905 if (!adev->scpm_enabled) { 1906 ret = smu_system_features_control(smu, false); 1907 if (ret) 1908 dev_err(adev->dev, "Failed to disable smu features.\n"); 1909 } 1910 } 1911 1912 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1913 * otherwise SMU will hang while interacting with RLC if RLC is halted 1914 * this is a WA for Vangogh asic which fix the SMU hang issue. 1915 */ 1916 ret = smu_notify_rlc_state(smu, false); 1917 if (ret) { 1918 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1919 return ret; 1920 } 1921 1922 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1923 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1924 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1925 adev->gfx.rlc.funcs->stop(adev); 1926 1927 return ret; 1928 } 1929 1930 static int smu_smc_hw_cleanup(struct smu_context *smu) 1931 { 1932 struct amdgpu_device *adev = smu->adev; 1933 int ret = 0; 1934 1935 smu_wbrf_fini(smu); 1936 1937 cancel_work_sync(&smu->throttling_logging_work); 1938 cancel_work_sync(&smu->interrupt_work); 1939 1940 ret = smu_disable_thermal_alert(smu); 1941 if (ret) { 1942 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1943 return ret; 1944 } 1945 1946 cancel_delayed_work_sync(&smu->swctf_delayed_work); 1947 1948 ret = smu_disable_dpms(smu); 1949 if (ret) { 1950 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1951 return ret; 1952 } 1953 1954 return 0; 1955 } 1956 1957 static int smu_reset_mp1_state(struct smu_context *smu) 1958 { 1959 struct amdgpu_device *adev = smu->adev; 1960 int ret = 0; 1961 1962 if ((!adev->in_runpm) && (!adev->in_suspend) && 1963 (!amdgpu_in_reset(adev))) 1964 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1965 case IP_VERSION(13, 0, 0): 1966 case IP_VERSION(13, 0, 7): 1967 case IP_VERSION(13, 0, 10): 1968 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 1969 break; 1970 default: 1971 break; 1972 } 1973 1974 return ret; 1975 } 1976 1977 static int smu_hw_fini(void *handle) 1978 { 1979 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1980 struct smu_context *smu = adev->powerplay.pp_handle; 1981 int ret; 1982 1983 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 1984 return 0; 1985 1986 smu_dpm_set_vcn_enable(smu, false); 1987 smu_dpm_set_jpeg_enable(smu, false); 1988 smu_dpm_set_vpe_enable(smu, false); 1989 smu_dpm_set_umsch_mm_enable(smu, false); 1990 1991 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1992 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1993 1994 if (!smu->pm_enabled) 1995 return 0; 1996 1997 adev->pm.dpm_enabled = false; 1998 1999 ret = smu_smc_hw_cleanup(smu); 2000 if (ret) 2001 return ret; 2002 2003 ret = smu_reset_mp1_state(smu); 2004 if (ret) 2005 return ret; 2006 2007 return 0; 2008 } 2009 2010 static void smu_late_fini(void *handle) 2011 { 2012 struct amdgpu_device *adev = handle; 2013 struct smu_context *smu = adev->powerplay.pp_handle; 2014 2015 kfree(smu); 2016 } 2017 2018 static int smu_reset(struct smu_context *smu) 2019 { 2020 struct amdgpu_device *adev = smu->adev; 2021 int ret; 2022 2023 ret = smu_hw_fini(adev); 2024 if (ret) 2025 return ret; 2026 2027 ret = smu_hw_init(adev); 2028 if (ret) 2029 return ret; 2030 2031 ret = smu_late_init(adev); 2032 if (ret) 2033 return ret; 2034 2035 return 0; 2036 } 2037 2038 static int smu_suspend(void *handle) 2039 { 2040 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2041 struct smu_context *smu = adev->powerplay.pp_handle; 2042 int ret; 2043 uint64_t count; 2044 2045 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2046 return 0; 2047 2048 if (!smu->pm_enabled) 2049 return 0; 2050 2051 adev->pm.dpm_enabled = false; 2052 2053 ret = smu_smc_hw_cleanup(smu); 2054 if (ret) 2055 return ret; 2056 2057 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2058 2059 smu_set_gfx_cgpg(smu, false); 2060 2061 /* 2062 * pwfw resets entrycount when device is suspended, so we save the 2063 * last value to be used when we resume to keep it consistent 2064 */ 2065 ret = smu_get_entrycount_gfxoff(smu, &count); 2066 if (!ret) 2067 adev->gfx.gfx_off_entrycount = count; 2068 2069 return 0; 2070 } 2071 2072 static int smu_resume(void *handle) 2073 { 2074 int ret; 2075 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2076 struct smu_context *smu = adev->powerplay.pp_handle; 2077 2078 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2079 return 0; 2080 2081 if (!smu->pm_enabled) 2082 return 0; 2083 2084 dev_info(adev->dev, "SMU is resuming...\n"); 2085 2086 ret = smu_start_smc_engine(smu); 2087 if (ret) { 2088 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2089 return ret; 2090 } 2091 2092 ret = smu_smc_hw_setup(smu); 2093 if (ret) { 2094 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2095 return ret; 2096 } 2097 2098 ret = smu_set_gfx_imu_enable(smu); 2099 if (ret) 2100 return ret; 2101 2102 smu_set_gfx_cgpg(smu, true); 2103 2104 smu->disable_uclk_switch = 0; 2105 2106 adev->pm.dpm_enabled = true; 2107 2108 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2109 2110 return 0; 2111 } 2112 2113 static int smu_display_configuration_change(void *handle, 2114 const struct amd_pp_display_configuration *display_config) 2115 { 2116 struct smu_context *smu = handle; 2117 2118 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2119 return -EOPNOTSUPP; 2120 2121 if (!display_config) 2122 return -EINVAL; 2123 2124 smu_set_min_dcef_deep_sleep(smu, 2125 display_config->min_dcef_deep_sleep_set_clk / 100); 2126 2127 return 0; 2128 } 2129 2130 static int smu_set_clockgating_state(void *handle, 2131 enum amd_clockgating_state state) 2132 { 2133 return 0; 2134 } 2135 2136 static int smu_set_powergating_state(void *handle, 2137 enum amd_powergating_state state) 2138 { 2139 return 0; 2140 } 2141 2142 static int smu_enable_umd_pstate(void *handle, 2143 enum amd_dpm_forced_level *level) 2144 { 2145 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2146 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2147 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2148 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2149 2150 struct smu_context *smu = (struct smu_context*)(handle); 2151 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2152 2153 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2154 return -EINVAL; 2155 2156 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2157 /* enter umd pstate, save current level, disable gfx cg*/ 2158 if (*level & profile_mode_mask) { 2159 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2160 smu_gpo_control(smu, false); 2161 smu_gfx_ulv_control(smu, false); 2162 smu_deep_sleep_control(smu, false); 2163 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2164 } 2165 } else { 2166 /* exit umd pstate, restore level, enable gfx cg*/ 2167 if (!(*level & profile_mode_mask)) { 2168 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2169 *level = smu_dpm_ctx->saved_dpm_level; 2170 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2171 smu_deep_sleep_control(smu, true); 2172 smu_gfx_ulv_control(smu, true); 2173 smu_gpo_control(smu, true); 2174 } 2175 } 2176 2177 return 0; 2178 } 2179 2180 static int smu_bump_power_profile_mode(struct smu_context *smu, 2181 long *param, 2182 uint32_t param_size) 2183 { 2184 int ret = 0; 2185 2186 if (smu->ppt_funcs->set_power_profile_mode) 2187 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2188 2189 return ret; 2190 } 2191 2192 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2193 enum amd_dpm_forced_level level, 2194 bool skip_display_settings) 2195 { 2196 int ret = 0; 2197 int index = 0; 2198 long workload; 2199 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2200 2201 if (!skip_display_settings) { 2202 ret = smu_display_config_changed(smu); 2203 if (ret) { 2204 dev_err(smu->adev->dev, "Failed to change display config!"); 2205 return ret; 2206 } 2207 } 2208 2209 ret = smu_apply_clocks_adjust_rules(smu); 2210 if (ret) { 2211 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2212 return ret; 2213 } 2214 2215 if (!skip_display_settings) { 2216 ret = smu_notify_smc_display_config(smu); 2217 if (ret) { 2218 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2219 return ret; 2220 } 2221 } 2222 2223 if (smu_dpm_ctx->dpm_level != level) { 2224 ret = smu_asic_set_performance_level(smu, level); 2225 if (ret) { 2226 dev_err(smu->adev->dev, "Failed to set performance level!"); 2227 return ret; 2228 } 2229 2230 /* update the saved copy */ 2231 smu_dpm_ctx->dpm_level = level; 2232 } 2233 2234 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2235 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2236 index = fls(smu->workload_mask); 2237 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2238 workload = smu->workload_setting[index]; 2239 2240 if (smu->power_profile_mode != workload) 2241 smu_bump_power_profile_mode(smu, &workload, 0); 2242 } 2243 2244 return ret; 2245 } 2246 2247 static int smu_handle_task(struct smu_context *smu, 2248 enum amd_dpm_forced_level level, 2249 enum amd_pp_task task_id) 2250 { 2251 int ret = 0; 2252 2253 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2254 return -EOPNOTSUPP; 2255 2256 switch (task_id) { 2257 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2258 ret = smu_pre_display_config_changed(smu); 2259 if (ret) 2260 return ret; 2261 ret = smu_adjust_power_state_dynamic(smu, level, false); 2262 break; 2263 case AMD_PP_TASK_COMPLETE_INIT: 2264 case AMD_PP_TASK_READJUST_POWER_STATE: 2265 ret = smu_adjust_power_state_dynamic(smu, level, true); 2266 break; 2267 default: 2268 break; 2269 } 2270 2271 return ret; 2272 } 2273 2274 static int smu_handle_dpm_task(void *handle, 2275 enum amd_pp_task task_id, 2276 enum amd_pm_state_type *user_state) 2277 { 2278 struct smu_context *smu = handle; 2279 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2280 2281 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2282 2283 } 2284 2285 static int smu_switch_power_profile(void *handle, 2286 enum PP_SMC_POWER_PROFILE type, 2287 bool en) 2288 { 2289 struct smu_context *smu = handle; 2290 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2291 long workload; 2292 uint32_t index; 2293 2294 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2295 return -EOPNOTSUPP; 2296 2297 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2298 return -EINVAL; 2299 2300 if (!en) { 2301 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 2302 index = fls(smu->workload_mask); 2303 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2304 workload = smu->workload_setting[index]; 2305 } else { 2306 smu->workload_mask |= (1 << smu->workload_prority[type]); 2307 index = fls(smu->workload_mask); 2308 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2309 workload = smu->workload_setting[index]; 2310 } 2311 2312 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2313 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2314 smu_bump_power_profile_mode(smu, &workload, 0); 2315 2316 return 0; 2317 } 2318 2319 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2320 { 2321 struct smu_context *smu = handle; 2322 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2323 2324 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2325 return -EOPNOTSUPP; 2326 2327 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2328 return -EINVAL; 2329 2330 return smu_dpm_ctx->dpm_level; 2331 } 2332 2333 static int smu_force_performance_level(void *handle, 2334 enum amd_dpm_forced_level level) 2335 { 2336 struct smu_context *smu = handle; 2337 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2338 int ret = 0; 2339 2340 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2341 return -EOPNOTSUPP; 2342 2343 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2344 return -EINVAL; 2345 2346 ret = smu_enable_umd_pstate(smu, &level); 2347 if (ret) 2348 return ret; 2349 2350 ret = smu_handle_task(smu, level, 2351 AMD_PP_TASK_READJUST_POWER_STATE); 2352 2353 /* reset user dpm clock state */ 2354 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2355 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2356 smu->user_dpm_profile.clk_dependency = 0; 2357 } 2358 2359 return ret; 2360 } 2361 2362 static int smu_set_display_count(void *handle, uint32_t count) 2363 { 2364 struct smu_context *smu = handle; 2365 2366 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2367 return -EOPNOTSUPP; 2368 2369 return smu_init_display_count(smu, count); 2370 } 2371 2372 static int smu_force_smuclk_levels(struct smu_context *smu, 2373 enum smu_clk_type clk_type, 2374 uint32_t mask) 2375 { 2376 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2377 int ret = 0; 2378 2379 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2380 return -EOPNOTSUPP; 2381 2382 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2383 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2384 return -EINVAL; 2385 } 2386 2387 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2388 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2389 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2390 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2391 smu_set_user_clk_dependencies(smu, clk_type); 2392 } 2393 } 2394 2395 return ret; 2396 } 2397 2398 static int smu_force_ppclk_levels(void *handle, 2399 enum pp_clock_type type, 2400 uint32_t mask) 2401 { 2402 struct smu_context *smu = handle; 2403 enum smu_clk_type clk_type; 2404 2405 switch (type) { 2406 case PP_SCLK: 2407 clk_type = SMU_SCLK; break; 2408 case PP_MCLK: 2409 clk_type = SMU_MCLK; break; 2410 case PP_PCIE: 2411 clk_type = SMU_PCIE; break; 2412 case PP_SOCCLK: 2413 clk_type = SMU_SOCCLK; break; 2414 case PP_FCLK: 2415 clk_type = SMU_FCLK; break; 2416 case PP_DCEFCLK: 2417 clk_type = SMU_DCEFCLK; break; 2418 case PP_VCLK: 2419 clk_type = SMU_VCLK; break; 2420 case PP_VCLK1: 2421 clk_type = SMU_VCLK1; break; 2422 case PP_DCLK: 2423 clk_type = SMU_DCLK; break; 2424 case PP_DCLK1: 2425 clk_type = SMU_DCLK1; break; 2426 case OD_SCLK: 2427 clk_type = SMU_OD_SCLK; break; 2428 case OD_MCLK: 2429 clk_type = SMU_OD_MCLK; break; 2430 case OD_VDDC_CURVE: 2431 clk_type = SMU_OD_VDDC_CURVE; break; 2432 case OD_RANGE: 2433 clk_type = SMU_OD_RANGE; break; 2434 default: 2435 return -EINVAL; 2436 } 2437 2438 return smu_force_smuclk_levels(smu, clk_type, mask); 2439 } 2440 2441 /* 2442 * On system suspending or resetting, the dpm_enabled 2443 * flag will be cleared. So that those SMU services which 2444 * are not supported will be gated. 2445 * However, the mp1 state setting should still be granted 2446 * even if the dpm_enabled cleared. 2447 */ 2448 static int smu_set_mp1_state(void *handle, 2449 enum pp_mp1_state mp1_state) 2450 { 2451 struct smu_context *smu = handle; 2452 int ret = 0; 2453 2454 if (!smu->pm_enabled) 2455 return -EOPNOTSUPP; 2456 2457 if (smu->ppt_funcs && 2458 smu->ppt_funcs->set_mp1_state) 2459 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2460 2461 return ret; 2462 } 2463 2464 static int smu_set_df_cstate(void *handle, 2465 enum pp_df_cstate state) 2466 { 2467 struct smu_context *smu = handle; 2468 int ret = 0; 2469 2470 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2471 return -EOPNOTSUPP; 2472 2473 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2474 return 0; 2475 2476 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2477 if (ret) 2478 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2479 2480 return ret; 2481 } 2482 2483 int smu_write_watermarks_table(struct smu_context *smu) 2484 { 2485 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2486 return -EOPNOTSUPP; 2487 2488 return smu_set_watermarks_table(smu, NULL); 2489 } 2490 2491 static int smu_set_watermarks_for_clock_ranges(void *handle, 2492 struct pp_smu_wm_range_sets *clock_ranges) 2493 { 2494 struct smu_context *smu = handle; 2495 2496 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2497 return -EOPNOTSUPP; 2498 2499 if (smu->disable_watermark) 2500 return 0; 2501 2502 return smu_set_watermarks_table(smu, clock_ranges); 2503 } 2504 2505 int smu_set_ac_dc(struct smu_context *smu) 2506 { 2507 int ret = 0; 2508 2509 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2510 return -EOPNOTSUPP; 2511 2512 /* controlled by firmware */ 2513 if (smu->dc_controlled_by_gpio) 2514 return 0; 2515 2516 ret = smu_set_power_source(smu, 2517 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2518 SMU_POWER_SOURCE_DC); 2519 if (ret) 2520 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2521 smu->adev->pm.ac_power ? "AC" : "DC"); 2522 2523 return ret; 2524 } 2525 2526 const struct amd_ip_funcs smu_ip_funcs = { 2527 .name = "smu", 2528 .early_init = smu_early_init, 2529 .late_init = smu_late_init, 2530 .sw_init = smu_sw_init, 2531 .sw_fini = smu_sw_fini, 2532 .hw_init = smu_hw_init, 2533 .hw_fini = smu_hw_fini, 2534 .late_fini = smu_late_fini, 2535 .suspend = smu_suspend, 2536 .resume = smu_resume, 2537 .is_idle = NULL, 2538 .check_soft_reset = NULL, 2539 .wait_for_idle = NULL, 2540 .soft_reset = NULL, 2541 .set_clockgating_state = smu_set_clockgating_state, 2542 .set_powergating_state = smu_set_powergating_state, 2543 }; 2544 2545 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2546 .type = AMD_IP_BLOCK_TYPE_SMC, 2547 .major = 11, 2548 .minor = 0, 2549 .rev = 0, 2550 .funcs = &smu_ip_funcs, 2551 }; 2552 2553 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2554 .type = AMD_IP_BLOCK_TYPE_SMC, 2555 .major = 12, 2556 .minor = 0, 2557 .rev = 0, 2558 .funcs = &smu_ip_funcs, 2559 }; 2560 2561 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2562 .type = AMD_IP_BLOCK_TYPE_SMC, 2563 .major = 13, 2564 .minor = 0, 2565 .rev = 0, 2566 .funcs = &smu_ip_funcs, 2567 }; 2568 2569 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2570 .type = AMD_IP_BLOCK_TYPE_SMC, 2571 .major = 14, 2572 .minor = 0, 2573 .rev = 0, 2574 .funcs = &smu_ip_funcs, 2575 }; 2576 2577 static int smu_load_microcode(void *handle) 2578 { 2579 struct smu_context *smu = handle; 2580 struct amdgpu_device *adev = smu->adev; 2581 int ret = 0; 2582 2583 if (!smu->pm_enabled) 2584 return -EOPNOTSUPP; 2585 2586 /* This should be used for non PSP loading */ 2587 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2588 return 0; 2589 2590 if (smu->ppt_funcs->load_microcode) { 2591 ret = smu->ppt_funcs->load_microcode(smu); 2592 if (ret) { 2593 dev_err(adev->dev, "Load microcode failed\n"); 2594 return ret; 2595 } 2596 } 2597 2598 if (smu->ppt_funcs->check_fw_status) { 2599 ret = smu->ppt_funcs->check_fw_status(smu); 2600 if (ret) { 2601 dev_err(adev->dev, "SMC is not ready\n"); 2602 return ret; 2603 } 2604 } 2605 2606 return ret; 2607 } 2608 2609 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2610 { 2611 int ret = 0; 2612 2613 if (smu->ppt_funcs->set_gfx_cgpg) 2614 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2615 2616 return ret; 2617 } 2618 2619 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2620 { 2621 struct smu_context *smu = handle; 2622 int ret = 0; 2623 2624 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2625 return -EOPNOTSUPP; 2626 2627 if (!smu->ppt_funcs->set_fan_speed_rpm) 2628 return -EOPNOTSUPP; 2629 2630 if (speed == U32_MAX) 2631 return -EINVAL; 2632 2633 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2634 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2635 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2636 smu->user_dpm_profile.fan_speed_rpm = speed; 2637 2638 /* Override custom PWM setting as they cannot co-exist */ 2639 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2640 smu->user_dpm_profile.fan_speed_pwm = 0; 2641 } 2642 2643 return ret; 2644 } 2645 2646 /** 2647 * smu_get_power_limit - Request one of the SMU Power Limits 2648 * 2649 * @handle: pointer to smu context 2650 * @limit: requested limit is written back to this variable 2651 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2652 * @pp_power_type: &pp_power_type type of power 2653 * Return: 0 on success, <0 on error 2654 * 2655 */ 2656 int smu_get_power_limit(void *handle, 2657 uint32_t *limit, 2658 enum pp_power_limit_level pp_limit_level, 2659 enum pp_power_type pp_power_type) 2660 { 2661 struct smu_context *smu = handle; 2662 struct amdgpu_device *adev = smu->adev; 2663 enum smu_ppt_limit_level limit_level; 2664 uint32_t limit_type; 2665 int ret = 0; 2666 2667 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2668 return -EOPNOTSUPP; 2669 2670 switch (pp_power_type) { 2671 case PP_PWR_TYPE_SUSTAINED: 2672 limit_type = SMU_DEFAULT_PPT_LIMIT; 2673 break; 2674 case PP_PWR_TYPE_FAST: 2675 limit_type = SMU_FAST_PPT_LIMIT; 2676 break; 2677 default: 2678 return -EOPNOTSUPP; 2679 } 2680 2681 switch (pp_limit_level) { 2682 case PP_PWR_LIMIT_CURRENT: 2683 limit_level = SMU_PPT_LIMIT_CURRENT; 2684 break; 2685 case PP_PWR_LIMIT_DEFAULT: 2686 limit_level = SMU_PPT_LIMIT_DEFAULT; 2687 break; 2688 case PP_PWR_LIMIT_MAX: 2689 limit_level = SMU_PPT_LIMIT_MAX; 2690 break; 2691 case PP_PWR_LIMIT_MIN: 2692 limit_level = SMU_PPT_LIMIT_MIN; 2693 break; 2694 default: 2695 return -EOPNOTSUPP; 2696 } 2697 2698 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2699 if (smu->ppt_funcs->get_ppt_limit) 2700 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2701 } else { 2702 switch (limit_level) { 2703 case SMU_PPT_LIMIT_CURRENT: 2704 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2705 case IP_VERSION(13, 0, 2): 2706 case IP_VERSION(13, 0, 6): 2707 case IP_VERSION(11, 0, 7): 2708 case IP_VERSION(11, 0, 11): 2709 case IP_VERSION(11, 0, 12): 2710 case IP_VERSION(11, 0, 13): 2711 ret = smu_get_asic_power_limits(smu, 2712 &smu->current_power_limit, 2713 NULL, NULL, NULL); 2714 break; 2715 default: 2716 break; 2717 } 2718 *limit = smu->current_power_limit; 2719 break; 2720 case SMU_PPT_LIMIT_DEFAULT: 2721 *limit = smu->default_power_limit; 2722 break; 2723 case SMU_PPT_LIMIT_MAX: 2724 *limit = smu->max_power_limit; 2725 break; 2726 case SMU_PPT_LIMIT_MIN: 2727 *limit = smu->min_power_limit; 2728 break; 2729 default: 2730 return -EINVAL; 2731 } 2732 } 2733 2734 return ret; 2735 } 2736 2737 static int smu_set_power_limit(void *handle, uint32_t limit) 2738 { 2739 struct smu_context *smu = handle; 2740 uint32_t limit_type = limit >> 24; 2741 int ret = 0; 2742 2743 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2744 return -EOPNOTSUPP; 2745 2746 limit &= (1<<24)-1; 2747 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2748 if (smu->ppt_funcs->set_power_limit) 2749 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2750 2751 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2752 dev_err(smu->adev->dev, 2753 "New power limit (%d) is out of range [%d,%d]\n", 2754 limit, smu->min_power_limit, smu->max_power_limit); 2755 return -EINVAL; 2756 } 2757 2758 if (!limit) 2759 limit = smu->current_power_limit; 2760 2761 if (smu->ppt_funcs->set_power_limit) { 2762 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2763 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2764 smu->user_dpm_profile.power_limit = limit; 2765 } 2766 2767 return ret; 2768 } 2769 2770 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2771 { 2772 int ret = 0; 2773 2774 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2775 return -EOPNOTSUPP; 2776 2777 if (smu->ppt_funcs->print_clk_levels) 2778 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2779 2780 return ret; 2781 } 2782 2783 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2784 { 2785 enum smu_clk_type clk_type; 2786 2787 switch (type) { 2788 case PP_SCLK: 2789 clk_type = SMU_SCLK; break; 2790 case PP_MCLK: 2791 clk_type = SMU_MCLK; break; 2792 case PP_PCIE: 2793 clk_type = SMU_PCIE; break; 2794 case PP_SOCCLK: 2795 clk_type = SMU_SOCCLK; break; 2796 case PP_FCLK: 2797 clk_type = SMU_FCLK; break; 2798 case PP_DCEFCLK: 2799 clk_type = SMU_DCEFCLK; break; 2800 case PP_VCLK: 2801 clk_type = SMU_VCLK; break; 2802 case PP_VCLK1: 2803 clk_type = SMU_VCLK1; break; 2804 case PP_DCLK: 2805 clk_type = SMU_DCLK; break; 2806 case PP_DCLK1: 2807 clk_type = SMU_DCLK1; break; 2808 case OD_SCLK: 2809 clk_type = SMU_OD_SCLK; break; 2810 case OD_MCLK: 2811 clk_type = SMU_OD_MCLK; break; 2812 case OD_VDDC_CURVE: 2813 clk_type = SMU_OD_VDDC_CURVE; break; 2814 case OD_RANGE: 2815 clk_type = SMU_OD_RANGE; break; 2816 case OD_VDDGFX_OFFSET: 2817 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2818 case OD_CCLK: 2819 clk_type = SMU_OD_CCLK; break; 2820 case OD_FAN_CURVE: 2821 clk_type = SMU_OD_FAN_CURVE; break; 2822 case OD_ACOUSTIC_LIMIT: 2823 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2824 case OD_ACOUSTIC_TARGET: 2825 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2826 case OD_FAN_TARGET_TEMPERATURE: 2827 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2828 case OD_FAN_MINIMUM_PWM: 2829 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2830 default: 2831 clk_type = SMU_CLK_COUNT; break; 2832 } 2833 2834 return clk_type; 2835 } 2836 2837 static int smu_print_ppclk_levels(void *handle, 2838 enum pp_clock_type type, 2839 char *buf) 2840 { 2841 struct smu_context *smu = handle; 2842 enum smu_clk_type clk_type; 2843 2844 clk_type = smu_convert_to_smuclk(type); 2845 if (clk_type == SMU_CLK_COUNT) 2846 return -EINVAL; 2847 2848 return smu_print_smuclk_levels(smu, clk_type, buf); 2849 } 2850 2851 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2852 { 2853 struct smu_context *smu = handle; 2854 enum smu_clk_type clk_type; 2855 2856 clk_type = smu_convert_to_smuclk(type); 2857 if (clk_type == SMU_CLK_COUNT) 2858 return -EINVAL; 2859 2860 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2861 return -EOPNOTSUPP; 2862 2863 if (!smu->ppt_funcs->emit_clk_levels) 2864 return -ENOENT; 2865 2866 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2867 2868 } 2869 2870 static int smu_od_edit_dpm_table(void *handle, 2871 enum PP_OD_DPM_TABLE_COMMAND type, 2872 long *input, uint32_t size) 2873 { 2874 struct smu_context *smu = handle; 2875 int ret = 0; 2876 2877 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2878 return -EOPNOTSUPP; 2879 2880 if (smu->ppt_funcs->od_edit_dpm_table) { 2881 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2882 } 2883 2884 return ret; 2885 } 2886 2887 static int smu_read_sensor(void *handle, 2888 int sensor, 2889 void *data, 2890 int *size_arg) 2891 { 2892 struct smu_context *smu = handle; 2893 struct smu_umd_pstate_table *pstate_table = 2894 &smu->pstate_table; 2895 int ret = 0; 2896 uint32_t *size, size_val; 2897 2898 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2899 return -EOPNOTSUPP; 2900 2901 if (!data || !size_arg) 2902 return -EINVAL; 2903 2904 size_val = *size_arg; 2905 size = &size_val; 2906 2907 if (smu->ppt_funcs->read_sensor) 2908 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2909 goto unlock; 2910 2911 switch (sensor) { 2912 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2913 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2914 *size = 4; 2915 break; 2916 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2917 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2918 *size = 4; 2919 break; 2920 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2921 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2922 *size = 4; 2923 break; 2924 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2925 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2926 *size = 4; 2927 break; 2928 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2929 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2930 *size = 8; 2931 break; 2932 case AMDGPU_PP_SENSOR_UVD_POWER: 2933 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2934 *size = 4; 2935 break; 2936 case AMDGPU_PP_SENSOR_VCE_POWER: 2937 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2938 *size = 4; 2939 break; 2940 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2941 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 2942 *size = 4; 2943 break; 2944 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2945 *(uint32_t *)data = 0; 2946 *size = 4; 2947 break; 2948 default: 2949 *size = 0; 2950 ret = -EOPNOTSUPP; 2951 break; 2952 } 2953 2954 unlock: 2955 // assign uint32_t to int 2956 *size_arg = size_val; 2957 2958 return ret; 2959 } 2960 2961 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 2962 { 2963 int ret = -EOPNOTSUPP; 2964 struct smu_context *smu = handle; 2965 2966 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 2967 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 2968 2969 return ret; 2970 } 2971 2972 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 2973 { 2974 int ret = -EOPNOTSUPP; 2975 struct smu_context *smu = handle; 2976 2977 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 2978 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 2979 2980 return ret; 2981 } 2982 2983 static int smu_get_power_profile_mode(void *handle, char *buf) 2984 { 2985 struct smu_context *smu = handle; 2986 2987 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2988 !smu->ppt_funcs->get_power_profile_mode) 2989 return -EOPNOTSUPP; 2990 if (!buf) 2991 return -EINVAL; 2992 2993 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2994 } 2995 2996 static int smu_set_power_profile_mode(void *handle, 2997 long *param, 2998 uint32_t param_size) 2999 { 3000 struct smu_context *smu = handle; 3001 3002 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3003 !smu->ppt_funcs->set_power_profile_mode) 3004 return -EOPNOTSUPP; 3005 3006 return smu_bump_power_profile_mode(smu, param, param_size); 3007 } 3008 3009 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3010 { 3011 struct smu_context *smu = handle; 3012 3013 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3014 return -EOPNOTSUPP; 3015 3016 if (!smu->ppt_funcs->get_fan_control_mode) 3017 return -EOPNOTSUPP; 3018 3019 if (!fan_mode) 3020 return -EINVAL; 3021 3022 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3023 3024 return 0; 3025 } 3026 3027 static int smu_set_fan_control_mode(void *handle, u32 value) 3028 { 3029 struct smu_context *smu = handle; 3030 int ret = 0; 3031 3032 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3033 return -EOPNOTSUPP; 3034 3035 if (!smu->ppt_funcs->set_fan_control_mode) 3036 return -EOPNOTSUPP; 3037 3038 if (value == U32_MAX) 3039 return -EINVAL; 3040 3041 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3042 if (ret) 3043 goto out; 3044 3045 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3046 smu->user_dpm_profile.fan_mode = value; 3047 3048 /* reset user dpm fan speed */ 3049 if (value != AMD_FAN_CTRL_MANUAL) { 3050 smu->user_dpm_profile.fan_speed_pwm = 0; 3051 smu->user_dpm_profile.fan_speed_rpm = 0; 3052 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3053 } 3054 } 3055 3056 out: 3057 return ret; 3058 } 3059 3060 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3061 { 3062 struct smu_context *smu = handle; 3063 int ret = 0; 3064 3065 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3066 return -EOPNOTSUPP; 3067 3068 if (!smu->ppt_funcs->get_fan_speed_pwm) 3069 return -EOPNOTSUPP; 3070 3071 if (!speed) 3072 return -EINVAL; 3073 3074 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3075 3076 return ret; 3077 } 3078 3079 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3080 { 3081 struct smu_context *smu = handle; 3082 int ret = 0; 3083 3084 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3085 return -EOPNOTSUPP; 3086 3087 if (!smu->ppt_funcs->set_fan_speed_pwm) 3088 return -EOPNOTSUPP; 3089 3090 if (speed == U32_MAX) 3091 return -EINVAL; 3092 3093 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3094 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3095 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3096 smu->user_dpm_profile.fan_speed_pwm = speed; 3097 3098 /* Override custom RPM setting as they cannot co-exist */ 3099 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3100 smu->user_dpm_profile.fan_speed_rpm = 0; 3101 } 3102 3103 return ret; 3104 } 3105 3106 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3107 { 3108 struct smu_context *smu = handle; 3109 int ret = 0; 3110 3111 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3112 return -EOPNOTSUPP; 3113 3114 if (!smu->ppt_funcs->get_fan_speed_rpm) 3115 return -EOPNOTSUPP; 3116 3117 if (!speed) 3118 return -EINVAL; 3119 3120 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3121 3122 return ret; 3123 } 3124 3125 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3126 { 3127 struct smu_context *smu = handle; 3128 3129 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3130 return -EOPNOTSUPP; 3131 3132 return smu_set_min_dcef_deep_sleep(smu, clk); 3133 } 3134 3135 static int smu_get_clock_by_type_with_latency(void *handle, 3136 enum amd_pp_clock_type type, 3137 struct pp_clock_levels_with_latency *clocks) 3138 { 3139 struct smu_context *smu = handle; 3140 enum smu_clk_type clk_type; 3141 int ret = 0; 3142 3143 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3144 return -EOPNOTSUPP; 3145 3146 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3147 switch (type) { 3148 case amd_pp_sys_clock: 3149 clk_type = SMU_GFXCLK; 3150 break; 3151 case amd_pp_mem_clock: 3152 clk_type = SMU_MCLK; 3153 break; 3154 case amd_pp_dcef_clock: 3155 clk_type = SMU_DCEFCLK; 3156 break; 3157 case amd_pp_disp_clock: 3158 clk_type = SMU_DISPCLK; 3159 break; 3160 default: 3161 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3162 return -EINVAL; 3163 } 3164 3165 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3166 } 3167 3168 return ret; 3169 } 3170 3171 static int smu_display_clock_voltage_request(void *handle, 3172 struct pp_display_clock_request *clock_req) 3173 { 3174 struct smu_context *smu = handle; 3175 int ret = 0; 3176 3177 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3178 return -EOPNOTSUPP; 3179 3180 if (smu->ppt_funcs->display_clock_voltage_request) 3181 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3182 3183 return ret; 3184 } 3185 3186 3187 static int smu_display_disable_memory_clock_switch(void *handle, 3188 bool disable_memory_clock_switch) 3189 { 3190 struct smu_context *smu = handle; 3191 int ret = -EINVAL; 3192 3193 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3194 return -EOPNOTSUPP; 3195 3196 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3197 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3198 3199 return ret; 3200 } 3201 3202 static int smu_set_xgmi_pstate(void *handle, 3203 uint32_t pstate) 3204 { 3205 struct smu_context *smu = handle; 3206 int ret = 0; 3207 3208 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3209 return -EOPNOTSUPP; 3210 3211 if (smu->ppt_funcs->set_xgmi_pstate) 3212 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3213 3214 if (ret) 3215 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3216 3217 return ret; 3218 } 3219 3220 static bool smu_get_baco_capability(void *handle) 3221 { 3222 struct smu_context *smu = handle; 3223 3224 if (!smu->pm_enabled) 3225 return false; 3226 3227 if (!smu->ppt_funcs || !smu->ppt_funcs->baco_is_support) 3228 return false; 3229 3230 return smu->ppt_funcs->baco_is_support(smu); 3231 } 3232 3233 static int smu_baco_set_state(void *handle, int state) 3234 { 3235 struct smu_context *smu = handle; 3236 int ret = 0; 3237 3238 if (!smu->pm_enabled) 3239 return -EOPNOTSUPP; 3240 3241 if (state == 0) { 3242 if (smu->ppt_funcs->baco_exit) 3243 ret = smu->ppt_funcs->baco_exit(smu); 3244 } else if (state == 1) { 3245 if (smu->ppt_funcs->baco_enter) 3246 ret = smu->ppt_funcs->baco_enter(smu); 3247 } else { 3248 return -EINVAL; 3249 } 3250 3251 if (ret) 3252 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3253 (state)?"enter":"exit"); 3254 3255 return ret; 3256 } 3257 3258 bool smu_mode1_reset_is_support(struct smu_context *smu) 3259 { 3260 bool ret = false; 3261 3262 if (!smu->pm_enabled) 3263 return false; 3264 3265 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3266 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3267 3268 return ret; 3269 } 3270 3271 bool smu_mode2_reset_is_support(struct smu_context *smu) 3272 { 3273 bool ret = false; 3274 3275 if (!smu->pm_enabled) 3276 return false; 3277 3278 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3279 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3280 3281 return ret; 3282 } 3283 3284 int smu_mode1_reset(struct smu_context *smu) 3285 { 3286 int ret = 0; 3287 3288 if (!smu->pm_enabled) 3289 return -EOPNOTSUPP; 3290 3291 if (smu->ppt_funcs->mode1_reset) 3292 ret = smu->ppt_funcs->mode1_reset(smu); 3293 3294 return ret; 3295 } 3296 3297 static int smu_mode2_reset(void *handle) 3298 { 3299 struct smu_context *smu = handle; 3300 int ret = 0; 3301 3302 if (!smu->pm_enabled) 3303 return -EOPNOTSUPP; 3304 3305 if (smu->ppt_funcs->mode2_reset) 3306 ret = smu->ppt_funcs->mode2_reset(smu); 3307 3308 if (ret) 3309 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3310 3311 return ret; 3312 } 3313 3314 static int smu_enable_gfx_features(void *handle) 3315 { 3316 struct smu_context *smu = handle; 3317 int ret = 0; 3318 3319 if (!smu->pm_enabled) 3320 return -EOPNOTSUPP; 3321 3322 if (smu->ppt_funcs->enable_gfx_features) 3323 ret = smu->ppt_funcs->enable_gfx_features(smu); 3324 3325 if (ret) 3326 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3327 3328 return ret; 3329 } 3330 3331 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3332 struct pp_smu_nv_clock_table *max_clocks) 3333 { 3334 struct smu_context *smu = handle; 3335 int ret = 0; 3336 3337 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3338 return -EOPNOTSUPP; 3339 3340 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3341 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3342 3343 return ret; 3344 } 3345 3346 static int smu_get_uclk_dpm_states(void *handle, 3347 unsigned int *clock_values_in_khz, 3348 unsigned int *num_states) 3349 { 3350 struct smu_context *smu = handle; 3351 int ret = 0; 3352 3353 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3354 return -EOPNOTSUPP; 3355 3356 if (smu->ppt_funcs->get_uclk_dpm_states) 3357 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3358 3359 return ret; 3360 } 3361 3362 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3363 { 3364 struct smu_context *smu = handle; 3365 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3366 3367 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3368 return -EOPNOTSUPP; 3369 3370 if (smu->ppt_funcs->get_current_power_state) 3371 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3372 3373 return pm_state; 3374 } 3375 3376 static int smu_get_dpm_clock_table(void *handle, 3377 struct dpm_clocks *clock_table) 3378 { 3379 struct smu_context *smu = handle; 3380 int ret = 0; 3381 3382 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3383 return -EOPNOTSUPP; 3384 3385 if (smu->ppt_funcs->get_dpm_clock_table) 3386 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3387 3388 return ret; 3389 } 3390 3391 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3392 { 3393 struct smu_context *smu = handle; 3394 3395 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3396 return -EOPNOTSUPP; 3397 3398 if (!smu->ppt_funcs->get_gpu_metrics) 3399 return -EOPNOTSUPP; 3400 3401 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3402 } 3403 3404 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3405 size_t size) 3406 { 3407 struct smu_context *smu = handle; 3408 3409 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3410 return -EOPNOTSUPP; 3411 3412 if (!smu->ppt_funcs->get_pm_metrics) 3413 return -EOPNOTSUPP; 3414 3415 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3416 } 3417 3418 static int smu_enable_mgpu_fan_boost(void *handle) 3419 { 3420 struct smu_context *smu = handle; 3421 int ret = 0; 3422 3423 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3424 return -EOPNOTSUPP; 3425 3426 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3427 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3428 3429 return ret; 3430 } 3431 3432 static int smu_gfx_state_change_set(void *handle, 3433 uint32_t state) 3434 { 3435 struct smu_context *smu = handle; 3436 int ret = 0; 3437 3438 if (smu->ppt_funcs->gfx_state_change_set) 3439 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3440 3441 return ret; 3442 } 3443 3444 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3445 { 3446 int ret = 0; 3447 3448 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3449 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3450 3451 return ret; 3452 } 3453 3454 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3455 { 3456 int ret = -EOPNOTSUPP; 3457 3458 if (smu->ppt_funcs && 3459 smu->ppt_funcs->get_ecc_info) 3460 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3461 3462 return ret; 3463 3464 } 3465 3466 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3467 { 3468 struct smu_context *smu = handle; 3469 struct smu_table_context *smu_table = &smu->smu_table; 3470 struct smu_table *memory_pool = &smu_table->memory_pool; 3471 3472 if (!addr || !size) 3473 return -EINVAL; 3474 3475 *addr = NULL; 3476 *size = 0; 3477 if (memory_pool->bo) { 3478 *addr = memory_pool->cpu_addr; 3479 *size = memory_pool->size; 3480 } 3481 3482 return 0; 3483 } 3484 3485 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 3486 enum pp_xgmi_plpd_mode mode) 3487 { 3488 int ret = -EOPNOTSUPP; 3489 3490 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3491 return ret; 3492 3493 /* PLPD policy is not supported if it's NONE */ 3494 if (smu->plpd_mode == XGMI_PLPD_NONE) 3495 return ret; 3496 3497 if (smu->plpd_mode == mode) 3498 return 0; 3499 3500 if (smu->ppt_funcs && smu->ppt_funcs->select_xgmi_plpd_policy) 3501 ret = smu->ppt_funcs->select_xgmi_plpd_policy(smu, mode); 3502 3503 if (!ret) 3504 smu->plpd_mode = mode; 3505 3506 return ret; 3507 } 3508 3509 static const struct amd_pm_funcs swsmu_pm_funcs = { 3510 /* export for sysfs */ 3511 .set_fan_control_mode = smu_set_fan_control_mode, 3512 .get_fan_control_mode = smu_get_fan_control_mode, 3513 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3514 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3515 .force_clock_level = smu_force_ppclk_levels, 3516 .print_clock_levels = smu_print_ppclk_levels, 3517 .emit_clock_levels = smu_emit_ppclk_levels, 3518 .force_performance_level = smu_force_performance_level, 3519 .read_sensor = smu_read_sensor, 3520 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3521 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3522 .get_performance_level = smu_get_performance_level, 3523 .get_current_power_state = smu_get_current_power_state, 3524 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3525 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3526 .get_pp_num_states = smu_get_power_num_states, 3527 .get_pp_table = smu_sys_get_pp_table, 3528 .set_pp_table = smu_sys_set_pp_table, 3529 .switch_power_profile = smu_switch_power_profile, 3530 /* export to amdgpu */ 3531 .dispatch_tasks = smu_handle_dpm_task, 3532 .load_firmware = smu_load_microcode, 3533 .set_powergating_by_smu = smu_dpm_set_power_gate, 3534 .set_power_limit = smu_set_power_limit, 3535 .get_power_limit = smu_get_power_limit, 3536 .get_power_profile_mode = smu_get_power_profile_mode, 3537 .set_power_profile_mode = smu_set_power_profile_mode, 3538 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3539 .set_mp1_state = smu_set_mp1_state, 3540 .gfx_state_change_set = smu_gfx_state_change_set, 3541 /* export to DC */ 3542 .get_sclk = smu_get_sclk, 3543 .get_mclk = smu_get_mclk, 3544 .display_configuration_change = smu_display_configuration_change, 3545 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3546 .display_clock_voltage_request = smu_display_clock_voltage_request, 3547 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3548 .set_active_display_count = smu_set_display_count, 3549 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3550 .get_asic_baco_capability = smu_get_baco_capability, 3551 .set_asic_baco_state = smu_baco_set_state, 3552 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3553 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3554 .asic_reset_mode_2 = smu_mode2_reset, 3555 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3556 .set_df_cstate = smu_set_df_cstate, 3557 .set_xgmi_pstate = smu_set_xgmi_pstate, 3558 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3559 .get_pm_metrics = smu_sys_get_pm_metrics, 3560 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3561 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3562 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3563 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3564 .get_dpm_clock_table = smu_get_dpm_clock_table, 3565 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3566 }; 3567 3568 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3569 uint64_t event_arg) 3570 { 3571 int ret = -EINVAL; 3572 3573 if (smu->ppt_funcs->wait_for_event) 3574 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3575 3576 return ret; 3577 } 3578 3579 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3580 { 3581 3582 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3583 return -EOPNOTSUPP; 3584 3585 /* Confirm the buffer allocated is of correct size */ 3586 if (size != smu->stb_context.stb_buf_size) 3587 return -EINVAL; 3588 3589 /* 3590 * No need to lock smu mutex as we access STB directly through MMIO 3591 * and not going through SMU messaging route (for now at least). 3592 * For registers access rely on implementation internal locking. 3593 */ 3594 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3595 } 3596 3597 #if defined(CONFIG_DEBUG_FS) 3598 3599 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3600 { 3601 struct amdgpu_device *adev = filp->f_inode->i_private; 3602 struct smu_context *smu = adev->powerplay.pp_handle; 3603 unsigned char *buf; 3604 int r; 3605 3606 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3607 if (!buf) 3608 return -ENOMEM; 3609 3610 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3611 if (r) 3612 goto out; 3613 3614 filp->private_data = buf; 3615 3616 return 0; 3617 3618 out: 3619 kvfree(buf); 3620 return r; 3621 } 3622 3623 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3624 loff_t *pos) 3625 { 3626 struct amdgpu_device *adev = filp->f_inode->i_private; 3627 struct smu_context *smu = adev->powerplay.pp_handle; 3628 3629 3630 if (!filp->private_data) 3631 return -EINVAL; 3632 3633 return simple_read_from_buffer(buf, 3634 size, 3635 pos, filp->private_data, 3636 smu->stb_context.stb_buf_size); 3637 } 3638 3639 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3640 { 3641 kvfree(filp->private_data); 3642 filp->private_data = NULL; 3643 3644 return 0; 3645 } 3646 3647 /* 3648 * We have to define not only read method but also 3649 * open and release because .read takes up to PAGE_SIZE 3650 * data each time so and so is invoked multiple times. 3651 * We allocate the STB buffer in .open and release it 3652 * in .release 3653 */ 3654 static const struct file_operations smu_stb_debugfs_fops = { 3655 .owner = THIS_MODULE, 3656 .open = smu_stb_debugfs_open, 3657 .read = smu_stb_debugfs_read, 3658 .release = smu_stb_debugfs_release, 3659 .llseek = default_llseek, 3660 }; 3661 3662 #endif 3663 3664 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3665 { 3666 #if defined(CONFIG_DEBUG_FS) 3667 3668 struct smu_context *smu = adev->powerplay.pp_handle; 3669 3670 if (!smu || (!smu->stb_context.stb_buf_size)) 3671 return; 3672 3673 debugfs_create_file_size("amdgpu_smu_stb_dump", 3674 S_IRUSR, 3675 adev_to_drm(adev)->primary->debugfs_root, 3676 adev, 3677 &smu_stb_debugfs_fops, 3678 smu->stb_context.stb_buf_size); 3679 #endif 3680 } 3681 3682 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3683 { 3684 int ret = 0; 3685 3686 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3687 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3688 3689 return ret; 3690 } 3691 3692 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3693 { 3694 int ret = 0; 3695 3696 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3697 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3698 3699 return ret; 3700 } 3701