1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "amd_pcie.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 static const struct amd_pm_funcs swsmu_pm_funcs; 61 static int smu_force_smuclk_levels(struct smu_context *smu, 62 enum smu_clk_type clk_type, 63 uint32_t mask); 64 static int smu_handle_task(struct smu_context *smu, 65 enum amd_dpm_forced_level level, 66 enum amd_pp_task task_id); 67 static int smu_reset(struct smu_context *smu); 68 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 69 static int smu_set_fan_control_mode(void *handle, u32 value); 70 static int smu_set_power_limit(void *handle, uint32_t limit); 71 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 72 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 73 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 74 75 static int smu_sys_get_pp_feature_mask(void *handle, 76 char *buf) 77 { 78 struct smu_context *smu = handle; 79 80 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 81 return -EOPNOTSUPP; 82 83 return smu_get_pp_feature_mask(smu, buf); 84 } 85 86 static int smu_sys_set_pp_feature_mask(void *handle, 87 uint64_t new_mask) 88 { 89 struct smu_context *smu = handle; 90 91 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 92 return -EOPNOTSUPP; 93 94 return smu_set_pp_feature_mask(smu, new_mask); 95 } 96 97 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 98 { 99 if (!smu->ppt_funcs->set_gfx_off_residency) 100 return -EINVAL; 101 102 return smu_set_gfx_off_residency(smu, value); 103 } 104 105 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 106 { 107 if (!smu->ppt_funcs->get_gfx_off_residency) 108 return -EINVAL; 109 110 return smu_get_gfx_off_residency(smu, value); 111 } 112 113 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 114 { 115 if (!smu->ppt_funcs->get_gfx_off_entrycount) 116 return -EINVAL; 117 118 return smu_get_gfx_off_entrycount(smu, value); 119 } 120 121 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 122 { 123 if (!smu->ppt_funcs->get_gfx_off_status) 124 return -EINVAL; 125 126 *value = smu_get_gfx_off_status(smu); 127 128 return 0; 129 } 130 131 int smu_set_soft_freq_range(struct smu_context *smu, 132 enum smu_clk_type clk_type, 133 uint32_t min, 134 uint32_t max) 135 { 136 int ret = 0; 137 138 if (smu->ppt_funcs->set_soft_freq_limited_range) 139 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 140 clk_type, 141 min, 142 max); 143 144 return ret; 145 } 146 147 int smu_get_dpm_freq_range(struct smu_context *smu, 148 enum smu_clk_type clk_type, 149 uint32_t *min, 150 uint32_t *max) 151 { 152 int ret = -ENOTSUPP; 153 154 if (!min && !max) 155 return -EINVAL; 156 157 if (smu->ppt_funcs->get_dpm_ultimate_freq) 158 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 159 clk_type, 160 min, 161 max); 162 163 return ret; 164 } 165 166 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 167 { 168 int ret = 0; 169 struct amdgpu_device *adev = smu->adev; 170 171 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 172 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 173 if (ret) 174 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 175 } 176 return ret; 177 } 178 179 static u32 smu_get_mclk(void *handle, bool low) 180 { 181 struct smu_context *smu = handle; 182 uint32_t clk_freq; 183 int ret = 0; 184 185 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 186 low ? &clk_freq : NULL, 187 !low ? &clk_freq : NULL); 188 if (ret) 189 return 0; 190 return clk_freq * 100; 191 } 192 193 static u32 smu_get_sclk(void *handle, bool low) 194 { 195 struct smu_context *smu = handle; 196 uint32_t clk_freq; 197 int ret = 0; 198 199 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 200 low ? &clk_freq : NULL, 201 !low ? &clk_freq : NULL); 202 if (ret) 203 return 0; 204 return clk_freq * 100; 205 } 206 207 static int smu_set_gfx_imu_enable(struct smu_context *smu) 208 { 209 struct amdgpu_device *adev = smu->adev; 210 211 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 212 return 0; 213 214 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 215 return 0; 216 217 return smu_set_gfx_power_up_by_imu(smu); 218 } 219 220 static bool is_vcn_enabled(struct amdgpu_device *adev) 221 { 222 int i; 223 224 for (i = 0; i < adev->num_ip_blocks; i++) { 225 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 226 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 227 !adev->ip_blocks[i].status.valid) 228 return false; 229 } 230 231 return true; 232 } 233 234 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 235 bool enable) 236 { 237 struct smu_power_context *smu_power = &smu->smu_power; 238 struct smu_power_gate *power_gate = &smu_power->power_gate; 239 int ret = 0; 240 241 /* 242 * don't poweron vcn/jpeg when they are skipped. 243 */ 244 if (!is_vcn_enabled(smu->adev)) 245 return 0; 246 247 if (!smu->ppt_funcs->dpm_set_vcn_enable) 248 return 0; 249 250 if (atomic_read(&power_gate->vcn_gated) ^ enable) 251 return 0; 252 253 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 254 if (!ret) 255 atomic_set(&power_gate->vcn_gated, !enable); 256 257 return ret; 258 } 259 260 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 261 bool enable) 262 { 263 struct smu_power_context *smu_power = &smu->smu_power; 264 struct smu_power_gate *power_gate = &smu_power->power_gate; 265 int ret = 0; 266 267 if (!is_vcn_enabled(smu->adev)) 268 return 0; 269 270 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 271 return 0; 272 273 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 274 return 0; 275 276 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 277 if (!ret) 278 atomic_set(&power_gate->jpeg_gated, !enable); 279 280 return ret; 281 } 282 283 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 284 bool enable) 285 { 286 struct smu_power_context *smu_power = &smu->smu_power; 287 struct smu_power_gate *power_gate = &smu_power->power_gate; 288 int ret = 0; 289 290 if (!smu->ppt_funcs->dpm_set_vpe_enable) 291 return 0; 292 293 if (atomic_read(&power_gate->vpe_gated) ^ enable) 294 return 0; 295 296 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 297 if (!ret) 298 atomic_set(&power_gate->vpe_gated, !enable); 299 300 return ret; 301 } 302 303 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 304 bool enable) 305 { 306 struct smu_power_context *smu_power = &smu->smu_power; 307 struct smu_power_gate *power_gate = &smu_power->power_gate; 308 int ret = 0; 309 310 if (!smu->adev->enable_umsch_mm) 311 return 0; 312 313 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 314 return 0; 315 316 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 317 return 0; 318 319 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 320 if (!ret) 321 atomic_set(&power_gate->umsch_mm_gated, !enable); 322 323 return ret; 324 } 325 326 /** 327 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 328 * 329 * @handle: smu_context pointer 330 * @block_type: the IP block to power gate/ungate 331 * @gate: to power gate if true, ungate otherwise 332 * 333 * This API uses no smu->mutex lock protection due to: 334 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 335 * This is guarded to be race condition free by the caller. 336 * 2. Or get called on user setting request of power_dpm_force_performance_level. 337 * Under this case, the smu->mutex lock protection is already enforced on 338 * the parent API smu_force_performance_level of the call path. 339 */ 340 static int smu_dpm_set_power_gate(void *handle, 341 uint32_t block_type, 342 bool gate) 343 { 344 struct smu_context *smu = handle; 345 int ret = 0; 346 347 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 348 dev_WARN(smu->adev->dev, 349 "SMU uninitialized but power %s requested for %u!\n", 350 gate ? "gate" : "ungate", block_type); 351 return -EOPNOTSUPP; 352 } 353 354 switch (block_type) { 355 /* 356 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 357 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 358 */ 359 case AMD_IP_BLOCK_TYPE_UVD: 360 case AMD_IP_BLOCK_TYPE_VCN: 361 ret = smu_dpm_set_vcn_enable(smu, !gate); 362 if (ret) 363 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 364 gate ? "gate" : "ungate"); 365 break; 366 case AMD_IP_BLOCK_TYPE_GFX: 367 ret = smu_gfx_off_control(smu, gate); 368 if (ret) 369 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 370 gate ? "enable" : "disable"); 371 break; 372 case AMD_IP_BLOCK_TYPE_SDMA: 373 ret = smu_powergate_sdma(smu, gate); 374 if (ret) 375 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 376 gate ? "gate" : "ungate"); 377 break; 378 case AMD_IP_BLOCK_TYPE_JPEG: 379 ret = smu_dpm_set_jpeg_enable(smu, !gate); 380 if (ret) 381 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 382 gate ? "gate" : "ungate"); 383 break; 384 case AMD_IP_BLOCK_TYPE_VPE: 385 ret = smu_dpm_set_vpe_enable(smu, !gate); 386 if (ret) 387 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 388 gate ? "gate" : "ungate"); 389 break; 390 default: 391 dev_err(smu->adev->dev, "Unsupported block type!\n"); 392 return -EINVAL; 393 } 394 395 return ret; 396 } 397 398 /** 399 * smu_set_user_clk_dependencies - set user profile clock dependencies 400 * 401 * @smu: smu_context pointer 402 * @clk: enum smu_clk_type type 403 * 404 * Enable/Disable the clock dependency for the @clk type. 405 */ 406 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 407 { 408 if (smu->adev->in_suspend) 409 return; 410 411 if (clk == SMU_MCLK) { 412 smu->user_dpm_profile.clk_dependency = 0; 413 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 414 } else if (clk == SMU_FCLK) { 415 /* MCLK takes precedence over FCLK */ 416 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 417 return; 418 419 smu->user_dpm_profile.clk_dependency = 0; 420 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 421 } else if (clk == SMU_SOCCLK) { 422 /* MCLK takes precedence over SOCCLK */ 423 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 424 return; 425 426 smu->user_dpm_profile.clk_dependency = 0; 427 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 428 } else 429 /* Add clk dependencies here, if any */ 430 return; 431 } 432 433 /** 434 * smu_restore_dpm_user_profile - reinstate user dpm profile 435 * 436 * @smu: smu_context pointer 437 * 438 * Restore the saved user power configurations include power limit, 439 * clock frequencies, fan control mode and fan speed. 440 */ 441 static void smu_restore_dpm_user_profile(struct smu_context *smu) 442 { 443 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 444 int ret = 0; 445 446 if (!smu->adev->in_suspend) 447 return; 448 449 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 450 return; 451 452 /* Enable restore flag */ 453 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 454 455 /* set the user dpm power limit */ 456 if (smu->user_dpm_profile.power_limit) { 457 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 458 if (ret) 459 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 460 } 461 462 /* set the user dpm clock configurations */ 463 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 464 enum smu_clk_type clk_type; 465 466 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 467 /* 468 * Iterate over smu clk type and force the saved user clk 469 * configs, skip if clock dependency is enabled 470 */ 471 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 472 smu->user_dpm_profile.clk_mask[clk_type]) { 473 ret = smu_force_smuclk_levels(smu, clk_type, 474 smu->user_dpm_profile.clk_mask[clk_type]); 475 if (ret) 476 dev_err(smu->adev->dev, 477 "Failed to set clock type = %d\n", clk_type); 478 } 479 } 480 } 481 482 /* set the user dpm fan configurations */ 483 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 484 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 485 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 486 if (ret != -EOPNOTSUPP) { 487 smu->user_dpm_profile.fan_speed_pwm = 0; 488 smu->user_dpm_profile.fan_speed_rpm = 0; 489 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 490 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 491 } 492 493 if (smu->user_dpm_profile.fan_speed_pwm) { 494 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 495 if (ret != -EOPNOTSUPP) 496 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 497 } 498 499 if (smu->user_dpm_profile.fan_speed_rpm) { 500 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 501 if (ret != -EOPNOTSUPP) 502 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 503 } 504 } 505 506 /* Restore user customized OD settings */ 507 if (smu->user_dpm_profile.user_od) { 508 if (smu->ppt_funcs->restore_user_od_settings) { 509 ret = smu->ppt_funcs->restore_user_od_settings(smu); 510 if (ret) 511 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 512 } 513 } 514 515 /* Disable restore flag */ 516 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 517 } 518 519 static int smu_get_power_num_states(void *handle, 520 struct pp_states_info *state_info) 521 { 522 if (!state_info) 523 return -EINVAL; 524 525 /* not support power state */ 526 memset(state_info, 0, sizeof(struct pp_states_info)); 527 state_info->nums = 1; 528 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 529 530 return 0; 531 } 532 533 bool is_support_sw_smu(struct amdgpu_device *adev) 534 { 535 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 536 if (adev->asic_type == CHIP_VEGA20) 537 return false; 538 539 if (amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) 540 return true; 541 542 return false; 543 } 544 545 bool is_support_cclk_dpm(struct amdgpu_device *adev) 546 { 547 struct smu_context *smu = adev->powerplay.pp_handle; 548 549 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 550 return false; 551 552 return true; 553 } 554 555 556 static int smu_sys_get_pp_table(void *handle, 557 char **table) 558 { 559 struct smu_context *smu = handle; 560 struct smu_table_context *smu_table = &smu->smu_table; 561 562 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 563 return -EOPNOTSUPP; 564 565 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 566 return -EINVAL; 567 568 if (smu_table->hardcode_pptable) 569 *table = smu_table->hardcode_pptable; 570 else 571 *table = smu_table->power_play_table; 572 573 return smu_table->power_play_table_size; 574 } 575 576 static int smu_sys_set_pp_table(void *handle, 577 const char *buf, 578 size_t size) 579 { 580 struct smu_context *smu = handle; 581 struct smu_table_context *smu_table = &smu->smu_table; 582 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 583 int ret = 0; 584 585 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 586 return -EOPNOTSUPP; 587 588 if (header->usStructureSize != size) { 589 dev_err(smu->adev->dev, "pp table size not matched !\n"); 590 return -EIO; 591 } 592 593 if (!smu_table->hardcode_pptable) { 594 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 595 if (!smu_table->hardcode_pptable) 596 return -ENOMEM; 597 } 598 599 memcpy(smu_table->hardcode_pptable, buf, size); 600 smu_table->power_play_table = smu_table->hardcode_pptable; 601 smu_table->power_play_table_size = size; 602 603 /* 604 * Special hw_fini action(for Navi1x, the DPMs disablement will be 605 * skipped) may be needed for custom pptable uploading. 606 */ 607 smu->uploading_custom_pp_table = true; 608 609 ret = smu_reset(smu); 610 if (ret) 611 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 612 613 smu->uploading_custom_pp_table = false; 614 615 return ret; 616 } 617 618 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 619 { 620 struct smu_feature *feature = &smu->smu_feature; 621 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 622 int ret = 0; 623 624 /* 625 * With SCPM enabled, the allowed featuremasks setting(via 626 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 627 * That means there is no way to let PMFW knows the settings below. 628 * Thus, we just assume all the features are allowed under 629 * such scenario. 630 */ 631 if (smu->adev->scpm_enabled) { 632 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 633 return 0; 634 } 635 636 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 637 638 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 639 SMU_FEATURE_MAX/32); 640 if (ret) 641 return ret; 642 643 bitmap_or(feature->allowed, feature->allowed, 644 (unsigned long *)allowed_feature_mask, 645 feature->feature_num); 646 647 return ret; 648 } 649 650 static int smu_set_funcs(struct amdgpu_device *adev) 651 { 652 struct smu_context *smu = adev->powerplay.pp_handle; 653 654 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 655 smu->od_enabled = true; 656 657 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 658 case IP_VERSION(11, 0, 0): 659 case IP_VERSION(11, 0, 5): 660 case IP_VERSION(11, 0, 9): 661 navi10_set_ppt_funcs(smu); 662 break; 663 case IP_VERSION(11, 0, 7): 664 case IP_VERSION(11, 0, 11): 665 case IP_VERSION(11, 0, 12): 666 case IP_VERSION(11, 0, 13): 667 sienna_cichlid_set_ppt_funcs(smu); 668 break; 669 case IP_VERSION(12, 0, 0): 670 case IP_VERSION(12, 0, 1): 671 renoir_set_ppt_funcs(smu); 672 break; 673 case IP_VERSION(11, 5, 0): 674 vangogh_set_ppt_funcs(smu); 675 break; 676 case IP_VERSION(13, 0, 1): 677 case IP_VERSION(13, 0, 3): 678 case IP_VERSION(13, 0, 8): 679 yellow_carp_set_ppt_funcs(smu); 680 break; 681 case IP_VERSION(13, 0, 4): 682 case IP_VERSION(13, 0, 11): 683 smu_v13_0_4_set_ppt_funcs(smu); 684 break; 685 case IP_VERSION(13, 0, 5): 686 smu_v13_0_5_set_ppt_funcs(smu); 687 break; 688 case IP_VERSION(11, 0, 8): 689 cyan_skillfish_set_ppt_funcs(smu); 690 break; 691 case IP_VERSION(11, 0, 2): 692 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 693 arcturus_set_ppt_funcs(smu); 694 /* OD is not supported on Arcturus */ 695 smu->od_enabled = false; 696 break; 697 case IP_VERSION(13, 0, 2): 698 aldebaran_set_ppt_funcs(smu); 699 /* Enable pp_od_clk_voltage node */ 700 smu->od_enabled = true; 701 break; 702 case IP_VERSION(13, 0, 0): 703 case IP_VERSION(13, 0, 10): 704 smu_v13_0_0_set_ppt_funcs(smu); 705 break; 706 case IP_VERSION(13, 0, 6): 707 smu_v13_0_6_set_ppt_funcs(smu); 708 /* Enable pp_od_clk_voltage node */ 709 smu->od_enabled = true; 710 break; 711 case IP_VERSION(13, 0, 7): 712 smu_v13_0_7_set_ppt_funcs(smu); 713 break; 714 case IP_VERSION(14, 0, 0): 715 smu_v14_0_0_set_ppt_funcs(smu); 716 break; 717 default: 718 return -EINVAL; 719 } 720 721 return 0; 722 } 723 724 static int smu_early_init(void *handle) 725 { 726 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 727 struct smu_context *smu; 728 int r; 729 730 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 731 if (!smu) 732 return -ENOMEM; 733 734 smu->adev = adev; 735 smu->pm_enabled = !!amdgpu_dpm; 736 smu->is_apu = false; 737 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 738 smu->smu_baco.platform_support = false; 739 smu->user_dpm_profile.fan_mode = -1; 740 741 mutex_init(&smu->message_lock); 742 743 adev->powerplay.pp_handle = smu; 744 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 745 746 r = smu_set_funcs(adev); 747 if (r) 748 return r; 749 return smu_init_microcode(smu); 750 } 751 752 static int smu_set_default_dpm_table(struct smu_context *smu) 753 { 754 struct amdgpu_device *adev = smu->adev; 755 struct smu_power_context *smu_power = &smu->smu_power; 756 struct smu_power_gate *power_gate = &smu_power->power_gate; 757 int vcn_gate, jpeg_gate; 758 int ret = 0; 759 760 if (!smu->ppt_funcs->set_default_dpm_table) 761 return 0; 762 763 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 764 vcn_gate = atomic_read(&power_gate->vcn_gated); 765 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 766 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 767 768 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 769 ret = smu_dpm_set_vcn_enable(smu, true); 770 if (ret) 771 return ret; 772 } 773 774 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 775 ret = smu_dpm_set_jpeg_enable(smu, true); 776 if (ret) 777 goto err_out; 778 } 779 780 ret = smu->ppt_funcs->set_default_dpm_table(smu); 781 if (ret) 782 dev_err(smu->adev->dev, 783 "Failed to setup default dpm clock tables!\n"); 784 785 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 786 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 787 err_out: 788 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 789 smu_dpm_set_vcn_enable(smu, !vcn_gate); 790 791 return ret; 792 } 793 794 static int smu_apply_default_config_table_settings(struct smu_context *smu) 795 { 796 struct amdgpu_device *adev = smu->adev; 797 int ret = 0; 798 799 ret = smu_get_default_config_table_settings(smu, 800 &adev->pm.config_table); 801 if (ret) 802 return ret; 803 804 return smu_set_config_table(smu, &adev->pm.config_table); 805 } 806 807 static int smu_late_init(void *handle) 808 { 809 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 810 struct smu_context *smu = adev->powerplay.pp_handle; 811 int ret = 0; 812 813 smu_set_fine_grain_gfx_freq_parameters(smu); 814 815 if (!smu->pm_enabled) 816 return 0; 817 818 ret = smu_post_init(smu); 819 if (ret) { 820 dev_err(adev->dev, "Failed to post smu init!\n"); 821 return ret; 822 } 823 824 /* 825 * Explicitly notify PMFW the power mode the system in. Since 826 * the PMFW may boot the ASIC with a different mode. 827 * For those supporting ACDC switch via gpio, PMFW will 828 * handle the switch automatically. Driver involvement 829 * is unnecessary. 830 */ 831 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 832 smu_set_ac_dc(smu); 833 834 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 835 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 836 return 0; 837 838 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 839 ret = smu_set_default_od_settings(smu); 840 if (ret) { 841 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 842 return ret; 843 } 844 } 845 846 ret = smu_populate_umd_state_clk(smu); 847 if (ret) { 848 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 849 return ret; 850 } 851 852 ret = smu_get_asic_power_limits(smu, 853 &smu->current_power_limit, 854 &smu->default_power_limit, 855 &smu->max_power_limit, 856 &smu->min_power_limit); 857 if (ret) { 858 dev_err(adev->dev, "Failed to get asic power limits!\n"); 859 return ret; 860 } 861 862 if (!amdgpu_sriov_vf(adev)) 863 smu_get_unique_id(smu); 864 865 smu_get_fan_parameters(smu); 866 867 smu_handle_task(smu, 868 smu->smu_dpm.dpm_level, 869 AMD_PP_TASK_COMPLETE_INIT); 870 871 ret = smu_apply_default_config_table_settings(smu); 872 if (ret && (ret != -EOPNOTSUPP)) { 873 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 874 return ret; 875 } 876 877 smu_restore_dpm_user_profile(smu); 878 879 return 0; 880 } 881 882 static int smu_init_fb_allocations(struct smu_context *smu) 883 { 884 struct amdgpu_device *adev = smu->adev; 885 struct smu_table_context *smu_table = &smu->smu_table; 886 struct smu_table *tables = smu_table->tables; 887 struct smu_table *driver_table = &(smu_table->driver_table); 888 uint32_t max_table_size = 0; 889 int ret, i; 890 891 /* VRAM allocation for tool table */ 892 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 893 ret = amdgpu_bo_create_kernel(adev, 894 tables[SMU_TABLE_PMSTATUSLOG].size, 895 tables[SMU_TABLE_PMSTATUSLOG].align, 896 tables[SMU_TABLE_PMSTATUSLOG].domain, 897 &tables[SMU_TABLE_PMSTATUSLOG].bo, 898 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 899 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 900 if (ret) { 901 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 902 return ret; 903 } 904 } 905 906 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 907 /* VRAM allocation for driver table */ 908 for (i = 0; i < SMU_TABLE_COUNT; i++) { 909 if (tables[i].size == 0) 910 continue; 911 912 /* If one of the tables has VRAM domain restriction, keep it in 913 * VRAM 914 */ 915 if ((tables[i].domain & 916 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 917 AMDGPU_GEM_DOMAIN_VRAM) 918 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 919 920 if (i == SMU_TABLE_PMSTATUSLOG) 921 continue; 922 923 if (max_table_size < tables[i].size) 924 max_table_size = tables[i].size; 925 } 926 927 driver_table->size = max_table_size; 928 driver_table->align = PAGE_SIZE; 929 930 ret = amdgpu_bo_create_kernel(adev, 931 driver_table->size, 932 driver_table->align, 933 driver_table->domain, 934 &driver_table->bo, 935 &driver_table->mc_address, 936 &driver_table->cpu_addr); 937 if (ret) { 938 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 939 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 940 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 941 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 942 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 943 } 944 945 return ret; 946 } 947 948 static int smu_fini_fb_allocations(struct smu_context *smu) 949 { 950 struct smu_table_context *smu_table = &smu->smu_table; 951 struct smu_table *tables = smu_table->tables; 952 struct smu_table *driver_table = &(smu_table->driver_table); 953 954 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 955 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 956 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 957 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 958 959 amdgpu_bo_free_kernel(&driver_table->bo, 960 &driver_table->mc_address, 961 &driver_table->cpu_addr); 962 963 return 0; 964 } 965 966 /** 967 * smu_alloc_memory_pool - allocate memory pool in the system memory 968 * 969 * @smu: amdgpu_device pointer 970 * 971 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 972 * and DramLogSetDramAddr can notify it changed. 973 * 974 * Returns 0 on success, error on failure. 975 */ 976 static int smu_alloc_memory_pool(struct smu_context *smu) 977 { 978 struct amdgpu_device *adev = smu->adev; 979 struct smu_table_context *smu_table = &smu->smu_table; 980 struct smu_table *memory_pool = &smu_table->memory_pool; 981 uint64_t pool_size = smu->pool_size; 982 int ret = 0; 983 984 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 985 return ret; 986 987 memory_pool->size = pool_size; 988 memory_pool->align = PAGE_SIZE; 989 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 990 991 switch (pool_size) { 992 case SMU_MEMORY_POOL_SIZE_256_MB: 993 case SMU_MEMORY_POOL_SIZE_512_MB: 994 case SMU_MEMORY_POOL_SIZE_1_GB: 995 case SMU_MEMORY_POOL_SIZE_2_GB: 996 ret = amdgpu_bo_create_kernel(adev, 997 memory_pool->size, 998 memory_pool->align, 999 memory_pool->domain, 1000 &memory_pool->bo, 1001 &memory_pool->mc_address, 1002 &memory_pool->cpu_addr); 1003 if (ret) 1004 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1005 break; 1006 default: 1007 break; 1008 } 1009 1010 return ret; 1011 } 1012 1013 static int smu_free_memory_pool(struct smu_context *smu) 1014 { 1015 struct smu_table_context *smu_table = &smu->smu_table; 1016 struct smu_table *memory_pool = &smu_table->memory_pool; 1017 1018 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1019 return 0; 1020 1021 amdgpu_bo_free_kernel(&memory_pool->bo, 1022 &memory_pool->mc_address, 1023 &memory_pool->cpu_addr); 1024 1025 memset(memory_pool, 0, sizeof(struct smu_table)); 1026 1027 return 0; 1028 } 1029 1030 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1031 { 1032 struct smu_table_context *smu_table = &smu->smu_table; 1033 struct smu_table *dummy_read_1_table = 1034 &smu_table->dummy_read_1_table; 1035 struct amdgpu_device *adev = smu->adev; 1036 int ret = 0; 1037 1038 if (!dummy_read_1_table->size) 1039 return 0; 1040 1041 ret = amdgpu_bo_create_kernel(adev, 1042 dummy_read_1_table->size, 1043 dummy_read_1_table->align, 1044 dummy_read_1_table->domain, 1045 &dummy_read_1_table->bo, 1046 &dummy_read_1_table->mc_address, 1047 &dummy_read_1_table->cpu_addr); 1048 if (ret) 1049 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1050 1051 return ret; 1052 } 1053 1054 static void smu_free_dummy_read_table(struct smu_context *smu) 1055 { 1056 struct smu_table_context *smu_table = &smu->smu_table; 1057 struct smu_table *dummy_read_1_table = 1058 &smu_table->dummy_read_1_table; 1059 1060 1061 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1062 &dummy_read_1_table->mc_address, 1063 &dummy_read_1_table->cpu_addr); 1064 1065 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1066 } 1067 1068 static int smu_smc_table_sw_init(struct smu_context *smu) 1069 { 1070 int ret; 1071 1072 /** 1073 * Create smu_table structure, and init smc tables such as 1074 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1075 */ 1076 ret = smu_init_smc_tables(smu); 1077 if (ret) { 1078 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1079 return ret; 1080 } 1081 1082 /** 1083 * Create smu_power_context structure, and allocate smu_dpm_context and 1084 * context size to fill the smu_power_context data. 1085 */ 1086 ret = smu_init_power(smu); 1087 if (ret) { 1088 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1089 return ret; 1090 } 1091 1092 /* 1093 * allocate vram bos to store smc table contents. 1094 */ 1095 ret = smu_init_fb_allocations(smu); 1096 if (ret) 1097 return ret; 1098 1099 ret = smu_alloc_memory_pool(smu); 1100 if (ret) 1101 return ret; 1102 1103 ret = smu_alloc_dummy_read_table(smu); 1104 if (ret) 1105 return ret; 1106 1107 ret = smu_i2c_init(smu); 1108 if (ret) 1109 return ret; 1110 1111 return 0; 1112 } 1113 1114 static int smu_smc_table_sw_fini(struct smu_context *smu) 1115 { 1116 int ret; 1117 1118 smu_i2c_fini(smu); 1119 1120 smu_free_dummy_read_table(smu); 1121 1122 ret = smu_free_memory_pool(smu); 1123 if (ret) 1124 return ret; 1125 1126 ret = smu_fini_fb_allocations(smu); 1127 if (ret) 1128 return ret; 1129 1130 ret = smu_fini_power(smu); 1131 if (ret) { 1132 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1133 return ret; 1134 } 1135 1136 ret = smu_fini_smc_tables(smu); 1137 if (ret) { 1138 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1139 return ret; 1140 } 1141 1142 return 0; 1143 } 1144 1145 static void smu_throttling_logging_work_fn(struct work_struct *work) 1146 { 1147 struct smu_context *smu = container_of(work, struct smu_context, 1148 throttling_logging_work); 1149 1150 smu_log_thermal_throttling(smu); 1151 } 1152 1153 static void smu_interrupt_work_fn(struct work_struct *work) 1154 { 1155 struct smu_context *smu = container_of(work, struct smu_context, 1156 interrupt_work); 1157 1158 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1159 smu->ppt_funcs->interrupt_work(smu); 1160 } 1161 1162 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1163 { 1164 struct smu_context *smu = 1165 container_of(work, struct smu_context, swctf_delayed_work.work); 1166 struct smu_temperature_range *range = 1167 &smu->thermal_range; 1168 struct amdgpu_device *adev = smu->adev; 1169 uint32_t hotspot_tmp, size; 1170 1171 /* 1172 * If the hotspot temperature is confirmed as below SW CTF setting point 1173 * after the delay enforced, nothing will be done. 1174 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1175 */ 1176 if (range->software_shutdown_temp && 1177 smu->ppt_funcs->read_sensor && 1178 !smu->ppt_funcs->read_sensor(smu, 1179 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1180 &hotspot_tmp, 1181 &size) && 1182 hotspot_tmp / 1000 < range->software_shutdown_temp) 1183 return; 1184 1185 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1186 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1187 orderly_poweroff(true); 1188 } 1189 1190 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1191 { 1192 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1193 smu->plpd_mode = XGMI_PLPD_DEFAULT; 1194 return; 1195 } 1196 1197 /* PMFW put PLPD into default policy after enabling the feature */ 1198 if (smu_feature_is_enabled(smu, 1199 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) 1200 smu->plpd_mode = XGMI_PLPD_DEFAULT; 1201 else 1202 smu->plpd_mode = XGMI_PLPD_NONE; 1203 } 1204 1205 static int smu_sw_init(void *handle) 1206 { 1207 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1208 struct smu_context *smu = adev->powerplay.pp_handle; 1209 int ret; 1210 1211 smu->pool_size = adev->pm.smu_prv_buffer_size; 1212 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1213 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1214 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1215 1216 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1217 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1218 atomic64_set(&smu->throttle_int_counter, 0); 1219 smu->watermarks_bitmap = 0; 1220 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1221 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1222 1223 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1224 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1225 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1226 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1227 1228 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1229 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1230 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1231 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1232 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1233 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1234 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1235 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1236 1237 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1238 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1239 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1240 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1241 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1242 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1243 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1244 smu->display_config = &adev->pm.pm_display_cfg; 1245 1246 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1247 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1248 1249 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1250 smu_swctf_delayed_work_handler); 1251 1252 ret = smu_smc_table_sw_init(smu); 1253 if (ret) { 1254 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1255 return ret; 1256 } 1257 1258 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1259 ret = smu_get_vbios_bootup_values(smu); 1260 if (ret) { 1261 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1262 return ret; 1263 } 1264 1265 ret = smu_init_pptable_microcode(smu); 1266 if (ret) { 1267 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1268 return ret; 1269 } 1270 1271 ret = smu_register_irq_handler(smu); 1272 if (ret) { 1273 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1274 return ret; 1275 } 1276 1277 /* If there is no way to query fan control mode, fan control is not supported */ 1278 if (!smu->ppt_funcs->get_fan_control_mode) 1279 smu->adev->pm.no_fan = true; 1280 1281 return 0; 1282 } 1283 1284 static int smu_sw_fini(void *handle) 1285 { 1286 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1287 struct smu_context *smu = adev->powerplay.pp_handle; 1288 int ret; 1289 1290 ret = smu_smc_table_sw_fini(smu); 1291 if (ret) { 1292 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1293 return ret; 1294 } 1295 1296 smu_fini_microcode(smu); 1297 1298 return 0; 1299 } 1300 1301 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1302 { 1303 struct amdgpu_device *adev = smu->adev; 1304 struct smu_temperature_range *range = 1305 &smu->thermal_range; 1306 int ret = 0; 1307 1308 if (!smu->ppt_funcs->get_thermal_temperature_range) 1309 return 0; 1310 1311 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1312 if (ret) 1313 return ret; 1314 1315 adev->pm.dpm.thermal.min_temp = range->min; 1316 adev->pm.dpm.thermal.max_temp = range->max; 1317 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1318 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1319 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1320 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1321 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1322 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1323 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1324 1325 return ret; 1326 } 1327 1328 /** 1329 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1330 * 1331 * @smu: smu_context pointer 1332 * 1333 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1334 * Returns 0 on success, error on failure. 1335 */ 1336 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1337 { 1338 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1339 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1340 struct amdgpu_device *adev = smu->adev; 1341 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1342 uint64_t start, end; 1343 int ret, i, j; 1344 1345 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1346 if (ret) { 1347 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1348 return ret; 1349 } 1350 1351 /* 1352 * The exclusion ranges array we got might be filled with holes and duplicate 1353 * entries. For example: 1354 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1355 * We need to do some sortups to eliminate those holes and duplicate entries. 1356 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1357 */ 1358 for (i = 0; i < num_of_wbrf_ranges; i++) { 1359 start = wifi_bands[i].start; 1360 end = wifi_bands[i].end; 1361 1362 /* get the last valid entry to fill the intermediate hole */ 1363 if (!start && !end) { 1364 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1365 if (wifi_bands[j].start && wifi_bands[j].end) 1366 break; 1367 1368 /* no valid entry left */ 1369 if (j <= i) 1370 break; 1371 1372 start = wifi_bands[i].start = wifi_bands[j].start; 1373 end = wifi_bands[i].end = wifi_bands[j].end; 1374 wifi_bands[j].start = 0; 1375 wifi_bands[j].end = 0; 1376 num_of_wbrf_ranges = j; 1377 } 1378 1379 /* eliminate duplicate entries */ 1380 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1381 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1382 wifi_bands[j].start = 0; 1383 wifi_bands[j].end = 0; 1384 } 1385 } 1386 } 1387 1388 /* Send the sorted wifi_bands to PMFW */ 1389 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1390 /* Try to set the wifi_bands again */ 1391 if (unlikely(ret == -EBUSY)) { 1392 mdelay(5); 1393 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1394 } 1395 1396 return ret; 1397 } 1398 1399 /** 1400 * smu_wbrf_event_handler - handle notify events 1401 * 1402 * @nb: notifier block 1403 * @action: event type 1404 * @_arg: event data 1405 * 1406 * Calls relevant amdgpu function in response to wbrf event 1407 * notification from kernel. 1408 */ 1409 static int smu_wbrf_event_handler(struct notifier_block *nb, 1410 unsigned long action, void *_arg) 1411 { 1412 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1413 1414 switch (action) { 1415 case WBRF_CHANGED: 1416 schedule_delayed_work(&smu->wbrf_delayed_work, 1417 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1418 break; 1419 default: 1420 return NOTIFY_DONE; 1421 } 1422 1423 return NOTIFY_OK; 1424 } 1425 1426 /** 1427 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1428 * 1429 * @work: struct work_struct pointer 1430 * 1431 * Flood is over and driver will consume the latest exclusion ranges. 1432 */ 1433 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1434 { 1435 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1436 1437 smu_wbrf_handle_exclusion_ranges(smu); 1438 } 1439 1440 /** 1441 * smu_wbrf_support_check - check wbrf support 1442 * 1443 * @smu: smu_context pointer 1444 * 1445 * Verifies the ACPI interface whether wbrf is supported. 1446 */ 1447 static void smu_wbrf_support_check(struct smu_context *smu) 1448 { 1449 struct amdgpu_device *adev = smu->adev; 1450 1451 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1452 acpi_amd_wbrf_supported_consumer(adev->dev); 1453 1454 if (smu->wbrf_supported) 1455 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1456 } 1457 1458 /** 1459 * smu_wbrf_init - init driver wbrf support 1460 * 1461 * @smu: smu_context pointer 1462 * 1463 * Verifies the AMD ACPI interfaces and registers with the wbrf 1464 * notifier chain if wbrf feature is supported. 1465 * Returns 0 on success, error on failure. 1466 */ 1467 static int smu_wbrf_init(struct smu_context *smu) 1468 { 1469 int ret; 1470 1471 if (!smu->wbrf_supported) 1472 return 0; 1473 1474 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1475 1476 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1477 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1478 if (ret) 1479 return ret; 1480 1481 /* 1482 * Some wifiband exclusion ranges may be already there 1483 * before our driver loaded. To make sure our driver 1484 * is awared of those exclusion ranges. 1485 */ 1486 schedule_delayed_work(&smu->wbrf_delayed_work, 1487 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1488 1489 return 0; 1490 } 1491 1492 /** 1493 * smu_wbrf_fini - tear down driver wbrf support 1494 * 1495 * @smu: smu_context pointer 1496 * 1497 * Unregisters with the wbrf notifier chain. 1498 */ 1499 static void smu_wbrf_fini(struct smu_context *smu) 1500 { 1501 if (!smu->wbrf_supported) 1502 return; 1503 1504 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1505 1506 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1507 } 1508 1509 static int smu_smc_hw_setup(struct smu_context *smu) 1510 { 1511 struct smu_feature *feature = &smu->smu_feature; 1512 struct amdgpu_device *adev = smu->adev; 1513 uint8_t pcie_gen = 0, pcie_width = 0; 1514 uint64_t features_supported; 1515 int ret = 0; 1516 1517 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1518 case IP_VERSION(11, 0, 7): 1519 case IP_VERSION(11, 0, 11): 1520 case IP_VERSION(11, 5, 0): 1521 case IP_VERSION(11, 0, 12): 1522 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1523 dev_info(adev->dev, "dpm has been enabled\n"); 1524 ret = smu_system_features_control(smu, true); 1525 if (ret) 1526 dev_err(adev->dev, "Failed system features control!\n"); 1527 return ret; 1528 } 1529 break; 1530 default: 1531 break; 1532 } 1533 1534 ret = smu_init_display_count(smu, 0); 1535 if (ret) { 1536 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1537 return ret; 1538 } 1539 1540 ret = smu_set_driver_table_location(smu); 1541 if (ret) { 1542 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1543 return ret; 1544 } 1545 1546 /* 1547 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1548 */ 1549 ret = smu_set_tool_table_location(smu); 1550 if (ret) { 1551 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1552 return ret; 1553 } 1554 1555 /* 1556 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1557 * pool location. 1558 */ 1559 ret = smu_notify_memory_pool_location(smu); 1560 if (ret) { 1561 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1562 return ret; 1563 } 1564 1565 /* 1566 * It is assumed the pptable used before runpm is same as 1567 * the one used afterwards. Thus, we can reuse the stored 1568 * copy and do not need to resetup the pptable again. 1569 */ 1570 if (!adev->in_runpm) { 1571 ret = smu_setup_pptable(smu); 1572 if (ret) { 1573 dev_err(adev->dev, "Failed to setup pptable!\n"); 1574 return ret; 1575 } 1576 } 1577 1578 /* smu_dump_pptable(smu); */ 1579 1580 /* 1581 * With SCPM enabled, PSP is responsible for the PPTable transferring 1582 * (to SMU). Driver involvement is not needed and permitted. 1583 */ 1584 if (!adev->scpm_enabled) { 1585 /* 1586 * Copy pptable bo in the vram to smc with SMU MSGs such as 1587 * SetDriverDramAddr and TransferTableDram2Smu. 1588 */ 1589 ret = smu_write_pptable(smu); 1590 if (ret) { 1591 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1592 return ret; 1593 } 1594 } 1595 1596 /* issue Run*Btc msg */ 1597 ret = smu_run_btc(smu); 1598 if (ret) 1599 return ret; 1600 1601 /* Enable UclkShadow on wbrf supported */ 1602 if (smu->wbrf_supported) { 1603 ret = smu_enable_uclk_shadow(smu, true); 1604 if (ret) { 1605 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1606 return ret; 1607 } 1608 } 1609 1610 /* 1611 * With SCPM enabled, these actions(and relevant messages) are 1612 * not needed and permitted. 1613 */ 1614 if (!adev->scpm_enabled) { 1615 ret = smu_feature_set_allowed_mask(smu); 1616 if (ret) { 1617 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1618 return ret; 1619 } 1620 } 1621 1622 ret = smu_system_features_control(smu, true); 1623 if (ret) { 1624 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1625 return ret; 1626 } 1627 1628 smu_init_xgmi_plpd_mode(smu); 1629 1630 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1631 if (ret) { 1632 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1633 return ret; 1634 } 1635 bitmap_copy(feature->supported, 1636 (unsigned long *)&features_supported, 1637 feature->feature_num); 1638 1639 if (!smu_is_dpm_running(smu)) 1640 dev_info(adev->dev, "dpm has been disabled\n"); 1641 1642 /* 1643 * Set initialized values (get from vbios) to dpm tables context such as 1644 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1645 * type of clks. 1646 */ 1647 ret = smu_set_default_dpm_table(smu); 1648 if (ret) { 1649 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1650 return ret; 1651 } 1652 1653 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1654 pcie_gen = 3; 1655 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1656 pcie_gen = 2; 1657 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1658 pcie_gen = 1; 1659 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1660 pcie_gen = 0; 1661 1662 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1663 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1664 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1665 */ 1666 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1667 pcie_width = 6; 1668 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1669 pcie_width = 5; 1670 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1671 pcie_width = 4; 1672 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1673 pcie_width = 3; 1674 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1675 pcie_width = 2; 1676 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1677 pcie_width = 1; 1678 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1679 if (ret) { 1680 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1681 return ret; 1682 } 1683 1684 ret = smu_get_thermal_temperature_range(smu); 1685 if (ret) { 1686 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1687 return ret; 1688 } 1689 1690 ret = smu_enable_thermal_alert(smu); 1691 if (ret) { 1692 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1693 return ret; 1694 } 1695 1696 ret = smu_notify_display_change(smu); 1697 if (ret) { 1698 dev_err(adev->dev, "Failed to notify display change!\n"); 1699 return ret; 1700 } 1701 1702 /* 1703 * Set min deep sleep dce fclk with bootup value from vbios via 1704 * SetMinDeepSleepDcefclk MSG. 1705 */ 1706 ret = smu_set_min_dcef_deep_sleep(smu, 1707 smu->smu_table.boot_values.dcefclk / 100); 1708 if (ret) { 1709 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1710 return ret; 1711 } 1712 1713 /* Init wbrf support. Properly setup the notifier */ 1714 ret = smu_wbrf_init(smu); 1715 if (ret) 1716 dev_err(adev->dev, "Error during wbrf init call\n"); 1717 1718 return ret; 1719 } 1720 1721 static int smu_start_smc_engine(struct smu_context *smu) 1722 { 1723 struct amdgpu_device *adev = smu->adev; 1724 int ret = 0; 1725 1726 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1727 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1728 if (smu->ppt_funcs->load_microcode) { 1729 ret = smu->ppt_funcs->load_microcode(smu); 1730 if (ret) 1731 return ret; 1732 } 1733 } 1734 } 1735 1736 if (smu->ppt_funcs->check_fw_status) { 1737 ret = smu->ppt_funcs->check_fw_status(smu); 1738 if (ret) { 1739 dev_err(adev->dev, "SMC is not ready\n"); 1740 return ret; 1741 } 1742 } 1743 1744 /* 1745 * Send msg GetDriverIfVersion to check if the return value is equal 1746 * with DRIVER_IF_VERSION of smc header. 1747 */ 1748 ret = smu_check_fw_version(smu); 1749 if (ret) 1750 return ret; 1751 1752 return ret; 1753 } 1754 1755 static int smu_hw_init(void *handle) 1756 { 1757 int ret; 1758 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1759 struct smu_context *smu = adev->powerplay.pp_handle; 1760 1761 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1762 smu->pm_enabled = false; 1763 return 0; 1764 } 1765 1766 ret = smu_start_smc_engine(smu); 1767 if (ret) { 1768 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1769 return ret; 1770 } 1771 1772 /* 1773 * Check whether wbrf is supported. This needs to be done 1774 * before SMU setup starts since part of SMU configuration 1775 * relies on this. 1776 */ 1777 smu_wbrf_support_check(smu); 1778 1779 if (smu->is_apu) { 1780 ret = smu_set_gfx_imu_enable(smu); 1781 if (ret) 1782 return ret; 1783 smu_dpm_set_vcn_enable(smu, true); 1784 smu_dpm_set_jpeg_enable(smu, true); 1785 smu_dpm_set_vpe_enable(smu, true); 1786 smu_dpm_set_umsch_mm_enable(smu, true); 1787 smu_set_gfx_cgpg(smu, true); 1788 } 1789 1790 if (!smu->pm_enabled) 1791 return 0; 1792 1793 ret = smu_get_driver_allowed_feature_mask(smu); 1794 if (ret) 1795 return ret; 1796 1797 ret = smu_smc_hw_setup(smu); 1798 if (ret) { 1799 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1800 return ret; 1801 } 1802 1803 /* 1804 * Move maximum sustainable clock retrieving here considering 1805 * 1. It is not needed on resume(from S3). 1806 * 2. DAL settings come between .hw_init and .late_init of SMU. 1807 * And DAL needs to know the maximum sustainable clocks. Thus 1808 * it cannot be put in .late_init(). 1809 */ 1810 ret = smu_init_max_sustainable_clocks(smu); 1811 if (ret) { 1812 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1813 return ret; 1814 } 1815 1816 adev->pm.dpm_enabled = true; 1817 1818 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1819 1820 return 0; 1821 } 1822 1823 static int smu_disable_dpms(struct smu_context *smu) 1824 { 1825 struct amdgpu_device *adev = smu->adev; 1826 int ret = 0; 1827 bool use_baco = !smu->is_apu && 1828 ((amdgpu_in_reset(adev) && 1829 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1830 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1831 1832 /* 1833 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1834 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1835 */ 1836 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1837 case IP_VERSION(13, 0, 0): 1838 case IP_VERSION(13, 0, 7): 1839 case IP_VERSION(13, 0, 10): 1840 return 0; 1841 default: 1842 break; 1843 } 1844 1845 /* 1846 * For custom pptable uploading, skip the DPM features 1847 * disable process on Navi1x ASICs. 1848 * - As the gfx related features are under control of 1849 * RLC on those ASICs. RLC reinitialization will be 1850 * needed to reenable them. That will cost much more 1851 * efforts. 1852 * 1853 * - SMU firmware can handle the DPM reenablement 1854 * properly. 1855 */ 1856 if (smu->uploading_custom_pp_table) { 1857 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1858 case IP_VERSION(11, 0, 0): 1859 case IP_VERSION(11, 0, 5): 1860 case IP_VERSION(11, 0, 9): 1861 case IP_VERSION(11, 0, 7): 1862 case IP_VERSION(11, 0, 11): 1863 case IP_VERSION(11, 5, 0): 1864 case IP_VERSION(11, 0, 12): 1865 case IP_VERSION(11, 0, 13): 1866 return 0; 1867 default: 1868 break; 1869 } 1870 } 1871 1872 /* 1873 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1874 * on BACO in. Driver involvement is unnecessary. 1875 */ 1876 if (use_baco) { 1877 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1878 case IP_VERSION(11, 0, 7): 1879 case IP_VERSION(11, 0, 0): 1880 case IP_VERSION(11, 0, 5): 1881 case IP_VERSION(11, 0, 9): 1882 case IP_VERSION(13, 0, 7): 1883 return 0; 1884 default: 1885 break; 1886 } 1887 } 1888 1889 /* 1890 * For SMU 13.0.4/11 and 14.0.0, PMFW will handle the features disablement properly 1891 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1892 */ 1893 if (amdgpu_in_reset(adev) || adev->in_s0ix) { 1894 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1895 case IP_VERSION(13, 0, 4): 1896 case IP_VERSION(13, 0, 11): 1897 case IP_VERSION(14, 0, 0): 1898 return 0; 1899 default: 1900 break; 1901 } 1902 } 1903 1904 /* 1905 * For gpu reset, runpm and hibernation through BACO, 1906 * BACO feature has to be kept enabled. 1907 */ 1908 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1909 ret = smu_disable_all_features_with_exception(smu, 1910 SMU_FEATURE_BACO_BIT); 1911 if (ret) 1912 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1913 } else { 1914 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1915 if (!adev->scpm_enabled) { 1916 ret = smu_system_features_control(smu, false); 1917 if (ret) 1918 dev_err(adev->dev, "Failed to disable smu features.\n"); 1919 } 1920 } 1921 1922 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1923 * otherwise SMU will hang while interacting with RLC if RLC is halted 1924 * this is a WA for Vangogh asic which fix the SMU hang issue. 1925 */ 1926 ret = smu_notify_rlc_state(smu, false); 1927 if (ret) { 1928 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1929 return ret; 1930 } 1931 1932 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1933 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1934 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1935 adev->gfx.rlc.funcs->stop(adev); 1936 1937 return ret; 1938 } 1939 1940 static int smu_smc_hw_cleanup(struct smu_context *smu) 1941 { 1942 struct amdgpu_device *adev = smu->adev; 1943 int ret = 0; 1944 1945 smu_wbrf_fini(smu); 1946 1947 cancel_work_sync(&smu->throttling_logging_work); 1948 cancel_work_sync(&smu->interrupt_work); 1949 1950 ret = smu_disable_thermal_alert(smu); 1951 if (ret) { 1952 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1953 return ret; 1954 } 1955 1956 cancel_delayed_work_sync(&smu->swctf_delayed_work); 1957 1958 ret = smu_disable_dpms(smu); 1959 if (ret) { 1960 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1961 return ret; 1962 } 1963 1964 return 0; 1965 } 1966 1967 static int smu_hw_fini(void *handle) 1968 { 1969 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1970 struct smu_context *smu = adev->powerplay.pp_handle; 1971 1972 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 1973 return 0; 1974 1975 smu_dpm_set_vcn_enable(smu, false); 1976 smu_dpm_set_jpeg_enable(smu, false); 1977 smu_dpm_set_vpe_enable(smu, false); 1978 smu_dpm_set_umsch_mm_enable(smu, false); 1979 1980 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1981 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1982 1983 if (!smu->pm_enabled) 1984 return 0; 1985 1986 adev->pm.dpm_enabled = false; 1987 1988 return smu_smc_hw_cleanup(smu); 1989 } 1990 1991 static void smu_late_fini(void *handle) 1992 { 1993 struct amdgpu_device *adev = handle; 1994 struct smu_context *smu = adev->powerplay.pp_handle; 1995 1996 kfree(smu); 1997 } 1998 1999 static int smu_reset(struct smu_context *smu) 2000 { 2001 struct amdgpu_device *adev = smu->adev; 2002 int ret; 2003 2004 ret = smu_hw_fini(adev); 2005 if (ret) 2006 return ret; 2007 2008 ret = smu_hw_init(adev); 2009 if (ret) 2010 return ret; 2011 2012 ret = smu_late_init(adev); 2013 if (ret) 2014 return ret; 2015 2016 return 0; 2017 } 2018 2019 static int smu_suspend(void *handle) 2020 { 2021 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2022 struct smu_context *smu = adev->powerplay.pp_handle; 2023 int ret; 2024 uint64_t count; 2025 2026 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2027 return 0; 2028 2029 if (!smu->pm_enabled) 2030 return 0; 2031 2032 adev->pm.dpm_enabled = false; 2033 2034 ret = smu_smc_hw_cleanup(smu); 2035 if (ret) 2036 return ret; 2037 2038 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2039 2040 smu_set_gfx_cgpg(smu, false); 2041 2042 /* 2043 * pwfw resets entrycount when device is suspended, so we save the 2044 * last value to be used when we resume to keep it consistent 2045 */ 2046 ret = smu_get_entrycount_gfxoff(smu, &count); 2047 if (!ret) 2048 adev->gfx.gfx_off_entrycount = count; 2049 2050 return 0; 2051 } 2052 2053 static int smu_resume(void *handle) 2054 { 2055 int ret; 2056 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2057 struct smu_context *smu = adev->powerplay.pp_handle; 2058 2059 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2060 return 0; 2061 2062 if (!smu->pm_enabled) 2063 return 0; 2064 2065 dev_info(adev->dev, "SMU is resuming...\n"); 2066 2067 ret = smu_start_smc_engine(smu); 2068 if (ret) { 2069 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2070 return ret; 2071 } 2072 2073 ret = smu_smc_hw_setup(smu); 2074 if (ret) { 2075 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2076 return ret; 2077 } 2078 2079 ret = smu_set_gfx_imu_enable(smu); 2080 if (ret) 2081 return ret; 2082 2083 smu_set_gfx_cgpg(smu, true); 2084 2085 smu->disable_uclk_switch = 0; 2086 2087 adev->pm.dpm_enabled = true; 2088 2089 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2090 2091 return 0; 2092 } 2093 2094 static int smu_display_configuration_change(void *handle, 2095 const struct amd_pp_display_configuration *display_config) 2096 { 2097 struct smu_context *smu = handle; 2098 2099 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2100 return -EOPNOTSUPP; 2101 2102 if (!display_config) 2103 return -EINVAL; 2104 2105 smu_set_min_dcef_deep_sleep(smu, 2106 display_config->min_dcef_deep_sleep_set_clk / 100); 2107 2108 return 0; 2109 } 2110 2111 static int smu_set_clockgating_state(void *handle, 2112 enum amd_clockgating_state state) 2113 { 2114 return 0; 2115 } 2116 2117 static int smu_set_powergating_state(void *handle, 2118 enum amd_powergating_state state) 2119 { 2120 return 0; 2121 } 2122 2123 static int smu_enable_umd_pstate(void *handle, 2124 enum amd_dpm_forced_level *level) 2125 { 2126 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2127 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2128 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2129 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2130 2131 struct smu_context *smu = (struct smu_context*)(handle); 2132 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2133 2134 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2135 return -EINVAL; 2136 2137 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2138 /* enter umd pstate, save current level, disable gfx cg*/ 2139 if (*level & profile_mode_mask) { 2140 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2141 smu_gpo_control(smu, false); 2142 smu_gfx_ulv_control(smu, false); 2143 smu_deep_sleep_control(smu, false); 2144 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2145 } 2146 } else { 2147 /* exit umd pstate, restore level, enable gfx cg*/ 2148 if (!(*level & profile_mode_mask)) { 2149 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2150 *level = smu_dpm_ctx->saved_dpm_level; 2151 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2152 smu_deep_sleep_control(smu, true); 2153 smu_gfx_ulv_control(smu, true); 2154 smu_gpo_control(smu, true); 2155 } 2156 } 2157 2158 return 0; 2159 } 2160 2161 static int smu_bump_power_profile_mode(struct smu_context *smu, 2162 long *param, 2163 uint32_t param_size) 2164 { 2165 int ret = 0; 2166 2167 if (smu->ppt_funcs->set_power_profile_mode) 2168 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2169 2170 return ret; 2171 } 2172 2173 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2174 enum amd_dpm_forced_level level, 2175 bool skip_display_settings) 2176 { 2177 int ret = 0; 2178 int index = 0; 2179 long workload; 2180 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2181 2182 if (!skip_display_settings) { 2183 ret = smu_display_config_changed(smu); 2184 if (ret) { 2185 dev_err(smu->adev->dev, "Failed to change display config!"); 2186 return ret; 2187 } 2188 } 2189 2190 ret = smu_apply_clocks_adjust_rules(smu); 2191 if (ret) { 2192 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2193 return ret; 2194 } 2195 2196 if (!skip_display_settings) { 2197 ret = smu_notify_smc_display_config(smu); 2198 if (ret) { 2199 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2200 return ret; 2201 } 2202 } 2203 2204 if (smu_dpm_ctx->dpm_level != level) { 2205 ret = smu_asic_set_performance_level(smu, level); 2206 if (ret) { 2207 dev_err(smu->adev->dev, "Failed to set performance level!"); 2208 return ret; 2209 } 2210 2211 /* update the saved copy */ 2212 smu_dpm_ctx->dpm_level = level; 2213 } 2214 2215 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2216 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2217 index = fls(smu->workload_mask); 2218 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2219 workload = smu->workload_setting[index]; 2220 2221 if (smu->power_profile_mode != workload) 2222 smu_bump_power_profile_mode(smu, &workload, 0); 2223 } 2224 2225 return ret; 2226 } 2227 2228 static int smu_handle_task(struct smu_context *smu, 2229 enum amd_dpm_forced_level level, 2230 enum amd_pp_task task_id) 2231 { 2232 int ret = 0; 2233 2234 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2235 return -EOPNOTSUPP; 2236 2237 switch (task_id) { 2238 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2239 ret = smu_pre_display_config_changed(smu); 2240 if (ret) 2241 return ret; 2242 ret = smu_adjust_power_state_dynamic(smu, level, false); 2243 break; 2244 case AMD_PP_TASK_COMPLETE_INIT: 2245 case AMD_PP_TASK_READJUST_POWER_STATE: 2246 ret = smu_adjust_power_state_dynamic(smu, level, true); 2247 break; 2248 default: 2249 break; 2250 } 2251 2252 return ret; 2253 } 2254 2255 static int smu_handle_dpm_task(void *handle, 2256 enum amd_pp_task task_id, 2257 enum amd_pm_state_type *user_state) 2258 { 2259 struct smu_context *smu = handle; 2260 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2261 2262 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2263 2264 } 2265 2266 static int smu_switch_power_profile(void *handle, 2267 enum PP_SMC_POWER_PROFILE type, 2268 bool en) 2269 { 2270 struct smu_context *smu = handle; 2271 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2272 long workload; 2273 uint32_t index; 2274 2275 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2276 return -EOPNOTSUPP; 2277 2278 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2279 return -EINVAL; 2280 2281 if (!en) { 2282 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 2283 index = fls(smu->workload_mask); 2284 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2285 workload = smu->workload_setting[index]; 2286 } else { 2287 smu->workload_mask |= (1 << smu->workload_prority[type]); 2288 index = fls(smu->workload_mask); 2289 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2290 workload = smu->workload_setting[index]; 2291 } 2292 2293 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2294 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2295 smu_bump_power_profile_mode(smu, &workload, 0); 2296 2297 return 0; 2298 } 2299 2300 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2301 { 2302 struct smu_context *smu = handle; 2303 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2304 2305 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2306 return -EOPNOTSUPP; 2307 2308 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2309 return -EINVAL; 2310 2311 return smu_dpm_ctx->dpm_level; 2312 } 2313 2314 static int smu_force_performance_level(void *handle, 2315 enum amd_dpm_forced_level level) 2316 { 2317 struct smu_context *smu = handle; 2318 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2319 int ret = 0; 2320 2321 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2322 return -EOPNOTSUPP; 2323 2324 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2325 return -EINVAL; 2326 2327 ret = smu_enable_umd_pstate(smu, &level); 2328 if (ret) 2329 return ret; 2330 2331 ret = smu_handle_task(smu, level, 2332 AMD_PP_TASK_READJUST_POWER_STATE); 2333 2334 /* reset user dpm clock state */ 2335 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2336 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2337 smu->user_dpm_profile.clk_dependency = 0; 2338 } 2339 2340 return ret; 2341 } 2342 2343 static int smu_set_display_count(void *handle, uint32_t count) 2344 { 2345 struct smu_context *smu = handle; 2346 2347 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2348 return -EOPNOTSUPP; 2349 2350 return smu_init_display_count(smu, count); 2351 } 2352 2353 static int smu_force_smuclk_levels(struct smu_context *smu, 2354 enum smu_clk_type clk_type, 2355 uint32_t mask) 2356 { 2357 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2358 int ret = 0; 2359 2360 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2361 return -EOPNOTSUPP; 2362 2363 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2364 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2365 return -EINVAL; 2366 } 2367 2368 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2369 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2370 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2371 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2372 smu_set_user_clk_dependencies(smu, clk_type); 2373 } 2374 } 2375 2376 return ret; 2377 } 2378 2379 static int smu_force_ppclk_levels(void *handle, 2380 enum pp_clock_type type, 2381 uint32_t mask) 2382 { 2383 struct smu_context *smu = handle; 2384 enum smu_clk_type clk_type; 2385 2386 switch (type) { 2387 case PP_SCLK: 2388 clk_type = SMU_SCLK; break; 2389 case PP_MCLK: 2390 clk_type = SMU_MCLK; break; 2391 case PP_PCIE: 2392 clk_type = SMU_PCIE; break; 2393 case PP_SOCCLK: 2394 clk_type = SMU_SOCCLK; break; 2395 case PP_FCLK: 2396 clk_type = SMU_FCLK; break; 2397 case PP_DCEFCLK: 2398 clk_type = SMU_DCEFCLK; break; 2399 case PP_VCLK: 2400 clk_type = SMU_VCLK; break; 2401 case PP_VCLK1: 2402 clk_type = SMU_VCLK1; break; 2403 case PP_DCLK: 2404 clk_type = SMU_DCLK; break; 2405 case PP_DCLK1: 2406 clk_type = SMU_DCLK1; break; 2407 case OD_SCLK: 2408 clk_type = SMU_OD_SCLK; break; 2409 case OD_MCLK: 2410 clk_type = SMU_OD_MCLK; break; 2411 case OD_VDDC_CURVE: 2412 clk_type = SMU_OD_VDDC_CURVE; break; 2413 case OD_RANGE: 2414 clk_type = SMU_OD_RANGE; break; 2415 default: 2416 return -EINVAL; 2417 } 2418 2419 return smu_force_smuclk_levels(smu, clk_type, mask); 2420 } 2421 2422 /* 2423 * On system suspending or resetting, the dpm_enabled 2424 * flag will be cleared. So that those SMU services which 2425 * are not supported will be gated. 2426 * However, the mp1 state setting should still be granted 2427 * even if the dpm_enabled cleared. 2428 */ 2429 static int smu_set_mp1_state(void *handle, 2430 enum pp_mp1_state mp1_state) 2431 { 2432 struct smu_context *smu = handle; 2433 int ret = 0; 2434 2435 if (!smu->pm_enabled) 2436 return -EOPNOTSUPP; 2437 2438 if (smu->ppt_funcs && 2439 smu->ppt_funcs->set_mp1_state) 2440 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2441 2442 return ret; 2443 } 2444 2445 static int smu_set_df_cstate(void *handle, 2446 enum pp_df_cstate state) 2447 { 2448 struct smu_context *smu = handle; 2449 int ret = 0; 2450 2451 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2452 return -EOPNOTSUPP; 2453 2454 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2455 return 0; 2456 2457 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2458 if (ret) 2459 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2460 2461 return ret; 2462 } 2463 2464 int smu_write_watermarks_table(struct smu_context *smu) 2465 { 2466 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2467 return -EOPNOTSUPP; 2468 2469 return smu_set_watermarks_table(smu, NULL); 2470 } 2471 2472 static int smu_set_watermarks_for_clock_ranges(void *handle, 2473 struct pp_smu_wm_range_sets *clock_ranges) 2474 { 2475 struct smu_context *smu = handle; 2476 2477 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2478 return -EOPNOTSUPP; 2479 2480 if (smu->disable_watermark) 2481 return 0; 2482 2483 return smu_set_watermarks_table(smu, clock_ranges); 2484 } 2485 2486 int smu_set_ac_dc(struct smu_context *smu) 2487 { 2488 int ret = 0; 2489 2490 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2491 return -EOPNOTSUPP; 2492 2493 /* controlled by firmware */ 2494 if (smu->dc_controlled_by_gpio) 2495 return 0; 2496 2497 ret = smu_set_power_source(smu, 2498 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2499 SMU_POWER_SOURCE_DC); 2500 if (ret) 2501 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2502 smu->adev->pm.ac_power ? "AC" : "DC"); 2503 2504 return ret; 2505 } 2506 2507 const struct amd_ip_funcs smu_ip_funcs = { 2508 .name = "smu", 2509 .early_init = smu_early_init, 2510 .late_init = smu_late_init, 2511 .sw_init = smu_sw_init, 2512 .sw_fini = smu_sw_fini, 2513 .hw_init = smu_hw_init, 2514 .hw_fini = smu_hw_fini, 2515 .late_fini = smu_late_fini, 2516 .suspend = smu_suspend, 2517 .resume = smu_resume, 2518 .is_idle = NULL, 2519 .check_soft_reset = NULL, 2520 .wait_for_idle = NULL, 2521 .soft_reset = NULL, 2522 .set_clockgating_state = smu_set_clockgating_state, 2523 .set_powergating_state = smu_set_powergating_state, 2524 }; 2525 2526 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2527 .type = AMD_IP_BLOCK_TYPE_SMC, 2528 .major = 11, 2529 .minor = 0, 2530 .rev = 0, 2531 .funcs = &smu_ip_funcs, 2532 }; 2533 2534 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2535 .type = AMD_IP_BLOCK_TYPE_SMC, 2536 .major = 12, 2537 .minor = 0, 2538 .rev = 0, 2539 .funcs = &smu_ip_funcs, 2540 }; 2541 2542 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2543 .type = AMD_IP_BLOCK_TYPE_SMC, 2544 .major = 13, 2545 .minor = 0, 2546 .rev = 0, 2547 .funcs = &smu_ip_funcs, 2548 }; 2549 2550 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2551 .type = AMD_IP_BLOCK_TYPE_SMC, 2552 .major = 14, 2553 .minor = 0, 2554 .rev = 0, 2555 .funcs = &smu_ip_funcs, 2556 }; 2557 2558 static int smu_load_microcode(void *handle) 2559 { 2560 struct smu_context *smu = handle; 2561 struct amdgpu_device *adev = smu->adev; 2562 int ret = 0; 2563 2564 if (!smu->pm_enabled) 2565 return -EOPNOTSUPP; 2566 2567 /* This should be used for non PSP loading */ 2568 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2569 return 0; 2570 2571 if (smu->ppt_funcs->load_microcode) { 2572 ret = smu->ppt_funcs->load_microcode(smu); 2573 if (ret) { 2574 dev_err(adev->dev, "Load microcode failed\n"); 2575 return ret; 2576 } 2577 } 2578 2579 if (smu->ppt_funcs->check_fw_status) { 2580 ret = smu->ppt_funcs->check_fw_status(smu); 2581 if (ret) { 2582 dev_err(adev->dev, "SMC is not ready\n"); 2583 return ret; 2584 } 2585 } 2586 2587 return ret; 2588 } 2589 2590 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2591 { 2592 int ret = 0; 2593 2594 if (smu->ppt_funcs->set_gfx_cgpg) 2595 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2596 2597 return ret; 2598 } 2599 2600 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2601 { 2602 struct smu_context *smu = handle; 2603 int ret = 0; 2604 2605 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2606 return -EOPNOTSUPP; 2607 2608 if (!smu->ppt_funcs->set_fan_speed_rpm) 2609 return -EOPNOTSUPP; 2610 2611 if (speed == U32_MAX) 2612 return -EINVAL; 2613 2614 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2615 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2616 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2617 smu->user_dpm_profile.fan_speed_rpm = speed; 2618 2619 /* Override custom PWM setting as they cannot co-exist */ 2620 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2621 smu->user_dpm_profile.fan_speed_pwm = 0; 2622 } 2623 2624 return ret; 2625 } 2626 2627 /** 2628 * smu_get_power_limit - Request one of the SMU Power Limits 2629 * 2630 * @handle: pointer to smu context 2631 * @limit: requested limit is written back to this variable 2632 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2633 * @pp_power_type: &pp_power_type type of power 2634 * Return: 0 on success, <0 on error 2635 * 2636 */ 2637 int smu_get_power_limit(void *handle, 2638 uint32_t *limit, 2639 enum pp_power_limit_level pp_limit_level, 2640 enum pp_power_type pp_power_type) 2641 { 2642 struct smu_context *smu = handle; 2643 struct amdgpu_device *adev = smu->adev; 2644 enum smu_ppt_limit_level limit_level; 2645 uint32_t limit_type; 2646 int ret = 0; 2647 2648 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2649 return -EOPNOTSUPP; 2650 2651 switch (pp_power_type) { 2652 case PP_PWR_TYPE_SUSTAINED: 2653 limit_type = SMU_DEFAULT_PPT_LIMIT; 2654 break; 2655 case PP_PWR_TYPE_FAST: 2656 limit_type = SMU_FAST_PPT_LIMIT; 2657 break; 2658 default: 2659 return -EOPNOTSUPP; 2660 } 2661 2662 switch (pp_limit_level) { 2663 case PP_PWR_LIMIT_CURRENT: 2664 limit_level = SMU_PPT_LIMIT_CURRENT; 2665 break; 2666 case PP_PWR_LIMIT_DEFAULT: 2667 limit_level = SMU_PPT_LIMIT_DEFAULT; 2668 break; 2669 case PP_PWR_LIMIT_MAX: 2670 limit_level = SMU_PPT_LIMIT_MAX; 2671 break; 2672 case PP_PWR_LIMIT_MIN: 2673 limit_level = SMU_PPT_LIMIT_MIN; 2674 break; 2675 default: 2676 return -EOPNOTSUPP; 2677 } 2678 2679 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2680 if (smu->ppt_funcs->get_ppt_limit) 2681 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2682 } else { 2683 switch (limit_level) { 2684 case SMU_PPT_LIMIT_CURRENT: 2685 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2686 case IP_VERSION(13, 0, 2): 2687 case IP_VERSION(13, 0, 6): 2688 case IP_VERSION(11, 0, 7): 2689 case IP_VERSION(11, 0, 11): 2690 case IP_VERSION(11, 0, 12): 2691 case IP_VERSION(11, 0, 13): 2692 ret = smu_get_asic_power_limits(smu, 2693 &smu->current_power_limit, 2694 NULL, NULL, NULL); 2695 break; 2696 default: 2697 break; 2698 } 2699 *limit = smu->current_power_limit; 2700 break; 2701 case SMU_PPT_LIMIT_DEFAULT: 2702 *limit = smu->default_power_limit; 2703 break; 2704 case SMU_PPT_LIMIT_MAX: 2705 *limit = smu->max_power_limit; 2706 break; 2707 case SMU_PPT_LIMIT_MIN: 2708 *limit = smu->min_power_limit; 2709 break; 2710 default: 2711 return -EINVAL; 2712 } 2713 } 2714 2715 return ret; 2716 } 2717 2718 static int smu_set_power_limit(void *handle, uint32_t limit) 2719 { 2720 struct smu_context *smu = handle; 2721 uint32_t limit_type = limit >> 24; 2722 int ret = 0; 2723 2724 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2725 return -EOPNOTSUPP; 2726 2727 limit &= (1<<24)-1; 2728 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2729 if (smu->ppt_funcs->set_power_limit) 2730 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2731 2732 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2733 dev_err(smu->adev->dev, 2734 "New power limit (%d) is out of range [%d,%d]\n", 2735 limit, smu->min_power_limit, smu->max_power_limit); 2736 return -EINVAL; 2737 } 2738 2739 if (!limit) 2740 limit = smu->current_power_limit; 2741 2742 if (smu->ppt_funcs->set_power_limit) { 2743 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2744 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2745 smu->user_dpm_profile.power_limit = limit; 2746 } 2747 2748 return ret; 2749 } 2750 2751 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2752 { 2753 int ret = 0; 2754 2755 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2756 return -EOPNOTSUPP; 2757 2758 if (smu->ppt_funcs->print_clk_levels) 2759 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2760 2761 return ret; 2762 } 2763 2764 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2765 { 2766 enum smu_clk_type clk_type; 2767 2768 switch (type) { 2769 case PP_SCLK: 2770 clk_type = SMU_SCLK; break; 2771 case PP_MCLK: 2772 clk_type = SMU_MCLK; break; 2773 case PP_PCIE: 2774 clk_type = SMU_PCIE; break; 2775 case PP_SOCCLK: 2776 clk_type = SMU_SOCCLK; break; 2777 case PP_FCLK: 2778 clk_type = SMU_FCLK; break; 2779 case PP_DCEFCLK: 2780 clk_type = SMU_DCEFCLK; break; 2781 case PP_VCLK: 2782 clk_type = SMU_VCLK; break; 2783 case PP_VCLK1: 2784 clk_type = SMU_VCLK1; break; 2785 case PP_DCLK: 2786 clk_type = SMU_DCLK; break; 2787 case PP_DCLK1: 2788 clk_type = SMU_DCLK1; break; 2789 case OD_SCLK: 2790 clk_type = SMU_OD_SCLK; break; 2791 case OD_MCLK: 2792 clk_type = SMU_OD_MCLK; break; 2793 case OD_VDDC_CURVE: 2794 clk_type = SMU_OD_VDDC_CURVE; break; 2795 case OD_RANGE: 2796 clk_type = SMU_OD_RANGE; break; 2797 case OD_VDDGFX_OFFSET: 2798 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2799 case OD_CCLK: 2800 clk_type = SMU_OD_CCLK; break; 2801 case OD_FAN_CURVE: 2802 clk_type = SMU_OD_FAN_CURVE; break; 2803 case OD_ACOUSTIC_LIMIT: 2804 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2805 case OD_ACOUSTIC_TARGET: 2806 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2807 case OD_FAN_TARGET_TEMPERATURE: 2808 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2809 case OD_FAN_MINIMUM_PWM: 2810 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2811 default: 2812 clk_type = SMU_CLK_COUNT; break; 2813 } 2814 2815 return clk_type; 2816 } 2817 2818 static int smu_print_ppclk_levels(void *handle, 2819 enum pp_clock_type type, 2820 char *buf) 2821 { 2822 struct smu_context *smu = handle; 2823 enum smu_clk_type clk_type; 2824 2825 clk_type = smu_convert_to_smuclk(type); 2826 if (clk_type == SMU_CLK_COUNT) 2827 return -EINVAL; 2828 2829 return smu_print_smuclk_levels(smu, clk_type, buf); 2830 } 2831 2832 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2833 { 2834 struct smu_context *smu = handle; 2835 enum smu_clk_type clk_type; 2836 2837 clk_type = smu_convert_to_smuclk(type); 2838 if (clk_type == SMU_CLK_COUNT) 2839 return -EINVAL; 2840 2841 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2842 return -EOPNOTSUPP; 2843 2844 if (!smu->ppt_funcs->emit_clk_levels) 2845 return -ENOENT; 2846 2847 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2848 2849 } 2850 2851 static int smu_od_edit_dpm_table(void *handle, 2852 enum PP_OD_DPM_TABLE_COMMAND type, 2853 long *input, uint32_t size) 2854 { 2855 struct smu_context *smu = handle; 2856 int ret = 0; 2857 2858 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2859 return -EOPNOTSUPP; 2860 2861 if (smu->ppt_funcs->od_edit_dpm_table) { 2862 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2863 } 2864 2865 return ret; 2866 } 2867 2868 static int smu_read_sensor(void *handle, 2869 int sensor, 2870 void *data, 2871 int *size_arg) 2872 { 2873 struct smu_context *smu = handle; 2874 struct smu_umd_pstate_table *pstate_table = 2875 &smu->pstate_table; 2876 int ret = 0; 2877 uint32_t *size, size_val; 2878 2879 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2880 return -EOPNOTSUPP; 2881 2882 if (!data || !size_arg) 2883 return -EINVAL; 2884 2885 size_val = *size_arg; 2886 size = &size_val; 2887 2888 if (smu->ppt_funcs->read_sensor) 2889 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2890 goto unlock; 2891 2892 switch (sensor) { 2893 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2894 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2895 *size = 4; 2896 break; 2897 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2898 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2899 *size = 4; 2900 break; 2901 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2902 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2903 *size = 4; 2904 break; 2905 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2906 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2907 *size = 4; 2908 break; 2909 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2910 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2911 *size = 8; 2912 break; 2913 case AMDGPU_PP_SENSOR_UVD_POWER: 2914 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2915 *size = 4; 2916 break; 2917 case AMDGPU_PP_SENSOR_VCE_POWER: 2918 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2919 *size = 4; 2920 break; 2921 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2922 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 2923 *size = 4; 2924 break; 2925 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2926 *(uint32_t *)data = 0; 2927 *size = 4; 2928 break; 2929 default: 2930 *size = 0; 2931 ret = -EOPNOTSUPP; 2932 break; 2933 } 2934 2935 unlock: 2936 // assign uint32_t to int 2937 *size_arg = size_val; 2938 2939 return ret; 2940 } 2941 2942 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 2943 { 2944 int ret = -EOPNOTSUPP; 2945 struct smu_context *smu = handle; 2946 2947 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 2948 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 2949 2950 return ret; 2951 } 2952 2953 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 2954 { 2955 int ret = -EOPNOTSUPP; 2956 struct smu_context *smu = handle; 2957 2958 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 2959 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 2960 2961 return ret; 2962 } 2963 2964 static int smu_get_power_profile_mode(void *handle, char *buf) 2965 { 2966 struct smu_context *smu = handle; 2967 2968 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2969 !smu->ppt_funcs->get_power_profile_mode) 2970 return -EOPNOTSUPP; 2971 if (!buf) 2972 return -EINVAL; 2973 2974 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2975 } 2976 2977 static int smu_set_power_profile_mode(void *handle, 2978 long *param, 2979 uint32_t param_size) 2980 { 2981 struct smu_context *smu = handle; 2982 2983 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2984 !smu->ppt_funcs->set_power_profile_mode) 2985 return -EOPNOTSUPP; 2986 2987 return smu_bump_power_profile_mode(smu, param, param_size); 2988 } 2989 2990 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2991 { 2992 struct smu_context *smu = handle; 2993 2994 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2995 return -EOPNOTSUPP; 2996 2997 if (!smu->ppt_funcs->get_fan_control_mode) 2998 return -EOPNOTSUPP; 2999 3000 if (!fan_mode) 3001 return -EINVAL; 3002 3003 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3004 3005 return 0; 3006 } 3007 3008 static int smu_set_fan_control_mode(void *handle, u32 value) 3009 { 3010 struct smu_context *smu = handle; 3011 int ret = 0; 3012 3013 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3014 return -EOPNOTSUPP; 3015 3016 if (!smu->ppt_funcs->set_fan_control_mode) 3017 return -EOPNOTSUPP; 3018 3019 if (value == U32_MAX) 3020 return -EINVAL; 3021 3022 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3023 if (ret) 3024 goto out; 3025 3026 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3027 smu->user_dpm_profile.fan_mode = value; 3028 3029 /* reset user dpm fan speed */ 3030 if (value != AMD_FAN_CTRL_MANUAL) { 3031 smu->user_dpm_profile.fan_speed_pwm = 0; 3032 smu->user_dpm_profile.fan_speed_rpm = 0; 3033 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3034 } 3035 } 3036 3037 out: 3038 return ret; 3039 } 3040 3041 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3042 { 3043 struct smu_context *smu = handle; 3044 int ret = 0; 3045 3046 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3047 return -EOPNOTSUPP; 3048 3049 if (!smu->ppt_funcs->get_fan_speed_pwm) 3050 return -EOPNOTSUPP; 3051 3052 if (!speed) 3053 return -EINVAL; 3054 3055 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3056 3057 return ret; 3058 } 3059 3060 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3061 { 3062 struct smu_context *smu = handle; 3063 int ret = 0; 3064 3065 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3066 return -EOPNOTSUPP; 3067 3068 if (!smu->ppt_funcs->set_fan_speed_pwm) 3069 return -EOPNOTSUPP; 3070 3071 if (speed == U32_MAX) 3072 return -EINVAL; 3073 3074 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3075 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3076 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3077 smu->user_dpm_profile.fan_speed_pwm = speed; 3078 3079 /* Override custom RPM setting as they cannot co-exist */ 3080 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3081 smu->user_dpm_profile.fan_speed_rpm = 0; 3082 } 3083 3084 return ret; 3085 } 3086 3087 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3088 { 3089 struct smu_context *smu = handle; 3090 int ret = 0; 3091 3092 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3093 return -EOPNOTSUPP; 3094 3095 if (!smu->ppt_funcs->get_fan_speed_rpm) 3096 return -EOPNOTSUPP; 3097 3098 if (!speed) 3099 return -EINVAL; 3100 3101 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3102 3103 return ret; 3104 } 3105 3106 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3107 { 3108 struct smu_context *smu = handle; 3109 3110 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3111 return -EOPNOTSUPP; 3112 3113 return smu_set_min_dcef_deep_sleep(smu, clk); 3114 } 3115 3116 static int smu_get_clock_by_type_with_latency(void *handle, 3117 enum amd_pp_clock_type type, 3118 struct pp_clock_levels_with_latency *clocks) 3119 { 3120 struct smu_context *smu = handle; 3121 enum smu_clk_type clk_type; 3122 int ret = 0; 3123 3124 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3125 return -EOPNOTSUPP; 3126 3127 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3128 switch (type) { 3129 case amd_pp_sys_clock: 3130 clk_type = SMU_GFXCLK; 3131 break; 3132 case amd_pp_mem_clock: 3133 clk_type = SMU_MCLK; 3134 break; 3135 case amd_pp_dcef_clock: 3136 clk_type = SMU_DCEFCLK; 3137 break; 3138 case amd_pp_disp_clock: 3139 clk_type = SMU_DISPCLK; 3140 break; 3141 default: 3142 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3143 return -EINVAL; 3144 } 3145 3146 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3147 } 3148 3149 return ret; 3150 } 3151 3152 static int smu_display_clock_voltage_request(void *handle, 3153 struct pp_display_clock_request *clock_req) 3154 { 3155 struct smu_context *smu = handle; 3156 int ret = 0; 3157 3158 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3159 return -EOPNOTSUPP; 3160 3161 if (smu->ppt_funcs->display_clock_voltage_request) 3162 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3163 3164 return ret; 3165 } 3166 3167 3168 static int smu_display_disable_memory_clock_switch(void *handle, 3169 bool disable_memory_clock_switch) 3170 { 3171 struct smu_context *smu = handle; 3172 int ret = -EINVAL; 3173 3174 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3175 return -EOPNOTSUPP; 3176 3177 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3178 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3179 3180 return ret; 3181 } 3182 3183 static int smu_set_xgmi_pstate(void *handle, 3184 uint32_t pstate) 3185 { 3186 struct smu_context *smu = handle; 3187 int ret = 0; 3188 3189 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3190 return -EOPNOTSUPP; 3191 3192 if (smu->ppt_funcs->set_xgmi_pstate) 3193 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3194 3195 if (ret) 3196 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3197 3198 return ret; 3199 } 3200 3201 static bool smu_get_baco_capability(void *handle) 3202 { 3203 struct smu_context *smu = handle; 3204 3205 if (!smu->pm_enabled) 3206 return false; 3207 3208 if (!smu->ppt_funcs || !smu->ppt_funcs->baco_is_support) 3209 return false; 3210 3211 return smu->ppt_funcs->baco_is_support(smu); 3212 } 3213 3214 static int smu_baco_set_state(void *handle, int state) 3215 { 3216 struct smu_context *smu = handle; 3217 int ret = 0; 3218 3219 if (!smu->pm_enabled) 3220 return -EOPNOTSUPP; 3221 3222 if (state == 0) { 3223 if (smu->ppt_funcs->baco_exit) 3224 ret = smu->ppt_funcs->baco_exit(smu); 3225 } else if (state == 1) { 3226 if (smu->ppt_funcs->baco_enter) 3227 ret = smu->ppt_funcs->baco_enter(smu); 3228 } else { 3229 return -EINVAL; 3230 } 3231 3232 if (ret) 3233 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3234 (state)?"enter":"exit"); 3235 3236 return ret; 3237 } 3238 3239 bool smu_mode1_reset_is_support(struct smu_context *smu) 3240 { 3241 bool ret = false; 3242 3243 if (!smu->pm_enabled) 3244 return false; 3245 3246 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3247 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3248 3249 return ret; 3250 } 3251 3252 bool smu_mode2_reset_is_support(struct smu_context *smu) 3253 { 3254 bool ret = false; 3255 3256 if (!smu->pm_enabled) 3257 return false; 3258 3259 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3260 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3261 3262 return ret; 3263 } 3264 3265 int smu_mode1_reset(struct smu_context *smu) 3266 { 3267 int ret = 0; 3268 3269 if (!smu->pm_enabled) 3270 return -EOPNOTSUPP; 3271 3272 if (smu->ppt_funcs->mode1_reset) 3273 ret = smu->ppt_funcs->mode1_reset(smu); 3274 3275 return ret; 3276 } 3277 3278 static int smu_mode2_reset(void *handle) 3279 { 3280 struct smu_context *smu = handle; 3281 int ret = 0; 3282 3283 if (!smu->pm_enabled) 3284 return -EOPNOTSUPP; 3285 3286 if (smu->ppt_funcs->mode2_reset) 3287 ret = smu->ppt_funcs->mode2_reset(smu); 3288 3289 if (ret) 3290 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3291 3292 return ret; 3293 } 3294 3295 static int smu_enable_gfx_features(void *handle) 3296 { 3297 struct smu_context *smu = handle; 3298 int ret = 0; 3299 3300 if (!smu->pm_enabled) 3301 return -EOPNOTSUPP; 3302 3303 if (smu->ppt_funcs->enable_gfx_features) 3304 ret = smu->ppt_funcs->enable_gfx_features(smu); 3305 3306 if (ret) 3307 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3308 3309 return ret; 3310 } 3311 3312 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3313 struct pp_smu_nv_clock_table *max_clocks) 3314 { 3315 struct smu_context *smu = handle; 3316 int ret = 0; 3317 3318 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3319 return -EOPNOTSUPP; 3320 3321 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3322 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3323 3324 return ret; 3325 } 3326 3327 static int smu_get_uclk_dpm_states(void *handle, 3328 unsigned int *clock_values_in_khz, 3329 unsigned int *num_states) 3330 { 3331 struct smu_context *smu = handle; 3332 int ret = 0; 3333 3334 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3335 return -EOPNOTSUPP; 3336 3337 if (smu->ppt_funcs->get_uclk_dpm_states) 3338 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3339 3340 return ret; 3341 } 3342 3343 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3344 { 3345 struct smu_context *smu = handle; 3346 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3347 3348 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3349 return -EOPNOTSUPP; 3350 3351 if (smu->ppt_funcs->get_current_power_state) 3352 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3353 3354 return pm_state; 3355 } 3356 3357 static int smu_get_dpm_clock_table(void *handle, 3358 struct dpm_clocks *clock_table) 3359 { 3360 struct smu_context *smu = handle; 3361 int ret = 0; 3362 3363 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3364 return -EOPNOTSUPP; 3365 3366 if (smu->ppt_funcs->get_dpm_clock_table) 3367 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3368 3369 return ret; 3370 } 3371 3372 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3373 { 3374 struct smu_context *smu = handle; 3375 3376 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3377 return -EOPNOTSUPP; 3378 3379 if (!smu->ppt_funcs->get_gpu_metrics) 3380 return -EOPNOTSUPP; 3381 3382 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3383 } 3384 3385 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3386 size_t size) 3387 { 3388 struct smu_context *smu = handle; 3389 3390 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3391 return -EOPNOTSUPP; 3392 3393 if (!smu->ppt_funcs->get_pm_metrics) 3394 return -EOPNOTSUPP; 3395 3396 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3397 } 3398 3399 static int smu_enable_mgpu_fan_boost(void *handle) 3400 { 3401 struct smu_context *smu = handle; 3402 int ret = 0; 3403 3404 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3405 return -EOPNOTSUPP; 3406 3407 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3408 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3409 3410 return ret; 3411 } 3412 3413 static int smu_gfx_state_change_set(void *handle, 3414 uint32_t state) 3415 { 3416 struct smu_context *smu = handle; 3417 int ret = 0; 3418 3419 if (smu->ppt_funcs->gfx_state_change_set) 3420 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3421 3422 return ret; 3423 } 3424 3425 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3426 { 3427 int ret = 0; 3428 3429 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3430 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3431 3432 return ret; 3433 } 3434 3435 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3436 { 3437 int ret = -EOPNOTSUPP; 3438 3439 if (smu->ppt_funcs && 3440 smu->ppt_funcs->get_ecc_info) 3441 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3442 3443 return ret; 3444 3445 } 3446 3447 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3448 { 3449 struct smu_context *smu = handle; 3450 struct smu_table_context *smu_table = &smu->smu_table; 3451 struct smu_table *memory_pool = &smu_table->memory_pool; 3452 3453 if (!addr || !size) 3454 return -EINVAL; 3455 3456 *addr = NULL; 3457 *size = 0; 3458 if (memory_pool->bo) { 3459 *addr = memory_pool->cpu_addr; 3460 *size = memory_pool->size; 3461 } 3462 3463 return 0; 3464 } 3465 3466 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 3467 enum pp_xgmi_plpd_mode mode) 3468 { 3469 int ret = -EOPNOTSUPP; 3470 3471 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3472 return ret; 3473 3474 /* PLPD policy is not supported if it's NONE */ 3475 if (smu->plpd_mode == XGMI_PLPD_NONE) 3476 return ret; 3477 3478 if (smu->plpd_mode == mode) 3479 return 0; 3480 3481 if (smu->ppt_funcs && smu->ppt_funcs->select_xgmi_plpd_policy) 3482 ret = smu->ppt_funcs->select_xgmi_plpd_policy(smu, mode); 3483 3484 if (!ret) 3485 smu->plpd_mode = mode; 3486 3487 return ret; 3488 } 3489 3490 static const struct amd_pm_funcs swsmu_pm_funcs = { 3491 /* export for sysfs */ 3492 .set_fan_control_mode = smu_set_fan_control_mode, 3493 .get_fan_control_mode = smu_get_fan_control_mode, 3494 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3495 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3496 .force_clock_level = smu_force_ppclk_levels, 3497 .print_clock_levels = smu_print_ppclk_levels, 3498 .emit_clock_levels = smu_emit_ppclk_levels, 3499 .force_performance_level = smu_force_performance_level, 3500 .read_sensor = smu_read_sensor, 3501 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3502 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3503 .get_performance_level = smu_get_performance_level, 3504 .get_current_power_state = smu_get_current_power_state, 3505 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3506 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3507 .get_pp_num_states = smu_get_power_num_states, 3508 .get_pp_table = smu_sys_get_pp_table, 3509 .set_pp_table = smu_sys_set_pp_table, 3510 .switch_power_profile = smu_switch_power_profile, 3511 /* export to amdgpu */ 3512 .dispatch_tasks = smu_handle_dpm_task, 3513 .load_firmware = smu_load_microcode, 3514 .set_powergating_by_smu = smu_dpm_set_power_gate, 3515 .set_power_limit = smu_set_power_limit, 3516 .get_power_limit = smu_get_power_limit, 3517 .get_power_profile_mode = smu_get_power_profile_mode, 3518 .set_power_profile_mode = smu_set_power_profile_mode, 3519 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3520 .set_mp1_state = smu_set_mp1_state, 3521 .gfx_state_change_set = smu_gfx_state_change_set, 3522 /* export to DC */ 3523 .get_sclk = smu_get_sclk, 3524 .get_mclk = smu_get_mclk, 3525 .display_configuration_change = smu_display_configuration_change, 3526 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3527 .display_clock_voltage_request = smu_display_clock_voltage_request, 3528 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3529 .set_active_display_count = smu_set_display_count, 3530 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3531 .get_asic_baco_capability = smu_get_baco_capability, 3532 .set_asic_baco_state = smu_baco_set_state, 3533 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3534 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3535 .asic_reset_mode_2 = smu_mode2_reset, 3536 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3537 .set_df_cstate = smu_set_df_cstate, 3538 .set_xgmi_pstate = smu_set_xgmi_pstate, 3539 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3540 .get_pm_metrics = smu_sys_get_pm_metrics, 3541 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3542 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3543 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3544 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3545 .get_dpm_clock_table = smu_get_dpm_clock_table, 3546 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3547 }; 3548 3549 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3550 uint64_t event_arg) 3551 { 3552 int ret = -EINVAL; 3553 3554 if (smu->ppt_funcs->wait_for_event) 3555 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3556 3557 return ret; 3558 } 3559 3560 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3561 { 3562 3563 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3564 return -EOPNOTSUPP; 3565 3566 /* Confirm the buffer allocated is of correct size */ 3567 if (size != smu->stb_context.stb_buf_size) 3568 return -EINVAL; 3569 3570 /* 3571 * No need to lock smu mutex as we access STB directly through MMIO 3572 * and not going through SMU messaging route (for now at least). 3573 * For registers access rely on implementation internal locking. 3574 */ 3575 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3576 } 3577 3578 #if defined(CONFIG_DEBUG_FS) 3579 3580 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3581 { 3582 struct amdgpu_device *adev = filp->f_inode->i_private; 3583 struct smu_context *smu = adev->powerplay.pp_handle; 3584 unsigned char *buf; 3585 int r; 3586 3587 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3588 if (!buf) 3589 return -ENOMEM; 3590 3591 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3592 if (r) 3593 goto out; 3594 3595 filp->private_data = buf; 3596 3597 return 0; 3598 3599 out: 3600 kvfree(buf); 3601 return r; 3602 } 3603 3604 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3605 loff_t *pos) 3606 { 3607 struct amdgpu_device *adev = filp->f_inode->i_private; 3608 struct smu_context *smu = adev->powerplay.pp_handle; 3609 3610 3611 if (!filp->private_data) 3612 return -EINVAL; 3613 3614 return simple_read_from_buffer(buf, 3615 size, 3616 pos, filp->private_data, 3617 smu->stb_context.stb_buf_size); 3618 } 3619 3620 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3621 { 3622 kvfree(filp->private_data); 3623 filp->private_data = NULL; 3624 3625 return 0; 3626 } 3627 3628 /* 3629 * We have to define not only read method but also 3630 * open and release because .read takes up to PAGE_SIZE 3631 * data each time so and so is invoked multiple times. 3632 * We allocate the STB buffer in .open and release it 3633 * in .release 3634 */ 3635 static const struct file_operations smu_stb_debugfs_fops = { 3636 .owner = THIS_MODULE, 3637 .open = smu_stb_debugfs_open, 3638 .read = smu_stb_debugfs_read, 3639 .release = smu_stb_debugfs_release, 3640 .llseek = default_llseek, 3641 }; 3642 3643 #endif 3644 3645 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3646 { 3647 #if defined(CONFIG_DEBUG_FS) 3648 3649 struct smu_context *smu = adev->powerplay.pp_handle; 3650 3651 if (!smu || (!smu->stb_context.stb_buf_size)) 3652 return; 3653 3654 debugfs_create_file_size("amdgpu_smu_stb_dump", 3655 S_IRUSR, 3656 adev_to_drm(adev)->primary->debugfs_root, 3657 adev, 3658 &smu_stb_debugfs_fops, 3659 smu->stb_context.stb_buf_size); 3660 #endif 3661 } 3662 3663 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3664 { 3665 int ret = 0; 3666 3667 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3668 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3669 3670 return ret; 3671 } 3672 3673 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3674 { 3675 int ret = 0; 3676 3677 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3678 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3679 3680 return ret; 3681 } 3682 3683 int smu_send_rma_reason(struct smu_context *smu) 3684 { 3685 int ret = 0; 3686 3687 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3688 ret = smu->ppt_funcs->send_rma_reason(smu); 3689 3690 return ret; 3691 } 3692