1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 static void smu_power_profile_mode_get(struct smu_context *smu, 76 enum PP_SMC_POWER_PROFILE profile_mode); 77 static void smu_power_profile_mode_put(struct smu_context *smu, 78 enum PP_SMC_POWER_PROFILE profile_mode); 79 80 static int smu_sys_get_pp_feature_mask(void *handle, 81 char *buf) 82 { 83 struct smu_context *smu = handle; 84 85 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 86 return -EOPNOTSUPP; 87 88 return smu_get_pp_feature_mask(smu, buf); 89 } 90 91 static int smu_sys_set_pp_feature_mask(void *handle, 92 uint64_t new_mask) 93 { 94 struct smu_context *smu = handle; 95 96 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 97 return -EOPNOTSUPP; 98 99 return smu_set_pp_feature_mask(smu, new_mask); 100 } 101 102 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 103 { 104 if (!smu->ppt_funcs->set_gfx_off_residency) 105 return -EINVAL; 106 107 return smu_set_gfx_off_residency(smu, value); 108 } 109 110 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 111 { 112 if (!smu->ppt_funcs->get_gfx_off_residency) 113 return -EINVAL; 114 115 return smu_get_gfx_off_residency(smu, value); 116 } 117 118 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 119 { 120 if (!smu->ppt_funcs->get_gfx_off_entrycount) 121 return -EINVAL; 122 123 return smu_get_gfx_off_entrycount(smu, value); 124 } 125 126 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 127 { 128 if (!smu->ppt_funcs->get_gfx_off_status) 129 return -EINVAL; 130 131 *value = smu_get_gfx_off_status(smu); 132 133 return 0; 134 } 135 136 int smu_set_soft_freq_range(struct smu_context *smu, 137 enum smu_clk_type clk_type, 138 uint32_t min, 139 uint32_t max) 140 { 141 int ret = 0; 142 143 if (smu->ppt_funcs->set_soft_freq_limited_range) 144 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 145 clk_type, 146 min, 147 max, 148 false); 149 150 return ret; 151 } 152 153 int smu_get_dpm_freq_range(struct smu_context *smu, 154 enum smu_clk_type clk_type, 155 uint32_t *min, 156 uint32_t *max) 157 { 158 int ret = -ENOTSUPP; 159 160 if (!min && !max) 161 return -EINVAL; 162 163 if (smu->ppt_funcs->get_dpm_ultimate_freq) 164 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 165 clk_type, 166 min, 167 max); 168 169 return ret; 170 } 171 172 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 173 { 174 int ret = 0; 175 struct amdgpu_device *adev = smu->adev; 176 177 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 178 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 179 if (ret) 180 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 181 } 182 return ret; 183 } 184 185 static u32 smu_get_mclk(void *handle, bool low) 186 { 187 struct smu_context *smu = handle; 188 uint32_t clk_freq; 189 int ret = 0; 190 191 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 192 low ? &clk_freq : NULL, 193 !low ? &clk_freq : NULL); 194 if (ret) 195 return 0; 196 return clk_freq * 100; 197 } 198 199 static u32 smu_get_sclk(void *handle, bool low) 200 { 201 struct smu_context *smu = handle; 202 uint32_t clk_freq; 203 int ret = 0; 204 205 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 206 low ? &clk_freq : NULL, 207 !low ? &clk_freq : NULL); 208 if (ret) 209 return 0; 210 return clk_freq * 100; 211 } 212 213 static int smu_set_gfx_imu_enable(struct smu_context *smu) 214 { 215 struct amdgpu_device *adev = smu->adev; 216 217 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 218 return 0; 219 220 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 221 return 0; 222 223 return smu_set_gfx_power_up_by_imu(smu); 224 } 225 226 static bool is_vcn_enabled(struct amdgpu_device *adev) 227 { 228 int i; 229 230 for (i = 0; i < adev->num_ip_blocks; i++) { 231 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 232 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 233 !adev->ip_blocks[i].status.valid) 234 return false; 235 } 236 237 return true; 238 } 239 240 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 241 bool enable, 242 int inst) 243 { 244 struct smu_power_context *smu_power = &smu->smu_power; 245 struct smu_power_gate *power_gate = &smu_power->power_gate; 246 int ret = 0; 247 248 /* 249 * don't poweron vcn/jpeg when they are skipped. 250 */ 251 if (!is_vcn_enabled(smu->adev)) 252 return 0; 253 254 if (!smu->ppt_funcs->dpm_set_vcn_enable) 255 return 0; 256 257 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable) 258 return 0; 259 260 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst); 261 if (!ret) 262 atomic_set(&power_gate->vcn_gated[inst], !enable); 263 264 return ret; 265 } 266 267 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 268 bool enable) 269 { 270 struct smu_power_context *smu_power = &smu->smu_power; 271 struct smu_power_gate *power_gate = &smu_power->power_gate; 272 int ret = 0; 273 274 if (!is_vcn_enabled(smu->adev)) 275 return 0; 276 277 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 278 return 0; 279 280 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 281 return 0; 282 283 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 284 if (!ret) 285 atomic_set(&power_gate->jpeg_gated, !enable); 286 287 return ret; 288 } 289 290 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 291 bool enable) 292 { 293 struct smu_power_context *smu_power = &smu->smu_power; 294 struct smu_power_gate *power_gate = &smu_power->power_gate; 295 int ret = 0; 296 297 if (!smu->ppt_funcs->dpm_set_vpe_enable) 298 return 0; 299 300 if (atomic_read(&power_gate->vpe_gated) ^ enable) 301 return 0; 302 303 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 304 if (!ret) 305 atomic_set(&power_gate->vpe_gated, !enable); 306 307 return ret; 308 } 309 310 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 311 bool enable) 312 { 313 struct smu_power_context *smu_power = &smu->smu_power; 314 struct smu_power_gate *power_gate = &smu_power->power_gate; 315 int ret = 0; 316 317 if (!smu->adev->enable_umsch_mm) 318 return 0; 319 320 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 321 return 0; 322 323 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 324 return 0; 325 326 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 327 if (!ret) 328 atomic_set(&power_gate->umsch_mm_gated, !enable); 329 330 return ret; 331 } 332 333 static int smu_set_mall_enable(struct smu_context *smu) 334 { 335 int ret = 0; 336 337 if (!smu->ppt_funcs->set_mall_enable) 338 return 0; 339 340 ret = smu->ppt_funcs->set_mall_enable(smu); 341 342 return ret; 343 } 344 345 /** 346 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 347 * 348 * @handle: smu_context pointer 349 * @block_type: the IP block to power gate/ungate 350 * @gate: to power gate if true, ungate otherwise 351 * @inst: the instance of the IP block to power gate/ungate 352 * 353 * This API uses no smu->mutex lock protection due to: 354 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 355 * This is guarded to be race condition free by the caller. 356 * 2. Or get called on user setting request of power_dpm_force_performance_level. 357 * Under this case, the smu->mutex lock protection is already enforced on 358 * the parent API smu_force_performance_level of the call path. 359 */ 360 static int smu_dpm_set_power_gate(void *handle, 361 uint32_t block_type, 362 bool gate, 363 int inst) 364 { 365 struct smu_context *smu = handle; 366 int ret = 0; 367 368 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 369 dev_WARN(smu->adev->dev, 370 "SMU uninitialized but power %s requested for %u!\n", 371 gate ? "gate" : "ungate", block_type); 372 return -EOPNOTSUPP; 373 } 374 375 switch (block_type) { 376 /* 377 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 378 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 379 */ 380 case AMD_IP_BLOCK_TYPE_UVD: 381 case AMD_IP_BLOCK_TYPE_VCN: 382 ret = smu_dpm_set_vcn_enable(smu, !gate, inst); 383 if (ret) 384 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n", 385 gate ? "gate" : "ungate", inst); 386 break; 387 case AMD_IP_BLOCK_TYPE_GFX: 388 ret = smu_gfx_off_control(smu, gate); 389 if (ret) 390 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 391 gate ? "enable" : "disable"); 392 break; 393 case AMD_IP_BLOCK_TYPE_SDMA: 394 ret = smu_powergate_sdma(smu, gate); 395 if (ret) 396 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 397 gate ? "gate" : "ungate"); 398 break; 399 case AMD_IP_BLOCK_TYPE_JPEG: 400 ret = smu_dpm_set_jpeg_enable(smu, !gate); 401 if (ret) 402 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 403 gate ? "gate" : "ungate"); 404 break; 405 case AMD_IP_BLOCK_TYPE_VPE: 406 ret = smu_dpm_set_vpe_enable(smu, !gate); 407 if (ret) 408 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 409 gate ? "gate" : "ungate"); 410 break; 411 default: 412 dev_err(smu->adev->dev, "Unsupported block type!\n"); 413 return -EINVAL; 414 } 415 416 return ret; 417 } 418 419 /** 420 * smu_set_user_clk_dependencies - set user profile clock dependencies 421 * 422 * @smu: smu_context pointer 423 * @clk: enum smu_clk_type type 424 * 425 * Enable/Disable the clock dependency for the @clk type. 426 */ 427 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 428 { 429 if (smu->adev->in_suspend) 430 return; 431 432 if (clk == SMU_MCLK) { 433 smu->user_dpm_profile.clk_dependency = 0; 434 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 435 } else if (clk == SMU_FCLK) { 436 /* MCLK takes precedence over FCLK */ 437 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 438 return; 439 440 smu->user_dpm_profile.clk_dependency = 0; 441 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 442 } else if (clk == SMU_SOCCLK) { 443 /* MCLK takes precedence over SOCCLK */ 444 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 445 return; 446 447 smu->user_dpm_profile.clk_dependency = 0; 448 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 449 } else 450 /* Add clk dependencies here, if any */ 451 return; 452 } 453 454 /** 455 * smu_restore_dpm_user_profile - reinstate user dpm profile 456 * 457 * @smu: smu_context pointer 458 * 459 * Restore the saved user power configurations include power limit, 460 * clock frequencies, fan control mode and fan speed. 461 */ 462 static void smu_restore_dpm_user_profile(struct smu_context *smu) 463 { 464 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 465 int ret = 0; 466 467 if (!smu->adev->in_suspend) 468 return; 469 470 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 471 return; 472 473 /* Enable restore flag */ 474 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 475 476 /* set the user dpm power limit */ 477 if (smu->user_dpm_profile.power_limit) { 478 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 479 if (ret) 480 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 481 } 482 483 /* set the user dpm clock configurations */ 484 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 485 enum smu_clk_type clk_type; 486 487 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 488 /* 489 * Iterate over smu clk type and force the saved user clk 490 * configs, skip if clock dependency is enabled 491 */ 492 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 493 smu->user_dpm_profile.clk_mask[clk_type]) { 494 ret = smu_force_smuclk_levels(smu, clk_type, 495 smu->user_dpm_profile.clk_mask[clk_type]); 496 if (ret) 497 dev_err(smu->adev->dev, 498 "Failed to set clock type = %d\n", clk_type); 499 } 500 } 501 } 502 503 /* set the user dpm fan configurations */ 504 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 505 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 506 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 507 if (ret != -EOPNOTSUPP) { 508 smu->user_dpm_profile.fan_speed_pwm = 0; 509 smu->user_dpm_profile.fan_speed_rpm = 0; 510 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 511 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 512 } 513 514 if (smu->user_dpm_profile.fan_speed_pwm) { 515 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 516 if (ret != -EOPNOTSUPP) 517 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 518 } 519 520 if (smu->user_dpm_profile.fan_speed_rpm) { 521 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 522 if (ret != -EOPNOTSUPP) 523 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 524 } 525 } 526 527 /* Restore user customized OD settings */ 528 if (smu->user_dpm_profile.user_od) { 529 if (smu->ppt_funcs->restore_user_od_settings) { 530 ret = smu->ppt_funcs->restore_user_od_settings(smu); 531 if (ret) 532 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 533 } 534 } 535 536 /* Disable restore flag */ 537 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 538 } 539 540 static int smu_get_power_num_states(void *handle, 541 struct pp_states_info *state_info) 542 { 543 if (!state_info) 544 return -EINVAL; 545 546 /* not support power state */ 547 memset(state_info, 0, sizeof(struct pp_states_info)); 548 state_info->nums = 1; 549 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 550 551 return 0; 552 } 553 554 bool is_support_sw_smu(struct amdgpu_device *adev) 555 { 556 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 557 if (adev->asic_type == CHIP_VEGA20) 558 return false; 559 560 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && 561 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) 562 return true; 563 564 return false; 565 } 566 567 bool is_support_cclk_dpm(struct amdgpu_device *adev) 568 { 569 struct smu_context *smu = adev->powerplay.pp_handle; 570 571 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 572 return false; 573 574 return true; 575 } 576 577 578 static int smu_sys_get_pp_table(void *handle, 579 char **table) 580 { 581 struct smu_context *smu = handle; 582 struct smu_table_context *smu_table = &smu->smu_table; 583 584 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 585 return -EOPNOTSUPP; 586 587 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 588 return -EINVAL; 589 590 if (smu_table->hardcode_pptable) 591 *table = smu_table->hardcode_pptable; 592 else 593 *table = smu_table->power_play_table; 594 595 return smu_table->power_play_table_size; 596 } 597 598 static int smu_sys_set_pp_table(void *handle, 599 const char *buf, 600 size_t size) 601 { 602 struct smu_context *smu = handle; 603 struct smu_table_context *smu_table = &smu->smu_table; 604 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 605 int ret = 0; 606 607 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 608 return -EOPNOTSUPP; 609 610 if (header->usStructureSize != size) { 611 dev_err(smu->adev->dev, "pp table size not matched !\n"); 612 return -EIO; 613 } 614 615 if (!smu_table->hardcode_pptable) { 616 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 617 if (!smu_table->hardcode_pptable) 618 return -ENOMEM; 619 } 620 621 memcpy(smu_table->hardcode_pptable, buf, size); 622 smu_table->power_play_table = smu_table->hardcode_pptable; 623 smu_table->power_play_table_size = size; 624 625 /* 626 * Special hw_fini action(for Navi1x, the DPMs disablement will be 627 * skipped) may be needed for custom pptable uploading. 628 */ 629 smu->uploading_custom_pp_table = true; 630 631 ret = smu_reset(smu); 632 if (ret) 633 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 634 635 smu->uploading_custom_pp_table = false; 636 637 return ret; 638 } 639 640 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 641 { 642 struct smu_feature *feature = &smu->smu_feature; 643 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 644 int ret = 0; 645 646 /* 647 * With SCPM enabled, the allowed featuremasks setting(via 648 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 649 * That means there is no way to let PMFW knows the settings below. 650 * Thus, we just assume all the features are allowed under 651 * such scenario. 652 */ 653 if (smu->adev->scpm_enabled) { 654 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 655 return 0; 656 } 657 658 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 659 660 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 661 SMU_FEATURE_MAX/32); 662 if (ret) 663 return ret; 664 665 bitmap_or(feature->allowed, feature->allowed, 666 (unsigned long *)allowed_feature_mask, 667 feature->feature_num); 668 669 return ret; 670 } 671 672 static int smu_set_funcs(struct amdgpu_device *adev) 673 { 674 struct smu_context *smu = adev->powerplay.pp_handle; 675 676 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 677 smu->od_enabled = true; 678 679 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 680 case IP_VERSION(11, 0, 0): 681 case IP_VERSION(11, 0, 5): 682 case IP_VERSION(11, 0, 9): 683 navi10_set_ppt_funcs(smu); 684 break; 685 case IP_VERSION(11, 0, 7): 686 case IP_VERSION(11, 0, 11): 687 case IP_VERSION(11, 0, 12): 688 case IP_VERSION(11, 0, 13): 689 sienna_cichlid_set_ppt_funcs(smu); 690 break; 691 case IP_VERSION(12, 0, 0): 692 case IP_VERSION(12, 0, 1): 693 renoir_set_ppt_funcs(smu); 694 break; 695 case IP_VERSION(11, 5, 0): 696 vangogh_set_ppt_funcs(smu); 697 break; 698 case IP_VERSION(13, 0, 1): 699 case IP_VERSION(13, 0, 3): 700 case IP_VERSION(13, 0, 8): 701 yellow_carp_set_ppt_funcs(smu); 702 break; 703 case IP_VERSION(13, 0, 4): 704 case IP_VERSION(13, 0, 11): 705 smu_v13_0_4_set_ppt_funcs(smu); 706 break; 707 case IP_VERSION(13, 0, 5): 708 smu_v13_0_5_set_ppt_funcs(smu); 709 break; 710 case IP_VERSION(11, 0, 8): 711 cyan_skillfish_set_ppt_funcs(smu); 712 break; 713 case IP_VERSION(11, 0, 2): 714 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 715 arcturus_set_ppt_funcs(smu); 716 /* OD is not supported on Arcturus */ 717 smu->od_enabled = false; 718 break; 719 case IP_VERSION(13, 0, 2): 720 aldebaran_set_ppt_funcs(smu); 721 /* Enable pp_od_clk_voltage node */ 722 smu->od_enabled = true; 723 break; 724 case IP_VERSION(13, 0, 0): 725 case IP_VERSION(13, 0, 10): 726 smu_v13_0_0_set_ppt_funcs(smu); 727 break; 728 case IP_VERSION(13, 0, 6): 729 case IP_VERSION(13, 0, 14): 730 case IP_VERSION(13, 0, 12): 731 smu_v13_0_6_set_ppt_funcs(smu); 732 /* Enable pp_od_clk_voltage node */ 733 smu->od_enabled = true; 734 break; 735 case IP_VERSION(13, 0, 7): 736 smu_v13_0_7_set_ppt_funcs(smu); 737 break; 738 case IP_VERSION(14, 0, 0): 739 case IP_VERSION(14, 0, 1): 740 case IP_VERSION(14, 0, 4): 741 smu_v14_0_0_set_ppt_funcs(smu); 742 break; 743 case IP_VERSION(14, 0, 2): 744 case IP_VERSION(14, 0, 3): 745 smu_v14_0_2_set_ppt_funcs(smu); 746 break; 747 default: 748 return -EINVAL; 749 } 750 751 return 0; 752 } 753 754 static int smu_early_init(struct amdgpu_ip_block *ip_block) 755 { 756 struct amdgpu_device *adev = ip_block->adev; 757 struct smu_context *smu; 758 int r; 759 760 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 761 if (!smu) 762 return -ENOMEM; 763 764 smu->adev = adev; 765 smu->pm_enabled = !!amdgpu_dpm; 766 smu->is_apu = false; 767 smu->smu_baco.state = SMU_BACO_STATE_NONE; 768 smu->smu_baco.platform_support = false; 769 smu->smu_baco.maco_support = false; 770 smu->user_dpm_profile.fan_mode = -1; 771 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN; 772 773 mutex_init(&smu->message_lock); 774 775 adev->powerplay.pp_handle = smu; 776 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 777 778 r = smu_set_funcs(adev); 779 if (r) 780 return r; 781 return smu_init_microcode(smu); 782 } 783 784 static int smu_set_default_dpm_table(struct smu_context *smu) 785 { 786 struct amdgpu_device *adev = smu->adev; 787 struct smu_power_context *smu_power = &smu->smu_power; 788 struct smu_power_gate *power_gate = &smu_power->power_gate; 789 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i; 790 int ret = 0; 791 792 if (!smu->ppt_funcs->set_default_dpm_table) 793 return 0; 794 795 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 796 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 797 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]); 798 } 799 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 800 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 801 802 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 803 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 804 ret = smu_dpm_set_vcn_enable(smu, true, i); 805 if (ret) 806 return ret; 807 } 808 } 809 810 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 811 ret = smu_dpm_set_jpeg_enable(smu, true); 812 if (ret) 813 goto err_out; 814 } 815 816 ret = smu->ppt_funcs->set_default_dpm_table(smu); 817 if (ret) 818 dev_err(smu->adev->dev, 819 "Failed to setup default dpm clock tables!\n"); 820 821 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 822 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 823 err_out: 824 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 825 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 826 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i); 827 } 828 829 return ret; 830 } 831 832 static int smu_apply_default_config_table_settings(struct smu_context *smu) 833 { 834 struct amdgpu_device *adev = smu->adev; 835 int ret = 0; 836 837 ret = smu_get_default_config_table_settings(smu, 838 &adev->pm.config_table); 839 if (ret) 840 return ret; 841 842 return smu_set_config_table(smu, &adev->pm.config_table); 843 } 844 845 static int smu_late_init(struct amdgpu_ip_block *ip_block) 846 { 847 struct amdgpu_device *adev = ip_block->adev; 848 struct smu_context *smu = adev->powerplay.pp_handle; 849 int ret = 0; 850 851 smu_set_fine_grain_gfx_freq_parameters(smu); 852 853 if (!smu->pm_enabled) 854 return 0; 855 856 ret = smu_post_init(smu); 857 if (ret) { 858 dev_err(adev->dev, "Failed to post smu init!\n"); 859 return ret; 860 } 861 862 /* 863 * Explicitly notify PMFW the power mode the system in. Since 864 * the PMFW may boot the ASIC with a different mode. 865 * For those supporting ACDC switch via gpio, PMFW will 866 * handle the switch automatically. Driver involvement 867 * is unnecessary. 868 */ 869 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 870 smu_set_ac_dc(smu); 871 872 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 873 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 874 return 0; 875 876 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 877 ret = smu_set_default_od_settings(smu); 878 if (ret) { 879 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 880 return ret; 881 } 882 } 883 884 ret = smu_populate_umd_state_clk(smu); 885 if (ret) { 886 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 887 return ret; 888 } 889 890 ret = smu_get_asic_power_limits(smu, 891 &smu->current_power_limit, 892 &smu->default_power_limit, 893 &smu->max_power_limit, 894 &smu->min_power_limit); 895 if (ret) { 896 dev_err(adev->dev, "Failed to get asic power limits!\n"); 897 return ret; 898 } 899 900 if (!amdgpu_sriov_vf(adev)) 901 smu_get_unique_id(smu); 902 903 smu_get_fan_parameters(smu); 904 905 smu_handle_task(smu, 906 smu->smu_dpm.dpm_level, 907 AMD_PP_TASK_COMPLETE_INIT); 908 909 ret = smu_apply_default_config_table_settings(smu); 910 if (ret && (ret != -EOPNOTSUPP)) { 911 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 912 return ret; 913 } 914 915 smu_restore_dpm_user_profile(smu); 916 917 return 0; 918 } 919 920 static int smu_init_fb_allocations(struct smu_context *smu) 921 { 922 struct amdgpu_device *adev = smu->adev; 923 struct smu_table_context *smu_table = &smu->smu_table; 924 struct smu_table *tables = smu_table->tables; 925 struct smu_table *driver_table = &(smu_table->driver_table); 926 uint32_t max_table_size = 0; 927 int ret, i; 928 929 /* VRAM allocation for tool table */ 930 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 931 ret = amdgpu_bo_create_kernel(adev, 932 tables[SMU_TABLE_PMSTATUSLOG].size, 933 tables[SMU_TABLE_PMSTATUSLOG].align, 934 tables[SMU_TABLE_PMSTATUSLOG].domain, 935 &tables[SMU_TABLE_PMSTATUSLOG].bo, 936 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 937 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 938 if (ret) { 939 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 940 return ret; 941 } 942 } 943 944 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 945 /* VRAM allocation for driver table */ 946 for (i = 0; i < SMU_TABLE_COUNT; i++) { 947 if (tables[i].size == 0) 948 continue; 949 950 /* If one of the tables has VRAM domain restriction, keep it in 951 * VRAM 952 */ 953 if ((tables[i].domain & 954 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 955 AMDGPU_GEM_DOMAIN_VRAM) 956 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 957 958 if (i == SMU_TABLE_PMSTATUSLOG) 959 continue; 960 961 if (max_table_size < tables[i].size) 962 max_table_size = tables[i].size; 963 } 964 965 driver_table->size = max_table_size; 966 driver_table->align = PAGE_SIZE; 967 968 ret = amdgpu_bo_create_kernel(adev, 969 driver_table->size, 970 driver_table->align, 971 driver_table->domain, 972 &driver_table->bo, 973 &driver_table->mc_address, 974 &driver_table->cpu_addr); 975 if (ret) { 976 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 977 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 978 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 979 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 980 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 981 } 982 983 return ret; 984 } 985 986 static int smu_fini_fb_allocations(struct smu_context *smu) 987 { 988 struct smu_table_context *smu_table = &smu->smu_table; 989 struct smu_table *tables = smu_table->tables; 990 struct smu_table *driver_table = &(smu_table->driver_table); 991 992 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 993 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 994 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 995 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 996 997 amdgpu_bo_free_kernel(&driver_table->bo, 998 &driver_table->mc_address, 999 &driver_table->cpu_addr); 1000 1001 return 0; 1002 } 1003 1004 /** 1005 * smu_alloc_memory_pool - allocate memory pool in the system memory 1006 * 1007 * @smu: amdgpu_device pointer 1008 * 1009 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 1010 * and DramLogSetDramAddr can notify it changed. 1011 * 1012 * Returns 0 on success, error on failure. 1013 */ 1014 static int smu_alloc_memory_pool(struct smu_context *smu) 1015 { 1016 struct amdgpu_device *adev = smu->adev; 1017 struct smu_table_context *smu_table = &smu->smu_table; 1018 struct smu_table *memory_pool = &smu_table->memory_pool; 1019 uint64_t pool_size = smu->pool_size; 1020 int ret = 0; 1021 1022 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1023 return ret; 1024 1025 memory_pool->size = pool_size; 1026 memory_pool->align = PAGE_SIZE; 1027 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 1028 1029 switch (pool_size) { 1030 case SMU_MEMORY_POOL_SIZE_256_MB: 1031 case SMU_MEMORY_POOL_SIZE_512_MB: 1032 case SMU_MEMORY_POOL_SIZE_1_GB: 1033 case SMU_MEMORY_POOL_SIZE_2_GB: 1034 ret = amdgpu_bo_create_kernel(adev, 1035 memory_pool->size, 1036 memory_pool->align, 1037 memory_pool->domain, 1038 &memory_pool->bo, 1039 &memory_pool->mc_address, 1040 &memory_pool->cpu_addr); 1041 if (ret) 1042 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1043 break; 1044 default: 1045 break; 1046 } 1047 1048 return ret; 1049 } 1050 1051 static int smu_free_memory_pool(struct smu_context *smu) 1052 { 1053 struct smu_table_context *smu_table = &smu->smu_table; 1054 struct smu_table *memory_pool = &smu_table->memory_pool; 1055 1056 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1057 return 0; 1058 1059 amdgpu_bo_free_kernel(&memory_pool->bo, 1060 &memory_pool->mc_address, 1061 &memory_pool->cpu_addr); 1062 1063 memset(memory_pool, 0, sizeof(struct smu_table)); 1064 1065 return 0; 1066 } 1067 1068 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1069 { 1070 struct smu_table_context *smu_table = &smu->smu_table; 1071 struct smu_table *dummy_read_1_table = 1072 &smu_table->dummy_read_1_table; 1073 struct amdgpu_device *adev = smu->adev; 1074 int ret = 0; 1075 1076 if (!dummy_read_1_table->size) 1077 return 0; 1078 1079 ret = amdgpu_bo_create_kernel(adev, 1080 dummy_read_1_table->size, 1081 dummy_read_1_table->align, 1082 dummy_read_1_table->domain, 1083 &dummy_read_1_table->bo, 1084 &dummy_read_1_table->mc_address, 1085 &dummy_read_1_table->cpu_addr); 1086 if (ret) 1087 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1088 1089 return ret; 1090 } 1091 1092 static void smu_free_dummy_read_table(struct smu_context *smu) 1093 { 1094 struct smu_table_context *smu_table = &smu->smu_table; 1095 struct smu_table *dummy_read_1_table = 1096 &smu_table->dummy_read_1_table; 1097 1098 1099 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1100 &dummy_read_1_table->mc_address, 1101 &dummy_read_1_table->cpu_addr); 1102 1103 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1104 } 1105 1106 static int smu_smc_table_sw_init(struct smu_context *smu) 1107 { 1108 int ret; 1109 1110 /** 1111 * Create smu_table structure, and init smc tables such as 1112 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1113 */ 1114 ret = smu_init_smc_tables(smu); 1115 if (ret) { 1116 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1117 return ret; 1118 } 1119 1120 /** 1121 * Create smu_power_context structure, and allocate smu_dpm_context and 1122 * context size to fill the smu_power_context data. 1123 */ 1124 ret = smu_init_power(smu); 1125 if (ret) { 1126 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1127 return ret; 1128 } 1129 1130 /* 1131 * allocate vram bos to store smc table contents. 1132 */ 1133 ret = smu_init_fb_allocations(smu); 1134 if (ret) 1135 return ret; 1136 1137 ret = smu_alloc_memory_pool(smu); 1138 if (ret) 1139 return ret; 1140 1141 ret = smu_alloc_dummy_read_table(smu); 1142 if (ret) 1143 return ret; 1144 1145 ret = smu_i2c_init(smu); 1146 if (ret) 1147 return ret; 1148 1149 return 0; 1150 } 1151 1152 static int smu_smc_table_sw_fini(struct smu_context *smu) 1153 { 1154 int ret; 1155 1156 smu_i2c_fini(smu); 1157 1158 smu_free_dummy_read_table(smu); 1159 1160 ret = smu_free_memory_pool(smu); 1161 if (ret) 1162 return ret; 1163 1164 ret = smu_fini_fb_allocations(smu); 1165 if (ret) 1166 return ret; 1167 1168 ret = smu_fini_power(smu); 1169 if (ret) { 1170 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1171 return ret; 1172 } 1173 1174 ret = smu_fini_smc_tables(smu); 1175 if (ret) { 1176 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1177 return ret; 1178 } 1179 1180 return 0; 1181 } 1182 1183 static void smu_throttling_logging_work_fn(struct work_struct *work) 1184 { 1185 struct smu_context *smu = container_of(work, struct smu_context, 1186 throttling_logging_work); 1187 1188 smu_log_thermal_throttling(smu); 1189 } 1190 1191 static void smu_interrupt_work_fn(struct work_struct *work) 1192 { 1193 struct smu_context *smu = container_of(work, struct smu_context, 1194 interrupt_work); 1195 1196 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1197 smu->ppt_funcs->interrupt_work(smu); 1198 } 1199 1200 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1201 { 1202 struct smu_context *smu = 1203 container_of(work, struct smu_context, swctf_delayed_work.work); 1204 struct smu_temperature_range *range = 1205 &smu->thermal_range; 1206 struct amdgpu_device *adev = smu->adev; 1207 uint32_t hotspot_tmp, size; 1208 1209 /* 1210 * If the hotspot temperature is confirmed as below SW CTF setting point 1211 * after the delay enforced, nothing will be done. 1212 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1213 */ 1214 if (range->software_shutdown_temp && 1215 smu->ppt_funcs->read_sensor && 1216 !smu->ppt_funcs->read_sensor(smu, 1217 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1218 &hotspot_tmp, 1219 &size) && 1220 hotspot_tmp / 1000 < range->software_shutdown_temp) 1221 return; 1222 1223 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1224 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1225 orderly_poweroff(true); 1226 } 1227 1228 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1229 { 1230 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1231 struct smu_dpm_policy_ctxt *policy_ctxt; 1232 struct smu_dpm_policy *policy; 1233 1234 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1235 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1236 if (policy) 1237 policy->current_level = XGMI_PLPD_DEFAULT; 1238 return; 1239 } 1240 1241 /* PMFW put PLPD into default policy after enabling the feature */ 1242 if (smu_feature_is_enabled(smu, 1243 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1244 if (policy) 1245 policy->current_level = XGMI_PLPD_DEFAULT; 1246 } else { 1247 policy_ctxt = dpm_ctxt->dpm_policies; 1248 if (policy_ctxt) 1249 policy_ctxt->policy_mask &= 1250 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1251 } 1252 } 1253 1254 static bool smu_is_workload_profile_available(struct smu_context *smu, 1255 u32 profile) 1256 { 1257 if (profile >= PP_SMC_POWER_PROFILE_COUNT) 1258 return false; 1259 return smu->workload_map && smu->workload_map[profile].valid_mapping; 1260 } 1261 1262 static void smu_init_power_profile(struct smu_context *smu) 1263 { 1264 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) { 1265 if (smu->is_apu || 1266 !smu_is_workload_profile_available( 1267 smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D)) 1268 smu->power_profile_mode = 1269 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1270 else 1271 smu->power_profile_mode = 1272 PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1273 } 1274 smu_power_profile_mode_get(smu, smu->power_profile_mode); 1275 } 1276 1277 static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1278 { 1279 struct amdgpu_device *adev = ip_block->adev; 1280 struct smu_context *smu = adev->powerplay.pp_handle; 1281 int i, ret; 1282 1283 smu->pool_size = adev->pm.smu_prv_buffer_size; 1284 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1285 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1286 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1287 1288 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1289 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1290 atomic64_set(&smu->throttle_int_counter, 0); 1291 smu->watermarks_bitmap = 0; 1292 1293 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1294 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1); 1295 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1296 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1297 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1298 1299 smu_init_power_profile(smu); 1300 smu->display_config = &adev->pm.pm_display_cfg; 1301 1302 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1303 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1304 1305 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1306 smu_swctf_delayed_work_handler); 1307 1308 ret = smu_smc_table_sw_init(smu); 1309 if (ret) { 1310 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1311 return ret; 1312 } 1313 1314 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1315 ret = smu_get_vbios_bootup_values(smu); 1316 if (ret) { 1317 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1318 return ret; 1319 } 1320 1321 ret = smu_init_pptable_microcode(smu); 1322 if (ret) { 1323 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1324 return ret; 1325 } 1326 1327 ret = smu_register_irq_handler(smu); 1328 if (ret) { 1329 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1330 return ret; 1331 } 1332 1333 /* If there is no way to query fan control mode, fan control is not supported */ 1334 if (!smu->ppt_funcs->get_fan_control_mode) 1335 smu->adev->pm.no_fan = true; 1336 1337 return 0; 1338 } 1339 1340 static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1341 { 1342 struct amdgpu_device *adev = ip_block->adev; 1343 struct smu_context *smu = adev->powerplay.pp_handle; 1344 int ret; 1345 1346 ret = smu_smc_table_sw_fini(smu); 1347 if (ret) { 1348 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1349 return ret; 1350 } 1351 1352 if (smu->custom_profile_params) { 1353 kfree(smu->custom_profile_params); 1354 smu->custom_profile_params = NULL; 1355 } 1356 1357 smu_fini_microcode(smu); 1358 1359 return 0; 1360 } 1361 1362 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1363 { 1364 struct amdgpu_device *adev = smu->adev; 1365 struct smu_temperature_range *range = 1366 &smu->thermal_range; 1367 int ret = 0; 1368 1369 if (!smu->ppt_funcs->get_thermal_temperature_range) 1370 return 0; 1371 1372 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1373 if (ret) 1374 return ret; 1375 1376 adev->pm.dpm.thermal.min_temp = range->min; 1377 adev->pm.dpm.thermal.max_temp = range->max; 1378 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1379 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1380 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1381 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1382 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1383 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1384 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1385 1386 return ret; 1387 } 1388 1389 /** 1390 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1391 * 1392 * @smu: smu_context pointer 1393 * 1394 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1395 * Returns 0 on success, error on failure. 1396 */ 1397 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1398 { 1399 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1400 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1401 struct amdgpu_device *adev = smu->adev; 1402 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1403 uint64_t start, end; 1404 int ret, i, j; 1405 1406 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1407 if (ret) { 1408 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1409 return ret; 1410 } 1411 1412 /* 1413 * The exclusion ranges array we got might be filled with holes and duplicate 1414 * entries. For example: 1415 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1416 * We need to do some sortups to eliminate those holes and duplicate entries. 1417 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1418 */ 1419 for (i = 0; i < num_of_wbrf_ranges; i++) { 1420 start = wifi_bands[i].start; 1421 end = wifi_bands[i].end; 1422 1423 /* get the last valid entry to fill the intermediate hole */ 1424 if (!start && !end) { 1425 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1426 if (wifi_bands[j].start && wifi_bands[j].end) 1427 break; 1428 1429 /* no valid entry left */ 1430 if (j <= i) 1431 break; 1432 1433 start = wifi_bands[i].start = wifi_bands[j].start; 1434 end = wifi_bands[i].end = wifi_bands[j].end; 1435 wifi_bands[j].start = 0; 1436 wifi_bands[j].end = 0; 1437 num_of_wbrf_ranges = j; 1438 } 1439 1440 /* eliminate duplicate entries */ 1441 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1442 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1443 wifi_bands[j].start = 0; 1444 wifi_bands[j].end = 0; 1445 } 1446 } 1447 } 1448 1449 /* Send the sorted wifi_bands to PMFW */ 1450 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1451 /* Try to set the wifi_bands again */ 1452 if (unlikely(ret == -EBUSY)) { 1453 mdelay(5); 1454 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1455 } 1456 1457 return ret; 1458 } 1459 1460 /** 1461 * smu_wbrf_event_handler - handle notify events 1462 * 1463 * @nb: notifier block 1464 * @action: event type 1465 * @_arg: event data 1466 * 1467 * Calls relevant amdgpu function in response to wbrf event 1468 * notification from kernel. 1469 */ 1470 static int smu_wbrf_event_handler(struct notifier_block *nb, 1471 unsigned long action, void *_arg) 1472 { 1473 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1474 1475 switch (action) { 1476 case WBRF_CHANGED: 1477 schedule_delayed_work(&smu->wbrf_delayed_work, 1478 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1479 break; 1480 default: 1481 return NOTIFY_DONE; 1482 } 1483 1484 return NOTIFY_OK; 1485 } 1486 1487 /** 1488 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1489 * 1490 * @work: struct work_struct pointer 1491 * 1492 * Flood is over and driver will consume the latest exclusion ranges. 1493 */ 1494 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1495 { 1496 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1497 1498 smu_wbrf_handle_exclusion_ranges(smu); 1499 } 1500 1501 /** 1502 * smu_wbrf_support_check - check wbrf support 1503 * 1504 * @smu: smu_context pointer 1505 * 1506 * Verifies the ACPI interface whether wbrf is supported. 1507 */ 1508 static void smu_wbrf_support_check(struct smu_context *smu) 1509 { 1510 struct amdgpu_device *adev = smu->adev; 1511 1512 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1513 acpi_amd_wbrf_supported_consumer(adev->dev); 1514 1515 if (smu->wbrf_supported) 1516 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1517 } 1518 1519 /** 1520 * smu_wbrf_init - init driver wbrf support 1521 * 1522 * @smu: smu_context pointer 1523 * 1524 * Verifies the AMD ACPI interfaces and registers with the wbrf 1525 * notifier chain if wbrf feature is supported. 1526 * Returns 0 on success, error on failure. 1527 */ 1528 static int smu_wbrf_init(struct smu_context *smu) 1529 { 1530 int ret; 1531 1532 if (!smu->wbrf_supported) 1533 return 0; 1534 1535 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1536 1537 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1538 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1539 if (ret) 1540 return ret; 1541 1542 /* 1543 * Some wifiband exclusion ranges may be already there 1544 * before our driver loaded. To make sure our driver 1545 * is awared of those exclusion ranges. 1546 */ 1547 schedule_delayed_work(&smu->wbrf_delayed_work, 1548 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1549 1550 return 0; 1551 } 1552 1553 /** 1554 * smu_wbrf_fini - tear down driver wbrf support 1555 * 1556 * @smu: smu_context pointer 1557 * 1558 * Unregisters with the wbrf notifier chain. 1559 */ 1560 static void smu_wbrf_fini(struct smu_context *smu) 1561 { 1562 if (!smu->wbrf_supported) 1563 return; 1564 1565 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1566 1567 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1568 } 1569 1570 static int smu_smc_hw_setup(struct smu_context *smu) 1571 { 1572 struct smu_feature *feature = &smu->smu_feature; 1573 struct amdgpu_device *adev = smu->adev; 1574 uint8_t pcie_gen = 0, pcie_width = 0; 1575 uint64_t features_supported; 1576 int ret = 0; 1577 1578 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1579 case IP_VERSION(11, 0, 7): 1580 case IP_VERSION(11, 0, 11): 1581 case IP_VERSION(11, 5, 0): 1582 case IP_VERSION(11, 0, 12): 1583 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1584 dev_info(adev->dev, "dpm has been enabled\n"); 1585 ret = smu_system_features_control(smu, true); 1586 if (ret) 1587 dev_err(adev->dev, "Failed system features control!\n"); 1588 return ret; 1589 } 1590 break; 1591 default: 1592 break; 1593 } 1594 1595 ret = smu_init_display_count(smu, 0); 1596 if (ret) { 1597 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1598 return ret; 1599 } 1600 1601 ret = smu_set_driver_table_location(smu); 1602 if (ret) { 1603 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1604 return ret; 1605 } 1606 1607 /* 1608 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1609 */ 1610 ret = smu_set_tool_table_location(smu); 1611 if (ret) { 1612 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1613 return ret; 1614 } 1615 1616 /* 1617 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1618 * pool location. 1619 */ 1620 ret = smu_notify_memory_pool_location(smu); 1621 if (ret) { 1622 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1623 return ret; 1624 } 1625 1626 /* 1627 * It is assumed the pptable used before runpm is same as 1628 * the one used afterwards. Thus, we can reuse the stored 1629 * copy and do not need to resetup the pptable again. 1630 */ 1631 if (!adev->in_runpm) { 1632 ret = smu_setup_pptable(smu); 1633 if (ret) { 1634 dev_err(adev->dev, "Failed to setup pptable!\n"); 1635 return ret; 1636 } 1637 } 1638 1639 /* smu_dump_pptable(smu); */ 1640 1641 /* 1642 * With SCPM enabled, PSP is responsible for the PPTable transferring 1643 * (to SMU). Driver involvement is not needed and permitted. 1644 */ 1645 if (!adev->scpm_enabled) { 1646 /* 1647 * Copy pptable bo in the vram to smc with SMU MSGs such as 1648 * SetDriverDramAddr and TransferTableDram2Smu. 1649 */ 1650 ret = smu_write_pptable(smu); 1651 if (ret) { 1652 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1653 return ret; 1654 } 1655 } 1656 1657 /* issue Run*Btc msg */ 1658 ret = smu_run_btc(smu); 1659 if (ret) 1660 return ret; 1661 1662 /* Enable UclkShadow on wbrf supported */ 1663 if (smu->wbrf_supported) { 1664 ret = smu_enable_uclk_shadow(smu, true); 1665 if (ret) { 1666 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1667 return ret; 1668 } 1669 } 1670 1671 /* 1672 * With SCPM enabled, these actions(and relevant messages) are 1673 * not needed and permitted. 1674 */ 1675 if (!adev->scpm_enabled) { 1676 ret = smu_feature_set_allowed_mask(smu); 1677 if (ret) { 1678 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1679 return ret; 1680 } 1681 } 1682 1683 ret = smu_system_features_control(smu, true); 1684 if (ret) { 1685 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1686 return ret; 1687 } 1688 1689 smu_init_xgmi_plpd_mode(smu); 1690 1691 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1692 if (ret) { 1693 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1694 return ret; 1695 } 1696 bitmap_copy(feature->supported, 1697 (unsigned long *)&features_supported, 1698 feature->feature_num); 1699 1700 if (!smu_is_dpm_running(smu)) 1701 dev_info(adev->dev, "dpm has been disabled\n"); 1702 1703 /* 1704 * Set initialized values (get from vbios) to dpm tables context such as 1705 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1706 * type of clks. 1707 */ 1708 ret = smu_set_default_dpm_table(smu); 1709 if (ret) { 1710 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1711 return ret; 1712 } 1713 1714 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) 1715 pcie_gen = 4; 1716 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1717 pcie_gen = 3; 1718 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1719 pcie_gen = 2; 1720 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1721 pcie_gen = 1; 1722 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1723 pcie_gen = 0; 1724 1725 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1726 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1727 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1728 */ 1729 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) 1730 pcie_width = 7; 1731 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1732 pcie_width = 6; 1733 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1734 pcie_width = 5; 1735 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1736 pcie_width = 4; 1737 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1738 pcie_width = 3; 1739 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1740 pcie_width = 2; 1741 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1742 pcie_width = 1; 1743 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1744 if (ret) { 1745 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1746 return ret; 1747 } 1748 1749 ret = smu_get_thermal_temperature_range(smu); 1750 if (ret) { 1751 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1752 return ret; 1753 } 1754 1755 ret = smu_enable_thermal_alert(smu); 1756 if (ret) { 1757 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1758 return ret; 1759 } 1760 1761 ret = smu_notify_display_change(smu); 1762 if (ret) { 1763 dev_err(adev->dev, "Failed to notify display change!\n"); 1764 return ret; 1765 } 1766 1767 /* 1768 * Set min deep sleep dce fclk with bootup value from vbios via 1769 * SetMinDeepSleepDcefclk MSG. 1770 */ 1771 ret = smu_set_min_dcef_deep_sleep(smu, 1772 smu->smu_table.boot_values.dcefclk / 100); 1773 if (ret) { 1774 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1775 return ret; 1776 } 1777 1778 /* Init wbrf support. Properly setup the notifier */ 1779 ret = smu_wbrf_init(smu); 1780 if (ret) 1781 dev_err(adev->dev, "Error during wbrf init call\n"); 1782 1783 return ret; 1784 } 1785 1786 static int smu_start_smc_engine(struct smu_context *smu) 1787 { 1788 struct amdgpu_device *adev = smu->adev; 1789 int ret = 0; 1790 1791 smu->smc_fw_state = SMU_FW_INIT; 1792 1793 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1794 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1795 if (smu->ppt_funcs->load_microcode) { 1796 ret = smu->ppt_funcs->load_microcode(smu); 1797 if (ret) 1798 return ret; 1799 } 1800 } 1801 } 1802 1803 if (smu->ppt_funcs->check_fw_status) { 1804 ret = smu->ppt_funcs->check_fw_status(smu); 1805 if (ret) { 1806 dev_err(adev->dev, "SMC is not ready\n"); 1807 return ret; 1808 } 1809 } 1810 1811 /* 1812 * Send msg GetDriverIfVersion to check if the return value is equal 1813 * with DRIVER_IF_VERSION of smc header. 1814 */ 1815 ret = smu_check_fw_version(smu); 1816 if (ret) 1817 return ret; 1818 1819 return ret; 1820 } 1821 1822 static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1823 { 1824 int i, ret; 1825 struct amdgpu_device *adev = ip_block->adev; 1826 struct smu_context *smu = adev->powerplay.pp_handle; 1827 1828 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1829 smu->pm_enabled = false; 1830 return 0; 1831 } 1832 1833 ret = smu_start_smc_engine(smu); 1834 if (ret) { 1835 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1836 return ret; 1837 } 1838 1839 /* 1840 * Check whether wbrf is supported. This needs to be done 1841 * before SMU setup starts since part of SMU configuration 1842 * relies on this. 1843 */ 1844 smu_wbrf_support_check(smu); 1845 1846 if (smu->is_apu) { 1847 ret = smu_set_gfx_imu_enable(smu); 1848 if (ret) 1849 return ret; 1850 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1851 smu_dpm_set_vcn_enable(smu, true, i); 1852 smu_dpm_set_jpeg_enable(smu, true); 1853 smu_dpm_set_vpe_enable(smu, true); 1854 smu_dpm_set_umsch_mm_enable(smu, true); 1855 smu_set_mall_enable(smu); 1856 smu_set_gfx_cgpg(smu, true); 1857 } 1858 1859 if (!smu->pm_enabled) 1860 return 0; 1861 1862 ret = smu_get_driver_allowed_feature_mask(smu); 1863 if (ret) 1864 return ret; 1865 1866 ret = smu_smc_hw_setup(smu); 1867 if (ret) { 1868 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1869 return ret; 1870 } 1871 1872 /* 1873 * Move maximum sustainable clock retrieving here considering 1874 * 1. It is not needed on resume(from S3). 1875 * 2. DAL settings come between .hw_init and .late_init of SMU. 1876 * And DAL needs to know the maximum sustainable clocks. Thus 1877 * it cannot be put in .late_init(). 1878 */ 1879 ret = smu_init_max_sustainable_clocks(smu); 1880 if (ret) { 1881 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1882 return ret; 1883 } 1884 1885 adev->pm.dpm_enabled = true; 1886 1887 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1888 1889 return 0; 1890 } 1891 1892 static int smu_disable_dpms(struct smu_context *smu) 1893 { 1894 struct amdgpu_device *adev = smu->adev; 1895 int ret = 0; 1896 bool use_baco = !smu->is_apu && 1897 ((amdgpu_in_reset(adev) && 1898 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1899 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1900 1901 /* 1902 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1903 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1904 */ 1905 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1906 case IP_VERSION(13, 0, 0): 1907 case IP_VERSION(13, 0, 7): 1908 case IP_VERSION(13, 0, 10): 1909 case IP_VERSION(14, 0, 2): 1910 case IP_VERSION(14, 0, 3): 1911 return 0; 1912 default: 1913 break; 1914 } 1915 1916 /* 1917 * For custom pptable uploading, skip the DPM features 1918 * disable process on Navi1x ASICs. 1919 * - As the gfx related features are under control of 1920 * RLC on those ASICs. RLC reinitialization will be 1921 * needed to reenable them. That will cost much more 1922 * efforts. 1923 * 1924 * - SMU firmware can handle the DPM reenablement 1925 * properly. 1926 */ 1927 if (smu->uploading_custom_pp_table) { 1928 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1929 case IP_VERSION(11, 0, 0): 1930 case IP_VERSION(11, 0, 5): 1931 case IP_VERSION(11, 0, 9): 1932 case IP_VERSION(11, 0, 7): 1933 case IP_VERSION(11, 0, 11): 1934 case IP_VERSION(11, 5, 0): 1935 case IP_VERSION(11, 0, 12): 1936 case IP_VERSION(11, 0, 13): 1937 return 0; 1938 default: 1939 break; 1940 } 1941 } 1942 1943 /* 1944 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1945 * on BACO in. Driver involvement is unnecessary. 1946 */ 1947 if (use_baco) { 1948 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1949 case IP_VERSION(11, 0, 7): 1950 case IP_VERSION(11, 0, 0): 1951 case IP_VERSION(11, 0, 5): 1952 case IP_VERSION(11, 0, 9): 1953 case IP_VERSION(13, 0, 7): 1954 return 0; 1955 default: 1956 break; 1957 } 1958 } 1959 1960 /* 1961 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 1962 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1963 */ 1964 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 1965 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 1966 return 0; 1967 1968 /* 1969 * For gpu reset, runpm and hibernation through BACO, 1970 * BACO feature has to be kept enabled. 1971 */ 1972 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1973 ret = smu_disable_all_features_with_exception(smu, 1974 SMU_FEATURE_BACO_BIT); 1975 if (ret) 1976 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1977 } else { 1978 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1979 if (!adev->scpm_enabled) { 1980 ret = smu_system_features_control(smu, false); 1981 if (ret) 1982 dev_err(adev->dev, "Failed to disable smu features.\n"); 1983 } 1984 } 1985 1986 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1987 * otherwise SMU will hang while interacting with RLC if RLC is halted 1988 * this is a WA for Vangogh asic which fix the SMU hang issue. 1989 */ 1990 ret = smu_notify_rlc_state(smu, false); 1991 if (ret) { 1992 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1993 return ret; 1994 } 1995 1996 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1997 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1998 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1999 adev->gfx.rlc.funcs->stop(adev); 2000 2001 return ret; 2002 } 2003 2004 static int smu_smc_hw_cleanup(struct smu_context *smu) 2005 { 2006 struct amdgpu_device *adev = smu->adev; 2007 int ret = 0; 2008 2009 smu_wbrf_fini(smu); 2010 2011 cancel_work_sync(&smu->throttling_logging_work); 2012 cancel_work_sync(&smu->interrupt_work); 2013 2014 ret = smu_disable_thermal_alert(smu); 2015 if (ret) { 2016 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 2017 return ret; 2018 } 2019 2020 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2021 2022 ret = smu_disable_dpms(smu); 2023 if (ret) { 2024 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2025 return ret; 2026 } 2027 2028 return 0; 2029 } 2030 2031 static int smu_reset_mp1_state(struct smu_context *smu) 2032 { 2033 struct amdgpu_device *adev = smu->adev; 2034 int ret = 0; 2035 2036 if ((!adev->in_runpm) && (!adev->in_suspend) && 2037 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 2038 IP_VERSION(13, 0, 10) && 2039 !amdgpu_device_has_display_hardware(adev)) 2040 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2041 2042 return ret; 2043 } 2044 2045 static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2046 { 2047 struct amdgpu_device *adev = ip_block->adev; 2048 struct smu_context *smu = adev->powerplay.pp_handle; 2049 int i, ret; 2050 2051 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2052 return 0; 2053 2054 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 2055 smu_dpm_set_vcn_enable(smu, false, i); 2056 smu_dpm_set_jpeg_enable(smu, false); 2057 smu_dpm_set_vpe_enable(smu, false); 2058 smu_dpm_set_umsch_mm_enable(smu, false); 2059 2060 adev->vcn.cur_state = AMD_PG_STATE_GATE; 2061 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2062 2063 if (!smu->pm_enabled) 2064 return 0; 2065 2066 adev->pm.dpm_enabled = false; 2067 2068 ret = smu_smc_hw_cleanup(smu); 2069 if (ret) 2070 return ret; 2071 2072 ret = smu_reset_mp1_state(smu); 2073 if (ret) 2074 return ret; 2075 2076 return 0; 2077 } 2078 2079 static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2080 { 2081 struct amdgpu_device *adev = ip_block->adev; 2082 struct smu_context *smu = adev->powerplay.pp_handle; 2083 2084 kfree(smu); 2085 } 2086 2087 static int smu_reset(struct smu_context *smu) 2088 { 2089 struct amdgpu_device *adev = smu->adev; 2090 struct amdgpu_ip_block *ip_block; 2091 int ret; 2092 2093 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2094 if (!ip_block) 2095 return -EINVAL; 2096 2097 ret = smu_hw_fini(ip_block); 2098 if (ret) 2099 return ret; 2100 2101 ret = smu_hw_init(ip_block); 2102 if (ret) 2103 return ret; 2104 2105 ret = smu_late_init(ip_block); 2106 if (ret) 2107 return ret; 2108 2109 return 0; 2110 } 2111 2112 static int smu_suspend(struct amdgpu_ip_block *ip_block) 2113 { 2114 struct amdgpu_device *adev = ip_block->adev; 2115 struct smu_context *smu = adev->powerplay.pp_handle; 2116 int ret; 2117 uint64_t count; 2118 2119 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2120 return 0; 2121 2122 if (!smu->pm_enabled) 2123 return 0; 2124 2125 adev->pm.dpm_enabled = false; 2126 2127 ret = smu_smc_hw_cleanup(smu); 2128 if (ret) 2129 return ret; 2130 2131 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2132 2133 smu_set_gfx_cgpg(smu, false); 2134 2135 /* 2136 * pwfw resets entrycount when device is suspended, so we save the 2137 * last value to be used when we resume to keep it consistent 2138 */ 2139 ret = smu_get_entrycount_gfxoff(smu, &count); 2140 if (!ret) 2141 adev->gfx.gfx_off_entrycount = count; 2142 2143 /* clear this on suspend so it will get reprogrammed on resume */ 2144 smu->workload_mask = 0; 2145 2146 return 0; 2147 } 2148 2149 static int smu_resume(struct amdgpu_ip_block *ip_block) 2150 { 2151 int ret; 2152 struct amdgpu_device *adev = ip_block->adev; 2153 struct smu_context *smu = adev->powerplay.pp_handle; 2154 2155 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2156 return 0; 2157 2158 if (!smu->pm_enabled) 2159 return 0; 2160 2161 dev_info(adev->dev, "SMU is resuming...\n"); 2162 2163 ret = smu_start_smc_engine(smu); 2164 if (ret) { 2165 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2166 return ret; 2167 } 2168 2169 ret = smu_smc_hw_setup(smu); 2170 if (ret) { 2171 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2172 return ret; 2173 } 2174 2175 ret = smu_set_gfx_imu_enable(smu); 2176 if (ret) 2177 return ret; 2178 2179 smu_set_gfx_cgpg(smu, true); 2180 2181 smu->disable_uclk_switch = 0; 2182 2183 adev->pm.dpm_enabled = true; 2184 2185 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2186 2187 return 0; 2188 } 2189 2190 static int smu_display_configuration_change(void *handle, 2191 const struct amd_pp_display_configuration *display_config) 2192 { 2193 struct smu_context *smu = handle; 2194 2195 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2196 return -EOPNOTSUPP; 2197 2198 if (!display_config) 2199 return -EINVAL; 2200 2201 smu_set_min_dcef_deep_sleep(smu, 2202 display_config->min_dcef_deep_sleep_set_clk / 100); 2203 2204 return 0; 2205 } 2206 2207 static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2208 enum amd_clockgating_state state) 2209 { 2210 return 0; 2211 } 2212 2213 static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block, 2214 enum amd_powergating_state state) 2215 { 2216 return 0; 2217 } 2218 2219 static int smu_enable_umd_pstate(void *handle, 2220 enum amd_dpm_forced_level *level) 2221 { 2222 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2223 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2224 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2225 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2226 2227 struct smu_context *smu = (struct smu_context*)(handle); 2228 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2229 2230 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2231 return -EINVAL; 2232 2233 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2234 /* enter umd pstate, save current level, disable gfx cg*/ 2235 if (*level & profile_mode_mask) { 2236 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2237 smu_gpo_control(smu, false); 2238 smu_gfx_ulv_control(smu, false); 2239 smu_deep_sleep_control(smu, false); 2240 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2241 } 2242 } else { 2243 /* exit umd pstate, restore level, enable gfx cg*/ 2244 if (!(*level & profile_mode_mask)) { 2245 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2246 *level = smu_dpm_ctx->saved_dpm_level; 2247 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2248 smu_deep_sleep_control(smu, true); 2249 smu_gfx_ulv_control(smu, true); 2250 smu_gpo_control(smu, true); 2251 } 2252 } 2253 2254 return 0; 2255 } 2256 2257 static int smu_bump_power_profile_mode(struct smu_context *smu, 2258 long *custom_params, 2259 u32 custom_params_max_idx) 2260 { 2261 u32 workload_mask = 0; 2262 int i, ret = 0; 2263 2264 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2265 if (smu->workload_refcount[i]) 2266 workload_mask |= 1 << i; 2267 } 2268 2269 if (smu->workload_mask == workload_mask) 2270 return 0; 2271 2272 if (smu->ppt_funcs->set_power_profile_mode) 2273 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask, 2274 custom_params, 2275 custom_params_max_idx); 2276 2277 if (!ret) 2278 smu->workload_mask = workload_mask; 2279 2280 return ret; 2281 } 2282 2283 static void smu_power_profile_mode_get(struct smu_context *smu, 2284 enum PP_SMC_POWER_PROFILE profile_mode) 2285 { 2286 smu->workload_refcount[profile_mode]++; 2287 } 2288 2289 static void smu_power_profile_mode_put(struct smu_context *smu, 2290 enum PP_SMC_POWER_PROFILE profile_mode) 2291 { 2292 if (smu->workload_refcount[profile_mode]) 2293 smu->workload_refcount[profile_mode]--; 2294 } 2295 2296 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2297 enum amd_dpm_forced_level level, 2298 bool skip_display_settings) 2299 { 2300 int ret = 0; 2301 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2302 2303 if (!skip_display_settings) { 2304 ret = smu_display_config_changed(smu); 2305 if (ret) { 2306 dev_err(smu->adev->dev, "Failed to change display config!"); 2307 return ret; 2308 } 2309 } 2310 2311 ret = smu_apply_clocks_adjust_rules(smu); 2312 if (ret) { 2313 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2314 return ret; 2315 } 2316 2317 if (!skip_display_settings) { 2318 ret = smu_notify_smc_display_config(smu); 2319 if (ret) { 2320 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2321 return ret; 2322 } 2323 } 2324 2325 if (smu_dpm_ctx->dpm_level != level) { 2326 ret = smu_asic_set_performance_level(smu, level); 2327 if (ret) { 2328 dev_err(smu->adev->dev, "Failed to set performance level!"); 2329 return ret; 2330 } 2331 2332 /* update the saved copy */ 2333 smu_dpm_ctx->dpm_level = level; 2334 } 2335 2336 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2337 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2338 smu_bump_power_profile_mode(smu, NULL, 0); 2339 2340 return ret; 2341 } 2342 2343 static int smu_handle_task(struct smu_context *smu, 2344 enum amd_dpm_forced_level level, 2345 enum amd_pp_task task_id) 2346 { 2347 int ret = 0; 2348 2349 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2350 return -EOPNOTSUPP; 2351 2352 switch (task_id) { 2353 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2354 ret = smu_pre_display_config_changed(smu); 2355 if (ret) 2356 return ret; 2357 ret = smu_adjust_power_state_dynamic(smu, level, false); 2358 break; 2359 case AMD_PP_TASK_COMPLETE_INIT: 2360 ret = smu_adjust_power_state_dynamic(smu, level, true); 2361 break; 2362 case AMD_PP_TASK_READJUST_POWER_STATE: 2363 ret = smu_adjust_power_state_dynamic(smu, level, true); 2364 break; 2365 default: 2366 break; 2367 } 2368 2369 return ret; 2370 } 2371 2372 static int smu_handle_dpm_task(void *handle, 2373 enum amd_pp_task task_id, 2374 enum amd_pm_state_type *user_state) 2375 { 2376 struct smu_context *smu = handle; 2377 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2378 2379 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2380 2381 } 2382 2383 static int smu_switch_power_profile(void *handle, 2384 enum PP_SMC_POWER_PROFILE type, 2385 bool enable) 2386 { 2387 struct smu_context *smu = handle; 2388 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2389 int ret; 2390 2391 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2392 return -EOPNOTSUPP; 2393 2394 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2395 return -EINVAL; 2396 2397 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2398 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2399 if (enable) 2400 smu_power_profile_mode_get(smu, type); 2401 else 2402 smu_power_profile_mode_put(smu, type); 2403 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2404 if (ret) { 2405 if (enable) 2406 smu_power_profile_mode_put(smu, type); 2407 else 2408 smu_power_profile_mode_get(smu, type); 2409 return ret; 2410 } 2411 } 2412 2413 return 0; 2414 } 2415 2416 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2417 { 2418 struct smu_context *smu = handle; 2419 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2420 2421 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2422 return -EOPNOTSUPP; 2423 2424 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2425 return -EINVAL; 2426 2427 return smu_dpm_ctx->dpm_level; 2428 } 2429 2430 static int smu_force_performance_level(void *handle, 2431 enum amd_dpm_forced_level level) 2432 { 2433 struct smu_context *smu = handle; 2434 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2435 int ret = 0; 2436 2437 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2438 return -EOPNOTSUPP; 2439 2440 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2441 return -EINVAL; 2442 2443 ret = smu_enable_umd_pstate(smu, &level); 2444 if (ret) 2445 return ret; 2446 2447 ret = smu_handle_task(smu, level, 2448 AMD_PP_TASK_READJUST_POWER_STATE); 2449 2450 /* reset user dpm clock state */ 2451 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2452 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2453 smu->user_dpm_profile.clk_dependency = 0; 2454 } 2455 2456 return ret; 2457 } 2458 2459 static int smu_set_display_count(void *handle, uint32_t count) 2460 { 2461 struct smu_context *smu = handle; 2462 2463 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2464 return -EOPNOTSUPP; 2465 2466 return smu_init_display_count(smu, count); 2467 } 2468 2469 static int smu_force_smuclk_levels(struct smu_context *smu, 2470 enum smu_clk_type clk_type, 2471 uint32_t mask) 2472 { 2473 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2474 int ret = 0; 2475 2476 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2477 return -EOPNOTSUPP; 2478 2479 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2480 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2481 return -EINVAL; 2482 } 2483 2484 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2485 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2486 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2487 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2488 smu_set_user_clk_dependencies(smu, clk_type); 2489 } 2490 } 2491 2492 return ret; 2493 } 2494 2495 static int smu_force_ppclk_levels(void *handle, 2496 enum pp_clock_type type, 2497 uint32_t mask) 2498 { 2499 struct smu_context *smu = handle; 2500 enum smu_clk_type clk_type; 2501 2502 switch (type) { 2503 case PP_SCLK: 2504 clk_type = SMU_SCLK; break; 2505 case PP_MCLK: 2506 clk_type = SMU_MCLK; break; 2507 case PP_PCIE: 2508 clk_type = SMU_PCIE; break; 2509 case PP_SOCCLK: 2510 clk_type = SMU_SOCCLK; break; 2511 case PP_FCLK: 2512 clk_type = SMU_FCLK; break; 2513 case PP_DCEFCLK: 2514 clk_type = SMU_DCEFCLK; break; 2515 case PP_VCLK: 2516 clk_type = SMU_VCLK; break; 2517 case PP_VCLK1: 2518 clk_type = SMU_VCLK1; break; 2519 case PP_DCLK: 2520 clk_type = SMU_DCLK; break; 2521 case PP_DCLK1: 2522 clk_type = SMU_DCLK1; break; 2523 case OD_SCLK: 2524 clk_type = SMU_OD_SCLK; break; 2525 case OD_MCLK: 2526 clk_type = SMU_OD_MCLK; break; 2527 case OD_VDDC_CURVE: 2528 clk_type = SMU_OD_VDDC_CURVE; break; 2529 case OD_RANGE: 2530 clk_type = SMU_OD_RANGE; break; 2531 default: 2532 return -EINVAL; 2533 } 2534 2535 return smu_force_smuclk_levels(smu, clk_type, mask); 2536 } 2537 2538 /* 2539 * On system suspending or resetting, the dpm_enabled 2540 * flag will be cleared. So that those SMU services which 2541 * are not supported will be gated. 2542 * However, the mp1 state setting should still be granted 2543 * even if the dpm_enabled cleared. 2544 */ 2545 static int smu_set_mp1_state(void *handle, 2546 enum pp_mp1_state mp1_state) 2547 { 2548 struct smu_context *smu = handle; 2549 int ret = 0; 2550 2551 if (!smu->pm_enabled) 2552 return -EOPNOTSUPP; 2553 2554 if (smu->ppt_funcs && 2555 smu->ppt_funcs->set_mp1_state) 2556 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2557 2558 return ret; 2559 } 2560 2561 static int smu_set_df_cstate(void *handle, 2562 enum pp_df_cstate state) 2563 { 2564 struct smu_context *smu = handle; 2565 int ret = 0; 2566 2567 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2568 return -EOPNOTSUPP; 2569 2570 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2571 return 0; 2572 2573 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2574 if (ret) 2575 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2576 2577 return ret; 2578 } 2579 2580 int smu_write_watermarks_table(struct smu_context *smu) 2581 { 2582 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2583 return -EOPNOTSUPP; 2584 2585 return smu_set_watermarks_table(smu, NULL); 2586 } 2587 2588 static int smu_set_watermarks_for_clock_ranges(void *handle, 2589 struct pp_smu_wm_range_sets *clock_ranges) 2590 { 2591 struct smu_context *smu = handle; 2592 2593 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2594 return -EOPNOTSUPP; 2595 2596 if (smu->disable_watermark) 2597 return 0; 2598 2599 return smu_set_watermarks_table(smu, clock_ranges); 2600 } 2601 2602 int smu_set_ac_dc(struct smu_context *smu) 2603 { 2604 int ret = 0; 2605 2606 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2607 return -EOPNOTSUPP; 2608 2609 /* controlled by firmware */ 2610 if (smu->dc_controlled_by_gpio) 2611 return 0; 2612 2613 ret = smu_set_power_source(smu, 2614 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2615 SMU_POWER_SOURCE_DC); 2616 if (ret) 2617 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2618 smu->adev->pm.ac_power ? "AC" : "DC"); 2619 2620 return ret; 2621 } 2622 2623 const struct amd_ip_funcs smu_ip_funcs = { 2624 .name = "smu", 2625 .early_init = smu_early_init, 2626 .late_init = smu_late_init, 2627 .sw_init = smu_sw_init, 2628 .sw_fini = smu_sw_fini, 2629 .hw_init = smu_hw_init, 2630 .hw_fini = smu_hw_fini, 2631 .late_fini = smu_late_fini, 2632 .suspend = smu_suspend, 2633 .resume = smu_resume, 2634 .is_idle = NULL, 2635 .check_soft_reset = NULL, 2636 .wait_for_idle = NULL, 2637 .soft_reset = NULL, 2638 .set_clockgating_state = smu_set_clockgating_state, 2639 .set_powergating_state = smu_set_powergating_state, 2640 }; 2641 2642 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2643 .type = AMD_IP_BLOCK_TYPE_SMC, 2644 .major = 11, 2645 .minor = 0, 2646 .rev = 0, 2647 .funcs = &smu_ip_funcs, 2648 }; 2649 2650 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2651 .type = AMD_IP_BLOCK_TYPE_SMC, 2652 .major = 12, 2653 .minor = 0, 2654 .rev = 0, 2655 .funcs = &smu_ip_funcs, 2656 }; 2657 2658 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2659 .type = AMD_IP_BLOCK_TYPE_SMC, 2660 .major = 13, 2661 .minor = 0, 2662 .rev = 0, 2663 .funcs = &smu_ip_funcs, 2664 }; 2665 2666 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2667 .type = AMD_IP_BLOCK_TYPE_SMC, 2668 .major = 14, 2669 .minor = 0, 2670 .rev = 0, 2671 .funcs = &smu_ip_funcs, 2672 }; 2673 2674 static int smu_load_microcode(void *handle) 2675 { 2676 struct smu_context *smu = handle; 2677 struct amdgpu_device *adev = smu->adev; 2678 int ret = 0; 2679 2680 if (!smu->pm_enabled) 2681 return -EOPNOTSUPP; 2682 2683 /* This should be used for non PSP loading */ 2684 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2685 return 0; 2686 2687 if (smu->ppt_funcs->load_microcode) { 2688 ret = smu->ppt_funcs->load_microcode(smu); 2689 if (ret) { 2690 dev_err(adev->dev, "Load microcode failed\n"); 2691 return ret; 2692 } 2693 } 2694 2695 if (smu->ppt_funcs->check_fw_status) { 2696 ret = smu->ppt_funcs->check_fw_status(smu); 2697 if (ret) { 2698 dev_err(adev->dev, "SMC is not ready\n"); 2699 return ret; 2700 } 2701 } 2702 2703 return ret; 2704 } 2705 2706 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2707 { 2708 int ret = 0; 2709 2710 if (smu->ppt_funcs->set_gfx_cgpg) 2711 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2712 2713 return ret; 2714 } 2715 2716 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2717 { 2718 struct smu_context *smu = handle; 2719 int ret = 0; 2720 2721 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2722 return -EOPNOTSUPP; 2723 2724 if (!smu->ppt_funcs->set_fan_speed_rpm) 2725 return -EOPNOTSUPP; 2726 2727 if (speed == U32_MAX) 2728 return -EINVAL; 2729 2730 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2731 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2732 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2733 smu->user_dpm_profile.fan_speed_rpm = speed; 2734 2735 /* Override custom PWM setting as they cannot co-exist */ 2736 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2737 smu->user_dpm_profile.fan_speed_pwm = 0; 2738 } 2739 2740 return ret; 2741 } 2742 2743 /** 2744 * smu_get_power_limit - Request one of the SMU Power Limits 2745 * 2746 * @handle: pointer to smu context 2747 * @limit: requested limit is written back to this variable 2748 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2749 * @pp_power_type: &pp_power_type type of power 2750 * Return: 0 on success, <0 on error 2751 * 2752 */ 2753 int smu_get_power_limit(void *handle, 2754 uint32_t *limit, 2755 enum pp_power_limit_level pp_limit_level, 2756 enum pp_power_type pp_power_type) 2757 { 2758 struct smu_context *smu = handle; 2759 struct amdgpu_device *adev = smu->adev; 2760 enum smu_ppt_limit_level limit_level; 2761 uint32_t limit_type; 2762 int ret = 0; 2763 2764 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2765 return -EOPNOTSUPP; 2766 2767 switch (pp_power_type) { 2768 case PP_PWR_TYPE_SUSTAINED: 2769 limit_type = SMU_DEFAULT_PPT_LIMIT; 2770 break; 2771 case PP_PWR_TYPE_FAST: 2772 limit_type = SMU_FAST_PPT_LIMIT; 2773 break; 2774 default: 2775 return -EOPNOTSUPP; 2776 } 2777 2778 switch (pp_limit_level) { 2779 case PP_PWR_LIMIT_CURRENT: 2780 limit_level = SMU_PPT_LIMIT_CURRENT; 2781 break; 2782 case PP_PWR_LIMIT_DEFAULT: 2783 limit_level = SMU_PPT_LIMIT_DEFAULT; 2784 break; 2785 case PP_PWR_LIMIT_MAX: 2786 limit_level = SMU_PPT_LIMIT_MAX; 2787 break; 2788 case PP_PWR_LIMIT_MIN: 2789 limit_level = SMU_PPT_LIMIT_MIN; 2790 break; 2791 default: 2792 return -EOPNOTSUPP; 2793 } 2794 2795 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2796 if (smu->ppt_funcs->get_ppt_limit) 2797 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2798 } else { 2799 switch (limit_level) { 2800 case SMU_PPT_LIMIT_CURRENT: 2801 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2802 case IP_VERSION(13, 0, 2): 2803 case IP_VERSION(13, 0, 6): 2804 case IP_VERSION(13, 0, 14): 2805 case IP_VERSION(11, 0, 7): 2806 case IP_VERSION(11, 0, 11): 2807 case IP_VERSION(11, 0, 12): 2808 case IP_VERSION(11, 0, 13): 2809 ret = smu_get_asic_power_limits(smu, 2810 &smu->current_power_limit, 2811 NULL, NULL, NULL); 2812 break; 2813 default: 2814 break; 2815 } 2816 *limit = smu->current_power_limit; 2817 break; 2818 case SMU_PPT_LIMIT_DEFAULT: 2819 *limit = smu->default_power_limit; 2820 break; 2821 case SMU_PPT_LIMIT_MAX: 2822 *limit = smu->max_power_limit; 2823 break; 2824 case SMU_PPT_LIMIT_MIN: 2825 *limit = smu->min_power_limit; 2826 break; 2827 default: 2828 return -EINVAL; 2829 } 2830 } 2831 2832 return ret; 2833 } 2834 2835 static int smu_set_power_limit(void *handle, uint32_t limit) 2836 { 2837 struct smu_context *smu = handle; 2838 uint32_t limit_type = limit >> 24; 2839 int ret = 0; 2840 2841 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2842 return -EOPNOTSUPP; 2843 2844 limit &= (1<<24)-1; 2845 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2846 if (smu->ppt_funcs->set_power_limit) 2847 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2848 2849 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2850 dev_err(smu->adev->dev, 2851 "New power limit (%d) is out of range [%d,%d]\n", 2852 limit, smu->min_power_limit, smu->max_power_limit); 2853 return -EINVAL; 2854 } 2855 2856 if (!limit) 2857 limit = smu->current_power_limit; 2858 2859 if (smu->ppt_funcs->set_power_limit) { 2860 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2861 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2862 smu->user_dpm_profile.power_limit = limit; 2863 } 2864 2865 return ret; 2866 } 2867 2868 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2869 { 2870 int ret = 0; 2871 2872 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2873 return -EOPNOTSUPP; 2874 2875 if (smu->ppt_funcs->print_clk_levels) 2876 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2877 2878 return ret; 2879 } 2880 2881 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2882 { 2883 enum smu_clk_type clk_type; 2884 2885 switch (type) { 2886 case PP_SCLK: 2887 clk_type = SMU_SCLK; break; 2888 case PP_MCLK: 2889 clk_type = SMU_MCLK; break; 2890 case PP_PCIE: 2891 clk_type = SMU_PCIE; break; 2892 case PP_SOCCLK: 2893 clk_type = SMU_SOCCLK; break; 2894 case PP_FCLK: 2895 clk_type = SMU_FCLK; break; 2896 case PP_DCEFCLK: 2897 clk_type = SMU_DCEFCLK; break; 2898 case PP_VCLK: 2899 clk_type = SMU_VCLK; break; 2900 case PP_VCLK1: 2901 clk_type = SMU_VCLK1; break; 2902 case PP_DCLK: 2903 clk_type = SMU_DCLK; break; 2904 case PP_DCLK1: 2905 clk_type = SMU_DCLK1; break; 2906 case OD_SCLK: 2907 clk_type = SMU_OD_SCLK; break; 2908 case OD_MCLK: 2909 clk_type = SMU_OD_MCLK; break; 2910 case OD_VDDC_CURVE: 2911 clk_type = SMU_OD_VDDC_CURVE; break; 2912 case OD_RANGE: 2913 clk_type = SMU_OD_RANGE; break; 2914 case OD_VDDGFX_OFFSET: 2915 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2916 case OD_CCLK: 2917 clk_type = SMU_OD_CCLK; break; 2918 case OD_FAN_CURVE: 2919 clk_type = SMU_OD_FAN_CURVE; break; 2920 case OD_ACOUSTIC_LIMIT: 2921 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2922 case OD_ACOUSTIC_TARGET: 2923 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2924 case OD_FAN_TARGET_TEMPERATURE: 2925 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2926 case OD_FAN_MINIMUM_PWM: 2927 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2928 case OD_FAN_ZERO_RPM_ENABLE: 2929 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 2930 case OD_FAN_ZERO_RPM_STOP_TEMP: 2931 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 2932 default: 2933 clk_type = SMU_CLK_COUNT; break; 2934 } 2935 2936 return clk_type; 2937 } 2938 2939 static int smu_print_ppclk_levels(void *handle, 2940 enum pp_clock_type type, 2941 char *buf) 2942 { 2943 struct smu_context *smu = handle; 2944 enum smu_clk_type clk_type; 2945 2946 clk_type = smu_convert_to_smuclk(type); 2947 if (clk_type == SMU_CLK_COUNT) 2948 return -EINVAL; 2949 2950 return smu_print_smuclk_levels(smu, clk_type, buf); 2951 } 2952 2953 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2954 { 2955 struct smu_context *smu = handle; 2956 enum smu_clk_type clk_type; 2957 2958 clk_type = smu_convert_to_smuclk(type); 2959 if (clk_type == SMU_CLK_COUNT) 2960 return -EINVAL; 2961 2962 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2963 return -EOPNOTSUPP; 2964 2965 if (!smu->ppt_funcs->emit_clk_levels) 2966 return -ENOENT; 2967 2968 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2969 2970 } 2971 2972 static int smu_od_edit_dpm_table(void *handle, 2973 enum PP_OD_DPM_TABLE_COMMAND type, 2974 long *input, uint32_t size) 2975 { 2976 struct smu_context *smu = handle; 2977 int ret = 0; 2978 2979 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2980 return -EOPNOTSUPP; 2981 2982 if (smu->ppt_funcs->od_edit_dpm_table) { 2983 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2984 } 2985 2986 return ret; 2987 } 2988 2989 static int smu_read_sensor(void *handle, 2990 int sensor, 2991 void *data, 2992 int *size_arg) 2993 { 2994 struct smu_context *smu = handle; 2995 struct amdgpu_device *adev = smu->adev; 2996 struct smu_umd_pstate_table *pstate_table = 2997 &smu->pstate_table; 2998 int i, ret = 0; 2999 uint32_t *size, size_val; 3000 3001 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3002 return -EOPNOTSUPP; 3003 3004 if (!data || !size_arg) 3005 return -EINVAL; 3006 3007 size_val = *size_arg; 3008 size = &size_val; 3009 3010 if (smu->ppt_funcs->read_sensor) 3011 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 3012 goto unlock; 3013 3014 switch (sensor) { 3015 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 3016 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 3017 *size = 4; 3018 break; 3019 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 3020 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 3021 *size = 4; 3022 break; 3023 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 3024 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 3025 *size = 4; 3026 break; 3027 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 3028 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3029 *size = 4; 3030 break; 3031 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 3032 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 3033 *size = 8; 3034 break; 3035 case AMDGPU_PP_SENSOR_UVD_POWER: 3036 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3037 *size = 4; 3038 break; 3039 case AMDGPU_PP_SENSOR_VCE_POWER: 3040 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 3041 *size = 4; 3042 break; 3043 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3044 *(uint32_t *)data = 0; 3045 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 3046 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) { 3047 *(uint32_t *)data = 1; 3048 break; 3049 } 3050 } 3051 *size = 4; 3052 break; 3053 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3054 *(uint32_t *)data = 0; 3055 *size = 4; 3056 break; 3057 default: 3058 *size = 0; 3059 ret = -EOPNOTSUPP; 3060 break; 3061 } 3062 3063 unlock: 3064 // assign uint32_t to int 3065 *size_arg = size_val; 3066 3067 return ret; 3068 } 3069 3070 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3071 { 3072 int ret = -EOPNOTSUPP; 3073 struct smu_context *smu = handle; 3074 3075 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3076 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3077 3078 return ret; 3079 } 3080 3081 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3082 { 3083 int ret = -EOPNOTSUPP; 3084 struct smu_context *smu = handle; 3085 3086 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3087 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3088 3089 return ret; 3090 } 3091 3092 static int smu_get_power_profile_mode(void *handle, char *buf) 3093 { 3094 struct smu_context *smu = handle; 3095 3096 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3097 !smu->ppt_funcs->get_power_profile_mode) 3098 return -EOPNOTSUPP; 3099 if (!buf) 3100 return -EINVAL; 3101 3102 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3103 } 3104 3105 static int smu_set_power_profile_mode(void *handle, 3106 long *param, 3107 uint32_t param_size) 3108 { 3109 struct smu_context *smu = handle; 3110 bool custom = false; 3111 int ret = 0; 3112 3113 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3114 !smu->ppt_funcs->set_power_profile_mode) 3115 return -EOPNOTSUPP; 3116 3117 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) { 3118 custom = true; 3119 /* clear frontend mask so custom changes propogate */ 3120 smu->workload_mask = 0; 3121 } 3122 3123 if ((param[param_size] != smu->power_profile_mode) || custom) { 3124 /* clear the old user preference */ 3125 smu_power_profile_mode_put(smu, smu->power_profile_mode); 3126 /* set the new user preference */ 3127 smu_power_profile_mode_get(smu, param[param_size]); 3128 ret = smu_bump_power_profile_mode(smu, 3129 custom ? param : NULL, 3130 custom ? param_size : 0); 3131 if (ret) 3132 smu_power_profile_mode_put(smu, param[param_size]); 3133 else 3134 /* store the user's preference */ 3135 smu->power_profile_mode = param[param_size]; 3136 } 3137 3138 return ret; 3139 } 3140 3141 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3142 { 3143 struct smu_context *smu = handle; 3144 3145 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3146 return -EOPNOTSUPP; 3147 3148 if (!smu->ppt_funcs->get_fan_control_mode) 3149 return -EOPNOTSUPP; 3150 3151 if (!fan_mode) 3152 return -EINVAL; 3153 3154 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3155 3156 return 0; 3157 } 3158 3159 static int smu_set_fan_control_mode(void *handle, u32 value) 3160 { 3161 struct smu_context *smu = handle; 3162 int ret = 0; 3163 3164 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3165 return -EOPNOTSUPP; 3166 3167 if (!smu->ppt_funcs->set_fan_control_mode) 3168 return -EOPNOTSUPP; 3169 3170 if (value == U32_MAX) 3171 return -EINVAL; 3172 3173 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3174 if (ret) 3175 goto out; 3176 3177 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3178 smu->user_dpm_profile.fan_mode = value; 3179 3180 /* reset user dpm fan speed */ 3181 if (value != AMD_FAN_CTRL_MANUAL) { 3182 smu->user_dpm_profile.fan_speed_pwm = 0; 3183 smu->user_dpm_profile.fan_speed_rpm = 0; 3184 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3185 } 3186 } 3187 3188 out: 3189 return ret; 3190 } 3191 3192 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3193 { 3194 struct smu_context *smu = handle; 3195 int ret = 0; 3196 3197 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3198 return -EOPNOTSUPP; 3199 3200 if (!smu->ppt_funcs->get_fan_speed_pwm) 3201 return -EOPNOTSUPP; 3202 3203 if (!speed) 3204 return -EINVAL; 3205 3206 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3207 3208 return ret; 3209 } 3210 3211 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3212 { 3213 struct smu_context *smu = handle; 3214 int ret = 0; 3215 3216 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3217 return -EOPNOTSUPP; 3218 3219 if (!smu->ppt_funcs->set_fan_speed_pwm) 3220 return -EOPNOTSUPP; 3221 3222 if (speed == U32_MAX) 3223 return -EINVAL; 3224 3225 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3226 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3227 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3228 smu->user_dpm_profile.fan_speed_pwm = speed; 3229 3230 /* Override custom RPM setting as they cannot co-exist */ 3231 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3232 smu->user_dpm_profile.fan_speed_rpm = 0; 3233 } 3234 3235 return ret; 3236 } 3237 3238 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3239 { 3240 struct smu_context *smu = handle; 3241 int ret = 0; 3242 3243 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3244 return -EOPNOTSUPP; 3245 3246 if (!smu->ppt_funcs->get_fan_speed_rpm) 3247 return -EOPNOTSUPP; 3248 3249 if (!speed) 3250 return -EINVAL; 3251 3252 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3253 3254 return ret; 3255 } 3256 3257 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3258 { 3259 struct smu_context *smu = handle; 3260 3261 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3262 return -EOPNOTSUPP; 3263 3264 return smu_set_min_dcef_deep_sleep(smu, clk); 3265 } 3266 3267 static int smu_get_clock_by_type_with_latency(void *handle, 3268 enum amd_pp_clock_type type, 3269 struct pp_clock_levels_with_latency *clocks) 3270 { 3271 struct smu_context *smu = handle; 3272 enum smu_clk_type clk_type; 3273 int ret = 0; 3274 3275 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3276 return -EOPNOTSUPP; 3277 3278 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3279 switch (type) { 3280 case amd_pp_sys_clock: 3281 clk_type = SMU_GFXCLK; 3282 break; 3283 case amd_pp_mem_clock: 3284 clk_type = SMU_MCLK; 3285 break; 3286 case amd_pp_dcef_clock: 3287 clk_type = SMU_DCEFCLK; 3288 break; 3289 case amd_pp_disp_clock: 3290 clk_type = SMU_DISPCLK; 3291 break; 3292 default: 3293 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3294 return -EINVAL; 3295 } 3296 3297 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3298 } 3299 3300 return ret; 3301 } 3302 3303 static int smu_display_clock_voltage_request(void *handle, 3304 struct pp_display_clock_request *clock_req) 3305 { 3306 struct smu_context *smu = handle; 3307 int ret = 0; 3308 3309 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3310 return -EOPNOTSUPP; 3311 3312 if (smu->ppt_funcs->display_clock_voltage_request) 3313 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3314 3315 return ret; 3316 } 3317 3318 3319 static int smu_display_disable_memory_clock_switch(void *handle, 3320 bool disable_memory_clock_switch) 3321 { 3322 struct smu_context *smu = handle; 3323 int ret = -EINVAL; 3324 3325 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3326 return -EOPNOTSUPP; 3327 3328 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3329 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3330 3331 return ret; 3332 } 3333 3334 static int smu_set_xgmi_pstate(void *handle, 3335 uint32_t pstate) 3336 { 3337 struct smu_context *smu = handle; 3338 int ret = 0; 3339 3340 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3341 return -EOPNOTSUPP; 3342 3343 if (smu->ppt_funcs->set_xgmi_pstate) 3344 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3345 3346 if (ret) 3347 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3348 3349 return ret; 3350 } 3351 3352 static int smu_get_baco_capability(void *handle) 3353 { 3354 struct smu_context *smu = handle; 3355 3356 if (!smu->pm_enabled) 3357 return false; 3358 3359 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3360 return false; 3361 3362 return smu->ppt_funcs->get_bamaco_support(smu); 3363 } 3364 3365 static int smu_baco_set_state(void *handle, int state) 3366 { 3367 struct smu_context *smu = handle; 3368 int ret = 0; 3369 3370 if (!smu->pm_enabled) 3371 return -EOPNOTSUPP; 3372 3373 if (state == 0) { 3374 if (smu->ppt_funcs->baco_exit) 3375 ret = smu->ppt_funcs->baco_exit(smu); 3376 } else if (state == 1) { 3377 if (smu->ppt_funcs->baco_enter) 3378 ret = smu->ppt_funcs->baco_enter(smu); 3379 } else { 3380 return -EINVAL; 3381 } 3382 3383 if (ret) 3384 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3385 (state)?"enter":"exit"); 3386 3387 return ret; 3388 } 3389 3390 bool smu_mode1_reset_is_support(struct smu_context *smu) 3391 { 3392 bool ret = false; 3393 3394 if (!smu->pm_enabled) 3395 return false; 3396 3397 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3398 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3399 3400 return ret; 3401 } 3402 3403 bool smu_mode2_reset_is_support(struct smu_context *smu) 3404 { 3405 bool ret = false; 3406 3407 if (!smu->pm_enabled) 3408 return false; 3409 3410 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3411 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3412 3413 return ret; 3414 } 3415 3416 int smu_mode1_reset(struct smu_context *smu) 3417 { 3418 int ret = 0; 3419 3420 if (!smu->pm_enabled) 3421 return -EOPNOTSUPP; 3422 3423 if (smu->ppt_funcs->mode1_reset) 3424 ret = smu->ppt_funcs->mode1_reset(smu); 3425 3426 return ret; 3427 } 3428 3429 static int smu_mode2_reset(void *handle) 3430 { 3431 struct smu_context *smu = handle; 3432 int ret = 0; 3433 3434 if (!smu->pm_enabled) 3435 return -EOPNOTSUPP; 3436 3437 if (smu->ppt_funcs->mode2_reset) 3438 ret = smu->ppt_funcs->mode2_reset(smu); 3439 3440 if (ret) 3441 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3442 3443 return ret; 3444 } 3445 3446 static int smu_enable_gfx_features(void *handle) 3447 { 3448 struct smu_context *smu = handle; 3449 int ret = 0; 3450 3451 if (!smu->pm_enabled) 3452 return -EOPNOTSUPP; 3453 3454 if (smu->ppt_funcs->enable_gfx_features) 3455 ret = smu->ppt_funcs->enable_gfx_features(smu); 3456 3457 if (ret) 3458 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3459 3460 return ret; 3461 } 3462 3463 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3464 struct pp_smu_nv_clock_table *max_clocks) 3465 { 3466 struct smu_context *smu = handle; 3467 int ret = 0; 3468 3469 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3470 return -EOPNOTSUPP; 3471 3472 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3473 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3474 3475 return ret; 3476 } 3477 3478 static int smu_get_uclk_dpm_states(void *handle, 3479 unsigned int *clock_values_in_khz, 3480 unsigned int *num_states) 3481 { 3482 struct smu_context *smu = handle; 3483 int ret = 0; 3484 3485 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3486 return -EOPNOTSUPP; 3487 3488 if (smu->ppt_funcs->get_uclk_dpm_states) 3489 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3490 3491 return ret; 3492 } 3493 3494 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3495 { 3496 struct smu_context *smu = handle; 3497 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3498 3499 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3500 return -EOPNOTSUPP; 3501 3502 if (smu->ppt_funcs->get_current_power_state) 3503 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3504 3505 return pm_state; 3506 } 3507 3508 static int smu_get_dpm_clock_table(void *handle, 3509 struct dpm_clocks *clock_table) 3510 { 3511 struct smu_context *smu = handle; 3512 int ret = 0; 3513 3514 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3515 return -EOPNOTSUPP; 3516 3517 if (smu->ppt_funcs->get_dpm_clock_table) 3518 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3519 3520 return ret; 3521 } 3522 3523 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3524 { 3525 struct smu_context *smu = handle; 3526 3527 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3528 return -EOPNOTSUPP; 3529 3530 if (!smu->ppt_funcs->get_gpu_metrics) 3531 return -EOPNOTSUPP; 3532 3533 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3534 } 3535 3536 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3537 size_t size) 3538 { 3539 struct smu_context *smu = handle; 3540 3541 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3542 return -EOPNOTSUPP; 3543 3544 if (!smu->ppt_funcs->get_pm_metrics) 3545 return -EOPNOTSUPP; 3546 3547 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3548 } 3549 3550 static int smu_enable_mgpu_fan_boost(void *handle) 3551 { 3552 struct smu_context *smu = handle; 3553 int ret = 0; 3554 3555 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3556 return -EOPNOTSUPP; 3557 3558 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3559 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3560 3561 return ret; 3562 } 3563 3564 static int smu_gfx_state_change_set(void *handle, 3565 uint32_t state) 3566 { 3567 struct smu_context *smu = handle; 3568 int ret = 0; 3569 3570 if (smu->ppt_funcs->gfx_state_change_set) 3571 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3572 3573 return ret; 3574 } 3575 3576 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3577 { 3578 int ret = 0; 3579 3580 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3581 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3582 3583 return ret; 3584 } 3585 3586 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3587 { 3588 int ret = -EOPNOTSUPP; 3589 3590 if (smu->ppt_funcs && 3591 smu->ppt_funcs->get_ecc_info) 3592 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3593 3594 return ret; 3595 3596 } 3597 3598 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3599 { 3600 struct smu_context *smu = handle; 3601 struct smu_table_context *smu_table = &smu->smu_table; 3602 struct smu_table *memory_pool = &smu_table->memory_pool; 3603 3604 if (!addr || !size) 3605 return -EINVAL; 3606 3607 *addr = NULL; 3608 *size = 0; 3609 if (memory_pool->bo) { 3610 *addr = memory_pool->cpu_addr; 3611 *size = memory_pool->size; 3612 } 3613 3614 return 0; 3615 } 3616 3617 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3618 size_t *size) 3619 { 3620 size_t offset = *size; 3621 int level; 3622 3623 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3624 if (level == policy->current_level) 3625 offset += sysfs_emit_at(sysbuf, offset, 3626 "%d : %s*\n", level, 3627 policy->desc->get_desc(policy, level)); 3628 else 3629 offset += sysfs_emit_at(sysbuf, offset, 3630 "%d : %s\n", level, 3631 policy->desc->get_desc(policy, level)); 3632 } 3633 3634 *size = offset; 3635 } 3636 3637 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3638 enum pp_pm_policy p_type, char *sysbuf) 3639 { 3640 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3641 struct smu_dpm_policy_ctxt *policy_ctxt; 3642 struct smu_dpm_policy *dpm_policy; 3643 size_t offset = 0; 3644 3645 policy_ctxt = dpm_ctxt->dpm_policies; 3646 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3647 !policy_ctxt->policy_mask) 3648 return -EOPNOTSUPP; 3649 3650 if (p_type == PP_PM_POLICY_NONE) 3651 return -EINVAL; 3652 3653 dpm_policy = smu_get_pm_policy(smu, p_type); 3654 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3655 return -ENOENT; 3656 3657 if (!sysbuf) 3658 return -EINVAL; 3659 3660 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3661 3662 return offset; 3663 } 3664 3665 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3666 enum pp_pm_policy p_type) 3667 { 3668 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3669 struct smu_dpm_policy_ctxt *policy_ctxt; 3670 int i; 3671 3672 policy_ctxt = dpm_ctxt->dpm_policies; 3673 if (!policy_ctxt) 3674 return NULL; 3675 3676 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3677 if (policy_ctxt->policies[i].policy_type == p_type) 3678 return &policy_ctxt->policies[i]; 3679 } 3680 3681 return NULL; 3682 } 3683 3684 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3685 int level) 3686 { 3687 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3688 struct smu_dpm_policy *dpm_policy = NULL; 3689 struct smu_dpm_policy_ctxt *policy_ctxt; 3690 int ret = -EOPNOTSUPP; 3691 3692 policy_ctxt = dpm_ctxt->dpm_policies; 3693 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3694 !policy_ctxt->policy_mask) 3695 return ret; 3696 3697 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3698 return -EINVAL; 3699 3700 dpm_policy = smu_get_pm_policy(smu, p_type); 3701 3702 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3703 return ret; 3704 3705 if (dpm_policy->current_level == level) 3706 return 0; 3707 3708 ret = dpm_policy->set_policy(smu, level); 3709 3710 if (!ret) 3711 dpm_policy->current_level = level; 3712 3713 return ret; 3714 } 3715 3716 static const struct amd_pm_funcs swsmu_pm_funcs = { 3717 /* export for sysfs */ 3718 .set_fan_control_mode = smu_set_fan_control_mode, 3719 .get_fan_control_mode = smu_get_fan_control_mode, 3720 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3721 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3722 .force_clock_level = smu_force_ppclk_levels, 3723 .print_clock_levels = smu_print_ppclk_levels, 3724 .emit_clock_levels = smu_emit_ppclk_levels, 3725 .force_performance_level = smu_force_performance_level, 3726 .read_sensor = smu_read_sensor, 3727 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3728 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3729 .get_performance_level = smu_get_performance_level, 3730 .get_current_power_state = smu_get_current_power_state, 3731 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3732 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3733 .get_pp_num_states = smu_get_power_num_states, 3734 .get_pp_table = smu_sys_get_pp_table, 3735 .set_pp_table = smu_sys_set_pp_table, 3736 .switch_power_profile = smu_switch_power_profile, 3737 /* export to amdgpu */ 3738 .dispatch_tasks = smu_handle_dpm_task, 3739 .load_firmware = smu_load_microcode, 3740 .set_powergating_by_smu = smu_dpm_set_power_gate, 3741 .set_power_limit = smu_set_power_limit, 3742 .get_power_limit = smu_get_power_limit, 3743 .get_power_profile_mode = smu_get_power_profile_mode, 3744 .set_power_profile_mode = smu_set_power_profile_mode, 3745 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3746 .set_mp1_state = smu_set_mp1_state, 3747 .gfx_state_change_set = smu_gfx_state_change_set, 3748 /* export to DC */ 3749 .get_sclk = smu_get_sclk, 3750 .get_mclk = smu_get_mclk, 3751 .display_configuration_change = smu_display_configuration_change, 3752 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3753 .display_clock_voltage_request = smu_display_clock_voltage_request, 3754 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3755 .set_active_display_count = smu_set_display_count, 3756 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3757 .get_asic_baco_capability = smu_get_baco_capability, 3758 .set_asic_baco_state = smu_baco_set_state, 3759 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3760 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3761 .asic_reset_mode_2 = smu_mode2_reset, 3762 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3763 .set_df_cstate = smu_set_df_cstate, 3764 .set_xgmi_pstate = smu_set_xgmi_pstate, 3765 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3766 .get_pm_metrics = smu_sys_get_pm_metrics, 3767 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3768 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3769 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3770 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3771 .get_dpm_clock_table = smu_get_dpm_clock_table, 3772 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3773 }; 3774 3775 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3776 uint64_t event_arg) 3777 { 3778 int ret = -EINVAL; 3779 3780 if (smu->ppt_funcs->wait_for_event) 3781 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3782 3783 return ret; 3784 } 3785 3786 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3787 { 3788 3789 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3790 return -EOPNOTSUPP; 3791 3792 /* Confirm the buffer allocated is of correct size */ 3793 if (size != smu->stb_context.stb_buf_size) 3794 return -EINVAL; 3795 3796 /* 3797 * No need to lock smu mutex as we access STB directly through MMIO 3798 * and not going through SMU messaging route (for now at least). 3799 * For registers access rely on implementation internal locking. 3800 */ 3801 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3802 } 3803 3804 #if defined(CONFIG_DEBUG_FS) 3805 3806 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3807 { 3808 struct amdgpu_device *adev = filp->f_inode->i_private; 3809 struct smu_context *smu = adev->powerplay.pp_handle; 3810 unsigned char *buf; 3811 int r; 3812 3813 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3814 if (!buf) 3815 return -ENOMEM; 3816 3817 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3818 if (r) 3819 goto out; 3820 3821 filp->private_data = buf; 3822 3823 return 0; 3824 3825 out: 3826 kvfree(buf); 3827 return r; 3828 } 3829 3830 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3831 loff_t *pos) 3832 { 3833 struct amdgpu_device *adev = filp->f_inode->i_private; 3834 struct smu_context *smu = adev->powerplay.pp_handle; 3835 3836 3837 if (!filp->private_data) 3838 return -EINVAL; 3839 3840 return simple_read_from_buffer(buf, 3841 size, 3842 pos, filp->private_data, 3843 smu->stb_context.stb_buf_size); 3844 } 3845 3846 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3847 { 3848 kvfree(filp->private_data); 3849 filp->private_data = NULL; 3850 3851 return 0; 3852 } 3853 3854 /* 3855 * We have to define not only read method but also 3856 * open and release because .read takes up to PAGE_SIZE 3857 * data each time so and so is invoked multiple times. 3858 * We allocate the STB buffer in .open and release it 3859 * in .release 3860 */ 3861 static const struct file_operations smu_stb_debugfs_fops = { 3862 .owner = THIS_MODULE, 3863 .open = smu_stb_debugfs_open, 3864 .read = smu_stb_debugfs_read, 3865 .release = smu_stb_debugfs_release, 3866 .llseek = default_llseek, 3867 }; 3868 3869 #endif 3870 3871 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3872 { 3873 #if defined(CONFIG_DEBUG_FS) 3874 3875 struct smu_context *smu = adev->powerplay.pp_handle; 3876 3877 if (!smu || (!smu->stb_context.stb_buf_size)) 3878 return; 3879 3880 debugfs_create_file_size("amdgpu_smu_stb_dump", 3881 S_IRUSR, 3882 adev_to_drm(adev)->primary->debugfs_root, 3883 adev, 3884 &smu_stb_debugfs_fops, 3885 smu->stb_context.stb_buf_size); 3886 #endif 3887 } 3888 3889 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3890 { 3891 int ret = 0; 3892 3893 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3894 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3895 3896 return ret; 3897 } 3898 3899 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3900 { 3901 int ret = 0; 3902 3903 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3904 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3905 3906 return ret; 3907 } 3908 3909 int smu_send_rma_reason(struct smu_context *smu) 3910 { 3911 int ret = 0; 3912 3913 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3914 ret = smu->ppt_funcs->send_rma_reason(smu); 3915 3916 return ret; 3917 } 3918 3919 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask) 3920 { 3921 int ret = 0; 3922 3923 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma) 3924 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask); 3925 3926 return ret; 3927 } 3928