1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 static void smu_power_profile_mode_get(struct smu_context *smu, 76 enum PP_SMC_POWER_PROFILE profile_mode); 77 static void smu_power_profile_mode_put(struct smu_context *smu, 78 enum PP_SMC_POWER_PROFILE profile_mode); 79 80 static int smu_sys_get_pp_feature_mask(void *handle, 81 char *buf) 82 { 83 struct smu_context *smu = handle; 84 85 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 86 return -EOPNOTSUPP; 87 88 return smu_get_pp_feature_mask(smu, buf); 89 } 90 91 static int smu_sys_set_pp_feature_mask(void *handle, 92 uint64_t new_mask) 93 { 94 struct smu_context *smu = handle; 95 96 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 97 return -EOPNOTSUPP; 98 99 return smu_set_pp_feature_mask(smu, new_mask); 100 } 101 102 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 103 { 104 if (!smu->ppt_funcs->set_gfx_off_residency) 105 return -EINVAL; 106 107 return smu_set_gfx_off_residency(smu, value); 108 } 109 110 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 111 { 112 if (!smu->ppt_funcs->get_gfx_off_residency) 113 return -EINVAL; 114 115 return smu_get_gfx_off_residency(smu, value); 116 } 117 118 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 119 { 120 if (!smu->ppt_funcs->get_gfx_off_entrycount) 121 return -EINVAL; 122 123 return smu_get_gfx_off_entrycount(smu, value); 124 } 125 126 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 127 { 128 if (!smu->ppt_funcs->get_gfx_off_status) 129 return -EINVAL; 130 131 *value = smu_get_gfx_off_status(smu); 132 133 return 0; 134 } 135 136 int smu_set_soft_freq_range(struct smu_context *smu, 137 enum smu_clk_type clk_type, 138 uint32_t min, 139 uint32_t max) 140 { 141 int ret = 0; 142 143 if (smu->ppt_funcs->set_soft_freq_limited_range) 144 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 145 clk_type, 146 min, 147 max, 148 false); 149 150 return ret; 151 } 152 153 int smu_get_dpm_freq_range(struct smu_context *smu, 154 enum smu_clk_type clk_type, 155 uint32_t *min, 156 uint32_t *max) 157 { 158 int ret = -ENOTSUPP; 159 160 if (!min && !max) 161 return -EINVAL; 162 163 if (smu->ppt_funcs->get_dpm_ultimate_freq) 164 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 165 clk_type, 166 min, 167 max); 168 169 return ret; 170 } 171 172 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 173 { 174 int ret = 0; 175 struct amdgpu_device *adev = smu->adev; 176 177 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 178 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 179 if (ret) 180 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 181 } 182 return ret; 183 } 184 185 static u32 smu_get_mclk(void *handle, bool low) 186 { 187 struct smu_context *smu = handle; 188 uint32_t clk_freq; 189 int ret = 0; 190 191 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 192 low ? &clk_freq : NULL, 193 !low ? &clk_freq : NULL); 194 if (ret) 195 return 0; 196 return clk_freq * 100; 197 } 198 199 static u32 smu_get_sclk(void *handle, bool low) 200 { 201 struct smu_context *smu = handle; 202 uint32_t clk_freq; 203 int ret = 0; 204 205 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 206 low ? &clk_freq : NULL, 207 !low ? &clk_freq : NULL); 208 if (ret) 209 return 0; 210 return clk_freq * 100; 211 } 212 213 static int smu_set_gfx_imu_enable(struct smu_context *smu) 214 { 215 struct amdgpu_device *adev = smu->adev; 216 217 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 218 return 0; 219 220 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 221 return 0; 222 223 return smu_set_gfx_power_up_by_imu(smu); 224 } 225 226 static bool is_vcn_enabled(struct amdgpu_device *adev) 227 { 228 int i; 229 230 for (i = 0; i < adev->num_ip_blocks; i++) { 231 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 232 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 233 !adev->ip_blocks[i].status.valid) 234 return false; 235 } 236 237 return true; 238 } 239 240 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 241 bool enable, 242 int inst) 243 { 244 struct smu_power_context *smu_power = &smu->smu_power; 245 struct smu_power_gate *power_gate = &smu_power->power_gate; 246 int ret = 0; 247 248 /* 249 * don't poweron vcn/jpeg when they are skipped. 250 */ 251 if (!is_vcn_enabled(smu->adev)) 252 return 0; 253 254 if (!smu->ppt_funcs->dpm_set_vcn_enable) 255 return 0; 256 257 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable) 258 return 0; 259 260 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst); 261 if (!ret) 262 atomic_set(&power_gate->vcn_gated[inst], !enable); 263 264 return ret; 265 } 266 267 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 268 bool enable) 269 { 270 struct smu_power_context *smu_power = &smu->smu_power; 271 struct smu_power_gate *power_gate = &smu_power->power_gate; 272 int ret = 0; 273 274 if (!is_vcn_enabled(smu->adev)) 275 return 0; 276 277 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 278 return 0; 279 280 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 281 return 0; 282 283 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 284 if (!ret) 285 atomic_set(&power_gate->jpeg_gated, !enable); 286 287 return ret; 288 } 289 290 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 291 bool enable) 292 { 293 struct smu_power_context *smu_power = &smu->smu_power; 294 struct smu_power_gate *power_gate = &smu_power->power_gate; 295 int ret = 0; 296 297 if (!smu->ppt_funcs->dpm_set_vpe_enable) 298 return 0; 299 300 if (atomic_read(&power_gate->vpe_gated) ^ enable) 301 return 0; 302 303 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 304 if (!ret) 305 atomic_set(&power_gate->vpe_gated, !enable); 306 307 return ret; 308 } 309 310 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 311 bool enable) 312 { 313 struct smu_power_context *smu_power = &smu->smu_power; 314 struct smu_power_gate *power_gate = &smu_power->power_gate; 315 int ret = 0; 316 317 if (!smu->adev->enable_umsch_mm) 318 return 0; 319 320 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 321 return 0; 322 323 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 324 return 0; 325 326 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 327 if (!ret) 328 atomic_set(&power_gate->umsch_mm_gated, !enable); 329 330 return ret; 331 } 332 333 static int smu_set_mall_enable(struct smu_context *smu) 334 { 335 int ret = 0; 336 337 if (!smu->ppt_funcs->set_mall_enable) 338 return 0; 339 340 ret = smu->ppt_funcs->set_mall_enable(smu); 341 342 return ret; 343 } 344 345 /** 346 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 347 * 348 * @handle: smu_context pointer 349 * @block_type: the IP block to power gate/ungate 350 * @gate: to power gate if true, ungate otherwise 351 * @inst: the instance of the IP block to power gate/ungate 352 * 353 * This API uses no smu->mutex lock protection due to: 354 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 355 * This is guarded to be race condition free by the caller. 356 * 2. Or get called on user setting request of power_dpm_force_performance_level. 357 * Under this case, the smu->mutex lock protection is already enforced on 358 * the parent API smu_force_performance_level of the call path. 359 */ 360 static int smu_dpm_set_power_gate(void *handle, 361 uint32_t block_type, 362 bool gate, 363 int inst) 364 { 365 struct smu_context *smu = handle; 366 int ret = 0; 367 368 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 369 dev_WARN(smu->adev->dev, 370 "SMU uninitialized but power %s requested for %u!\n", 371 gate ? "gate" : "ungate", block_type); 372 return -EOPNOTSUPP; 373 } 374 375 switch (block_type) { 376 /* 377 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 378 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 379 */ 380 case AMD_IP_BLOCK_TYPE_UVD: 381 case AMD_IP_BLOCK_TYPE_VCN: 382 ret = smu_dpm_set_vcn_enable(smu, !gate, inst); 383 if (ret) 384 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n", 385 gate ? "gate" : "ungate", inst); 386 break; 387 case AMD_IP_BLOCK_TYPE_GFX: 388 ret = smu_gfx_off_control(smu, gate); 389 if (ret) 390 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 391 gate ? "enable" : "disable"); 392 break; 393 case AMD_IP_BLOCK_TYPE_SDMA: 394 ret = smu_powergate_sdma(smu, gate); 395 if (ret) 396 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 397 gate ? "gate" : "ungate"); 398 break; 399 case AMD_IP_BLOCK_TYPE_JPEG: 400 ret = smu_dpm_set_jpeg_enable(smu, !gate); 401 if (ret) 402 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 403 gate ? "gate" : "ungate"); 404 break; 405 case AMD_IP_BLOCK_TYPE_VPE: 406 ret = smu_dpm_set_vpe_enable(smu, !gate); 407 if (ret) 408 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 409 gate ? "gate" : "ungate"); 410 break; 411 default: 412 dev_err(smu->adev->dev, "Unsupported block type!\n"); 413 return -EINVAL; 414 } 415 416 return ret; 417 } 418 419 /** 420 * smu_set_user_clk_dependencies - set user profile clock dependencies 421 * 422 * @smu: smu_context pointer 423 * @clk: enum smu_clk_type type 424 * 425 * Enable/Disable the clock dependency for the @clk type. 426 */ 427 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 428 { 429 if (smu->adev->in_suspend) 430 return; 431 432 if (clk == SMU_MCLK) { 433 smu->user_dpm_profile.clk_dependency = 0; 434 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 435 } else if (clk == SMU_FCLK) { 436 /* MCLK takes precedence over FCLK */ 437 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 438 return; 439 440 smu->user_dpm_profile.clk_dependency = 0; 441 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 442 } else if (clk == SMU_SOCCLK) { 443 /* MCLK takes precedence over SOCCLK */ 444 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 445 return; 446 447 smu->user_dpm_profile.clk_dependency = 0; 448 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 449 } else 450 /* Add clk dependencies here, if any */ 451 return; 452 } 453 454 /** 455 * smu_restore_dpm_user_profile - reinstate user dpm profile 456 * 457 * @smu: smu_context pointer 458 * 459 * Restore the saved user power configurations include power limit, 460 * clock frequencies, fan control mode and fan speed. 461 */ 462 static void smu_restore_dpm_user_profile(struct smu_context *smu) 463 { 464 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 465 int ret = 0; 466 467 if (!smu->adev->in_suspend) 468 return; 469 470 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 471 return; 472 473 /* Enable restore flag */ 474 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 475 476 /* set the user dpm power limit */ 477 if (smu->user_dpm_profile.power_limit) { 478 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 479 if (ret) 480 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 481 } 482 483 /* set the user dpm clock configurations */ 484 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 485 enum smu_clk_type clk_type; 486 487 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 488 /* 489 * Iterate over smu clk type and force the saved user clk 490 * configs, skip if clock dependency is enabled 491 */ 492 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 493 smu->user_dpm_profile.clk_mask[clk_type]) { 494 ret = smu_force_smuclk_levels(smu, clk_type, 495 smu->user_dpm_profile.clk_mask[clk_type]); 496 if (ret) 497 dev_err(smu->adev->dev, 498 "Failed to set clock type = %d\n", clk_type); 499 } 500 } 501 } 502 503 /* set the user dpm fan configurations */ 504 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 505 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 506 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 507 if (ret != -EOPNOTSUPP) { 508 smu->user_dpm_profile.fan_speed_pwm = 0; 509 smu->user_dpm_profile.fan_speed_rpm = 0; 510 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 511 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 512 } 513 514 if (smu->user_dpm_profile.fan_speed_pwm) { 515 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 516 if (ret != -EOPNOTSUPP) 517 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 518 } 519 520 if (smu->user_dpm_profile.fan_speed_rpm) { 521 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 522 if (ret != -EOPNOTSUPP) 523 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 524 } 525 } 526 527 /* Restore user customized OD settings */ 528 if (smu->user_dpm_profile.user_od) { 529 if (smu->ppt_funcs->restore_user_od_settings) { 530 ret = smu->ppt_funcs->restore_user_od_settings(smu); 531 if (ret) 532 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 533 } 534 } 535 536 /* Disable restore flag */ 537 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 538 } 539 540 static int smu_get_power_num_states(void *handle, 541 struct pp_states_info *state_info) 542 { 543 if (!state_info) 544 return -EINVAL; 545 546 /* not support power state */ 547 memset(state_info, 0, sizeof(struct pp_states_info)); 548 state_info->nums = 1; 549 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 550 551 return 0; 552 } 553 554 bool is_support_sw_smu(struct amdgpu_device *adev) 555 { 556 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 557 if (adev->asic_type == CHIP_VEGA20) 558 return false; 559 560 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && 561 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) 562 return true; 563 564 return false; 565 } 566 567 bool is_support_cclk_dpm(struct amdgpu_device *adev) 568 { 569 struct smu_context *smu = adev->powerplay.pp_handle; 570 571 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 572 return false; 573 574 return true; 575 } 576 577 578 static int smu_sys_get_pp_table(void *handle, 579 char **table) 580 { 581 struct smu_context *smu = handle; 582 struct smu_table_context *smu_table = &smu->smu_table; 583 584 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 585 return -EOPNOTSUPP; 586 587 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 588 return -EINVAL; 589 590 if (smu_table->hardcode_pptable) 591 *table = smu_table->hardcode_pptable; 592 else 593 *table = smu_table->power_play_table; 594 595 return smu_table->power_play_table_size; 596 } 597 598 static int smu_sys_set_pp_table(void *handle, 599 const char *buf, 600 size_t size) 601 { 602 struct smu_context *smu = handle; 603 struct smu_table_context *smu_table = &smu->smu_table; 604 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 605 int ret = 0; 606 607 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 608 return -EOPNOTSUPP; 609 610 if (header->usStructureSize != size) { 611 dev_err(smu->adev->dev, "pp table size not matched !\n"); 612 return -EIO; 613 } 614 615 if (!smu_table->hardcode_pptable || smu_table->power_play_table_size < size) { 616 kfree(smu_table->hardcode_pptable); 617 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 618 if (!smu_table->hardcode_pptable) 619 return -ENOMEM; 620 } 621 622 memcpy(smu_table->hardcode_pptable, buf, size); 623 smu_table->power_play_table = smu_table->hardcode_pptable; 624 smu_table->power_play_table_size = size; 625 626 /* 627 * Special hw_fini action(for Navi1x, the DPMs disablement will be 628 * skipped) may be needed for custom pptable uploading. 629 */ 630 smu->uploading_custom_pp_table = true; 631 632 ret = smu_reset(smu); 633 if (ret) 634 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 635 636 smu->uploading_custom_pp_table = false; 637 638 return ret; 639 } 640 641 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 642 { 643 struct smu_feature *feature = &smu->smu_feature; 644 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 645 int ret = 0; 646 647 /* 648 * With SCPM enabled, the allowed featuremasks setting(via 649 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 650 * That means there is no way to let PMFW knows the settings below. 651 * Thus, we just assume all the features are allowed under 652 * such scenario. 653 */ 654 if (smu->adev->scpm_enabled) { 655 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 656 return 0; 657 } 658 659 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 660 661 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 662 SMU_FEATURE_MAX/32); 663 if (ret) 664 return ret; 665 666 bitmap_or(feature->allowed, feature->allowed, 667 (unsigned long *)allowed_feature_mask, 668 feature->feature_num); 669 670 return ret; 671 } 672 673 static int smu_set_funcs(struct amdgpu_device *adev) 674 { 675 struct smu_context *smu = adev->powerplay.pp_handle; 676 677 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 678 smu->od_enabled = true; 679 680 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 681 case IP_VERSION(11, 0, 0): 682 case IP_VERSION(11, 0, 5): 683 case IP_VERSION(11, 0, 9): 684 navi10_set_ppt_funcs(smu); 685 break; 686 case IP_VERSION(11, 0, 7): 687 case IP_VERSION(11, 0, 11): 688 case IP_VERSION(11, 0, 12): 689 case IP_VERSION(11, 0, 13): 690 sienna_cichlid_set_ppt_funcs(smu); 691 break; 692 case IP_VERSION(12, 0, 0): 693 case IP_VERSION(12, 0, 1): 694 renoir_set_ppt_funcs(smu); 695 break; 696 case IP_VERSION(11, 5, 0): 697 case IP_VERSION(11, 5, 2): 698 vangogh_set_ppt_funcs(smu); 699 break; 700 case IP_VERSION(13, 0, 1): 701 case IP_VERSION(13, 0, 3): 702 case IP_VERSION(13, 0, 8): 703 yellow_carp_set_ppt_funcs(smu); 704 break; 705 case IP_VERSION(13, 0, 4): 706 case IP_VERSION(13, 0, 11): 707 smu_v13_0_4_set_ppt_funcs(smu); 708 break; 709 case IP_VERSION(13, 0, 5): 710 smu_v13_0_5_set_ppt_funcs(smu); 711 break; 712 case IP_VERSION(11, 0, 8): 713 cyan_skillfish_set_ppt_funcs(smu); 714 break; 715 case IP_VERSION(11, 0, 2): 716 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 717 arcturus_set_ppt_funcs(smu); 718 /* OD is not supported on Arcturus */ 719 smu->od_enabled = false; 720 break; 721 case IP_VERSION(13, 0, 2): 722 aldebaran_set_ppt_funcs(smu); 723 /* Enable pp_od_clk_voltage node */ 724 smu->od_enabled = true; 725 break; 726 case IP_VERSION(13, 0, 0): 727 case IP_VERSION(13, 0, 10): 728 smu_v13_0_0_set_ppt_funcs(smu); 729 break; 730 case IP_VERSION(13, 0, 6): 731 case IP_VERSION(13, 0, 14): 732 case IP_VERSION(13, 0, 12): 733 smu_v13_0_6_set_ppt_funcs(smu); 734 /* Enable pp_od_clk_voltage node */ 735 smu->od_enabled = true; 736 break; 737 case IP_VERSION(13, 0, 7): 738 smu_v13_0_7_set_ppt_funcs(smu); 739 break; 740 case IP_VERSION(14, 0, 0): 741 case IP_VERSION(14, 0, 1): 742 case IP_VERSION(14, 0, 4): 743 case IP_VERSION(14, 0, 5): 744 smu_v14_0_0_set_ppt_funcs(smu); 745 break; 746 case IP_VERSION(14, 0, 2): 747 case IP_VERSION(14, 0, 3): 748 smu_v14_0_2_set_ppt_funcs(smu); 749 break; 750 default: 751 return -EINVAL; 752 } 753 754 return 0; 755 } 756 757 static int smu_early_init(struct amdgpu_ip_block *ip_block) 758 { 759 struct amdgpu_device *adev = ip_block->adev; 760 struct smu_context *smu; 761 int r; 762 763 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 764 if (!smu) 765 return -ENOMEM; 766 767 smu->adev = adev; 768 smu->pm_enabled = !!amdgpu_dpm; 769 smu->is_apu = false; 770 smu->smu_baco.state = SMU_BACO_STATE_NONE; 771 smu->smu_baco.platform_support = false; 772 smu->smu_baco.maco_support = false; 773 smu->user_dpm_profile.fan_mode = -1; 774 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN; 775 776 mutex_init(&smu->message_lock); 777 778 adev->powerplay.pp_handle = smu; 779 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 780 781 r = smu_set_funcs(adev); 782 if (r) 783 return r; 784 return smu_init_microcode(smu); 785 } 786 787 static int smu_set_default_dpm_table(struct smu_context *smu) 788 { 789 struct amdgpu_device *adev = smu->adev; 790 struct smu_power_context *smu_power = &smu->smu_power; 791 struct smu_power_gate *power_gate = &smu_power->power_gate; 792 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i; 793 int ret = 0; 794 795 if (!smu->ppt_funcs->set_default_dpm_table) 796 return 0; 797 798 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 799 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 800 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]); 801 } 802 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 803 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 804 805 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 806 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 807 ret = smu_dpm_set_vcn_enable(smu, true, i); 808 if (ret) 809 return ret; 810 } 811 } 812 813 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 814 ret = smu_dpm_set_jpeg_enable(smu, true); 815 if (ret) 816 goto err_out; 817 } 818 819 ret = smu->ppt_funcs->set_default_dpm_table(smu); 820 if (ret) 821 dev_err(smu->adev->dev, 822 "Failed to setup default dpm clock tables!\n"); 823 824 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 825 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 826 err_out: 827 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 828 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 829 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i); 830 } 831 832 return ret; 833 } 834 835 static int smu_apply_default_config_table_settings(struct smu_context *smu) 836 { 837 struct amdgpu_device *adev = smu->adev; 838 int ret = 0; 839 840 ret = smu_get_default_config_table_settings(smu, 841 &adev->pm.config_table); 842 if (ret) 843 return ret; 844 845 return smu_set_config_table(smu, &adev->pm.config_table); 846 } 847 848 static int smu_late_init(struct amdgpu_ip_block *ip_block) 849 { 850 struct amdgpu_device *adev = ip_block->adev; 851 struct smu_context *smu = adev->powerplay.pp_handle; 852 int ret = 0; 853 854 smu_set_fine_grain_gfx_freq_parameters(smu); 855 856 if (!smu->pm_enabled) 857 return 0; 858 859 ret = smu_post_init(smu); 860 if (ret) { 861 dev_err(adev->dev, "Failed to post smu init!\n"); 862 return ret; 863 } 864 865 /* 866 * Explicitly notify PMFW the power mode the system in. Since 867 * the PMFW may boot the ASIC with a different mode. 868 * For those supporting ACDC switch via gpio, PMFW will 869 * handle the switch automatically. Driver involvement 870 * is unnecessary. 871 */ 872 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 873 smu_set_ac_dc(smu); 874 875 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 876 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 877 return 0; 878 879 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 880 ret = smu_set_default_od_settings(smu); 881 if (ret) { 882 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 883 return ret; 884 } 885 } 886 887 ret = smu_populate_umd_state_clk(smu); 888 if (ret) { 889 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 890 return ret; 891 } 892 893 ret = smu_get_asic_power_limits(smu, 894 &smu->current_power_limit, 895 &smu->default_power_limit, 896 &smu->max_power_limit, 897 &smu->min_power_limit); 898 if (ret) { 899 dev_err(adev->dev, "Failed to get asic power limits!\n"); 900 return ret; 901 } 902 903 if (!amdgpu_sriov_vf(adev)) 904 smu_get_unique_id(smu); 905 906 smu_get_fan_parameters(smu); 907 908 smu_handle_task(smu, 909 smu->smu_dpm.dpm_level, 910 AMD_PP_TASK_COMPLETE_INIT); 911 912 ret = smu_apply_default_config_table_settings(smu); 913 if (ret && (ret != -EOPNOTSUPP)) { 914 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 915 return ret; 916 } 917 918 smu_restore_dpm_user_profile(smu); 919 920 return 0; 921 } 922 923 static int smu_init_fb_allocations(struct smu_context *smu) 924 { 925 struct amdgpu_device *adev = smu->adev; 926 struct smu_table_context *smu_table = &smu->smu_table; 927 struct smu_table *tables = smu_table->tables; 928 struct smu_table *driver_table = &(smu_table->driver_table); 929 uint32_t max_table_size = 0; 930 int ret, i; 931 932 /* VRAM allocation for tool table */ 933 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 934 ret = amdgpu_bo_create_kernel(adev, 935 tables[SMU_TABLE_PMSTATUSLOG].size, 936 tables[SMU_TABLE_PMSTATUSLOG].align, 937 tables[SMU_TABLE_PMSTATUSLOG].domain, 938 &tables[SMU_TABLE_PMSTATUSLOG].bo, 939 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 940 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 941 if (ret) { 942 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 943 return ret; 944 } 945 } 946 947 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 948 /* VRAM allocation for driver table */ 949 for (i = 0; i < SMU_TABLE_COUNT; i++) { 950 if (tables[i].size == 0) 951 continue; 952 953 /* If one of the tables has VRAM domain restriction, keep it in 954 * VRAM 955 */ 956 if ((tables[i].domain & 957 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 958 AMDGPU_GEM_DOMAIN_VRAM) 959 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 960 961 if (i == SMU_TABLE_PMSTATUSLOG) 962 continue; 963 964 if (max_table_size < tables[i].size) 965 max_table_size = tables[i].size; 966 } 967 968 driver_table->size = max_table_size; 969 driver_table->align = PAGE_SIZE; 970 971 ret = amdgpu_bo_create_kernel(adev, 972 driver_table->size, 973 driver_table->align, 974 driver_table->domain, 975 &driver_table->bo, 976 &driver_table->mc_address, 977 &driver_table->cpu_addr); 978 if (ret) { 979 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 980 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 981 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 982 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 983 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 984 } 985 986 return ret; 987 } 988 989 static int smu_fini_fb_allocations(struct smu_context *smu) 990 { 991 struct smu_table_context *smu_table = &smu->smu_table; 992 struct smu_table *tables = smu_table->tables; 993 struct smu_table *driver_table = &(smu_table->driver_table); 994 995 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 996 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 997 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 998 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 999 1000 amdgpu_bo_free_kernel(&driver_table->bo, 1001 &driver_table->mc_address, 1002 &driver_table->cpu_addr); 1003 1004 return 0; 1005 } 1006 1007 /** 1008 * smu_alloc_memory_pool - allocate memory pool in the system memory 1009 * 1010 * @smu: amdgpu_device pointer 1011 * 1012 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 1013 * and DramLogSetDramAddr can notify it changed. 1014 * 1015 * Returns 0 on success, error on failure. 1016 */ 1017 static int smu_alloc_memory_pool(struct smu_context *smu) 1018 { 1019 struct amdgpu_device *adev = smu->adev; 1020 struct smu_table_context *smu_table = &smu->smu_table; 1021 struct smu_table *memory_pool = &smu_table->memory_pool; 1022 uint64_t pool_size = smu->pool_size; 1023 int ret = 0; 1024 1025 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1026 return ret; 1027 1028 memory_pool->size = pool_size; 1029 memory_pool->align = PAGE_SIZE; 1030 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 1031 1032 switch (pool_size) { 1033 case SMU_MEMORY_POOL_SIZE_256_MB: 1034 case SMU_MEMORY_POOL_SIZE_512_MB: 1035 case SMU_MEMORY_POOL_SIZE_1_GB: 1036 case SMU_MEMORY_POOL_SIZE_2_GB: 1037 ret = amdgpu_bo_create_kernel(adev, 1038 memory_pool->size, 1039 memory_pool->align, 1040 memory_pool->domain, 1041 &memory_pool->bo, 1042 &memory_pool->mc_address, 1043 &memory_pool->cpu_addr); 1044 if (ret) 1045 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1046 break; 1047 default: 1048 break; 1049 } 1050 1051 return ret; 1052 } 1053 1054 static int smu_free_memory_pool(struct smu_context *smu) 1055 { 1056 struct smu_table_context *smu_table = &smu->smu_table; 1057 struct smu_table *memory_pool = &smu_table->memory_pool; 1058 1059 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1060 return 0; 1061 1062 amdgpu_bo_free_kernel(&memory_pool->bo, 1063 &memory_pool->mc_address, 1064 &memory_pool->cpu_addr); 1065 1066 memset(memory_pool, 0, sizeof(struct smu_table)); 1067 1068 return 0; 1069 } 1070 1071 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1072 { 1073 struct smu_table_context *smu_table = &smu->smu_table; 1074 struct smu_table *dummy_read_1_table = 1075 &smu_table->dummy_read_1_table; 1076 struct amdgpu_device *adev = smu->adev; 1077 int ret = 0; 1078 1079 if (!dummy_read_1_table->size) 1080 return 0; 1081 1082 ret = amdgpu_bo_create_kernel(adev, 1083 dummy_read_1_table->size, 1084 dummy_read_1_table->align, 1085 dummy_read_1_table->domain, 1086 &dummy_read_1_table->bo, 1087 &dummy_read_1_table->mc_address, 1088 &dummy_read_1_table->cpu_addr); 1089 if (ret) 1090 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1091 1092 return ret; 1093 } 1094 1095 static void smu_free_dummy_read_table(struct smu_context *smu) 1096 { 1097 struct smu_table_context *smu_table = &smu->smu_table; 1098 struct smu_table *dummy_read_1_table = 1099 &smu_table->dummy_read_1_table; 1100 1101 1102 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1103 &dummy_read_1_table->mc_address, 1104 &dummy_read_1_table->cpu_addr); 1105 1106 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1107 } 1108 1109 static int smu_smc_table_sw_init(struct smu_context *smu) 1110 { 1111 int ret; 1112 1113 /** 1114 * Create smu_table structure, and init smc tables such as 1115 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1116 */ 1117 ret = smu_init_smc_tables(smu); 1118 if (ret) { 1119 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1120 return ret; 1121 } 1122 1123 /** 1124 * Create smu_power_context structure, and allocate smu_dpm_context and 1125 * context size to fill the smu_power_context data. 1126 */ 1127 ret = smu_init_power(smu); 1128 if (ret) { 1129 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1130 return ret; 1131 } 1132 1133 /* 1134 * allocate vram bos to store smc table contents. 1135 */ 1136 ret = smu_init_fb_allocations(smu); 1137 if (ret) 1138 return ret; 1139 1140 ret = smu_alloc_memory_pool(smu); 1141 if (ret) 1142 return ret; 1143 1144 ret = smu_alloc_dummy_read_table(smu); 1145 if (ret) 1146 return ret; 1147 1148 ret = smu_i2c_init(smu); 1149 if (ret) 1150 return ret; 1151 1152 return 0; 1153 } 1154 1155 static int smu_smc_table_sw_fini(struct smu_context *smu) 1156 { 1157 int ret; 1158 1159 smu_i2c_fini(smu); 1160 1161 smu_free_dummy_read_table(smu); 1162 1163 ret = smu_free_memory_pool(smu); 1164 if (ret) 1165 return ret; 1166 1167 ret = smu_fini_fb_allocations(smu); 1168 if (ret) 1169 return ret; 1170 1171 ret = smu_fini_power(smu); 1172 if (ret) { 1173 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1174 return ret; 1175 } 1176 1177 ret = smu_fini_smc_tables(smu); 1178 if (ret) { 1179 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1180 return ret; 1181 } 1182 1183 return 0; 1184 } 1185 1186 static void smu_throttling_logging_work_fn(struct work_struct *work) 1187 { 1188 struct smu_context *smu = container_of(work, struct smu_context, 1189 throttling_logging_work); 1190 1191 smu_log_thermal_throttling(smu); 1192 } 1193 1194 static void smu_interrupt_work_fn(struct work_struct *work) 1195 { 1196 struct smu_context *smu = container_of(work, struct smu_context, 1197 interrupt_work); 1198 1199 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1200 smu->ppt_funcs->interrupt_work(smu); 1201 } 1202 1203 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1204 { 1205 struct smu_context *smu = 1206 container_of(work, struct smu_context, swctf_delayed_work.work); 1207 struct smu_temperature_range *range = 1208 &smu->thermal_range; 1209 struct amdgpu_device *adev = smu->adev; 1210 uint32_t hotspot_tmp, size; 1211 1212 /* 1213 * If the hotspot temperature is confirmed as below SW CTF setting point 1214 * after the delay enforced, nothing will be done. 1215 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1216 */ 1217 if (range->software_shutdown_temp && 1218 smu->ppt_funcs->read_sensor && 1219 !smu->ppt_funcs->read_sensor(smu, 1220 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1221 &hotspot_tmp, 1222 &size) && 1223 hotspot_tmp / 1000 < range->software_shutdown_temp) 1224 return; 1225 1226 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1227 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1228 orderly_poweroff(true); 1229 } 1230 1231 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1232 { 1233 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1234 struct smu_dpm_policy_ctxt *policy_ctxt; 1235 struct smu_dpm_policy *policy; 1236 1237 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1238 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1239 if (policy) 1240 policy->current_level = XGMI_PLPD_DEFAULT; 1241 return; 1242 } 1243 1244 /* PMFW put PLPD into default policy after enabling the feature */ 1245 if (smu_feature_is_enabled(smu, 1246 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1247 if (policy) 1248 policy->current_level = XGMI_PLPD_DEFAULT; 1249 } else { 1250 policy_ctxt = dpm_ctxt->dpm_policies; 1251 if (policy_ctxt) 1252 policy_ctxt->policy_mask &= 1253 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1254 } 1255 } 1256 1257 static void smu_init_power_profile(struct smu_context *smu) 1258 { 1259 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) 1260 smu->power_profile_mode = 1261 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1262 smu_power_profile_mode_get(smu, smu->power_profile_mode); 1263 } 1264 1265 static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1266 { 1267 struct amdgpu_device *adev = ip_block->adev; 1268 struct smu_context *smu = adev->powerplay.pp_handle; 1269 int i, ret; 1270 1271 smu->pool_size = adev->pm.smu_prv_buffer_size; 1272 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1273 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1274 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1275 1276 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1277 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1278 atomic64_set(&smu->throttle_int_counter, 0); 1279 smu->watermarks_bitmap = 0; 1280 1281 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1282 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1); 1283 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1284 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1285 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1286 1287 smu_init_power_profile(smu); 1288 smu->display_config = &adev->pm.pm_display_cfg; 1289 1290 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1291 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1292 1293 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1294 smu_swctf_delayed_work_handler); 1295 1296 ret = smu_smc_table_sw_init(smu); 1297 if (ret) { 1298 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1299 return ret; 1300 } 1301 1302 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1303 ret = smu_get_vbios_bootup_values(smu); 1304 if (ret) { 1305 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1306 return ret; 1307 } 1308 1309 ret = smu_init_pptable_microcode(smu); 1310 if (ret) { 1311 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1312 return ret; 1313 } 1314 1315 ret = smu_register_irq_handler(smu); 1316 if (ret) { 1317 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1318 return ret; 1319 } 1320 1321 /* If there is no way to query fan control mode, fan control is not supported */ 1322 if (!smu->ppt_funcs->get_fan_control_mode) 1323 smu->adev->pm.no_fan = true; 1324 1325 return 0; 1326 } 1327 1328 static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1329 { 1330 struct amdgpu_device *adev = ip_block->adev; 1331 struct smu_context *smu = adev->powerplay.pp_handle; 1332 int ret; 1333 1334 ret = smu_smc_table_sw_fini(smu); 1335 if (ret) { 1336 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1337 return ret; 1338 } 1339 1340 if (smu->custom_profile_params) { 1341 kfree(smu->custom_profile_params); 1342 smu->custom_profile_params = NULL; 1343 } 1344 1345 smu_fini_microcode(smu); 1346 1347 return 0; 1348 } 1349 1350 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1351 { 1352 struct amdgpu_device *adev = smu->adev; 1353 struct smu_temperature_range *range = 1354 &smu->thermal_range; 1355 int ret = 0; 1356 1357 if (!smu->ppt_funcs->get_thermal_temperature_range) 1358 return 0; 1359 1360 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1361 if (ret) 1362 return ret; 1363 1364 adev->pm.dpm.thermal.min_temp = range->min; 1365 adev->pm.dpm.thermal.max_temp = range->max; 1366 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1367 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1368 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1369 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1370 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1371 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1372 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1373 1374 return ret; 1375 } 1376 1377 /** 1378 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1379 * 1380 * @smu: smu_context pointer 1381 * 1382 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1383 * Returns 0 on success, error on failure. 1384 */ 1385 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1386 { 1387 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1388 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1389 struct amdgpu_device *adev = smu->adev; 1390 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1391 uint64_t start, end; 1392 int ret, i, j; 1393 1394 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1395 if (ret) { 1396 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1397 return ret; 1398 } 1399 1400 /* 1401 * The exclusion ranges array we got might be filled with holes and duplicate 1402 * entries. For example: 1403 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1404 * We need to do some sortups to eliminate those holes and duplicate entries. 1405 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1406 */ 1407 for (i = 0; i < num_of_wbrf_ranges; i++) { 1408 start = wifi_bands[i].start; 1409 end = wifi_bands[i].end; 1410 1411 /* get the last valid entry to fill the intermediate hole */ 1412 if (!start && !end) { 1413 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1414 if (wifi_bands[j].start && wifi_bands[j].end) 1415 break; 1416 1417 /* no valid entry left */ 1418 if (j <= i) 1419 break; 1420 1421 start = wifi_bands[i].start = wifi_bands[j].start; 1422 end = wifi_bands[i].end = wifi_bands[j].end; 1423 wifi_bands[j].start = 0; 1424 wifi_bands[j].end = 0; 1425 num_of_wbrf_ranges = j; 1426 } 1427 1428 /* eliminate duplicate entries */ 1429 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1430 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1431 wifi_bands[j].start = 0; 1432 wifi_bands[j].end = 0; 1433 } 1434 } 1435 } 1436 1437 /* Send the sorted wifi_bands to PMFW */ 1438 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1439 /* Try to set the wifi_bands again */ 1440 if (unlikely(ret == -EBUSY)) { 1441 mdelay(5); 1442 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1443 } 1444 1445 return ret; 1446 } 1447 1448 /** 1449 * smu_wbrf_event_handler - handle notify events 1450 * 1451 * @nb: notifier block 1452 * @action: event type 1453 * @_arg: event data 1454 * 1455 * Calls relevant amdgpu function in response to wbrf event 1456 * notification from kernel. 1457 */ 1458 static int smu_wbrf_event_handler(struct notifier_block *nb, 1459 unsigned long action, void *_arg) 1460 { 1461 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1462 1463 switch (action) { 1464 case WBRF_CHANGED: 1465 schedule_delayed_work(&smu->wbrf_delayed_work, 1466 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1467 break; 1468 default: 1469 return NOTIFY_DONE; 1470 } 1471 1472 return NOTIFY_OK; 1473 } 1474 1475 /** 1476 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1477 * 1478 * @work: struct work_struct pointer 1479 * 1480 * Flood is over and driver will consume the latest exclusion ranges. 1481 */ 1482 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1483 { 1484 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1485 1486 smu_wbrf_handle_exclusion_ranges(smu); 1487 } 1488 1489 /** 1490 * smu_wbrf_support_check - check wbrf support 1491 * 1492 * @smu: smu_context pointer 1493 * 1494 * Verifies the ACPI interface whether wbrf is supported. 1495 */ 1496 static void smu_wbrf_support_check(struct smu_context *smu) 1497 { 1498 struct amdgpu_device *adev = smu->adev; 1499 1500 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1501 acpi_amd_wbrf_supported_consumer(adev->dev); 1502 1503 if (smu->wbrf_supported) 1504 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1505 } 1506 1507 /** 1508 * smu_wbrf_init - init driver wbrf support 1509 * 1510 * @smu: smu_context pointer 1511 * 1512 * Verifies the AMD ACPI interfaces and registers with the wbrf 1513 * notifier chain if wbrf feature is supported. 1514 * Returns 0 on success, error on failure. 1515 */ 1516 static int smu_wbrf_init(struct smu_context *smu) 1517 { 1518 int ret; 1519 1520 if (!smu->wbrf_supported) 1521 return 0; 1522 1523 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1524 1525 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1526 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1527 if (ret) 1528 return ret; 1529 1530 /* 1531 * Some wifiband exclusion ranges may be already there 1532 * before our driver loaded. To make sure our driver 1533 * is awared of those exclusion ranges. 1534 */ 1535 schedule_delayed_work(&smu->wbrf_delayed_work, 1536 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1537 1538 return 0; 1539 } 1540 1541 /** 1542 * smu_wbrf_fini - tear down driver wbrf support 1543 * 1544 * @smu: smu_context pointer 1545 * 1546 * Unregisters with the wbrf notifier chain. 1547 */ 1548 static void smu_wbrf_fini(struct smu_context *smu) 1549 { 1550 if (!smu->wbrf_supported) 1551 return; 1552 1553 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1554 1555 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1556 } 1557 1558 static int smu_smc_hw_setup(struct smu_context *smu) 1559 { 1560 struct smu_feature *feature = &smu->smu_feature; 1561 struct amdgpu_device *adev = smu->adev; 1562 uint8_t pcie_gen = 0, pcie_width = 0; 1563 uint64_t features_supported; 1564 int ret = 0; 1565 1566 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1567 case IP_VERSION(11, 0, 7): 1568 case IP_VERSION(11, 0, 11): 1569 case IP_VERSION(11, 5, 0): 1570 case IP_VERSION(11, 5, 2): 1571 case IP_VERSION(11, 0, 12): 1572 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1573 dev_info(adev->dev, "dpm has been enabled\n"); 1574 ret = smu_system_features_control(smu, true); 1575 if (ret) 1576 dev_err(adev->dev, "Failed system features control!\n"); 1577 return ret; 1578 } 1579 break; 1580 default: 1581 break; 1582 } 1583 1584 ret = smu_init_display_count(smu, 0); 1585 if (ret) { 1586 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1587 return ret; 1588 } 1589 1590 ret = smu_set_driver_table_location(smu); 1591 if (ret) { 1592 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1593 return ret; 1594 } 1595 1596 /* 1597 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1598 */ 1599 ret = smu_set_tool_table_location(smu); 1600 if (ret) { 1601 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1602 return ret; 1603 } 1604 1605 /* 1606 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1607 * pool location. 1608 */ 1609 ret = smu_notify_memory_pool_location(smu); 1610 if (ret) { 1611 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1612 return ret; 1613 } 1614 1615 /* 1616 * It is assumed the pptable used before runpm is same as 1617 * the one used afterwards. Thus, we can reuse the stored 1618 * copy and do not need to resetup the pptable again. 1619 */ 1620 if (!adev->in_runpm) { 1621 ret = smu_setup_pptable(smu); 1622 if (ret) { 1623 dev_err(adev->dev, "Failed to setup pptable!\n"); 1624 return ret; 1625 } 1626 } 1627 1628 /* smu_dump_pptable(smu); */ 1629 1630 /* 1631 * With SCPM enabled, PSP is responsible for the PPTable transferring 1632 * (to SMU). Driver involvement is not needed and permitted. 1633 */ 1634 if (!adev->scpm_enabled) { 1635 /* 1636 * Copy pptable bo in the vram to smc with SMU MSGs such as 1637 * SetDriverDramAddr and TransferTableDram2Smu. 1638 */ 1639 ret = smu_write_pptable(smu); 1640 if (ret) { 1641 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1642 return ret; 1643 } 1644 } 1645 1646 /* issue Run*Btc msg */ 1647 ret = smu_run_btc(smu); 1648 if (ret) 1649 return ret; 1650 1651 /* Enable UclkShadow on wbrf supported */ 1652 if (smu->wbrf_supported) { 1653 ret = smu_enable_uclk_shadow(smu, true); 1654 if (ret) { 1655 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1656 return ret; 1657 } 1658 } 1659 1660 /* 1661 * With SCPM enabled, these actions(and relevant messages) are 1662 * not needed and permitted. 1663 */ 1664 if (!adev->scpm_enabled) { 1665 ret = smu_feature_set_allowed_mask(smu); 1666 if (ret) { 1667 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1668 return ret; 1669 } 1670 } 1671 1672 ret = smu_system_features_control(smu, true); 1673 if (ret) { 1674 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1675 return ret; 1676 } 1677 1678 smu_init_xgmi_plpd_mode(smu); 1679 1680 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1681 if (ret) { 1682 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1683 return ret; 1684 } 1685 bitmap_copy(feature->supported, 1686 (unsigned long *)&features_supported, 1687 feature->feature_num); 1688 1689 if (!smu_is_dpm_running(smu)) 1690 dev_info(adev->dev, "dpm has been disabled\n"); 1691 1692 /* 1693 * Set initialized values (get from vbios) to dpm tables context such as 1694 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1695 * type of clks. 1696 */ 1697 ret = smu_set_default_dpm_table(smu); 1698 if (ret) { 1699 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1700 return ret; 1701 } 1702 1703 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) 1704 pcie_gen = 4; 1705 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1706 pcie_gen = 3; 1707 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1708 pcie_gen = 2; 1709 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1710 pcie_gen = 1; 1711 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1712 pcie_gen = 0; 1713 1714 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1715 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1716 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1717 */ 1718 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) 1719 pcie_width = 7; 1720 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1721 pcie_width = 6; 1722 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1723 pcie_width = 5; 1724 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1725 pcie_width = 4; 1726 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1727 pcie_width = 3; 1728 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1729 pcie_width = 2; 1730 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1731 pcie_width = 1; 1732 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1733 if (ret) { 1734 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1735 return ret; 1736 } 1737 1738 ret = smu_get_thermal_temperature_range(smu); 1739 if (ret) { 1740 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1741 return ret; 1742 } 1743 1744 ret = smu_enable_thermal_alert(smu); 1745 if (ret) { 1746 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1747 return ret; 1748 } 1749 1750 ret = smu_notify_display_change(smu); 1751 if (ret) { 1752 dev_err(adev->dev, "Failed to notify display change!\n"); 1753 return ret; 1754 } 1755 1756 /* 1757 * Set min deep sleep dce fclk with bootup value from vbios via 1758 * SetMinDeepSleepDcefclk MSG. 1759 */ 1760 ret = smu_set_min_dcef_deep_sleep(smu, 1761 smu->smu_table.boot_values.dcefclk / 100); 1762 if (ret) { 1763 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1764 return ret; 1765 } 1766 1767 /* Init wbrf support. Properly setup the notifier */ 1768 ret = smu_wbrf_init(smu); 1769 if (ret) 1770 dev_err(adev->dev, "Error during wbrf init call\n"); 1771 1772 return ret; 1773 } 1774 1775 static int smu_start_smc_engine(struct smu_context *smu) 1776 { 1777 struct amdgpu_device *adev = smu->adev; 1778 int ret = 0; 1779 1780 smu->smc_fw_state = SMU_FW_INIT; 1781 1782 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1783 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1784 if (smu->ppt_funcs->load_microcode) { 1785 ret = smu->ppt_funcs->load_microcode(smu); 1786 if (ret) 1787 return ret; 1788 } 1789 } 1790 } 1791 1792 if (smu->ppt_funcs->check_fw_status) { 1793 ret = smu->ppt_funcs->check_fw_status(smu); 1794 if (ret) { 1795 dev_err(adev->dev, "SMC is not ready\n"); 1796 return ret; 1797 } 1798 } 1799 1800 /* 1801 * Send msg GetDriverIfVersion to check if the return value is equal 1802 * with DRIVER_IF_VERSION of smc header. 1803 */ 1804 ret = smu_check_fw_version(smu); 1805 if (ret) 1806 return ret; 1807 1808 return ret; 1809 } 1810 1811 static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1812 { 1813 int i, ret; 1814 struct amdgpu_device *adev = ip_block->adev; 1815 struct smu_context *smu = adev->powerplay.pp_handle; 1816 1817 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1818 smu->pm_enabled = false; 1819 return 0; 1820 } 1821 1822 ret = smu_start_smc_engine(smu); 1823 if (ret) { 1824 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1825 return ret; 1826 } 1827 1828 /* 1829 * Check whether wbrf is supported. This needs to be done 1830 * before SMU setup starts since part of SMU configuration 1831 * relies on this. 1832 */ 1833 smu_wbrf_support_check(smu); 1834 1835 if (smu->is_apu) { 1836 ret = smu_set_gfx_imu_enable(smu); 1837 if (ret) 1838 return ret; 1839 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1840 smu_dpm_set_vcn_enable(smu, true, i); 1841 smu_dpm_set_jpeg_enable(smu, true); 1842 smu_dpm_set_vpe_enable(smu, true); 1843 smu_dpm_set_umsch_mm_enable(smu, true); 1844 smu_set_mall_enable(smu); 1845 smu_set_gfx_cgpg(smu, true); 1846 } 1847 1848 if (!smu->pm_enabled) 1849 return 0; 1850 1851 ret = smu_get_driver_allowed_feature_mask(smu); 1852 if (ret) 1853 return ret; 1854 1855 ret = smu_smc_hw_setup(smu); 1856 if (ret) { 1857 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1858 return ret; 1859 } 1860 1861 /* 1862 * Move maximum sustainable clock retrieving here considering 1863 * 1. It is not needed on resume(from S3). 1864 * 2. DAL settings come between .hw_init and .late_init of SMU. 1865 * And DAL needs to know the maximum sustainable clocks. Thus 1866 * it cannot be put in .late_init(). 1867 */ 1868 ret = smu_init_max_sustainable_clocks(smu); 1869 if (ret) { 1870 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1871 return ret; 1872 } 1873 1874 adev->pm.dpm_enabled = true; 1875 1876 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1877 1878 return 0; 1879 } 1880 1881 static int smu_disable_dpms(struct smu_context *smu) 1882 { 1883 struct amdgpu_device *adev = smu->adev; 1884 int ret = 0; 1885 bool use_baco = !smu->is_apu && 1886 ((amdgpu_in_reset(adev) && 1887 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1888 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1889 1890 /* 1891 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1892 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1893 */ 1894 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1895 case IP_VERSION(13, 0, 0): 1896 case IP_VERSION(13, 0, 7): 1897 case IP_VERSION(13, 0, 10): 1898 case IP_VERSION(14, 0, 2): 1899 case IP_VERSION(14, 0, 3): 1900 return 0; 1901 default: 1902 break; 1903 } 1904 1905 /* 1906 * For custom pptable uploading, skip the DPM features 1907 * disable process on Navi1x ASICs. 1908 * - As the gfx related features are under control of 1909 * RLC on those ASICs. RLC reinitialization will be 1910 * needed to reenable them. That will cost much more 1911 * efforts. 1912 * 1913 * - SMU firmware can handle the DPM reenablement 1914 * properly. 1915 */ 1916 if (smu->uploading_custom_pp_table) { 1917 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1918 case IP_VERSION(11, 0, 0): 1919 case IP_VERSION(11, 0, 5): 1920 case IP_VERSION(11, 0, 9): 1921 case IP_VERSION(11, 0, 7): 1922 case IP_VERSION(11, 0, 11): 1923 case IP_VERSION(11, 5, 0): 1924 case IP_VERSION(11, 5, 2): 1925 case IP_VERSION(11, 0, 12): 1926 case IP_VERSION(11, 0, 13): 1927 return 0; 1928 default: 1929 break; 1930 } 1931 } 1932 1933 /* 1934 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1935 * on BACO in. Driver involvement is unnecessary. 1936 */ 1937 if (use_baco) { 1938 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1939 case IP_VERSION(11, 0, 7): 1940 case IP_VERSION(11, 0, 0): 1941 case IP_VERSION(11, 0, 5): 1942 case IP_VERSION(11, 0, 9): 1943 case IP_VERSION(13, 0, 7): 1944 return 0; 1945 default: 1946 break; 1947 } 1948 } 1949 1950 /* 1951 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 1952 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1953 */ 1954 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 1955 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 1956 return 0; 1957 1958 /* 1959 * For gpu reset, runpm and hibernation through BACO, 1960 * BACO feature has to be kept enabled. 1961 */ 1962 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1963 ret = smu_disable_all_features_with_exception(smu, 1964 SMU_FEATURE_BACO_BIT); 1965 if (ret) 1966 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1967 } else { 1968 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1969 if (!adev->scpm_enabled) { 1970 ret = smu_system_features_control(smu, false); 1971 if (ret) 1972 dev_err(adev->dev, "Failed to disable smu features.\n"); 1973 } 1974 } 1975 1976 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1977 * otherwise SMU will hang while interacting with RLC if RLC is halted 1978 * this is a WA for Vangogh asic which fix the SMU hang issue. 1979 */ 1980 ret = smu_notify_rlc_state(smu, false); 1981 if (ret) { 1982 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1983 return ret; 1984 } 1985 1986 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1987 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1988 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1989 adev->gfx.rlc.funcs->stop(adev); 1990 1991 return ret; 1992 } 1993 1994 static int smu_smc_hw_cleanup(struct smu_context *smu) 1995 { 1996 struct amdgpu_device *adev = smu->adev; 1997 int ret = 0; 1998 1999 smu_wbrf_fini(smu); 2000 2001 cancel_work_sync(&smu->throttling_logging_work); 2002 cancel_work_sync(&smu->interrupt_work); 2003 2004 ret = smu_disable_thermal_alert(smu); 2005 if (ret) { 2006 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 2007 return ret; 2008 } 2009 2010 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2011 2012 ret = smu_disable_dpms(smu); 2013 if (ret) { 2014 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2015 return ret; 2016 } 2017 2018 return 0; 2019 } 2020 2021 static int smu_reset_mp1_state(struct smu_context *smu) 2022 { 2023 struct amdgpu_device *adev = smu->adev; 2024 int ret = 0; 2025 2026 if ((!adev->in_runpm) && (!adev->in_suspend) && 2027 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 2028 IP_VERSION(13, 0, 10) && 2029 !amdgpu_device_has_display_hardware(adev)) 2030 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2031 2032 return ret; 2033 } 2034 2035 static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2036 { 2037 struct amdgpu_device *adev = ip_block->adev; 2038 struct smu_context *smu = adev->powerplay.pp_handle; 2039 int i, ret; 2040 2041 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2042 return 0; 2043 2044 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 2045 smu_dpm_set_vcn_enable(smu, false, i); 2046 smu_dpm_set_jpeg_enable(smu, false); 2047 smu_dpm_set_vpe_enable(smu, false); 2048 smu_dpm_set_umsch_mm_enable(smu, false); 2049 2050 adev->vcn.cur_state = AMD_PG_STATE_GATE; 2051 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2052 2053 if (!smu->pm_enabled) 2054 return 0; 2055 2056 adev->pm.dpm_enabled = false; 2057 2058 ret = smu_smc_hw_cleanup(smu); 2059 if (ret) 2060 return ret; 2061 2062 ret = smu_reset_mp1_state(smu); 2063 if (ret) 2064 return ret; 2065 2066 return 0; 2067 } 2068 2069 static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2070 { 2071 struct amdgpu_device *adev = ip_block->adev; 2072 struct smu_context *smu = adev->powerplay.pp_handle; 2073 2074 kfree(smu); 2075 } 2076 2077 static int smu_reset(struct smu_context *smu) 2078 { 2079 struct amdgpu_device *adev = smu->adev; 2080 struct amdgpu_ip_block *ip_block; 2081 int ret; 2082 2083 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2084 if (!ip_block) 2085 return -EINVAL; 2086 2087 ret = smu_hw_fini(ip_block); 2088 if (ret) 2089 return ret; 2090 2091 ret = smu_hw_init(ip_block); 2092 if (ret) 2093 return ret; 2094 2095 ret = smu_late_init(ip_block); 2096 if (ret) 2097 return ret; 2098 2099 return 0; 2100 } 2101 2102 static int smu_suspend(struct amdgpu_ip_block *ip_block) 2103 { 2104 struct amdgpu_device *adev = ip_block->adev; 2105 struct smu_context *smu = adev->powerplay.pp_handle; 2106 int ret; 2107 uint64_t count; 2108 2109 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2110 return 0; 2111 2112 if (!smu->pm_enabled) 2113 return 0; 2114 2115 adev->pm.dpm_enabled = false; 2116 2117 ret = smu_smc_hw_cleanup(smu); 2118 if (ret) 2119 return ret; 2120 2121 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2122 2123 smu_set_gfx_cgpg(smu, false); 2124 2125 /* 2126 * pwfw resets entrycount when device is suspended, so we save the 2127 * last value to be used when we resume to keep it consistent 2128 */ 2129 ret = smu_get_entrycount_gfxoff(smu, &count); 2130 if (!ret) 2131 adev->gfx.gfx_off_entrycount = count; 2132 2133 /* clear this on suspend so it will get reprogrammed on resume */ 2134 smu->workload_mask = 0; 2135 2136 return 0; 2137 } 2138 2139 static int smu_resume(struct amdgpu_ip_block *ip_block) 2140 { 2141 int ret; 2142 struct amdgpu_device *adev = ip_block->adev; 2143 struct smu_context *smu = adev->powerplay.pp_handle; 2144 2145 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2146 return 0; 2147 2148 if (!smu->pm_enabled) 2149 return 0; 2150 2151 dev_info(adev->dev, "SMU is resuming...\n"); 2152 2153 ret = smu_start_smc_engine(smu); 2154 if (ret) { 2155 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2156 return ret; 2157 } 2158 2159 ret = smu_smc_hw_setup(smu); 2160 if (ret) { 2161 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2162 return ret; 2163 } 2164 2165 ret = smu_set_gfx_imu_enable(smu); 2166 if (ret) 2167 return ret; 2168 2169 smu_set_gfx_cgpg(smu, true); 2170 2171 smu->disable_uclk_switch = 0; 2172 2173 adev->pm.dpm_enabled = true; 2174 2175 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2176 2177 return 0; 2178 } 2179 2180 static int smu_display_configuration_change(void *handle, 2181 const struct amd_pp_display_configuration *display_config) 2182 { 2183 struct smu_context *smu = handle; 2184 2185 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2186 return -EOPNOTSUPP; 2187 2188 if (!display_config) 2189 return -EINVAL; 2190 2191 smu_set_min_dcef_deep_sleep(smu, 2192 display_config->min_dcef_deep_sleep_set_clk / 100); 2193 2194 return 0; 2195 } 2196 2197 static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2198 enum amd_clockgating_state state) 2199 { 2200 return 0; 2201 } 2202 2203 static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block, 2204 enum amd_powergating_state state) 2205 { 2206 return 0; 2207 } 2208 2209 static int smu_enable_umd_pstate(void *handle, 2210 enum amd_dpm_forced_level *level) 2211 { 2212 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2213 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2214 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2215 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2216 2217 struct smu_context *smu = (struct smu_context*)(handle); 2218 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2219 2220 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2221 return -EINVAL; 2222 2223 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2224 /* enter umd pstate, save current level, disable gfx cg*/ 2225 if (*level & profile_mode_mask) { 2226 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2227 smu_gpo_control(smu, false); 2228 smu_gfx_ulv_control(smu, false); 2229 smu_deep_sleep_control(smu, false); 2230 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2231 } 2232 } else { 2233 /* exit umd pstate, restore level, enable gfx cg*/ 2234 if (!(*level & profile_mode_mask)) { 2235 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2236 *level = smu_dpm_ctx->saved_dpm_level; 2237 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2238 smu_deep_sleep_control(smu, true); 2239 smu_gfx_ulv_control(smu, true); 2240 smu_gpo_control(smu, true); 2241 } 2242 } 2243 2244 return 0; 2245 } 2246 2247 static int smu_bump_power_profile_mode(struct smu_context *smu, 2248 long *custom_params, 2249 u32 custom_params_max_idx) 2250 { 2251 u32 workload_mask = 0; 2252 int i, ret = 0; 2253 2254 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2255 if (smu->workload_refcount[i]) 2256 workload_mask |= 1 << i; 2257 } 2258 2259 if (smu->workload_mask == workload_mask) 2260 return 0; 2261 2262 if (smu->ppt_funcs->set_power_profile_mode) 2263 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask, 2264 custom_params, 2265 custom_params_max_idx); 2266 2267 if (!ret) 2268 smu->workload_mask = workload_mask; 2269 2270 return ret; 2271 } 2272 2273 static void smu_power_profile_mode_get(struct smu_context *smu, 2274 enum PP_SMC_POWER_PROFILE profile_mode) 2275 { 2276 smu->workload_refcount[profile_mode]++; 2277 } 2278 2279 static void smu_power_profile_mode_put(struct smu_context *smu, 2280 enum PP_SMC_POWER_PROFILE profile_mode) 2281 { 2282 if (smu->workload_refcount[profile_mode]) 2283 smu->workload_refcount[profile_mode]--; 2284 } 2285 2286 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2287 enum amd_dpm_forced_level level, 2288 bool skip_display_settings) 2289 { 2290 int ret = 0; 2291 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2292 2293 if (!skip_display_settings) { 2294 ret = smu_display_config_changed(smu); 2295 if (ret) { 2296 dev_err(smu->adev->dev, "Failed to change display config!"); 2297 return ret; 2298 } 2299 } 2300 2301 ret = smu_apply_clocks_adjust_rules(smu); 2302 if (ret) { 2303 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2304 return ret; 2305 } 2306 2307 if (!skip_display_settings) { 2308 ret = smu_notify_smc_display_config(smu); 2309 if (ret) { 2310 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2311 return ret; 2312 } 2313 } 2314 2315 if (smu_dpm_ctx->dpm_level != level) { 2316 ret = smu_asic_set_performance_level(smu, level); 2317 if (ret) { 2318 dev_err(smu->adev->dev, "Failed to set performance level!"); 2319 return ret; 2320 } 2321 2322 /* update the saved copy */ 2323 smu_dpm_ctx->dpm_level = level; 2324 } 2325 2326 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2327 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2328 smu_bump_power_profile_mode(smu, NULL, 0); 2329 2330 return ret; 2331 } 2332 2333 static int smu_handle_task(struct smu_context *smu, 2334 enum amd_dpm_forced_level level, 2335 enum amd_pp_task task_id) 2336 { 2337 int ret = 0; 2338 2339 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2340 return -EOPNOTSUPP; 2341 2342 switch (task_id) { 2343 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2344 ret = smu_pre_display_config_changed(smu); 2345 if (ret) 2346 return ret; 2347 ret = smu_adjust_power_state_dynamic(smu, level, false); 2348 break; 2349 case AMD_PP_TASK_COMPLETE_INIT: 2350 ret = smu_adjust_power_state_dynamic(smu, level, true); 2351 break; 2352 case AMD_PP_TASK_READJUST_POWER_STATE: 2353 ret = smu_adjust_power_state_dynamic(smu, level, true); 2354 break; 2355 default: 2356 break; 2357 } 2358 2359 return ret; 2360 } 2361 2362 static int smu_handle_dpm_task(void *handle, 2363 enum amd_pp_task task_id, 2364 enum amd_pm_state_type *user_state) 2365 { 2366 struct smu_context *smu = handle; 2367 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2368 2369 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2370 2371 } 2372 2373 static int smu_switch_power_profile(void *handle, 2374 enum PP_SMC_POWER_PROFILE type, 2375 bool enable) 2376 { 2377 struct smu_context *smu = handle; 2378 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2379 int ret; 2380 2381 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2382 return -EOPNOTSUPP; 2383 2384 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2385 return -EINVAL; 2386 2387 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2388 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2389 if (enable) 2390 smu_power_profile_mode_get(smu, type); 2391 else 2392 smu_power_profile_mode_put(smu, type); 2393 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2394 if (ret) { 2395 if (enable) 2396 smu_power_profile_mode_put(smu, type); 2397 else 2398 smu_power_profile_mode_get(smu, type); 2399 return ret; 2400 } 2401 } 2402 2403 return 0; 2404 } 2405 2406 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2407 { 2408 struct smu_context *smu = handle; 2409 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2410 2411 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2412 return -EOPNOTSUPP; 2413 2414 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2415 return -EINVAL; 2416 2417 return smu_dpm_ctx->dpm_level; 2418 } 2419 2420 static int smu_force_performance_level(void *handle, 2421 enum amd_dpm_forced_level level) 2422 { 2423 struct smu_context *smu = handle; 2424 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2425 int ret = 0; 2426 2427 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2428 return -EOPNOTSUPP; 2429 2430 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2431 return -EINVAL; 2432 2433 ret = smu_enable_umd_pstate(smu, &level); 2434 if (ret) 2435 return ret; 2436 2437 ret = smu_handle_task(smu, level, 2438 AMD_PP_TASK_READJUST_POWER_STATE); 2439 2440 /* reset user dpm clock state */ 2441 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2442 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2443 smu->user_dpm_profile.clk_dependency = 0; 2444 } 2445 2446 return ret; 2447 } 2448 2449 static int smu_set_display_count(void *handle, uint32_t count) 2450 { 2451 struct smu_context *smu = handle; 2452 2453 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2454 return -EOPNOTSUPP; 2455 2456 return smu_init_display_count(smu, count); 2457 } 2458 2459 static int smu_force_smuclk_levels(struct smu_context *smu, 2460 enum smu_clk_type clk_type, 2461 uint32_t mask) 2462 { 2463 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2464 int ret = 0; 2465 2466 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2467 return -EOPNOTSUPP; 2468 2469 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2470 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2471 return -EINVAL; 2472 } 2473 2474 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2475 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2476 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2477 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2478 smu_set_user_clk_dependencies(smu, clk_type); 2479 } 2480 } 2481 2482 return ret; 2483 } 2484 2485 static int smu_force_ppclk_levels(void *handle, 2486 enum pp_clock_type type, 2487 uint32_t mask) 2488 { 2489 struct smu_context *smu = handle; 2490 enum smu_clk_type clk_type; 2491 2492 switch (type) { 2493 case PP_SCLK: 2494 clk_type = SMU_SCLK; break; 2495 case PP_MCLK: 2496 clk_type = SMU_MCLK; break; 2497 case PP_PCIE: 2498 clk_type = SMU_PCIE; break; 2499 case PP_SOCCLK: 2500 clk_type = SMU_SOCCLK; break; 2501 case PP_FCLK: 2502 clk_type = SMU_FCLK; break; 2503 case PP_DCEFCLK: 2504 clk_type = SMU_DCEFCLK; break; 2505 case PP_VCLK: 2506 clk_type = SMU_VCLK; break; 2507 case PP_VCLK1: 2508 clk_type = SMU_VCLK1; break; 2509 case PP_DCLK: 2510 clk_type = SMU_DCLK; break; 2511 case PP_DCLK1: 2512 clk_type = SMU_DCLK1; break; 2513 case OD_SCLK: 2514 clk_type = SMU_OD_SCLK; break; 2515 case OD_MCLK: 2516 clk_type = SMU_OD_MCLK; break; 2517 case OD_VDDC_CURVE: 2518 clk_type = SMU_OD_VDDC_CURVE; break; 2519 case OD_RANGE: 2520 clk_type = SMU_OD_RANGE; break; 2521 default: 2522 return -EINVAL; 2523 } 2524 2525 return smu_force_smuclk_levels(smu, clk_type, mask); 2526 } 2527 2528 /* 2529 * On system suspending or resetting, the dpm_enabled 2530 * flag will be cleared. So that those SMU services which 2531 * are not supported will be gated. 2532 * However, the mp1 state setting should still be granted 2533 * even if the dpm_enabled cleared. 2534 */ 2535 static int smu_set_mp1_state(void *handle, 2536 enum pp_mp1_state mp1_state) 2537 { 2538 struct smu_context *smu = handle; 2539 int ret = 0; 2540 2541 if (!smu->pm_enabled) 2542 return -EOPNOTSUPP; 2543 2544 if (smu->ppt_funcs && 2545 smu->ppt_funcs->set_mp1_state) 2546 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2547 2548 return ret; 2549 } 2550 2551 static int smu_set_df_cstate(void *handle, 2552 enum pp_df_cstate state) 2553 { 2554 struct smu_context *smu = handle; 2555 int ret = 0; 2556 2557 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2558 return -EOPNOTSUPP; 2559 2560 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2561 return 0; 2562 2563 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2564 if (ret) 2565 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2566 2567 return ret; 2568 } 2569 2570 int smu_write_watermarks_table(struct smu_context *smu) 2571 { 2572 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2573 return -EOPNOTSUPP; 2574 2575 return smu_set_watermarks_table(smu, NULL); 2576 } 2577 2578 static int smu_set_watermarks_for_clock_ranges(void *handle, 2579 struct pp_smu_wm_range_sets *clock_ranges) 2580 { 2581 struct smu_context *smu = handle; 2582 2583 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2584 return -EOPNOTSUPP; 2585 2586 if (smu->disable_watermark) 2587 return 0; 2588 2589 return smu_set_watermarks_table(smu, clock_ranges); 2590 } 2591 2592 int smu_set_ac_dc(struct smu_context *smu) 2593 { 2594 int ret = 0; 2595 2596 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2597 return -EOPNOTSUPP; 2598 2599 /* controlled by firmware */ 2600 if (smu->dc_controlled_by_gpio) 2601 return 0; 2602 2603 ret = smu_set_power_source(smu, 2604 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2605 SMU_POWER_SOURCE_DC); 2606 if (ret) 2607 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2608 smu->adev->pm.ac_power ? "AC" : "DC"); 2609 2610 return ret; 2611 } 2612 2613 const struct amd_ip_funcs smu_ip_funcs = { 2614 .name = "smu", 2615 .early_init = smu_early_init, 2616 .late_init = smu_late_init, 2617 .sw_init = smu_sw_init, 2618 .sw_fini = smu_sw_fini, 2619 .hw_init = smu_hw_init, 2620 .hw_fini = smu_hw_fini, 2621 .late_fini = smu_late_fini, 2622 .suspend = smu_suspend, 2623 .resume = smu_resume, 2624 .is_idle = NULL, 2625 .check_soft_reset = NULL, 2626 .wait_for_idle = NULL, 2627 .soft_reset = NULL, 2628 .set_clockgating_state = smu_set_clockgating_state, 2629 .set_powergating_state = smu_set_powergating_state, 2630 }; 2631 2632 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2633 .type = AMD_IP_BLOCK_TYPE_SMC, 2634 .major = 11, 2635 .minor = 0, 2636 .rev = 0, 2637 .funcs = &smu_ip_funcs, 2638 }; 2639 2640 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2641 .type = AMD_IP_BLOCK_TYPE_SMC, 2642 .major = 12, 2643 .minor = 0, 2644 .rev = 0, 2645 .funcs = &smu_ip_funcs, 2646 }; 2647 2648 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2649 .type = AMD_IP_BLOCK_TYPE_SMC, 2650 .major = 13, 2651 .minor = 0, 2652 .rev = 0, 2653 .funcs = &smu_ip_funcs, 2654 }; 2655 2656 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2657 .type = AMD_IP_BLOCK_TYPE_SMC, 2658 .major = 14, 2659 .minor = 0, 2660 .rev = 0, 2661 .funcs = &smu_ip_funcs, 2662 }; 2663 2664 static int smu_load_microcode(void *handle) 2665 { 2666 struct smu_context *smu = handle; 2667 struct amdgpu_device *adev = smu->adev; 2668 int ret = 0; 2669 2670 if (!smu->pm_enabled) 2671 return -EOPNOTSUPP; 2672 2673 /* This should be used for non PSP loading */ 2674 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2675 return 0; 2676 2677 if (smu->ppt_funcs->load_microcode) { 2678 ret = smu->ppt_funcs->load_microcode(smu); 2679 if (ret) { 2680 dev_err(adev->dev, "Load microcode failed\n"); 2681 return ret; 2682 } 2683 } 2684 2685 if (smu->ppt_funcs->check_fw_status) { 2686 ret = smu->ppt_funcs->check_fw_status(smu); 2687 if (ret) { 2688 dev_err(adev->dev, "SMC is not ready\n"); 2689 return ret; 2690 } 2691 } 2692 2693 return ret; 2694 } 2695 2696 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2697 { 2698 int ret = 0; 2699 2700 if (smu->ppt_funcs->set_gfx_cgpg) 2701 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2702 2703 return ret; 2704 } 2705 2706 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2707 { 2708 struct smu_context *smu = handle; 2709 int ret = 0; 2710 2711 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2712 return -EOPNOTSUPP; 2713 2714 if (!smu->ppt_funcs->set_fan_speed_rpm) 2715 return -EOPNOTSUPP; 2716 2717 if (speed == U32_MAX) 2718 return -EINVAL; 2719 2720 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2721 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2722 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2723 smu->user_dpm_profile.fan_speed_rpm = speed; 2724 2725 /* Override custom PWM setting as they cannot co-exist */ 2726 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2727 smu->user_dpm_profile.fan_speed_pwm = 0; 2728 } 2729 2730 return ret; 2731 } 2732 2733 /** 2734 * smu_get_power_limit - Request one of the SMU Power Limits 2735 * 2736 * @handle: pointer to smu context 2737 * @limit: requested limit is written back to this variable 2738 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2739 * @pp_power_type: &pp_power_type type of power 2740 * Return: 0 on success, <0 on error 2741 * 2742 */ 2743 int smu_get_power_limit(void *handle, 2744 uint32_t *limit, 2745 enum pp_power_limit_level pp_limit_level, 2746 enum pp_power_type pp_power_type) 2747 { 2748 struct smu_context *smu = handle; 2749 struct amdgpu_device *adev = smu->adev; 2750 enum smu_ppt_limit_level limit_level; 2751 uint32_t limit_type; 2752 int ret = 0; 2753 2754 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2755 return -EOPNOTSUPP; 2756 2757 switch (pp_power_type) { 2758 case PP_PWR_TYPE_SUSTAINED: 2759 limit_type = SMU_DEFAULT_PPT_LIMIT; 2760 break; 2761 case PP_PWR_TYPE_FAST: 2762 limit_type = SMU_FAST_PPT_LIMIT; 2763 break; 2764 default: 2765 return -EOPNOTSUPP; 2766 } 2767 2768 switch (pp_limit_level) { 2769 case PP_PWR_LIMIT_CURRENT: 2770 limit_level = SMU_PPT_LIMIT_CURRENT; 2771 break; 2772 case PP_PWR_LIMIT_DEFAULT: 2773 limit_level = SMU_PPT_LIMIT_DEFAULT; 2774 break; 2775 case PP_PWR_LIMIT_MAX: 2776 limit_level = SMU_PPT_LIMIT_MAX; 2777 break; 2778 case PP_PWR_LIMIT_MIN: 2779 limit_level = SMU_PPT_LIMIT_MIN; 2780 break; 2781 default: 2782 return -EOPNOTSUPP; 2783 } 2784 2785 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2786 if (smu->ppt_funcs->get_ppt_limit) 2787 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2788 } else { 2789 switch (limit_level) { 2790 case SMU_PPT_LIMIT_CURRENT: 2791 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2792 case IP_VERSION(13, 0, 2): 2793 case IP_VERSION(13, 0, 6): 2794 case IP_VERSION(13, 0, 14): 2795 case IP_VERSION(11, 0, 7): 2796 case IP_VERSION(11, 0, 11): 2797 case IP_VERSION(11, 0, 12): 2798 case IP_VERSION(11, 0, 13): 2799 ret = smu_get_asic_power_limits(smu, 2800 &smu->current_power_limit, 2801 NULL, NULL, NULL); 2802 break; 2803 default: 2804 break; 2805 } 2806 *limit = smu->current_power_limit; 2807 break; 2808 case SMU_PPT_LIMIT_DEFAULT: 2809 *limit = smu->default_power_limit; 2810 break; 2811 case SMU_PPT_LIMIT_MAX: 2812 *limit = smu->max_power_limit; 2813 break; 2814 case SMU_PPT_LIMIT_MIN: 2815 *limit = smu->min_power_limit; 2816 break; 2817 default: 2818 return -EINVAL; 2819 } 2820 } 2821 2822 return ret; 2823 } 2824 2825 static int smu_set_power_limit(void *handle, uint32_t limit) 2826 { 2827 struct smu_context *smu = handle; 2828 uint32_t limit_type = limit >> 24; 2829 int ret = 0; 2830 2831 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2832 return -EOPNOTSUPP; 2833 2834 limit &= (1<<24)-1; 2835 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2836 if (smu->ppt_funcs->set_power_limit) 2837 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2838 2839 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2840 dev_err(smu->adev->dev, 2841 "New power limit (%d) is out of range [%d,%d]\n", 2842 limit, smu->min_power_limit, smu->max_power_limit); 2843 return -EINVAL; 2844 } 2845 2846 if (!limit) 2847 limit = smu->current_power_limit; 2848 2849 if (smu->ppt_funcs->set_power_limit) { 2850 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2851 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2852 smu->user_dpm_profile.power_limit = limit; 2853 } 2854 2855 return ret; 2856 } 2857 2858 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2859 { 2860 int ret = 0; 2861 2862 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2863 return -EOPNOTSUPP; 2864 2865 if (smu->ppt_funcs->print_clk_levels) 2866 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2867 2868 return ret; 2869 } 2870 2871 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2872 { 2873 enum smu_clk_type clk_type; 2874 2875 switch (type) { 2876 case PP_SCLK: 2877 clk_type = SMU_SCLK; break; 2878 case PP_MCLK: 2879 clk_type = SMU_MCLK; break; 2880 case PP_PCIE: 2881 clk_type = SMU_PCIE; break; 2882 case PP_SOCCLK: 2883 clk_type = SMU_SOCCLK; break; 2884 case PP_FCLK: 2885 clk_type = SMU_FCLK; break; 2886 case PP_DCEFCLK: 2887 clk_type = SMU_DCEFCLK; break; 2888 case PP_VCLK: 2889 clk_type = SMU_VCLK; break; 2890 case PP_VCLK1: 2891 clk_type = SMU_VCLK1; break; 2892 case PP_DCLK: 2893 clk_type = SMU_DCLK; break; 2894 case PP_DCLK1: 2895 clk_type = SMU_DCLK1; break; 2896 case OD_SCLK: 2897 clk_type = SMU_OD_SCLK; break; 2898 case OD_MCLK: 2899 clk_type = SMU_OD_MCLK; break; 2900 case OD_VDDC_CURVE: 2901 clk_type = SMU_OD_VDDC_CURVE; break; 2902 case OD_RANGE: 2903 clk_type = SMU_OD_RANGE; break; 2904 case OD_VDDGFX_OFFSET: 2905 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2906 case OD_CCLK: 2907 clk_type = SMU_OD_CCLK; break; 2908 case OD_FAN_CURVE: 2909 clk_type = SMU_OD_FAN_CURVE; break; 2910 case OD_ACOUSTIC_LIMIT: 2911 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2912 case OD_ACOUSTIC_TARGET: 2913 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2914 case OD_FAN_TARGET_TEMPERATURE: 2915 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2916 case OD_FAN_MINIMUM_PWM: 2917 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2918 case OD_FAN_ZERO_RPM_ENABLE: 2919 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 2920 case OD_FAN_ZERO_RPM_STOP_TEMP: 2921 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 2922 default: 2923 clk_type = SMU_CLK_COUNT; break; 2924 } 2925 2926 return clk_type; 2927 } 2928 2929 static int smu_print_ppclk_levels(void *handle, 2930 enum pp_clock_type type, 2931 char *buf) 2932 { 2933 struct smu_context *smu = handle; 2934 enum smu_clk_type clk_type; 2935 2936 clk_type = smu_convert_to_smuclk(type); 2937 if (clk_type == SMU_CLK_COUNT) 2938 return -EINVAL; 2939 2940 return smu_print_smuclk_levels(smu, clk_type, buf); 2941 } 2942 2943 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2944 { 2945 struct smu_context *smu = handle; 2946 enum smu_clk_type clk_type; 2947 2948 clk_type = smu_convert_to_smuclk(type); 2949 if (clk_type == SMU_CLK_COUNT) 2950 return -EINVAL; 2951 2952 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2953 return -EOPNOTSUPP; 2954 2955 if (!smu->ppt_funcs->emit_clk_levels) 2956 return -ENOENT; 2957 2958 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2959 2960 } 2961 2962 static int smu_od_edit_dpm_table(void *handle, 2963 enum PP_OD_DPM_TABLE_COMMAND type, 2964 long *input, uint32_t size) 2965 { 2966 struct smu_context *smu = handle; 2967 int ret = 0; 2968 2969 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2970 return -EOPNOTSUPP; 2971 2972 if (smu->ppt_funcs->od_edit_dpm_table) { 2973 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2974 } 2975 2976 return ret; 2977 } 2978 2979 static int smu_read_sensor(void *handle, 2980 int sensor, 2981 void *data, 2982 int *size_arg) 2983 { 2984 struct smu_context *smu = handle; 2985 struct amdgpu_device *adev = smu->adev; 2986 struct smu_umd_pstate_table *pstate_table = 2987 &smu->pstate_table; 2988 int i, ret = 0; 2989 uint32_t *size, size_val; 2990 2991 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2992 return -EOPNOTSUPP; 2993 2994 if (!data || !size_arg) 2995 return -EINVAL; 2996 2997 size_val = *size_arg; 2998 size = &size_val; 2999 3000 if (smu->ppt_funcs->read_sensor) 3001 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 3002 goto unlock; 3003 3004 switch (sensor) { 3005 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 3006 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 3007 *size = 4; 3008 break; 3009 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 3010 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 3011 *size = 4; 3012 break; 3013 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 3014 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 3015 *size = 4; 3016 break; 3017 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 3018 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3019 *size = 4; 3020 break; 3021 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 3022 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 3023 *size = 8; 3024 break; 3025 case AMDGPU_PP_SENSOR_UVD_POWER: 3026 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3027 *size = 4; 3028 break; 3029 case AMDGPU_PP_SENSOR_VCE_POWER: 3030 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 3031 *size = 4; 3032 break; 3033 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3034 *(uint32_t *)data = 0; 3035 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 3036 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) { 3037 *(uint32_t *)data = 1; 3038 break; 3039 } 3040 } 3041 *size = 4; 3042 break; 3043 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3044 *(uint32_t *)data = 0; 3045 *size = 4; 3046 break; 3047 default: 3048 *size = 0; 3049 ret = -EOPNOTSUPP; 3050 break; 3051 } 3052 3053 unlock: 3054 // assign uint32_t to int 3055 *size_arg = size_val; 3056 3057 return ret; 3058 } 3059 3060 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3061 { 3062 int ret = -EOPNOTSUPP; 3063 struct smu_context *smu = handle; 3064 3065 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3066 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3067 3068 return ret; 3069 } 3070 3071 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3072 { 3073 int ret = -EOPNOTSUPP; 3074 struct smu_context *smu = handle; 3075 3076 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3077 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3078 3079 return ret; 3080 } 3081 3082 static int smu_get_power_profile_mode(void *handle, char *buf) 3083 { 3084 struct smu_context *smu = handle; 3085 3086 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3087 !smu->ppt_funcs->get_power_profile_mode) 3088 return -EOPNOTSUPP; 3089 if (!buf) 3090 return -EINVAL; 3091 3092 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3093 } 3094 3095 static int smu_set_power_profile_mode(void *handle, 3096 long *param, 3097 uint32_t param_size) 3098 { 3099 struct smu_context *smu = handle; 3100 bool custom = false; 3101 int ret = 0; 3102 3103 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3104 !smu->ppt_funcs->set_power_profile_mode) 3105 return -EOPNOTSUPP; 3106 3107 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) { 3108 custom = true; 3109 /* clear frontend mask so custom changes propogate */ 3110 smu->workload_mask = 0; 3111 } 3112 3113 if ((param[param_size] != smu->power_profile_mode) || custom) { 3114 /* clear the old user preference */ 3115 smu_power_profile_mode_put(smu, smu->power_profile_mode); 3116 /* set the new user preference */ 3117 smu_power_profile_mode_get(smu, param[param_size]); 3118 ret = smu_bump_power_profile_mode(smu, 3119 custom ? param : NULL, 3120 custom ? param_size : 0); 3121 if (ret) 3122 smu_power_profile_mode_put(smu, param[param_size]); 3123 else 3124 /* store the user's preference */ 3125 smu->power_profile_mode = param[param_size]; 3126 } 3127 3128 return ret; 3129 } 3130 3131 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3132 { 3133 struct smu_context *smu = handle; 3134 3135 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3136 return -EOPNOTSUPP; 3137 3138 if (!smu->ppt_funcs->get_fan_control_mode) 3139 return -EOPNOTSUPP; 3140 3141 if (!fan_mode) 3142 return -EINVAL; 3143 3144 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3145 3146 return 0; 3147 } 3148 3149 static int smu_set_fan_control_mode(void *handle, u32 value) 3150 { 3151 struct smu_context *smu = handle; 3152 int ret = 0; 3153 3154 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3155 return -EOPNOTSUPP; 3156 3157 if (!smu->ppt_funcs->set_fan_control_mode) 3158 return -EOPNOTSUPP; 3159 3160 if (value == U32_MAX) 3161 return -EINVAL; 3162 3163 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3164 if (ret) 3165 goto out; 3166 3167 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3168 smu->user_dpm_profile.fan_mode = value; 3169 3170 /* reset user dpm fan speed */ 3171 if (value != AMD_FAN_CTRL_MANUAL) { 3172 smu->user_dpm_profile.fan_speed_pwm = 0; 3173 smu->user_dpm_profile.fan_speed_rpm = 0; 3174 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3175 } 3176 } 3177 3178 out: 3179 return ret; 3180 } 3181 3182 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3183 { 3184 struct smu_context *smu = handle; 3185 int ret = 0; 3186 3187 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3188 return -EOPNOTSUPP; 3189 3190 if (!smu->ppt_funcs->get_fan_speed_pwm) 3191 return -EOPNOTSUPP; 3192 3193 if (!speed) 3194 return -EINVAL; 3195 3196 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3197 3198 return ret; 3199 } 3200 3201 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3202 { 3203 struct smu_context *smu = handle; 3204 int ret = 0; 3205 3206 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3207 return -EOPNOTSUPP; 3208 3209 if (!smu->ppt_funcs->set_fan_speed_pwm) 3210 return -EOPNOTSUPP; 3211 3212 if (speed == U32_MAX) 3213 return -EINVAL; 3214 3215 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3216 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3217 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3218 smu->user_dpm_profile.fan_speed_pwm = speed; 3219 3220 /* Override custom RPM setting as they cannot co-exist */ 3221 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3222 smu->user_dpm_profile.fan_speed_rpm = 0; 3223 } 3224 3225 return ret; 3226 } 3227 3228 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3229 { 3230 struct smu_context *smu = handle; 3231 int ret = 0; 3232 3233 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3234 return -EOPNOTSUPP; 3235 3236 if (!smu->ppt_funcs->get_fan_speed_rpm) 3237 return -EOPNOTSUPP; 3238 3239 if (!speed) 3240 return -EINVAL; 3241 3242 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3243 3244 return ret; 3245 } 3246 3247 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3248 { 3249 struct smu_context *smu = handle; 3250 3251 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3252 return -EOPNOTSUPP; 3253 3254 return smu_set_min_dcef_deep_sleep(smu, clk); 3255 } 3256 3257 static int smu_get_clock_by_type_with_latency(void *handle, 3258 enum amd_pp_clock_type type, 3259 struct pp_clock_levels_with_latency *clocks) 3260 { 3261 struct smu_context *smu = handle; 3262 enum smu_clk_type clk_type; 3263 int ret = 0; 3264 3265 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3266 return -EOPNOTSUPP; 3267 3268 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3269 switch (type) { 3270 case amd_pp_sys_clock: 3271 clk_type = SMU_GFXCLK; 3272 break; 3273 case amd_pp_mem_clock: 3274 clk_type = SMU_MCLK; 3275 break; 3276 case amd_pp_dcef_clock: 3277 clk_type = SMU_DCEFCLK; 3278 break; 3279 case amd_pp_disp_clock: 3280 clk_type = SMU_DISPCLK; 3281 break; 3282 default: 3283 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3284 return -EINVAL; 3285 } 3286 3287 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3288 } 3289 3290 return ret; 3291 } 3292 3293 static int smu_display_clock_voltage_request(void *handle, 3294 struct pp_display_clock_request *clock_req) 3295 { 3296 struct smu_context *smu = handle; 3297 int ret = 0; 3298 3299 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3300 return -EOPNOTSUPP; 3301 3302 if (smu->ppt_funcs->display_clock_voltage_request) 3303 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3304 3305 return ret; 3306 } 3307 3308 3309 static int smu_display_disable_memory_clock_switch(void *handle, 3310 bool disable_memory_clock_switch) 3311 { 3312 struct smu_context *smu = handle; 3313 int ret = -EINVAL; 3314 3315 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3316 return -EOPNOTSUPP; 3317 3318 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3319 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3320 3321 return ret; 3322 } 3323 3324 static int smu_set_xgmi_pstate(void *handle, 3325 uint32_t pstate) 3326 { 3327 struct smu_context *smu = handle; 3328 int ret = 0; 3329 3330 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3331 return -EOPNOTSUPP; 3332 3333 if (smu->ppt_funcs->set_xgmi_pstate) 3334 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3335 3336 if (ret) 3337 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3338 3339 return ret; 3340 } 3341 3342 static int smu_get_baco_capability(void *handle) 3343 { 3344 struct smu_context *smu = handle; 3345 3346 if (!smu->pm_enabled) 3347 return false; 3348 3349 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3350 return false; 3351 3352 return smu->ppt_funcs->get_bamaco_support(smu); 3353 } 3354 3355 static int smu_baco_set_state(void *handle, int state) 3356 { 3357 struct smu_context *smu = handle; 3358 int ret = 0; 3359 3360 if (!smu->pm_enabled) 3361 return -EOPNOTSUPP; 3362 3363 if (state == 0) { 3364 if (smu->ppt_funcs->baco_exit) 3365 ret = smu->ppt_funcs->baco_exit(smu); 3366 } else if (state == 1) { 3367 if (smu->ppt_funcs->baco_enter) 3368 ret = smu->ppt_funcs->baco_enter(smu); 3369 } else { 3370 return -EINVAL; 3371 } 3372 3373 if (ret) 3374 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3375 (state)?"enter":"exit"); 3376 3377 return ret; 3378 } 3379 3380 bool smu_mode1_reset_is_support(struct smu_context *smu) 3381 { 3382 bool ret = false; 3383 3384 if (!smu->pm_enabled) 3385 return false; 3386 3387 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3388 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3389 3390 return ret; 3391 } 3392 3393 bool smu_mode2_reset_is_support(struct smu_context *smu) 3394 { 3395 bool ret = false; 3396 3397 if (!smu->pm_enabled) 3398 return false; 3399 3400 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3401 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3402 3403 return ret; 3404 } 3405 3406 int smu_mode1_reset(struct smu_context *smu) 3407 { 3408 int ret = 0; 3409 3410 if (!smu->pm_enabled) 3411 return -EOPNOTSUPP; 3412 3413 if (smu->ppt_funcs->mode1_reset) 3414 ret = smu->ppt_funcs->mode1_reset(smu); 3415 3416 return ret; 3417 } 3418 3419 static int smu_mode2_reset(void *handle) 3420 { 3421 struct smu_context *smu = handle; 3422 int ret = 0; 3423 3424 if (!smu->pm_enabled) 3425 return -EOPNOTSUPP; 3426 3427 if (smu->ppt_funcs->mode2_reset) 3428 ret = smu->ppt_funcs->mode2_reset(smu); 3429 3430 if (ret) 3431 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3432 3433 return ret; 3434 } 3435 3436 static int smu_enable_gfx_features(void *handle) 3437 { 3438 struct smu_context *smu = handle; 3439 int ret = 0; 3440 3441 if (!smu->pm_enabled) 3442 return -EOPNOTSUPP; 3443 3444 if (smu->ppt_funcs->enable_gfx_features) 3445 ret = smu->ppt_funcs->enable_gfx_features(smu); 3446 3447 if (ret) 3448 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3449 3450 return ret; 3451 } 3452 3453 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3454 struct pp_smu_nv_clock_table *max_clocks) 3455 { 3456 struct smu_context *smu = handle; 3457 int ret = 0; 3458 3459 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3460 return -EOPNOTSUPP; 3461 3462 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3463 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3464 3465 return ret; 3466 } 3467 3468 static int smu_get_uclk_dpm_states(void *handle, 3469 unsigned int *clock_values_in_khz, 3470 unsigned int *num_states) 3471 { 3472 struct smu_context *smu = handle; 3473 int ret = 0; 3474 3475 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3476 return -EOPNOTSUPP; 3477 3478 if (smu->ppt_funcs->get_uclk_dpm_states) 3479 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3480 3481 return ret; 3482 } 3483 3484 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3485 { 3486 struct smu_context *smu = handle; 3487 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3488 3489 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3490 return -EOPNOTSUPP; 3491 3492 if (smu->ppt_funcs->get_current_power_state) 3493 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3494 3495 return pm_state; 3496 } 3497 3498 static int smu_get_dpm_clock_table(void *handle, 3499 struct dpm_clocks *clock_table) 3500 { 3501 struct smu_context *smu = handle; 3502 int ret = 0; 3503 3504 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3505 return -EOPNOTSUPP; 3506 3507 if (smu->ppt_funcs->get_dpm_clock_table) 3508 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3509 3510 return ret; 3511 } 3512 3513 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3514 { 3515 struct smu_context *smu = handle; 3516 3517 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3518 return -EOPNOTSUPP; 3519 3520 if (!smu->ppt_funcs->get_gpu_metrics) 3521 return -EOPNOTSUPP; 3522 3523 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3524 } 3525 3526 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3527 size_t size) 3528 { 3529 struct smu_context *smu = handle; 3530 3531 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3532 return -EOPNOTSUPP; 3533 3534 if (!smu->ppt_funcs->get_pm_metrics) 3535 return -EOPNOTSUPP; 3536 3537 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3538 } 3539 3540 static int smu_enable_mgpu_fan_boost(void *handle) 3541 { 3542 struct smu_context *smu = handle; 3543 int ret = 0; 3544 3545 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3546 return -EOPNOTSUPP; 3547 3548 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3549 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3550 3551 return ret; 3552 } 3553 3554 static int smu_gfx_state_change_set(void *handle, 3555 uint32_t state) 3556 { 3557 struct smu_context *smu = handle; 3558 int ret = 0; 3559 3560 if (smu->ppt_funcs->gfx_state_change_set) 3561 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3562 3563 return ret; 3564 } 3565 3566 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3567 { 3568 int ret = 0; 3569 3570 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3571 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3572 3573 return ret; 3574 } 3575 3576 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3577 { 3578 int ret = -EOPNOTSUPP; 3579 3580 if (smu->ppt_funcs && 3581 smu->ppt_funcs->get_ecc_info) 3582 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3583 3584 return ret; 3585 3586 } 3587 3588 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3589 { 3590 struct smu_context *smu = handle; 3591 struct smu_table_context *smu_table = &smu->smu_table; 3592 struct smu_table *memory_pool = &smu_table->memory_pool; 3593 3594 if (!addr || !size) 3595 return -EINVAL; 3596 3597 *addr = NULL; 3598 *size = 0; 3599 if (memory_pool->bo) { 3600 *addr = memory_pool->cpu_addr; 3601 *size = memory_pool->size; 3602 } 3603 3604 return 0; 3605 } 3606 3607 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3608 size_t *size) 3609 { 3610 size_t offset = *size; 3611 int level; 3612 3613 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3614 if (level == policy->current_level) 3615 offset += sysfs_emit_at(sysbuf, offset, 3616 "%d : %s*\n", level, 3617 policy->desc->get_desc(policy, level)); 3618 else 3619 offset += sysfs_emit_at(sysbuf, offset, 3620 "%d : %s\n", level, 3621 policy->desc->get_desc(policy, level)); 3622 } 3623 3624 *size = offset; 3625 } 3626 3627 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3628 enum pp_pm_policy p_type, char *sysbuf) 3629 { 3630 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3631 struct smu_dpm_policy_ctxt *policy_ctxt; 3632 struct smu_dpm_policy *dpm_policy; 3633 size_t offset = 0; 3634 3635 policy_ctxt = dpm_ctxt->dpm_policies; 3636 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3637 !policy_ctxt->policy_mask) 3638 return -EOPNOTSUPP; 3639 3640 if (p_type == PP_PM_POLICY_NONE) 3641 return -EINVAL; 3642 3643 dpm_policy = smu_get_pm_policy(smu, p_type); 3644 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3645 return -ENOENT; 3646 3647 if (!sysbuf) 3648 return -EINVAL; 3649 3650 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3651 3652 return offset; 3653 } 3654 3655 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3656 enum pp_pm_policy p_type) 3657 { 3658 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3659 struct smu_dpm_policy_ctxt *policy_ctxt; 3660 int i; 3661 3662 policy_ctxt = dpm_ctxt->dpm_policies; 3663 if (!policy_ctxt) 3664 return NULL; 3665 3666 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3667 if (policy_ctxt->policies[i].policy_type == p_type) 3668 return &policy_ctxt->policies[i]; 3669 } 3670 3671 return NULL; 3672 } 3673 3674 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3675 int level) 3676 { 3677 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3678 struct smu_dpm_policy *dpm_policy = NULL; 3679 struct smu_dpm_policy_ctxt *policy_ctxt; 3680 int ret = -EOPNOTSUPP; 3681 3682 policy_ctxt = dpm_ctxt->dpm_policies; 3683 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3684 !policy_ctxt->policy_mask) 3685 return ret; 3686 3687 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3688 return -EINVAL; 3689 3690 dpm_policy = smu_get_pm_policy(smu, p_type); 3691 3692 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3693 return ret; 3694 3695 if (dpm_policy->current_level == level) 3696 return 0; 3697 3698 ret = dpm_policy->set_policy(smu, level); 3699 3700 if (!ret) 3701 dpm_policy->current_level = level; 3702 3703 return ret; 3704 } 3705 3706 static const struct amd_pm_funcs swsmu_pm_funcs = { 3707 /* export for sysfs */ 3708 .set_fan_control_mode = smu_set_fan_control_mode, 3709 .get_fan_control_mode = smu_get_fan_control_mode, 3710 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3711 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3712 .force_clock_level = smu_force_ppclk_levels, 3713 .print_clock_levels = smu_print_ppclk_levels, 3714 .emit_clock_levels = smu_emit_ppclk_levels, 3715 .force_performance_level = smu_force_performance_level, 3716 .read_sensor = smu_read_sensor, 3717 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3718 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3719 .get_performance_level = smu_get_performance_level, 3720 .get_current_power_state = smu_get_current_power_state, 3721 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3722 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3723 .get_pp_num_states = smu_get_power_num_states, 3724 .get_pp_table = smu_sys_get_pp_table, 3725 .set_pp_table = smu_sys_set_pp_table, 3726 .switch_power_profile = smu_switch_power_profile, 3727 /* export to amdgpu */ 3728 .dispatch_tasks = smu_handle_dpm_task, 3729 .load_firmware = smu_load_microcode, 3730 .set_powergating_by_smu = smu_dpm_set_power_gate, 3731 .set_power_limit = smu_set_power_limit, 3732 .get_power_limit = smu_get_power_limit, 3733 .get_power_profile_mode = smu_get_power_profile_mode, 3734 .set_power_profile_mode = smu_set_power_profile_mode, 3735 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3736 .set_mp1_state = smu_set_mp1_state, 3737 .gfx_state_change_set = smu_gfx_state_change_set, 3738 /* export to DC */ 3739 .get_sclk = smu_get_sclk, 3740 .get_mclk = smu_get_mclk, 3741 .display_configuration_change = smu_display_configuration_change, 3742 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3743 .display_clock_voltage_request = smu_display_clock_voltage_request, 3744 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3745 .set_active_display_count = smu_set_display_count, 3746 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3747 .get_asic_baco_capability = smu_get_baco_capability, 3748 .set_asic_baco_state = smu_baco_set_state, 3749 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3750 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3751 .asic_reset_mode_2 = smu_mode2_reset, 3752 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3753 .set_df_cstate = smu_set_df_cstate, 3754 .set_xgmi_pstate = smu_set_xgmi_pstate, 3755 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3756 .get_pm_metrics = smu_sys_get_pm_metrics, 3757 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3758 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3759 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3760 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3761 .get_dpm_clock_table = smu_get_dpm_clock_table, 3762 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3763 }; 3764 3765 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3766 uint64_t event_arg) 3767 { 3768 int ret = -EINVAL; 3769 3770 if (smu->ppt_funcs->wait_for_event) 3771 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3772 3773 return ret; 3774 } 3775 3776 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3777 { 3778 3779 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3780 return -EOPNOTSUPP; 3781 3782 /* Confirm the buffer allocated is of correct size */ 3783 if (size != smu->stb_context.stb_buf_size) 3784 return -EINVAL; 3785 3786 /* 3787 * No need to lock smu mutex as we access STB directly through MMIO 3788 * and not going through SMU messaging route (for now at least). 3789 * For registers access rely on implementation internal locking. 3790 */ 3791 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3792 } 3793 3794 #if defined(CONFIG_DEBUG_FS) 3795 3796 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3797 { 3798 struct amdgpu_device *adev = filp->f_inode->i_private; 3799 struct smu_context *smu = adev->powerplay.pp_handle; 3800 unsigned char *buf; 3801 int r; 3802 3803 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3804 if (!buf) 3805 return -ENOMEM; 3806 3807 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3808 if (r) 3809 goto out; 3810 3811 filp->private_data = buf; 3812 3813 return 0; 3814 3815 out: 3816 kvfree(buf); 3817 return r; 3818 } 3819 3820 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3821 loff_t *pos) 3822 { 3823 struct amdgpu_device *adev = filp->f_inode->i_private; 3824 struct smu_context *smu = adev->powerplay.pp_handle; 3825 3826 3827 if (!filp->private_data) 3828 return -EINVAL; 3829 3830 return simple_read_from_buffer(buf, 3831 size, 3832 pos, filp->private_data, 3833 smu->stb_context.stb_buf_size); 3834 } 3835 3836 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3837 { 3838 kvfree(filp->private_data); 3839 filp->private_data = NULL; 3840 3841 return 0; 3842 } 3843 3844 /* 3845 * We have to define not only read method but also 3846 * open and release because .read takes up to PAGE_SIZE 3847 * data each time so and so is invoked multiple times. 3848 * We allocate the STB buffer in .open and release it 3849 * in .release 3850 */ 3851 static const struct file_operations smu_stb_debugfs_fops = { 3852 .owner = THIS_MODULE, 3853 .open = smu_stb_debugfs_open, 3854 .read = smu_stb_debugfs_read, 3855 .release = smu_stb_debugfs_release, 3856 .llseek = default_llseek, 3857 }; 3858 3859 #endif 3860 3861 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3862 { 3863 #if defined(CONFIG_DEBUG_FS) 3864 3865 struct smu_context *smu = adev->powerplay.pp_handle; 3866 3867 if (!smu || (!smu->stb_context.stb_buf_size)) 3868 return; 3869 3870 debugfs_create_file_size("amdgpu_smu_stb_dump", 3871 S_IRUSR, 3872 adev_to_drm(adev)->primary->debugfs_root, 3873 adev, 3874 &smu_stb_debugfs_fops, 3875 smu->stb_context.stb_buf_size); 3876 #endif 3877 } 3878 3879 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3880 { 3881 int ret = 0; 3882 3883 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3884 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3885 3886 return ret; 3887 } 3888 3889 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3890 { 3891 int ret = 0; 3892 3893 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3894 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3895 3896 return ret; 3897 } 3898 3899 int smu_send_rma_reason(struct smu_context *smu) 3900 { 3901 int ret = 0; 3902 3903 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3904 ret = smu->ppt_funcs->send_rma_reason(smu); 3905 3906 return ret; 3907 } 3908 3909 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask) 3910 { 3911 int ret = 0; 3912 3913 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma) 3914 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask); 3915 3916 return ret; 3917 } 3918