1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "smu_v15_0_0_ppt.h" 50 #include "smu_v15_0_8_ppt.h" 51 #include "amd_pcie.h" 52 53 /* 54 * DO NOT use these for err/warn/info/debug messages. 55 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 56 * They are more MGPU friendly. 57 */ 58 #undef pr_err 59 #undef pr_warn 60 #undef pr_info 61 #undef pr_debug 62 63 static const struct amd_pm_funcs swsmu_pm_funcs; 64 static int smu_force_smuclk_levels(struct smu_context *smu, 65 enum smu_clk_type clk_type, 66 uint32_t mask); 67 static int smu_handle_task(struct smu_context *smu, 68 enum amd_dpm_forced_level level, 69 enum amd_pp_task task_id); 70 static int smu_reset(struct smu_context *smu); 71 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 72 static int smu_set_fan_control_mode(void *handle, u32 value); 73 static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit); 74 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 75 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 76 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 77 static void smu_power_profile_mode_get(struct smu_context *smu, 78 enum PP_SMC_POWER_PROFILE profile_mode); 79 static void smu_power_profile_mode_put(struct smu_context *smu, 80 enum PP_SMC_POWER_PROFILE profile_mode); 81 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type); 82 static int smu_od_edit_dpm_table(void *handle, 83 enum PP_OD_DPM_TABLE_COMMAND type, 84 long *input, uint32_t size); 85 86 static int smu_sys_get_pp_feature_mask(void *handle, 87 char *buf) 88 { 89 struct smu_context *smu = handle; 90 91 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 92 return -EOPNOTSUPP; 93 94 return smu_get_pp_feature_mask(smu, buf); 95 } 96 97 static int smu_sys_set_pp_feature_mask(void *handle, 98 uint64_t new_mask) 99 { 100 struct smu_context *smu = handle; 101 102 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 103 return -EOPNOTSUPP; 104 105 return smu_set_pp_feature_mask(smu, new_mask); 106 } 107 108 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 109 { 110 if (!smu->ppt_funcs->set_gfx_off_residency) 111 return -EINVAL; 112 113 return smu_set_gfx_off_residency(smu, value); 114 } 115 116 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 117 { 118 if (!smu->ppt_funcs->get_gfx_off_residency) 119 return -EINVAL; 120 121 return smu_get_gfx_off_residency(smu, value); 122 } 123 124 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 125 { 126 if (!smu->ppt_funcs->get_gfx_off_entrycount) 127 return -EINVAL; 128 129 return smu_get_gfx_off_entrycount(smu, value); 130 } 131 132 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 133 { 134 if (!smu->ppt_funcs->get_gfx_off_status) 135 return -EINVAL; 136 137 *value = smu_get_gfx_off_status(smu); 138 139 return 0; 140 } 141 142 int smu_set_soft_freq_range(struct smu_context *smu, 143 enum pp_clock_type type, 144 uint32_t min, 145 uint32_t max) 146 { 147 enum smu_clk_type clk_type; 148 int ret = 0; 149 150 clk_type = smu_convert_to_smuclk(type); 151 if (clk_type == SMU_CLK_COUNT) 152 return -EINVAL; 153 154 if (smu->ppt_funcs->set_soft_freq_limited_range) 155 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 156 clk_type, 157 min, 158 max, 159 false); 160 161 return ret; 162 } 163 164 int smu_get_dpm_freq_range(struct smu_context *smu, 165 enum smu_clk_type clk_type, 166 uint32_t *min, 167 uint32_t *max) 168 { 169 int ret = -ENOTSUPP; 170 171 if (!min && !max) 172 return -EINVAL; 173 174 if (smu->ppt_funcs->get_dpm_ultimate_freq) 175 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 176 clk_type, 177 min, 178 max); 179 180 return ret; 181 } 182 183 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 184 { 185 int ret = 0; 186 struct amdgpu_device *adev = smu->adev; 187 188 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 189 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 190 if (ret) 191 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 192 } 193 return ret; 194 } 195 196 static u32 smu_get_mclk(void *handle, bool low) 197 { 198 struct smu_context *smu = handle; 199 uint32_t clk_freq; 200 int ret = 0; 201 202 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 203 low ? &clk_freq : NULL, 204 !low ? &clk_freq : NULL); 205 if (ret) 206 return 0; 207 return clk_freq * 100; 208 } 209 210 static u32 smu_get_sclk(void *handle, bool low) 211 { 212 struct smu_context *smu = handle; 213 uint32_t clk_freq; 214 int ret = 0; 215 216 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 217 low ? &clk_freq : NULL, 218 !low ? &clk_freq : NULL); 219 if (ret) 220 return 0; 221 return clk_freq * 100; 222 } 223 224 static int smu_set_gfx_imu_enable(struct smu_context *smu) 225 { 226 struct amdgpu_device *adev = smu->adev; 227 228 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 229 return 0; 230 231 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 232 return 0; 233 234 return smu_set_gfx_power_up_by_imu(smu); 235 } 236 237 static bool is_vcn_enabled(struct amdgpu_device *adev) 238 { 239 int i; 240 241 for (i = 0; i < adev->num_ip_blocks; i++) { 242 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 243 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 244 !adev->ip_blocks[i].status.valid) 245 return false; 246 } 247 248 return true; 249 } 250 251 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 252 bool enable, 253 int inst) 254 { 255 struct smu_power_context *smu_power = &smu->smu_power; 256 struct smu_power_gate *power_gate = &smu_power->power_gate; 257 int ret = 0; 258 259 /* 260 * don't poweron vcn/jpeg when they are skipped. 261 */ 262 if (!is_vcn_enabled(smu->adev)) 263 return 0; 264 265 if (!smu->ppt_funcs->dpm_set_vcn_enable) 266 return 0; 267 268 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable) 269 return 0; 270 271 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst); 272 if (!ret) 273 atomic_set(&power_gate->vcn_gated[inst], !enable); 274 275 return ret; 276 } 277 278 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 279 bool enable) 280 { 281 struct smu_power_context *smu_power = &smu->smu_power; 282 struct smu_power_gate *power_gate = &smu_power->power_gate; 283 int ret = 0; 284 285 if (!is_vcn_enabled(smu->adev)) 286 return 0; 287 288 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 289 return 0; 290 291 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 292 return 0; 293 294 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 295 if (!ret) 296 atomic_set(&power_gate->jpeg_gated, !enable); 297 298 return ret; 299 } 300 301 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 302 bool enable) 303 { 304 struct smu_power_context *smu_power = &smu->smu_power; 305 struct smu_power_gate *power_gate = &smu_power->power_gate; 306 int ret = 0; 307 308 if (!smu->ppt_funcs->dpm_set_vpe_enable) 309 return 0; 310 311 if (atomic_read(&power_gate->vpe_gated) ^ enable) 312 return 0; 313 314 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 315 if (!ret) 316 atomic_set(&power_gate->vpe_gated, !enable); 317 318 return ret; 319 } 320 321 static int smu_dpm_set_isp_enable(struct smu_context *smu, 322 bool enable) 323 { 324 struct smu_power_context *smu_power = &smu->smu_power; 325 struct smu_power_gate *power_gate = &smu_power->power_gate; 326 int ret; 327 328 if (!smu->ppt_funcs->dpm_set_isp_enable) 329 return 0; 330 331 if (atomic_read(&power_gate->isp_gated) ^ enable) 332 return 0; 333 334 ret = smu->ppt_funcs->dpm_set_isp_enable(smu, enable); 335 if (!ret) 336 atomic_set(&power_gate->isp_gated, !enable); 337 338 return ret; 339 } 340 341 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 342 bool enable) 343 { 344 struct smu_power_context *smu_power = &smu->smu_power; 345 struct smu_power_gate *power_gate = &smu_power->power_gate; 346 int ret = 0; 347 348 if (!smu->adev->enable_umsch_mm) 349 return 0; 350 351 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 352 return 0; 353 354 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 355 return 0; 356 357 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 358 if (!ret) 359 atomic_set(&power_gate->umsch_mm_gated, !enable); 360 361 return ret; 362 } 363 364 static int smu_set_mall_enable(struct smu_context *smu) 365 { 366 int ret = 0; 367 368 if (!smu->ppt_funcs->set_mall_enable) 369 return 0; 370 371 ret = smu->ppt_funcs->set_mall_enable(smu); 372 373 return ret; 374 } 375 376 /** 377 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 378 * 379 * @handle: smu_context pointer 380 * @block_type: the IP block to power gate/ungate 381 * @gate: to power gate if true, ungate otherwise 382 * @inst: the instance of the IP block to power gate/ungate 383 * 384 * This API uses no smu->mutex lock protection due to: 385 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 386 * This is guarded to be race condition free by the caller. 387 * 2. Or get called on user setting request of power_dpm_force_performance_level. 388 * Under this case, the smu->mutex lock protection is already enforced on 389 * the parent API smu_force_performance_level of the call path. 390 */ 391 static int smu_dpm_set_power_gate(void *handle, 392 uint32_t block_type, 393 bool gate, 394 int inst) 395 { 396 struct smu_context *smu = handle; 397 int ret = 0; 398 399 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 400 dev_WARN(smu->adev->dev, 401 "SMU uninitialized but power %s requested for %u!\n", 402 gate ? "gate" : "ungate", block_type); 403 return -EOPNOTSUPP; 404 } 405 406 switch (block_type) { 407 /* 408 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 409 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 410 */ 411 case AMD_IP_BLOCK_TYPE_UVD: 412 case AMD_IP_BLOCK_TYPE_VCN: 413 ret = smu_dpm_set_vcn_enable(smu, !gate, inst); 414 if (ret) 415 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n", 416 gate ? "gate" : "ungate", inst); 417 break; 418 case AMD_IP_BLOCK_TYPE_GFX: 419 ret = smu_gfx_off_control(smu, gate); 420 if (ret) 421 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 422 gate ? "enable" : "disable"); 423 break; 424 case AMD_IP_BLOCK_TYPE_SDMA: 425 ret = smu_powergate_sdma(smu, gate); 426 if (ret) 427 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 428 gate ? "gate" : "ungate"); 429 break; 430 case AMD_IP_BLOCK_TYPE_JPEG: 431 ret = smu_dpm_set_jpeg_enable(smu, !gate); 432 if (ret) 433 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 434 gate ? "gate" : "ungate"); 435 break; 436 case AMD_IP_BLOCK_TYPE_VPE: 437 ret = smu_dpm_set_vpe_enable(smu, !gate); 438 if (ret) 439 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 440 gate ? "gate" : "ungate"); 441 break; 442 case AMD_IP_BLOCK_TYPE_ISP: 443 ret = smu_dpm_set_isp_enable(smu, !gate); 444 if (ret) 445 dev_err(smu->adev->dev, "Failed to power %s ISP!\n", 446 gate ? "gate" : "ungate"); 447 break; 448 default: 449 dev_err(smu->adev->dev, "Unsupported block type!\n"); 450 return -EINVAL; 451 } 452 453 return ret; 454 } 455 456 /** 457 * smu_set_user_clk_dependencies - set user profile clock dependencies 458 * 459 * @smu: smu_context pointer 460 * @clk: enum smu_clk_type type 461 * 462 * Enable/Disable the clock dependency for the @clk type. 463 */ 464 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 465 { 466 if (smu->adev->in_suspend) 467 return; 468 469 if (clk == SMU_MCLK) { 470 smu->user_dpm_profile.clk_dependency = 0; 471 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 472 } else if (clk == SMU_FCLK) { 473 /* MCLK takes precedence over FCLK */ 474 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 475 return; 476 477 smu->user_dpm_profile.clk_dependency = 0; 478 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 479 } else if (clk == SMU_SOCCLK) { 480 /* MCLK takes precedence over SOCCLK */ 481 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 482 return; 483 484 smu->user_dpm_profile.clk_dependency = 0; 485 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 486 } else 487 /* Add clk dependencies here, if any */ 488 return; 489 } 490 491 /** 492 * smu_restore_dpm_user_profile - reinstate user dpm profile 493 * 494 * @smu: smu_context pointer 495 * 496 * Restore the saved user power configurations include power limit, 497 * clock frequencies, fan control mode and fan speed. 498 */ 499 static void smu_restore_dpm_user_profile(struct smu_context *smu) 500 { 501 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 502 int ret = 0; 503 504 if (!smu->adev->in_suspend) 505 return; 506 507 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 508 return; 509 510 /* Enable restore flag */ 511 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 512 513 /* set the user dpm power limits */ 514 for (int i = SMU_DEFAULT_PPT_LIMIT; i < SMU_LIMIT_TYPE_COUNT; i++) { 515 if (!smu->user_dpm_profile.power_limits[i]) 516 continue; 517 ret = smu_set_power_limit(smu, i, 518 smu->user_dpm_profile.power_limits[i]); 519 if (ret) 520 dev_err(smu->adev->dev, "Failed to set %d power limit value\n", i); 521 } 522 523 /* set the user dpm clock configurations */ 524 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 525 enum smu_clk_type clk_type; 526 527 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 528 /* 529 * Iterate over smu clk type and force the saved user clk 530 * configs, skip if clock dependency is enabled 531 */ 532 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 533 smu->user_dpm_profile.clk_mask[clk_type]) { 534 ret = smu_force_smuclk_levels(smu, clk_type, 535 smu->user_dpm_profile.clk_mask[clk_type]); 536 if (ret) 537 dev_err(smu->adev->dev, 538 "Failed to set clock type = %d\n", clk_type); 539 } 540 } 541 } 542 543 /* set the user dpm fan configurations */ 544 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 545 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 546 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 547 if (ret != -EOPNOTSUPP) { 548 smu->user_dpm_profile.fan_speed_pwm = 0; 549 smu->user_dpm_profile.fan_speed_rpm = 0; 550 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 551 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 552 } 553 554 if (smu->user_dpm_profile.fan_speed_pwm) { 555 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 556 if (ret != -EOPNOTSUPP) 557 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 558 } 559 560 if (smu->user_dpm_profile.fan_speed_rpm) { 561 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 562 if (ret != -EOPNOTSUPP) 563 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 564 } 565 } 566 567 /* Restore user customized OD settings */ 568 if (smu->user_dpm_profile.user_od) { 569 if (smu->ppt_funcs->restore_user_od_settings) { 570 ret = smu->ppt_funcs->restore_user_od_settings(smu); 571 if (ret) 572 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 573 } 574 } 575 576 /* Disable restore flag */ 577 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 578 } 579 580 static int smu_get_power_num_states(void *handle, 581 struct pp_states_info *state_info) 582 { 583 if (!state_info) 584 return -EINVAL; 585 586 /* not support power state */ 587 memset(state_info, 0, sizeof(struct pp_states_info)); 588 state_info->nums = 1; 589 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 590 591 return 0; 592 } 593 594 bool is_support_sw_smu(struct amdgpu_device *adev) 595 { 596 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 597 if (adev->asic_type == CHIP_VEGA20) 598 return false; 599 600 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && 601 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) 602 return true; 603 604 return false; 605 } 606 607 bool is_support_cclk_dpm(struct amdgpu_device *adev) 608 { 609 struct smu_context *smu = adev->powerplay.pp_handle; 610 611 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 612 return false; 613 614 return true; 615 } 616 617 int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, 618 uint32_t param, uint32_t *read_arg) 619 { 620 struct smu_context *smu = adev->powerplay.pp_handle; 621 int ret = -EOPNOTSUPP; 622 623 if (!smu) 624 return ret; 625 626 if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg) 627 ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg); 628 629 return ret; 630 } 631 632 int amdgpu_smu_ras_feature_is_enabled(struct amdgpu_device *adev, 633 enum smu_feature_mask mask) 634 { 635 struct smu_context *smu = adev->powerplay.pp_handle; 636 int ret = 0; 637 638 if (smu->ppt_funcs && smu->ppt_funcs->feature_is_enabled) 639 ret = smu->ppt_funcs->feature_is_enabled(smu, mask); 640 641 return ret; 642 } 643 644 static int smu_sys_get_pp_table(void *handle, 645 char **table) 646 { 647 struct smu_context *smu = handle; 648 struct smu_table_context *smu_table = &smu->smu_table; 649 650 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 651 return -EOPNOTSUPP; 652 653 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 654 return -EOPNOTSUPP; 655 656 if (smu_table->hardcode_pptable) 657 *table = smu_table->hardcode_pptable; 658 else 659 *table = smu_table->power_play_table; 660 661 return smu_table->power_play_table_size; 662 } 663 664 static int smu_sys_set_pp_table(void *handle, 665 const char *buf, 666 size_t size) 667 { 668 struct smu_context *smu = handle; 669 struct smu_table_context *smu_table = &smu->smu_table; 670 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 671 int ret = 0; 672 673 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 674 return -EOPNOTSUPP; 675 676 if (header->usStructureSize != size) { 677 dev_err(smu->adev->dev, "pp table size not matched !\n"); 678 return -EIO; 679 } 680 681 if (!smu_table->hardcode_pptable || smu_table->power_play_table_size < size) { 682 kfree(smu_table->hardcode_pptable); 683 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 684 if (!smu_table->hardcode_pptable) 685 return -ENOMEM; 686 } 687 688 memcpy(smu_table->hardcode_pptable, buf, size); 689 smu_table->power_play_table = smu_table->hardcode_pptable; 690 smu_table->power_play_table_size = size; 691 692 /* 693 * Special hw_fini action(for Navi1x, the DPMs disablement will be 694 * skipped) may be needed for custom pptable uploading. 695 */ 696 smu->uploading_custom_pp_table = true; 697 698 ret = smu_reset(smu); 699 if (ret) 700 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 701 702 smu->uploading_custom_pp_table = false; 703 704 return ret; 705 } 706 707 static int smu_init_driver_allowed_feature_mask(struct smu_context *smu) 708 { 709 /* 710 * With SCPM enabled, the allowed featuremasks setting(via 711 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 712 * That means there is no way to let PMFW knows the settings below. 713 * Thus, we just assume all the features are allowed under 714 * such scenario. 715 */ 716 if (smu->adev->scpm_enabled) { 717 smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); 718 return 0; 719 } 720 721 smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); 722 723 return smu_init_allowed_features(smu); 724 } 725 726 static int smu_set_funcs(struct amdgpu_device *adev) 727 { 728 struct smu_context *smu = adev->powerplay.pp_handle; 729 730 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 731 smu->od_enabled = true; 732 733 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 734 case IP_VERSION(11, 0, 0): 735 case IP_VERSION(11, 0, 5): 736 case IP_VERSION(11, 0, 9): 737 navi10_set_ppt_funcs(smu); 738 break; 739 case IP_VERSION(11, 0, 7): 740 case IP_VERSION(11, 0, 11): 741 case IP_VERSION(11, 0, 12): 742 case IP_VERSION(11, 0, 13): 743 sienna_cichlid_set_ppt_funcs(smu); 744 break; 745 case IP_VERSION(12, 0, 0): 746 case IP_VERSION(12, 0, 1): 747 renoir_set_ppt_funcs(smu); 748 break; 749 case IP_VERSION(11, 5, 0): 750 case IP_VERSION(11, 5, 2): 751 vangogh_set_ppt_funcs(smu); 752 break; 753 case IP_VERSION(13, 0, 1): 754 case IP_VERSION(13, 0, 3): 755 case IP_VERSION(13, 0, 8): 756 yellow_carp_set_ppt_funcs(smu); 757 break; 758 case IP_VERSION(13, 0, 4): 759 case IP_VERSION(13, 0, 11): 760 smu_v13_0_4_set_ppt_funcs(smu); 761 break; 762 case IP_VERSION(13, 0, 5): 763 smu_v13_0_5_set_ppt_funcs(smu); 764 break; 765 case IP_VERSION(11, 0, 8): 766 cyan_skillfish_set_ppt_funcs(smu); 767 break; 768 case IP_VERSION(11, 0, 2): 769 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 770 arcturus_set_ppt_funcs(smu); 771 /* OD is not supported on Arcturus */ 772 smu->od_enabled = false; 773 break; 774 case IP_VERSION(13, 0, 2): 775 aldebaran_set_ppt_funcs(smu); 776 /* Enable pp_od_clk_voltage node */ 777 smu->od_enabled = true; 778 break; 779 case IP_VERSION(13, 0, 0): 780 case IP_VERSION(13, 0, 10): 781 smu_v13_0_0_set_ppt_funcs(smu); 782 break; 783 case IP_VERSION(13, 0, 6): 784 case IP_VERSION(13, 0, 14): 785 case IP_VERSION(13, 0, 12): 786 smu_v13_0_6_set_ppt_funcs(smu); 787 /* Enable pp_od_clk_voltage node */ 788 smu->od_enabled = true; 789 break; 790 case IP_VERSION(13, 0, 7): 791 smu_v13_0_7_set_ppt_funcs(smu); 792 break; 793 case IP_VERSION(14, 0, 0): 794 case IP_VERSION(14, 0, 1): 795 case IP_VERSION(14, 0, 4): 796 case IP_VERSION(14, 0, 5): 797 smu_v14_0_0_set_ppt_funcs(smu); 798 break; 799 case IP_VERSION(14, 0, 2): 800 case IP_VERSION(14, 0, 3): 801 smu_v14_0_2_set_ppt_funcs(smu); 802 break; 803 case IP_VERSION(15, 0, 0): 804 case IP_VERSION(15, 0, 5): 805 case IP_VERSION(15, 0, 9): 806 smu_v15_0_0_set_ppt_funcs(smu); 807 break; 808 case IP_VERSION(15, 0, 8): 809 smu_v15_0_8_set_ppt_funcs(smu); 810 smu->od_enabled = true; 811 break; 812 default: 813 return -EINVAL; 814 } 815 816 return 0; 817 } 818 819 static int smu_early_init(struct amdgpu_ip_block *ip_block) 820 { 821 struct amdgpu_device *adev = ip_block->adev; 822 struct smu_context *smu; 823 int r; 824 825 smu = kzalloc_obj(struct smu_context); 826 if (!smu) 827 return -ENOMEM; 828 829 smu->adev = adev; 830 smu->pm_enabled = !!amdgpu_dpm; 831 smu->is_apu = false; 832 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 833 smu->smu_baco.platform_support = false; 834 smu->smu_baco.maco_support = false; 835 smu->user_dpm_profile.fan_mode = -1; 836 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN; 837 838 adev->powerplay.pp_handle = smu; 839 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 840 841 r = smu_set_funcs(adev); 842 if (r) 843 return r; 844 return smu_init_microcode(smu); 845 } 846 847 static int smu_set_default_dpm_table(struct smu_context *smu) 848 { 849 struct amdgpu_device *adev = smu->adev; 850 struct smu_power_context *smu_power = &smu->smu_power; 851 struct smu_power_gate *power_gate = &smu_power->power_gate; 852 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i; 853 int ret = 0; 854 855 if (!smu->ppt_funcs->set_default_dpm_table) 856 return 0; 857 858 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 859 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 860 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]); 861 } 862 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 863 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 864 865 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 866 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 867 ret = smu_dpm_set_vcn_enable(smu, true, i); 868 if (ret) 869 return ret; 870 } 871 } 872 873 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 874 ret = smu_dpm_set_jpeg_enable(smu, true); 875 if (ret) 876 goto err_out; 877 } 878 879 ret = smu->ppt_funcs->set_default_dpm_table(smu); 880 if (ret) 881 dev_err(smu->adev->dev, 882 "Failed to setup default dpm clock tables!\n"); 883 884 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 885 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 886 err_out: 887 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 888 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 889 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i); 890 } 891 892 return ret; 893 } 894 895 static int smu_apply_default_config_table_settings(struct smu_context *smu) 896 { 897 struct amdgpu_device *adev = smu->adev; 898 int ret = 0; 899 900 ret = smu_get_default_config_table_settings(smu, 901 &adev->pm.config_table); 902 if (ret) 903 return ret; 904 905 return smu_set_config_table(smu, &adev->pm.config_table); 906 } 907 908 static int smu_late_init(struct amdgpu_ip_block *ip_block) 909 { 910 struct amdgpu_device *adev = ip_block->adev; 911 struct smu_context *smu = adev->powerplay.pp_handle; 912 int ret = 0; 913 914 smu_set_fine_grain_gfx_freq_parameters(smu); 915 916 if (!smu->pm_enabled) 917 return 0; 918 919 ret = smu_post_init(smu); 920 if (ret) { 921 dev_err(adev->dev, "Failed to post smu init!\n"); 922 return ret; 923 } 924 925 /* 926 * Explicitly notify PMFW the power mode the system in. Since 927 * the PMFW may boot the ASIC with a different mode. 928 * For those supporting ACDC switch via gpio, PMFW will 929 * handle the switch automatically. Driver involvement 930 * is unnecessary. 931 */ 932 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 933 smu_set_ac_dc(smu); 934 935 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 936 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 937 return 0; 938 939 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 940 ret = smu_set_default_od_settings(smu); 941 if (ret) { 942 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 943 return ret; 944 } 945 } 946 947 ret = smu_populate_umd_state_clk(smu); 948 if (ret) { 949 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 950 return ret; 951 } 952 953 ret = smu_get_asic_power_limits(smu, 954 &smu->current_power_limit, 955 &smu->default_power_limit, 956 &smu->max_power_limit, 957 &smu->min_power_limit); 958 if (ret) { 959 dev_err(adev->dev, "Failed to get asic power limits!\n"); 960 return ret; 961 } 962 963 if (!amdgpu_sriov_vf(adev)) 964 smu_get_unique_id(smu); 965 966 smu_get_fan_parameters(smu); 967 968 smu_handle_task(smu, 969 smu->smu_dpm.dpm_level, 970 AMD_PP_TASK_COMPLETE_INIT); 971 972 ret = smu_apply_default_config_table_settings(smu); 973 if (ret && (ret != -EOPNOTSUPP)) { 974 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 975 return ret; 976 } 977 978 smu_restore_dpm_user_profile(smu); 979 980 return 0; 981 } 982 983 static int smu_init_fb_allocations(struct smu_context *smu) 984 { 985 struct amdgpu_device *adev = smu->adev; 986 struct smu_table_context *smu_table = &smu->smu_table; 987 struct smu_table *tables = smu_table->tables; 988 struct smu_table *driver_table = &(smu_table->driver_table); 989 uint32_t max_table_size = 0; 990 int ret, i; 991 992 /* VRAM allocation for tool table */ 993 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 994 ret = amdgpu_bo_create_kernel(adev, 995 tables[SMU_TABLE_PMSTATUSLOG].size, 996 tables[SMU_TABLE_PMSTATUSLOG].align, 997 tables[SMU_TABLE_PMSTATUSLOG].domain, 998 &tables[SMU_TABLE_PMSTATUSLOG].bo, 999 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1000 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1001 if (ret) { 1002 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 1003 return ret; 1004 } 1005 } 1006 1007 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 1008 /* VRAM allocation for driver table */ 1009 for (i = 0; i < SMU_TABLE_COUNT; i++) { 1010 if (tables[i].size == 0) 1011 continue; 1012 1013 /* If one of the tables has VRAM domain restriction, keep it in 1014 * VRAM 1015 */ 1016 if ((tables[i].domain & 1017 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 1018 AMDGPU_GEM_DOMAIN_VRAM) 1019 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 1020 1021 if (i == SMU_TABLE_PMSTATUSLOG) 1022 continue; 1023 1024 if (max_table_size < tables[i].size) 1025 max_table_size = tables[i].size; 1026 } 1027 1028 driver_table->size = max_table_size; 1029 driver_table->align = PAGE_SIZE; 1030 1031 ret = amdgpu_bo_create_kernel(adev, 1032 driver_table->size, 1033 driver_table->align, 1034 driver_table->domain, 1035 &driver_table->bo, 1036 &driver_table->mc_address, 1037 &driver_table->cpu_addr); 1038 if (ret) { 1039 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 1040 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 1041 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 1042 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1043 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1044 } 1045 1046 return ret; 1047 } 1048 1049 static int smu_fini_fb_allocations(struct smu_context *smu) 1050 { 1051 struct smu_table_context *smu_table = &smu->smu_table; 1052 struct smu_table *tables = smu_table->tables; 1053 struct smu_table *driver_table = &(smu_table->driver_table); 1054 1055 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 1056 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 1057 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1058 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1059 1060 amdgpu_bo_free_kernel(&driver_table->bo, 1061 &driver_table->mc_address, 1062 &driver_table->cpu_addr); 1063 1064 return 0; 1065 } 1066 1067 static void smu_update_gpu_addresses(struct smu_context *smu) 1068 { 1069 struct smu_table_context *smu_table = &smu->smu_table; 1070 struct smu_table *pm_status_table = smu_table->tables + SMU_TABLE_PMSTATUSLOG; 1071 struct smu_table *driver_table = &(smu_table->driver_table); 1072 struct smu_table *dummy_read_1_table = &smu_table->dummy_read_1_table; 1073 1074 if (pm_status_table->bo) 1075 pm_status_table->mc_address = amdgpu_bo_fb_aper_addr(pm_status_table->bo); 1076 if (driver_table->bo) 1077 driver_table->mc_address = amdgpu_bo_fb_aper_addr(driver_table->bo); 1078 if (dummy_read_1_table->bo) 1079 dummy_read_1_table->mc_address = amdgpu_bo_fb_aper_addr(dummy_read_1_table->bo); 1080 } 1081 1082 /** 1083 * smu_alloc_memory_pool - allocate memory pool in the system memory 1084 * 1085 * @smu: amdgpu_device pointer 1086 * 1087 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 1088 * and DramLogSetDramAddr can notify it changed. 1089 * 1090 * Returns 0 on success, error on failure. 1091 */ 1092 static int smu_alloc_memory_pool(struct smu_context *smu) 1093 { 1094 struct amdgpu_device *adev = smu->adev; 1095 struct smu_table_context *smu_table = &smu->smu_table; 1096 struct smu_table *memory_pool = &smu_table->memory_pool; 1097 uint64_t pool_size = smu->pool_size; 1098 int ret = 0; 1099 1100 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1101 return ret; 1102 1103 memory_pool->size = pool_size; 1104 memory_pool->align = PAGE_SIZE; 1105 memory_pool->domain = 1106 (adev->pm.smu_debug_mask & SMU_DEBUG_POOL_USE_VRAM) ? 1107 AMDGPU_GEM_DOMAIN_VRAM : 1108 AMDGPU_GEM_DOMAIN_GTT; 1109 1110 switch (pool_size) { 1111 case SMU_MEMORY_POOL_SIZE_256_MB: 1112 case SMU_MEMORY_POOL_SIZE_512_MB: 1113 case SMU_MEMORY_POOL_SIZE_1_GB: 1114 case SMU_MEMORY_POOL_SIZE_2_GB: 1115 ret = amdgpu_bo_create_kernel(adev, 1116 memory_pool->size, 1117 memory_pool->align, 1118 memory_pool->domain, 1119 &memory_pool->bo, 1120 &memory_pool->mc_address, 1121 &memory_pool->cpu_addr); 1122 if (ret) 1123 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1124 break; 1125 default: 1126 break; 1127 } 1128 1129 return ret; 1130 } 1131 1132 static int smu_free_memory_pool(struct smu_context *smu) 1133 { 1134 struct smu_table_context *smu_table = &smu->smu_table; 1135 struct smu_table *memory_pool = &smu_table->memory_pool; 1136 1137 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1138 return 0; 1139 1140 amdgpu_bo_free_kernel(&memory_pool->bo, 1141 &memory_pool->mc_address, 1142 &memory_pool->cpu_addr); 1143 1144 memset(memory_pool, 0, sizeof(struct smu_table)); 1145 1146 return 0; 1147 } 1148 1149 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1150 { 1151 struct smu_table_context *smu_table = &smu->smu_table; 1152 struct smu_table *dummy_read_1_table = 1153 &smu_table->dummy_read_1_table; 1154 struct amdgpu_device *adev = smu->adev; 1155 int ret = 0; 1156 1157 if (!dummy_read_1_table->size) 1158 return 0; 1159 1160 ret = amdgpu_bo_create_kernel(adev, 1161 dummy_read_1_table->size, 1162 dummy_read_1_table->align, 1163 dummy_read_1_table->domain, 1164 &dummy_read_1_table->bo, 1165 &dummy_read_1_table->mc_address, 1166 &dummy_read_1_table->cpu_addr); 1167 if (ret) 1168 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1169 1170 return ret; 1171 } 1172 1173 static void smu_free_dummy_read_table(struct smu_context *smu) 1174 { 1175 struct smu_table_context *smu_table = &smu->smu_table; 1176 struct smu_table *dummy_read_1_table = 1177 &smu_table->dummy_read_1_table; 1178 1179 1180 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1181 &dummy_read_1_table->mc_address, 1182 &dummy_read_1_table->cpu_addr); 1183 1184 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1185 } 1186 1187 static int smu_smc_table_sw_init(struct smu_context *smu) 1188 { 1189 int ret; 1190 1191 /** 1192 * Create smu_table structure, and init smc tables such as 1193 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1194 */ 1195 ret = smu_init_smc_tables(smu); 1196 if (ret) { 1197 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1198 return ret; 1199 } 1200 1201 /** 1202 * Create smu_power_context structure, and allocate smu_dpm_context and 1203 * context size to fill the smu_power_context data. 1204 */ 1205 ret = smu_init_power(smu); 1206 if (ret) { 1207 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1208 return ret; 1209 } 1210 1211 /* 1212 * allocate vram bos to store smc table contents. 1213 */ 1214 ret = smu_init_fb_allocations(smu); 1215 if (ret) 1216 return ret; 1217 1218 ret = smu_alloc_memory_pool(smu); 1219 if (ret) 1220 return ret; 1221 1222 ret = smu_alloc_dummy_read_table(smu); 1223 if (ret) 1224 return ret; 1225 1226 ret = smu_i2c_init(smu); 1227 if (ret) 1228 return ret; 1229 1230 return 0; 1231 } 1232 1233 static int smu_smc_table_sw_fini(struct smu_context *smu) 1234 { 1235 int ret; 1236 1237 smu_i2c_fini(smu); 1238 1239 smu_free_dummy_read_table(smu); 1240 1241 ret = smu_free_memory_pool(smu); 1242 if (ret) 1243 return ret; 1244 1245 ret = smu_fini_fb_allocations(smu); 1246 if (ret) 1247 return ret; 1248 1249 ret = smu_fini_power(smu); 1250 if (ret) { 1251 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1252 return ret; 1253 } 1254 1255 ret = smu_fini_smc_tables(smu); 1256 if (ret) { 1257 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1258 return ret; 1259 } 1260 1261 return 0; 1262 } 1263 1264 static void smu_throttling_logging_work_fn(struct work_struct *work) 1265 { 1266 struct smu_context *smu = container_of(work, struct smu_context, 1267 throttling_logging_work); 1268 1269 smu_log_thermal_throttling(smu); 1270 } 1271 1272 static void smu_interrupt_work_fn(struct work_struct *work) 1273 { 1274 struct smu_context *smu = container_of(work, struct smu_context, 1275 interrupt_work); 1276 1277 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1278 smu->ppt_funcs->interrupt_work(smu); 1279 } 1280 1281 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1282 { 1283 struct smu_context *smu = 1284 container_of(work, struct smu_context, swctf_delayed_work.work); 1285 struct smu_temperature_range *range = 1286 &smu->thermal_range; 1287 struct amdgpu_device *adev = smu->adev; 1288 uint32_t hotspot_tmp, size; 1289 1290 /* 1291 * If the hotspot temperature is confirmed as below SW CTF setting point 1292 * after the delay enforced, nothing will be done. 1293 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1294 */ 1295 if (range->software_shutdown_temp && 1296 smu->ppt_funcs->read_sensor && 1297 !smu->ppt_funcs->read_sensor(smu, 1298 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1299 &hotspot_tmp, 1300 &size) && 1301 hotspot_tmp / 1000 < range->software_shutdown_temp) 1302 return; 1303 1304 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1305 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1306 orderly_poweroff(true); 1307 } 1308 1309 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1310 { 1311 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1312 struct smu_dpm_policy_ctxt *policy_ctxt; 1313 struct smu_dpm_policy *policy; 1314 1315 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1316 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1317 if (policy) 1318 policy->current_level = XGMI_PLPD_DEFAULT; 1319 return; 1320 } 1321 1322 /* PMFW put PLPD into default policy after enabling the feature */ 1323 if (smu_feature_is_enabled(smu, 1324 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1325 if (policy) 1326 policy->current_level = XGMI_PLPD_DEFAULT; 1327 } else { 1328 policy_ctxt = dpm_ctxt->dpm_policies; 1329 if (policy_ctxt) 1330 policy_ctxt->policy_mask &= 1331 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1332 } 1333 } 1334 1335 static void smu_init_power_profile(struct smu_context *smu) 1336 { 1337 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) 1338 smu->power_profile_mode = 1339 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1340 smu_power_profile_mode_get(smu, smu->power_profile_mode); 1341 } 1342 1343 void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id) 1344 { 1345 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1346 1347 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT) 1348 return; 1349 1350 set_bit(fea_id, fea_cap->cap_map); 1351 } 1352 1353 bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id) 1354 { 1355 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1356 1357 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT) 1358 return false; 1359 1360 return test_bit(fea_id, fea_cap->cap_map); 1361 } 1362 1363 static void smu_feature_cap_init(struct smu_context *smu) 1364 { 1365 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1366 1367 bitmap_zero(fea_cap->cap_map, SMU_FEATURE_CAP_ID__COUNT); 1368 } 1369 1370 static int smu_set_power_dep(struct smu_context *smu, bool enable) 1371 { 1372 if (!smu->ppt_funcs->set_power_dep) 1373 return 0; 1374 1375 return smu->ppt_funcs->set_power_dep(smu, enable); 1376 } 1377 1378 static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1379 { 1380 struct amdgpu_device *adev = ip_block->adev; 1381 struct smu_context *smu = adev->powerplay.pp_handle; 1382 int i, ret; 1383 1384 smu->pool_size = adev->pm.smu_prv_buffer_size; 1385 smu_feature_init(smu, SMU_FEATURE_NUM_DEFAULT); 1386 1387 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1388 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1389 atomic64_set(&smu->throttle_int_counter, 0); 1390 smu->watermarks_bitmap = 0; 1391 1392 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1393 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1); 1394 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1395 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1396 atomic_set(&smu->smu_power.power_gate.isp_gated, 1); 1397 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1398 1399 smu_init_power_profile(smu); 1400 smu->display_config = &adev->pm.pm_display_cfg; 1401 1402 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1403 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1404 1405 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1406 smu_swctf_delayed_work_handler); 1407 1408 smu_feature_cap_init(smu); 1409 1410 ret = smu_smc_table_sw_init(smu); 1411 if (ret) { 1412 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1413 return ret; 1414 } 1415 1416 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1417 ret = smu_get_vbios_bootup_values(smu); 1418 if (ret) { 1419 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1420 return ret; 1421 } 1422 1423 ret = smu_init_pptable_microcode(smu); 1424 if (ret) { 1425 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1426 return ret; 1427 } 1428 1429 ret = smu_register_irq_handler(smu); 1430 if (ret) { 1431 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1432 return ret; 1433 } 1434 1435 /* If there is no way to query fan control mode, fan control is not supported */ 1436 if (!smu->ppt_funcs->get_fan_control_mode) 1437 smu->adev->pm.no_fan = true; 1438 1439 smu_set_power_dep(smu, true); 1440 1441 return 0; 1442 } 1443 1444 static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1445 { 1446 struct amdgpu_device *adev = ip_block->adev; 1447 struct smu_context *smu = adev->powerplay.pp_handle; 1448 int ret; 1449 1450 ret = smu_smc_table_sw_fini(smu); 1451 if (ret) { 1452 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1453 return ret; 1454 } 1455 1456 if (smu->custom_profile_params) { 1457 kfree(smu->custom_profile_params); 1458 smu->custom_profile_params = NULL; 1459 } 1460 1461 smu_fini_microcode(smu); 1462 1463 smu_set_power_dep(smu, false); 1464 1465 return 0; 1466 } 1467 1468 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1469 { 1470 struct amdgpu_device *adev = smu->adev; 1471 struct smu_temperature_range *range = 1472 &smu->thermal_range; 1473 int ret = 0; 1474 1475 if (!smu->ppt_funcs->get_thermal_temperature_range) 1476 return 0; 1477 1478 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1479 if (ret) 1480 return ret; 1481 1482 adev->pm.dpm.thermal.min_temp = range->min; 1483 adev->pm.dpm.thermal.max_temp = range->max; 1484 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1485 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1486 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1487 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1488 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1489 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1490 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1491 1492 return ret; 1493 } 1494 1495 /** 1496 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1497 * 1498 * @smu: smu_context pointer 1499 * 1500 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1501 * Returns 0 on success, error on failure. 1502 */ 1503 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1504 { 1505 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1506 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1507 struct amdgpu_device *adev = smu->adev; 1508 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1509 uint64_t start, end; 1510 int ret, i, j; 1511 1512 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1513 if (ret) { 1514 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1515 return ret; 1516 } 1517 1518 /* 1519 * The exclusion ranges array we got might be filled with holes and duplicate 1520 * entries. For example: 1521 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1522 * We need to do some sortups to eliminate those holes and duplicate entries. 1523 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1524 */ 1525 for (i = 0; i < num_of_wbrf_ranges; i++) { 1526 start = wifi_bands[i].start; 1527 end = wifi_bands[i].end; 1528 1529 /* get the last valid entry to fill the intermediate hole */ 1530 if (!start && !end) { 1531 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1532 if (wifi_bands[j].start && wifi_bands[j].end) 1533 break; 1534 1535 /* no valid entry left */ 1536 if (j <= i) 1537 break; 1538 1539 start = wifi_bands[i].start = wifi_bands[j].start; 1540 end = wifi_bands[i].end = wifi_bands[j].end; 1541 wifi_bands[j].start = 0; 1542 wifi_bands[j].end = 0; 1543 num_of_wbrf_ranges = j; 1544 } 1545 1546 /* eliminate duplicate entries */ 1547 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1548 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1549 wifi_bands[j].start = 0; 1550 wifi_bands[j].end = 0; 1551 } 1552 } 1553 } 1554 1555 /* Send the sorted wifi_bands to PMFW */ 1556 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1557 /* Try to set the wifi_bands again */ 1558 if (unlikely(ret == -EBUSY)) { 1559 mdelay(5); 1560 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1561 } 1562 1563 return ret; 1564 } 1565 1566 /** 1567 * smu_wbrf_event_handler - handle notify events 1568 * 1569 * @nb: notifier block 1570 * @action: event type 1571 * @_arg: event data 1572 * 1573 * Calls relevant amdgpu function in response to wbrf event 1574 * notification from kernel. 1575 */ 1576 static int smu_wbrf_event_handler(struct notifier_block *nb, 1577 unsigned long action, void *_arg) 1578 { 1579 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1580 1581 switch (action) { 1582 case WBRF_CHANGED: 1583 schedule_delayed_work(&smu->wbrf_delayed_work, 1584 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1585 break; 1586 default: 1587 return NOTIFY_DONE; 1588 } 1589 1590 return NOTIFY_OK; 1591 } 1592 1593 /** 1594 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1595 * 1596 * @work: struct work_struct pointer 1597 * 1598 * Flood is over and driver will consume the latest exclusion ranges. 1599 */ 1600 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1601 { 1602 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1603 1604 smu_wbrf_handle_exclusion_ranges(smu); 1605 } 1606 1607 /** 1608 * smu_wbrf_support_check - check wbrf support 1609 * 1610 * @smu: smu_context pointer 1611 * 1612 * Verifies the ACPI interface whether wbrf is supported. 1613 */ 1614 static void smu_wbrf_support_check(struct smu_context *smu) 1615 { 1616 struct amdgpu_device *adev = smu->adev; 1617 1618 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1619 acpi_amd_wbrf_supported_consumer(adev->dev); 1620 1621 if (smu->wbrf_supported) 1622 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1623 } 1624 1625 /** 1626 * smu_wbrf_init - init driver wbrf support 1627 * 1628 * @smu: smu_context pointer 1629 * 1630 * Verifies the AMD ACPI interfaces and registers with the wbrf 1631 * notifier chain if wbrf feature is supported. 1632 * Returns 0 on success, error on failure. 1633 */ 1634 static int smu_wbrf_init(struct smu_context *smu) 1635 { 1636 int ret; 1637 1638 if (!smu->wbrf_supported) 1639 return 0; 1640 1641 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1642 1643 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1644 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1645 if (ret) 1646 return ret; 1647 1648 /* 1649 * Some wifiband exclusion ranges may be already there 1650 * before our driver loaded. To make sure our driver 1651 * is awared of those exclusion ranges. 1652 */ 1653 schedule_delayed_work(&smu->wbrf_delayed_work, 1654 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1655 1656 return 0; 1657 } 1658 1659 /** 1660 * smu_wbrf_fini - tear down driver wbrf support 1661 * 1662 * @smu: smu_context pointer 1663 * 1664 * Unregisters with the wbrf notifier chain. 1665 */ 1666 static void smu_wbrf_fini(struct smu_context *smu) 1667 { 1668 if (!smu->wbrf_supported) 1669 return; 1670 1671 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1672 1673 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1674 } 1675 1676 static int smu_smc_hw_setup(struct smu_context *smu) 1677 { 1678 struct amdgpu_device *adev = smu->adev; 1679 uint8_t pcie_gen = 0, pcie_width = 0; 1680 struct smu_feature_bits features_supported; 1681 int ret = 0; 1682 1683 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1684 case IP_VERSION(11, 0, 7): 1685 case IP_VERSION(11, 0, 11): 1686 case IP_VERSION(11, 5, 0): 1687 case IP_VERSION(11, 5, 2): 1688 case IP_VERSION(11, 0, 12): 1689 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1690 dev_info(adev->dev, "dpm has been enabled\n"); 1691 ret = smu_system_features_control(smu, true); 1692 if (ret) { 1693 dev_err(adev->dev, "Failed system features control!\n"); 1694 return ret; 1695 } 1696 1697 return smu_enable_thermal_alert(smu); 1698 } 1699 break; 1700 default: 1701 break; 1702 } 1703 1704 ret = smu_init_display_count(smu, 0); 1705 if (ret) { 1706 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1707 return ret; 1708 } 1709 1710 ret = smu_set_driver_table_location(smu); 1711 if (ret) { 1712 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1713 return ret; 1714 } 1715 1716 /* 1717 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1718 */ 1719 ret = smu_set_tool_table_location(smu); 1720 if (ret) { 1721 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1722 return ret; 1723 } 1724 1725 /* 1726 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1727 * pool location. 1728 */ 1729 ret = smu_notify_memory_pool_location(smu); 1730 if (ret) { 1731 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1732 return ret; 1733 } 1734 1735 /* 1736 * It is assumed the pptable used before runpm is same as 1737 * the one used afterwards. Thus, we can reuse the stored 1738 * copy and do not need to resetup the pptable again. 1739 */ 1740 if (!adev->in_runpm) { 1741 ret = smu_setup_pptable(smu); 1742 if (ret) { 1743 dev_err(adev->dev, "Failed to setup pptable!\n"); 1744 return ret; 1745 } 1746 } 1747 1748 /* smu_dump_pptable(smu); */ 1749 1750 /* 1751 * With SCPM enabled, PSP is responsible for the PPTable transferring 1752 * (to SMU). Driver involvement is not needed and permitted. 1753 */ 1754 if (!adev->scpm_enabled) { 1755 /* 1756 * Copy pptable bo in the vram to smc with SMU MSGs such as 1757 * SetDriverDramAddr and TransferTableDram2Smu. 1758 */ 1759 ret = smu_write_pptable(smu); 1760 if (ret) { 1761 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1762 return ret; 1763 } 1764 } 1765 1766 /* issue Run*Btc msg */ 1767 ret = smu_run_btc(smu); 1768 if (ret) 1769 return ret; 1770 1771 /* Enable UclkShadow on wbrf supported */ 1772 if (smu->wbrf_supported) { 1773 ret = smu_enable_uclk_shadow(smu, true); 1774 if (ret) { 1775 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1776 return ret; 1777 } 1778 } 1779 1780 /* 1781 * With SCPM enabled, these actions(and relevant messages) are 1782 * not needed and permitted. 1783 */ 1784 if (!adev->scpm_enabled) { 1785 ret = smu_feature_set_allowed_mask(smu); 1786 if (ret) { 1787 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1788 return ret; 1789 } 1790 } 1791 1792 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) 1793 pcie_gen = 4; 1794 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1795 pcie_gen = 3; 1796 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1797 pcie_gen = 2; 1798 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1799 pcie_gen = 1; 1800 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1801 pcie_gen = 0; 1802 1803 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1804 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1805 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1806 */ 1807 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) 1808 pcie_width = 7; 1809 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1810 pcie_width = 6; 1811 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1812 pcie_width = 5; 1813 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1814 pcie_width = 4; 1815 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1816 pcie_width = 3; 1817 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1818 pcie_width = 2; 1819 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1820 pcie_width = 1; 1821 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1822 if (ret) { 1823 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1824 return ret; 1825 } 1826 1827 ret = smu_system_features_control(smu, true); 1828 if (ret) { 1829 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1830 return ret; 1831 } 1832 1833 smu_init_xgmi_plpd_mode(smu); 1834 1835 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1836 if (ret) { 1837 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1838 return ret; 1839 } 1840 smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED, 1841 features_supported.bits); 1842 1843 if (!smu_is_dpm_running(smu)) 1844 dev_info(adev->dev, "dpm has been disabled\n"); 1845 1846 /* 1847 * Set initialized values (get from vbios) to dpm tables context such as 1848 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1849 * type of clks. 1850 */ 1851 ret = smu_set_default_dpm_table(smu); 1852 if (ret) { 1853 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1854 return ret; 1855 } 1856 1857 ret = smu_get_thermal_temperature_range(smu); 1858 if (ret) { 1859 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1860 return ret; 1861 } 1862 1863 ret = smu_enable_thermal_alert(smu); 1864 if (ret) { 1865 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1866 return ret; 1867 } 1868 1869 ret = smu_notify_display_change(smu); 1870 if (ret) { 1871 dev_err(adev->dev, "Failed to notify display change!\n"); 1872 return ret; 1873 } 1874 1875 /* 1876 * Set min deep sleep dce fclk with bootup value from vbios via 1877 * SetMinDeepSleepDcefclk MSG. 1878 */ 1879 ret = smu_set_min_dcef_deep_sleep(smu, 1880 smu->smu_table.boot_values.dcefclk / 100); 1881 if (ret) { 1882 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1883 return ret; 1884 } 1885 1886 /* Init wbrf support. Properly setup the notifier */ 1887 ret = smu_wbrf_init(smu); 1888 if (ret) 1889 dev_err(adev->dev, "Error during wbrf init call\n"); 1890 1891 return ret; 1892 } 1893 1894 static int smu_start_smc_engine(struct smu_context *smu) 1895 { 1896 struct amdgpu_device *adev = smu->adev; 1897 int ret = 0; 1898 1899 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 1900 smu_update_gpu_addresses(smu); 1901 1902 smu->smc_fw_state = SMU_FW_INIT; 1903 1904 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1905 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1906 if (smu->ppt_funcs->load_microcode) { 1907 ret = smu->ppt_funcs->load_microcode(smu); 1908 if (ret) 1909 return ret; 1910 } 1911 } 1912 } 1913 1914 if (smu->ppt_funcs->check_fw_status) { 1915 ret = smu->ppt_funcs->check_fw_status(smu); 1916 if (ret) { 1917 dev_err(adev->dev, "SMC is not ready\n"); 1918 return ret; 1919 } 1920 } 1921 1922 /* 1923 * Send msg GetDriverIfVersion to check if the return value is equal 1924 * with DRIVER_IF_VERSION of smc header. 1925 */ 1926 ret = smu_check_fw_version(smu); 1927 if (ret) 1928 return ret; 1929 1930 return ret; 1931 } 1932 1933 static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1934 { 1935 int i, ret; 1936 struct amdgpu_device *adev = ip_block->adev; 1937 struct smu_context *smu = adev->powerplay.pp_handle; 1938 1939 if (amdgpu_sriov_multi_vf_mode(adev)) { 1940 smu->pm_enabled = false; 1941 return 0; 1942 } 1943 1944 ret = smu_start_smc_engine(smu); 1945 if (ret) { 1946 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1947 return ret; 1948 } 1949 1950 /* 1951 * Check whether wbrf is supported. This needs to be done 1952 * before SMU setup starts since part of SMU configuration 1953 * relies on this. 1954 */ 1955 smu_wbrf_support_check(smu); 1956 1957 if (smu->is_apu) { 1958 ret = smu_set_gfx_imu_enable(smu); 1959 if (ret) 1960 return ret; 1961 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1962 smu_dpm_set_vcn_enable(smu, true, i); 1963 smu_dpm_set_jpeg_enable(smu, true); 1964 smu_dpm_set_umsch_mm_enable(smu, true); 1965 smu_set_mall_enable(smu); 1966 smu_set_gfx_cgpg(smu, true); 1967 } 1968 1969 if (!smu->pm_enabled) 1970 return 0; 1971 1972 ret = smu_init_driver_allowed_feature_mask(smu); 1973 if (ret) 1974 return ret; 1975 1976 ret = smu_smc_hw_setup(smu); 1977 if (ret) { 1978 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1979 return ret; 1980 } 1981 1982 /* 1983 * Move maximum sustainable clock retrieving here considering 1984 * 1. It is not needed on resume(from S3). 1985 * 2. DAL settings come between .hw_init and .late_init of SMU. 1986 * And DAL needs to know the maximum sustainable clocks. Thus 1987 * it cannot be put in .late_init(). 1988 */ 1989 ret = smu_init_max_sustainable_clocks(smu); 1990 if (ret) { 1991 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1992 return ret; 1993 } 1994 1995 adev->pm.dpm_enabled = true; 1996 1997 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1998 1999 return 0; 2000 } 2001 2002 static int smu_disable_dpms(struct smu_context *smu) 2003 { 2004 struct amdgpu_device *adev = smu->adev; 2005 int ret = 0; 2006 bool use_baco = !smu->is_apu && 2007 ((amdgpu_in_reset(adev) && 2008 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 2009 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 2010 2011 /* 2012 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 2013 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 2014 */ 2015 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2016 case IP_VERSION(13, 0, 0): 2017 case IP_VERSION(13, 0, 7): 2018 case IP_VERSION(13, 0, 10): 2019 case IP_VERSION(14, 0, 2): 2020 case IP_VERSION(14, 0, 3): 2021 return 0; 2022 default: 2023 break; 2024 } 2025 2026 /* 2027 * For custom pptable uploading, skip the DPM features 2028 * disable process on Navi1x ASICs. 2029 * - As the gfx related features are under control of 2030 * RLC on those ASICs. RLC reinitialization will be 2031 * needed to reenable them. That will cost much more 2032 * efforts. 2033 * 2034 * - SMU firmware can handle the DPM reenablement 2035 * properly. 2036 */ 2037 if (smu->uploading_custom_pp_table) { 2038 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2039 case IP_VERSION(11, 0, 0): 2040 case IP_VERSION(11, 0, 5): 2041 case IP_VERSION(11, 0, 9): 2042 case IP_VERSION(11, 0, 7): 2043 case IP_VERSION(11, 0, 11): 2044 case IP_VERSION(11, 5, 0): 2045 case IP_VERSION(11, 5, 2): 2046 case IP_VERSION(11, 0, 12): 2047 case IP_VERSION(11, 0, 13): 2048 return 0; 2049 default: 2050 break; 2051 } 2052 } 2053 2054 /* 2055 * For Sienna_Cichlid, PMFW will handle the features disablement properly 2056 * on BACO in. Driver involvement is unnecessary. 2057 */ 2058 if (use_baco) { 2059 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2060 case IP_VERSION(11, 0, 7): 2061 case IP_VERSION(11, 0, 0): 2062 case IP_VERSION(11, 0, 5): 2063 case IP_VERSION(11, 0, 9): 2064 case IP_VERSION(13, 0, 7): 2065 return 0; 2066 default: 2067 break; 2068 } 2069 } 2070 2071 /* 2072 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 2073 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 2074 */ 2075 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 2076 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 2077 return 0; 2078 2079 /* vangogh s0ix */ 2080 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) || 2081 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2)) && 2082 adev->in_s0ix) 2083 return 0; 2084 2085 /* 2086 * For gpu reset, runpm and hibernation through BACO, 2087 * BACO feature has to be kept enabled. 2088 */ 2089 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 2090 ret = smu_disable_all_features_with_exception(smu, 2091 SMU_FEATURE_BACO_BIT); 2092 if (ret) 2093 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 2094 } else { 2095 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 2096 if (!adev->scpm_enabled) { 2097 ret = smu_system_features_control(smu, false); 2098 if (ret) 2099 dev_err(adev->dev, "Failed to disable smu features.\n"); 2100 } 2101 } 2102 2103 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 2104 * otherwise SMU will hang while interacting with RLC if RLC is halted 2105 * this is a WA for Vangogh asic which fix the SMU hang issue. 2106 */ 2107 ret = smu_notify_rlc_state(smu, false); 2108 if (ret) { 2109 dev_err(adev->dev, "Fail to notify rlc status!\n"); 2110 return ret; 2111 } 2112 2113 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 2114 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 2115 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 2116 adev->gfx.rlc.funcs->stop(adev); 2117 2118 return ret; 2119 } 2120 2121 static int smu_smc_hw_cleanup(struct smu_context *smu) 2122 { 2123 struct amdgpu_device *adev = smu->adev; 2124 int ret = 0; 2125 2126 smu_wbrf_fini(smu); 2127 2128 cancel_work_sync(&smu->throttling_logging_work); 2129 cancel_work_sync(&smu->interrupt_work); 2130 2131 ret = smu_disable_thermal_alert(smu); 2132 if (ret) { 2133 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 2134 return ret; 2135 } 2136 2137 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2138 2139 ret = smu_disable_dpms(smu); 2140 if (ret) { 2141 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2142 return ret; 2143 } 2144 2145 return 0; 2146 } 2147 2148 static int smu_reset_mp1_state(struct smu_context *smu) 2149 { 2150 struct amdgpu_device *adev = smu->adev; 2151 int ret = 0; 2152 2153 if ((!adev->in_runpm) && (!adev->in_suspend) && 2154 (!amdgpu_in_reset(adev)) && !smu->is_apu && 2155 amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(13, 0, 0)) 2156 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2157 2158 return ret; 2159 } 2160 2161 static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2162 { 2163 struct amdgpu_device *adev = ip_block->adev; 2164 struct smu_context *smu = adev->powerplay.pp_handle; 2165 int i, ret; 2166 2167 if (amdgpu_sriov_multi_vf_mode(adev)) 2168 return 0; 2169 2170 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2171 smu_dpm_set_vcn_enable(smu, false, i); 2172 adev->vcn.inst[i].cur_state = AMD_PG_STATE_GATE; 2173 } 2174 smu_dpm_set_jpeg_enable(smu, false); 2175 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2176 smu_dpm_set_umsch_mm_enable(smu, false); 2177 2178 if (!smu->pm_enabled) 2179 return 0; 2180 2181 adev->pm.dpm_enabled = false; 2182 2183 ret = smu_smc_hw_cleanup(smu); 2184 if (ret) 2185 return ret; 2186 2187 ret = smu_reset_mp1_state(smu); 2188 if (ret) 2189 return ret; 2190 2191 return 0; 2192 } 2193 2194 static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2195 { 2196 struct amdgpu_device *adev = ip_block->adev; 2197 struct smu_context *smu = adev->powerplay.pp_handle; 2198 2199 kfree(smu); 2200 } 2201 2202 static int smu_reset(struct smu_context *smu) 2203 { 2204 struct amdgpu_device *adev = smu->adev; 2205 struct amdgpu_ip_block *ip_block; 2206 int ret; 2207 2208 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2209 if (!ip_block) 2210 return -EINVAL; 2211 2212 ret = smu_hw_fini(ip_block); 2213 if (ret) 2214 return ret; 2215 2216 ret = smu_hw_init(ip_block); 2217 if (ret) 2218 return ret; 2219 2220 ret = smu_late_init(ip_block); 2221 if (ret) 2222 return ret; 2223 2224 return 0; 2225 } 2226 2227 static int smu_suspend(struct amdgpu_ip_block *ip_block) 2228 { 2229 struct amdgpu_device *adev = ip_block->adev; 2230 struct smu_context *smu = adev->powerplay.pp_handle; 2231 int ret; 2232 uint64_t count; 2233 2234 if (amdgpu_sriov_multi_vf_mode(adev)) 2235 return 0; 2236 2237 if (!smu->pm_enabled) 2238 return 0; 2239 2240 adev->pm.dpm_enabled = false; 2241 2242 ret = smu_smc_hw_cleanup(smu); 2243 if (ret) 2244 return ret; 2245 2246 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2247 2248 smu_set_gfx_cgpg(smu, false); 2249 2250 /* 2251 * pwfw resets entrycount when device is suspended, so we save the 2252 * last value to be used when we resume to keep it consistent 2253 */ 2254 ret = smu_get_entrycount_gfxoff(smu, &count); 2255 if (!ret) 2256 adev->gfx.gfx_off_entrycount = count; 2257 2258 /* clear this on suspend so it will get reprogrammed on resume */ 2259 smu->workload_mask = 0; 2260 2261 return 0; 2262 } 2263 2264 static int smu_resume(struct amdgpu_ip_block *ip_block) 2265 { 2266 int ret; 2267 struct amdgpu_device *adev = ip_block->adev; 2268 struct smu_context *smu = adev->powerplay.pp_handle; 2269 2270 if (amdgpu_sriov_multi_vf_mode(adev)) 2271 return 0; 2272 2273 if (!smu->pm_enabled) 2274 return 0; 2275 2276 dev_info(adev->dev, "SMU is resuming...\n"); 2277 2278 ret = smu_start_smc_engine(smu); 2279 if (ret) { 2280 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2281 return ret; 2282 } 2283 2284 ret = smu_smc_hw_setup(smu); 2285 if (ret) { 2286 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2287 return ret; 2288 } 2289 2290 ret = smu_set_gfx_imu_enable(smu); 2291 if (ret) 2292 return ret; 2293 2294 smu_set_gfx_cgpg(smu, true); 2295 2296 smu->disable_uclk_switch = 0; 2297 2298 adev->pm.dpm_enabled = true; 2299 2300 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2301 2302 return 0; 2303 } 2304 2305 static int smu_display_configuration_change(void *handle, 2306 const struct amd_pp_display_configuration *display_config) 2307 { 2308 struct smu_context *smu = handle; 2309 2310 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2311 return -EOPNOTSUPP; 2312 2313 if (!display_config) 2314 return -EINVAL; 2315 2316 smu_set_min_dcef_deep_sleep(smu, 2317 display_config->min_dcef_deep_sleep_set_clk / 100); 2318 2319 return 0; 2320 } 2321 2322 static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2323 enum amd_clockgating_state state) 2324 { 2325 return 0; 2326 } 2327 2328 static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block, 2329 enum amd_powergating_state state) 2330 { 2331 return 0; 2332 } 2333 2334 static int smu_enable_umd_pstate(void *handle, 2335 enum amd_dpm_forced_level *level) 2336 { 2337 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2338 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2339 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2340 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2341 2342 struct smu_context *smu = (struct smu_context*)(handle); 2343 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2344 2345 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2346 return -EINVAL; 2347 2348 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2349 /* enter umd pstate, save current level, disable gfx cg*/ 2350 if (*level & profile_mode_mask) { 2351 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2352 smu_gpo_control(smu, false); 2353 smu_gfx_ulv_control(smu, false); 2354 smu_deep_sleep_control(smu, false); 2355 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2356 } 2357 } else { 2358 /* exit umd pstate, restore level, enable gfx cg*/ 2359 if (!(*level & profile_mode_mask)) { 2360 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2361 *level = smu_dpm_ctx->saved_dpm_level; 2362 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2363 smu_deep_sleep_control(smu, true); 2364 smu_gfx_ulv_control(smu, true); 2365 smu_gpo_control(smu, true); 2366 } 2367 } 2368 2369 return 0; 2370 } 2371 2372 static int smu_bump_power_profile_mode(struct smu_context *smu, 2373 long *custom_params, 2374 u32 custom_params_max_idx) 2375 { 2376 u32 workload_mask = 0; 2377 int i, ret = 0; 2378 2379 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2380 if (smu->workload_refcount[i]) 2381 workload_mask |= 1 << i; 2382 } 2383 2384 if (smu->workload_mask == workload_mask) 2385 return 0; 2386 2387 if (smu->ppt_funcs->set_power_profile_mode) 2388 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask, 2389 custom_params, 2390 custom_params_max_idx); 2391 2392 if (!ret) 2393 smu->workload_mask = workload_mask; 2394 2395 return ret; 2396 } 2397 2398 static void smu_power_profile_mode_get(struct smu_context *smu, 2399 enum PP_SMC_POWER_PROFILE profile_mode) 2400 { 2401 smu->workload_refcount[profile_mode]++; 2402 } 2403 2404 static void smu_power_profile_mode_put(struct smu_context *smu, 2405 enum PP_SMC_POWER_PROFILE profile_mode) 2406 { 2407 if (smu->workload_refcount[profile_mode]) 2408 smu->workload_refcount[profile_mode]--; 2409 } 2410 2411 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2412 enum amd_dpm_forced_level level, 2413 bool skip_display_settings) 2414 { 2415 int ret = 0; 2416 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2417 2418 if (!skip_display_settings) { 2419 ret = smu_display_config_changed(smu); 2420 if (ret) { 2421 dev_err(smu->adev->dev, "Failed to change display config!"); 2422 return ret; 2423 } 2424 } 2425 2426 ret = smu_apply_clocks_adjust_rules(smu); 2427 if (ret) { 2428 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2429 return ret; 2430 } 2431 2432 if (!skip_display_settings) { 2433 ret = smu_notify_smc_display_config(smu); 2434 if (ret) { 2435 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2436 return ret; 2437 } 2438 } 2439 2440 if (smu_dpm_ctx->dpm_level != level) { 2441 ret = smu_asic_set_performance_level(smu, level); 2442 if (ret) { 2443 if (ret == -EOPNOTSUPP) 2444 dev_info(smu->adev->dev, "set performance level %d not supported", 2445 level); 2446 else 2447 dev_err(smu->adev->dev, "Failed to set performance level %d", 2448 level); 2449 return ret; 2450 } 2451 2452 /* update the saved copy */ 2453 smu_dpm_ctx->dpm_level = level; 2454 } 2455 2456 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2457 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2458 smu_bump_power_profile_mode(smu, NULL, 0); 2459 2460 return ret; 2461 } 2462 2463 static int smu_handle_task(struct smu_context *smu, 2464 enum amd_dpm_forced_level level, 2465 enum amd_pp_task task_id) 2466 { 2467 int ret = 0; 2468 2469 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2470 return -EOPNOTSUPP; 2471 2472 switch (task_id) { 2473 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2474 ret = smu_pre_display_config_changed(smu); 2475 if (ret) 2476 return ret; 2477 ret = smu_adjust_power_state_dynamic(smu, level, false); 2478 break; 2479 case AMD_PP_TASK_COMPLETE_INIT: 2480 ret = smu_adjust_power_state_dynamic(smu, level, true); 2481 break; 2482 case AMD_PP_TASK_READJUST_POWER_STATE: 2483 ret = smu_adjust_power_state_dynamic(smu, level, true); 2484 break; 2485 default: 2486 break; 2487 } 2488 2489 return ret; 2490 } 2491 2492 static int smu_handle_dpm_task(void *handle, 2493 enum amd_pp_task task_id, 2494 enum amd_pm_state_type *user_state) 2495 { 2496 struct smu_context *smu = handle; 2497 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2498 2499 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2500 2501 } 2502 2503 static int smu_switch_power_profile(void *handle, 2504 enum PP_SMC_POWER_PROFILE type, 2505 bool enable) 2506 { 2507 struct smu_context *smu = handle; 2508 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2509 int ret; 2510 2511 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2512 return -EOPNOTSUPP; 2513 2514 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2515 return -EINVAL; 2516 2517 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2518 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2519 if (enable) 2520 smu_power_profile_mode_get(smu, type); 2521 else 2522 smu_power_profile_mode_put(smu, type); 2523 /* don't switch the active workload when paused */ 2524 if (smu->pause_workload) 2525 ret = 0; 2526 else 2527 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2528 if (ret) { 2529 if (enable) 2530 smu_power_profile_mode_put(smu, type); 2531 else 2532 smu_power_profile_mode_get(smu, type); 2533 return ret; 2534 } 2535 } 2536 2537 return 0; 2538 } 2539 2540 static int smu_pause_power_profile(void *handle, 2541 bool pause) 2542 { 2543 struct smu_context *smu = handle; 2544 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2545 u32 workload_mask = 1 << PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 2546 int ret; 2547 2548 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2549 return -EOPNOTSUPP; 2550 2551 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2552 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2553 smu->pause_workload = pause; 2554 2555 /* force to bootup default profile */ 2556 if (smu->pause_workload && smu->ppt_funcs->set_power_profile_mode) 2557 ret = smu->ppt_funcs->set_power_profile_mode(smu, 2558 workload_mask, 2559 NULL, 2560 0); 2561 else 2562 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2563 return ret; 2564 } 2565 2566 return 0; 2567 } 2568 2569 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2570 { 2571 struct smu_context *smu = handle; 2572 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2573 2574 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2575 return -EOPNOTSUPP; 2576 2577 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2578 return -EINVAL; 2579 2580 return smu_dpm_ctx->dpm_level; 2581 } 2582 2583 static int smu_force_performance_level(void *handle, 2584 enum amd_dpm_forced_level level) 2585 { 2586 struct smu_context *smu = handle; 2587 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2588 int ret = 0; 2589 2590 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2591 return -EOPNOTSUPP; 2592 2593 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2594 return -EINVAL; 2595 2596 ret = smu_enable_umd_pstate(smu, &level); 2597 if (ret) 2598 return ret; 2599 2600 ret = smu_handle_task(smu, level, 2601 AMD_PP_TASK_READJUST_POWER_STATE); 2602 2603 /* reset user dpm clock state */ 2604 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2605 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2606 smu->user_dpm_profile.clk_dependency = 0; 2607 } 2608 2609 return ret; 2610 } 2611 2612 static int smu_set_display_count(void *handle, uint32_t count) 2613 { 2614 struct smu_context *smu = handle; 2615 2616 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2617 return -EOPNOTSUPP; 2618 2619 return smu_init_display_count(smu, count); 2620 } 2621 2622 static int smu_force_smuclk_levels(struct smu_context *smu, 2623 enum smu_clk_type clk_type, 2624 uint32_t mask) 2625 { 2626 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2627 int ret = 0; 2628 2629 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2630 return -EOPNOTSUPP; 2631 2632 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2633 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2634 return -EINVAL; 2635 } 2636 2637 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2638 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2639 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2640 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2641 smu_set_user_clk_dependencies(smu, clk_type); 2642 } 2643 } 2644 2645 return ret; 2646 } 2647 2648 static int smu_force_ppclk_levels(void *handle, 2649 enum pp_clock_type type, 2650 uint32_t mask) 2651 { 2652 struct smu_context *smu = handle; 2653 enum smu_clk_type clk_type; 2654 2655 switch (type) { 2656 case PP_SCLK: 2657 clk_type = SMU_SCLK; break; 2658 case PP_MCLK: 2659 clk_type = SMU_MCLK; break; 2660 case PP_PCIE: 2661 clk_type = SMU_PCIE; break; 2662 case PP_SOCCLK: 2663 clk_type = SMU_SOCCLK; break; 2664 case PP_FCLK: 2665 clk_type = SMU_FCLK; break; 2666 case PP_DCEFCLK: 2667 clk_type = SMU_DCEFCLK; break; 2668 case PP_VCLK: 2669 clk_type = SMU_VCLK; break; 2670 case PP_VCLK1: 2671 clk_type = SMU_VCLK1; break; 2672 case PP_DCLK: 2673 clk_type = SMU_DCLK; break; 2674 case PP_DCLK1: 2675 clk_type = SMU_DCLK1; break; 2676 case OD_SCLK: 2677 clk_type = SMU_OD_SCLK; break; 2678 case OD_MCLK: 2679 clk_type = SMU_OD_MCLK; break; 2680 case OD_VDDC_CURVE: 2681 clk_type = SMU_OD_VDDC_CURVE; break; 2682 case OD_RANGE: 2683 clk_type = SMU_OD_RANGE; break; 2684 default: 2685 return -EINVAL; 2686 } 2687 2688 return smu_force_smuclk_levels(smu, clk_type, mask); 2689 } 2690 2691 /* 2692 * On system suspending or resetting, the dpm_enabled 2693 * flag will be cleared. So that those SMU services which 2694 * are not supported will be gated. 2695 * However, the mp1 state setting should still be granted 2696 * even if the dpm_enabled cleared. 2697 */ 2698 static int smu_set_mp1_state(void *handle, 2699 enum pp_mp1_state mp1_state) 2700 { 2701 struct smu_context *smu = handle; 2702 int ret = 0; 2703 2704 if (!smu->pm_enabled) 2705 return -EOPNOTSUPP; 2706 2707 if (smu->ppt_funcs && 2708 smu->ppt_funcs->set_mp1_state) 2709 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2710 2711 return ret; 2712 } 2713 2714 static int smu_set_df_cstate(void *handle, 2715 enum pp_df_cstate state) 2716 { 2717 struct smu_context *smu = handle; 2718 int ret = 0; 2719 2720 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2721 return -EOPNOTSUPP; 2722 2723 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2724 return 0; 2725 2726 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2727 if (ret) 2728 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2729 2730 return ret; 2731 } 2732 2733 int smu_write_watermarks_table(struct smu_context *smu) 2734 { 2735 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2736 return -EOPNOTSUPP; 2737 2738 return smu_set_watermarks_table(smu, NULL); 2739 } 2740 2741 static int smu_set_watermarks_for_clock_ranges(void *handle, 2742 struct pp_smu_wm_range_sets *clock_ranges) 2743 { 2744 struct smu_context *smu = handle; 2745 2746 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2747 return -EOPNOTSUPP; 2748 2749 if (smu->disable_watermark) 2750 return 0; 2751 2752 return smu_set_watermarks_table(smu, clock_ranges); 2753 } 2754 2755 int smu_set_ac_dc(struct smu_context *smu) 2756 { 2757 int ret = 0; 2758 2759 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2760 return -EOPNOTSUPP; 2761 2762 /* controlled by firmware */ 2763 if (smu->dc_controlled_by_gpio) 2764 return 0; 2765 2766 ret = smu_set_power_source(smu, 2767 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2768 SMU_POWER_SOURCE_DC); 2769 if (ret) 2770 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2771 smu->adev->pm.ac_power ? "AC" : "DC"); 2772 2773 return ret; 2774 } 2775 2776 const struct amd_ip_funcs smu_ip_funcs = { 2777 .name = "smu", 2778 .early_init = smu_early_init, 2779 .late_init = smu_late_init, 2780 .sw_init = smu_sw_init, 2781 .sw_fini = smu_sw_fini, 2782 .hw_init = smu_hw_init, 2783 .hw_fini = smu_hw_fini, 2784 .late_fini = smu_late_fini, 2785 .suspend = smu_suspend, 2786 .resume = smu_resume, 2787 .is_idle = NULL, 2788 .check_soft_reset = NULL, 2789 .wait_for_idle = NULL, 2790 .soft_reset = NULL, 2791 .set_clockgating_state = smu_set_clockgating_state, 2792 .set_powergating_state = smu_set_powergating_state, 2793 }; 2794 2795 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2796 .type = AMD_IP_BLOCK_TYPE_SMC, 2797 .major = 11, 2798 .minor = 0, 2799 .rev = 0, 2800 .funcs = &smu_ip_funcs, 2801 }; 2802 2803 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2804 .type = AMD_IP_BLOCK_TYPE_SMC, 2805 .major = 12, 2806 .minor = 0, 2807 .rev = 0, 2808 .funcs = &smu_ip_funcs, 2809 }; 2810 2811 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2812 .type = AMD_IP_BLOCK_TYPE_SMC, 2813 .major = 13, 2814 .minor = 0, 2815 .rev = 0, 2816 .funcs = &smu_ip_funcs, 2817 }; 2818 2819 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2820 .type = AMD_IP_BLOCK_TYPE_SMC, 2821 .major = 14, 2822 .minor = 0, 2823 .rev = 0, 2824 .funcs = &smu_ip_funcs, 2825 }; 2826 2827 const struct amdgpu_ip_block_version smu_v15_0_ip_block = { 2828 .type = AMD_IP_BLOCK_TYPE_SMC, 2829 .major = 15, 2830 .minor = 0, 2831 .rev = 0, 2832 .funcs = &smu_ip_funcs, 2833 }; 2834 2835 const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle) 2836 { 2837 struct smu_context *smu = (struct smu_context *)handle; 2838 const struct ras_smu_drv *tmp = NULL; 2839 int ret; 2840 2841 ret = smu_get_ras_smu_drv(smu, &tmp); 2842 2843 return ret ? NULL : tmp; 2844 } 2845 2846 static int smu_load_microcode(void *handle) 2847 { 2848 struct smu_context *smu = handle; 2849 struct amdgpu_device *adev = smu->adev; 2850 int ret = 0; 2851 2852 if (!smu->pm_enabled) 2853 return -EOPNOTSUPP; 2854 2855 /* This should be used for non PSP loading */ 2856 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2857 return 0; 2858 2859 if (smu->ppt_funcs->load_microcode) { 2860 ret = smu->ppt_funcs->load_microcode(smu); 2861 if (ret) { 2862 dev_err(adev->dev, "Load microcode failed\n"); 2863 return ret; 2864 } 2865 } 2866 2867 if (smu->ppt_funcs->check_fw_status) { 2868 ret = smu->ppt_funcs->check_fw_status(smu); 2869 if (ret) { 2870 dev_err(adev->dev, "SMC is not ready\n"); 2871 return ret; 2872 } 2873 } 2874 2875 return ret; 2876 } 2877 2878 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2879 { 2880 int ret = 0; 2881 2882 if (smu->ppt_funcs->set_gfx_cgpg) 2883 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2884 2885 return ret; 2886 } 2887 2888 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2889 { 2890 struct smu_context *smu = handle; 2891 int ret = 0; 2892 2893 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2894 return -EOPNOTSUPP; 2895 2896 if (!smu->ppt_funcs->set_fan_speed_rpm) 2897 return -EOPNOTSUPP; 2898 2899 if (speed == U32_MAX) 2900 return -EINVAL; 2901 2902 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2903 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2904 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2905 smu->user_dpm_profile.fan_speed_rpm = speed; 2906 2907 /* Override custom PWM setting as they cannot co-exist */ 2908 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2909 smu->user_dpm_profile.fan_speed_pwm = 0; 2910 } 2911 2912 return ret; 2913 } 2914 2915 /** 2916 * smu_get_power_limit - Request one of the SMU Power Limits 2917 * 2918 * @handle: pointer to smu context 2919 * @limit: requested limit is written back to this variable 2920 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2921 * @pp_power_type: &pp_power_type type of power 2922 * Return: 0 on success, <0 on error 2923 * 2924 */ 2925 int smu_get_power_limit(void *handle, 2926 uint32_t *limit, 2927 enum pp_power_limit_level pp_limit_level, 2928 enum pp_power_type pp_power_type) 2929 { 2930 struct smu_context *smu = handle; 2931 struct amdgpu_device *adev = smu->adev; 2932 enum smu_ppt_limit_level limit_level; 2933 uint32_t limit_type; 2934 int ret = 0; 2935 2936 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2937 return -EOPNOTSUPP; 2938 2939 if (!limit) 2940 return -EINVAL; 2941 2942 switch (pp_power_type) { 2943 case PP_PWR_TYPE_SUSTAINED: 2944 limit_type = SMU_DEFAULT_PPT_LIMIT; 2945 break; 2946 case PP_PWR_TYPE_FAST: 2947 limit_type = SMU_FAST_PPT_LIMIT; 2948 break; 2949 default: 2950 return -EOPNOTSUPP; 2951 } 2952 2953 switch (pp_limit_level) { 2954 case PP_PWR_LIMIT_CURRENT: 2955 limit_level = SMU_PPT_LIMIT_CURRENT; 2956 break; 2957 case PP_PWR_LIMIT_DEFAULT: 2958 limit_level = SMU_PPT_LIMIT_DEFAULT; 2959 break; 2960 case PP_PWR_LIMIT_MAX: 2961 limit_level = SMU_PPT_LIMIT_MAX; 2962 break; 2963 case PP_PWR_LIMIT_MIN: 2964 limit_level = SMU_PPT_LIMIT_MIN; 2965 break; 2966 default: 2967 return -EOPNOTSUPP; 2968 } 2969 2970 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2971 if (smu->ppt_funcs->get_ppt_limit) 2972 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2973 else 2974 return -EOPNOTSUPP; 2975 } else { 2976 switch (limit_level) { 2977 case SMU_PPT_LIMIT_CURRENT: 2978 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2979 case IP_VERSION(13, 0, 2): 2980 case IP_VERSION(13, 0, 6): 2981 case IP_VERSION(13, 0, 12): 2982 case IP_VERSION(13, 0, 14): 2983 case IP_VERSION(11, 0, 7): 2984 case IP_VERSION(11, 0, 11): 2985 case IP_VERSION(11, 0, 12): 2986 case IP_VERSION(11, 0, 13): 2987 case IP_VERSION(15, 0, 8): 2988 ret = smu_get_asic_power_limits(smu, 2989 &smu->current_power_limit, 2990 NULL, NULL, NULL); 2991 break; 2992 default: 2993 break; 2994 } 2995 *limit = smu->current_power_limit; 2996 break; 2997 case SMU_PPT_LIMIT_DEFAULT: 2998 *limit = smu->default_power_limit; 2999 break; 3000 case SMU_PPT_LIMIT_MAX: 3001 *limit = smu->max_power_limit; 3002 break; 3003 case SMU_PPT_LIMIT_MIN: 3004 *limit = smu->min_power_limit; 3005 break; 3006 default: 3007 return -EINVAL; 3008 } 3009 } 3010 3011 return ret; 3012 } 3013 3014 static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit) 3015 { 3016 struct smu_context *smu = handle; 3017 int ret = 0; 3018 3019 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3020 return -EOPNOTSUPP; 3021 3022 if (limit_type == SMU_DEFAULT_PPT_LIMIT) { 3023 if (!limit) 3024 limit = smu->current_power_limit; 3025 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 3026 dev_err(smu->adev->dev, 3027 "New power limit (%d) is out of range [%d,%d]\n", 3028 limit, smu->min_power_limit, smu->max_power_limit); 3029 return -EINVAL; 3030 } 3031 } 3032 3033 if (smu->ppt_funcs->set_power_limit) { 3034 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 3035 if (ret) 3036 return ret; 3037 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 3038 smu->user_dpm_profile.power_limits[limit_type] = limit; 3039 } 3040 3041 return 0; 3042 } 3043 3044 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 3045 { 3046 enum smu_clk_type clk_type; 3047 3048 switch (type) { 3049 case PP_SCLK: 3050 clk_type = SMU_SCLK; break; 3051 case PP_MCLK: 3052 clk_type = SMU_MCLK; break; 3053 case PP_PCIE: 3054 clk_type = SMU_PCIE; break; 3055 case PP_SOCCLK: 3056 clk_type = SMU_SOCCLK; break; 3057 case PP_FCLK: 3058 clk_type = SMU_FCLK; break; 3059 case PP_DCEFCLK: 3060 clk_type = SMU_DCEFCLK; break; 3061 case PP_VCLK: 3062 clk_type = SMU_VCLK; break; 3063 case PP_VCLK1: 3064 clk_type = SMU_VCLK1; break; 3065 case PP_DCLK: 3066 clk_type = SMU_DCLK; break; 3067 case PP_DCLK1: 3068 clk_type = SMU_DCLK1; break; 3069 case PP_ISPICLK: 3070 clk_type = SMU_ISPICLK; 3071 break; 3072 case PP_ISPXCLK: 3073 clk_type = SMU_ISPXCLK; 3074 break; 3075 case OD_SCLK: 3076 clk_type = SMU_OD_SCLK; break; 3077 case OD_MCLK: 3078 clk_type = SMU_OD_MCLK; break; 3079 case OD_FCLK: 3080 clk_type = SMU_OD_FCLK; break; 3081 case OD_VDDC_CURVE: 3082 clk_type = SMU_OD_VDDC_CURVE; break; 3083 case OD_RANGE: 3084 clk_type = SMU_OD_RANGE; break; 3085 case OD_VDDGFX_OFFSET: 3086 clk_type = SMU_OD_VDDGFX_OFFSET; break; 3087 case OD_CCLK: 3088 clk_type = SMU_OD_CCLK; break; 3089 case OD_FAN_CURVE: 3090 clk_type = SMU_OD_FAN_CURVE; break; 3091 case OD_ACOUSTIC_LIMIT: 3092 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 3093 case OD_ACOUSTIC_TARGET: 3094 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 3095 case OD_FAN_TARGET_TEMPERATURE: 3096 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 3097 case OD_FAN_MINIMUM_PWM: 3098 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 3099 case OD_FAN_ZERO_RPM_ENABLE: 3100 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 3101 case OD_FAN_ZERO_RPM_STOP_TEMP: 3102 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 3103 default: 3104 clk_type = SMU_CLK_COUNT; break; 3105 } 3106 3107 return clk_type; 3108 } 3109 3110 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 3111 { 3112 struct smu_context *smu = handle; 3113 enum smu_clk_type clk_type; 3114 3115 clk_type = smu_convert_to_smuclk(type); 3116 if (clk_type == SMU_CLK_COUNT) 3117 return -EINVAL; 3118 3119 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3120 return -EOPNOTSUPP; 3121 3122 if (!smu->ppt_funcs->emit_clk_levels) 3123 return -ENOENT; 3124 3125 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 3126 3127 } 3128 3129 static int smu_od_edit_dpm_table(void *handle, 3130 enum PP_OD_DPM_TABLE_COMMAND type, 3131 long *input, uint32_t size) 3132 { 3133 struct smu_context *smu = handle; 3134 int ret = 0; 3135 3136 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3137 return -EOPNOTSUPP; 3138 3139 if (smu->ppt_funcs->od_edit_dpm_table) { 3140 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 3141 } 3142 3143 return ret; 3144 } 3145 3146 static int smu_read_sensor(void *handle, 3147 int sensor, 3148 void *data, 3149 int *size_arg) 3150 { 3151 struct smu_context *smu = handle; 3152 struct amdgpu_device *adev = smu->adev; 3153 struct smu_umd_pstate_table *pstate_table = 3154 &smu->pstate_table; 3155 int i, ret = 0; 3156 uint32_t *size, size_val; 3157 3158 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3159 return -EOPNOTSUPP; 3160 3161 if (!data || !size_arg) 3162 return -EINVAL; 3163 3164 size_val = *size_arg; 3165 size = &size_val; 3166 3167 if (smu->ppt_funcs->read_sensor) 3168 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 3169 goto unlock; 3170 3171 switch (sensor) { 3172 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 3173 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 3174 *size = 4; 3175 break; 3176 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 3177 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 3178 *size = 4; 3179 break; 3180 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 3181 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 3182 *size = 4; 3183 break; 3184 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 3185 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3186 *size = 4; 3187 break; 3188 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: { 3189 struct smu_feature_bits feature_mask; 3190 uint32_t features[2]; 3191 3192 /* TBD: need to handle for > 64 bits */ 3193 ret = smu_feature_get_enabled_mask(smu, &feature_mask); 3194 if (!ret) { 3195 smu_feature_bits_to_arr32(&feature_mask, features, 64); 3196 *(uint64_t *)data = *(uint64_t *)features; 3197 } 3198 *size = 8; 3199 break; 3200 } 3201 case AMDGPU_PP_SENSOR_UVD_POWER: 3202 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3203 *size = 4; 3204 break; 3205 case AMDGPU_PP_SENSOR_VCE_POWER: 3206 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 3207 *size = 4; 3208 break; 3209 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3210 *(uint32_t *)data = 0; 3211 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 3212 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) { 3213 *(uint32_t *)data = 1; 3214 break; 3215 } 3216 } 3217 *size = 4; 3218 break; 3219 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3220 *(uint32_t *)data = 0; 3221 *size = 4; 3222 break; 3223 default: 3224 *size = 0; 3225 ret = -EOPNOTSUPP; 3226 break; 3227 } 3228 3229 unlock: 3230 // assign uint32_t to int 3231 *size_arg = size_val; 3232 3233 return ret; 3234 } 3235 3236 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3237 { 3238 int ret = -EOPNOTSUPP; 3239 struct smu_context *smu = handle; 3240 3241 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3242 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3243 3244 return ret; 3245 } 3246 3247 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3248 { 3249 int ret = -EOPNOTSUPP; 3250 struct smu_context *smu = handle; 3251 3252 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3253 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3254 3255 return ret; 3256 } 3257 3258 static int smu_get_power_profile_mode(void *handle, char *buf) 3259 { 3260 struct smu_context *smu = handle; 3261 3262 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3263 !smu->ppt_funcs->get_power_profile_mode) 3264 return -EOPNOTSUPP; 3265 if (!buf) 3266 return -EINVAL; 3267 3268 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3269 } 3270 3271 static int smu_set_power_profile_mode(void *handle, 3272 long *param, 3273 uint32_t param_size) 3274 { 3275 struct smu_context *smu = handle; 3276 bool custom = false; 3277 int ret = 0; 3278 3279 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3280 !smu->ppt_funcs->set_power_profile_mode) 3281 return -EOPNOTSUPP; 3282 3283 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) { 3284 custom = true; 3285 /* clear frontend mask so custom changes propogate */ 3286 smu->workload_mask = 0; 3287 } 3288 3289 if ((param[param_size] != smu->power_profile_mode) || custom) { 3290 /* clear the old user preference */ 3291 smu_power_profile_mode_put(smu, smu->power_profile_mode); 3292 /* set the new user preference */ 3293 smu_power_profile_mode_get(smu, param[param_size]); 3294 ret = smu_bump_power_profile_mode(smu, 3295 custom ? param : NULL, 3296 custom ? param_size : 0); 3297 if (ret) 3298 smu_power_profile_mode_put(smu, param[param_size]); 3299 else 3300 /* store the user's preference */ 3301 smu->power_profile_mode = param[param_size]; 3302 } 3303 3304 return ret; 3305 } 3306 3307 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3308 { 3309 struct smu_context *smu = handle; 3310 3311 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3312 return -EOPNOTSUPP; 3313 3314 if (!smu->ppt_funcs->get_fan_control_mode) 3315 return -EOPNOTSUPP; 3316 3317 if (!fan_mode) 3318 return -EINVAL; 3319 3320 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3321 3322 return 0; 3323 } 3324 3325 static int smu_set_fan_control_mode(void *handle, u32 value) 3326 { 3327 struct smu_context *smu = handle; 3328 int ret = 0; 3329 3330 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3331 return -EOPNOTSUPP; 3332 3333 if (!smu->ppt_funcs->set_fan_control_mode) 3334 return -EOPNOTSUPP; 3335 3336 if (value == U32_MAX) 3337 return -EINVAL; 3338 3339 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3340 if (ret) 3341 goto out; 3342 3343 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3344 smu->user_dpm_profile.fan_mode = value; 3345 3346 /* reset user dpm fan speed */ 3347 if (value != AMD_FAN_CTRL_MANUAL) { 3348 smu->user_dpm_profile.fan_speed_pwm = 0; 3349 smu->user_dpm_profile.fan_speed_rpm = 0; 3350 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3351 } 3352 } 3353 3354 out: 3355 return ret; 3356 } 3357 3358 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3359 { 3360 struct smu_context *smu = handle; 3361 int ret = 0; 3362 3363 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3364 return -EOPNOTSUPP; 3365 3366 if (!smu->ppt_funcs->get_fan_speed_pwm) 3367 return -EOPNOTSUPP; 3368 3369 if (!speed) 3370 return -EINVAL; 3371 3372 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3373 3374 return ret; 3375 } 3376 3377 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3378 { 3379 struct smu_context *smu = handle; 3380 int ret = 0; 3381 3382 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3383 return -EOPNOTSUPP; 3384 3385 if (!smu->ppt_funcs->set_fan_speed_pwm) 3386 return -EOPNOTSUPP; 3387 3388 if (speed == U32_MAX) 3389 return -EINVAL; 3390 3391 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3392 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3393 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3394 smu->user_dpm_profile.fan_speed_pwm = speed; 3395 3396 /* Override custom RPM setting as they cannot co-exist */ 3397 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3398 smu->user_dpm_profile.fan_speed_rpm = 0; 3399 } 3400 3401 return ret; 3402 } 3403 3404 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3405 { 3406 struct smu_context *smu = handle; 3407 int ret = 0; 3408 3409 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3410 return -EOPNOTSUPP; 3411 3412 if (!smu->ppt_funcs->get_fan_speed_rpm) 3413 return -EOPNOTSUPP; 3414 3415 if (!speed) 3416 return -EINVAL; 3417 3418 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3419 3420 return ret; 3421 } 3422 3423 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3424 { 3425 struct smu_context *smu = handle; 3426 3427 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3428 return -EOPNOTSUPP; 3429 3430 return smu_set_min_dcef_deep_sleep(smu, clk); 3431 } 3432 3433 static int smu_get_clock_by_type_with_latency(void *handle, 3434 enum amd_pp_clock_type type, 3435 struct pp_clock_levels_with_latency *clocks) 3436 { 3437 struct smu_context *smu = handle; 3438 enum smu_clk_type clk_type; 3439 int ret = 0; 3440 3441 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3442 return -EOPNOTSUPP; 3443 3444 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3445 switch (type) { 3446 case amd_pp_sys_clock: 3447 clk_type = SMU_GFXCLK; 3448 break; 3449 case amd_pp_mem_clock: 3450 clk_type = SMU_MCLK; 3451 break; 3452 case amd_pp_dcef_clock: 3453 clk_type = SMU_DCEFCLK; 3454 break; 3455 case amd_pp_disp_clock: 3456 clk_type = SMU_DISPCLK; 3457 break; 3458 default: 3459 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3460 return -EINVAL; 3461 } 3462 3463 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3464 } 3465 3466 return ret; 3467 } 3468 3469 static int smu_display_clock_voltage_request(void *handle, 3470 struct pp_display_clock_request *clock_req) 3471 { 3472 struct smu_context *smu = handle; 3473 int ret = 0; 3474 3475 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3476 return -EOPNOTSUPP; 3477 3478 if (smu->ppt_funcs->display_clock_voltage_request) 3479 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3480 3481 return ret; 3482 } 3483 3484 3485 static int smu_display_disable_memory_clock_switch(void *handle, 3486 bool disable_memory_clock_switch) 3487 { 3488 struct smu_context *smu = handle; 3489 int ret = -EINVAL; 3490 3491 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3492 return -EOPNOTSUPP; 3493 3494 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3495 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3496 3497 return ret; 3498 } 3499 3500 static int smu_set_xgmi_pstate(void *handle, 3501 uint32_t pstate) 3502 { 3503 struct smu_context *smu = handle; 3504 int ret = 0; 3505 3506 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3507 return -EOPNOTSUPP; 3508 3509 if (smu->ppt_funcs->set_xgmi_pstate) 3510 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3511 3512 if (ret) 3513 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3514 3515 return ret; 3516 } 3517 3518 static int smu_get_baco_capability(void *handle) 3519 { 3520 struct smu_context *smu = handle; 3521 3522 if (!smu->pm_enabled) 3523 return false; 3524 3525 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3526 return false; 3527 3528 return smu->ppt_funcs->get_bamaco_support(smu); 3529 } 3530 3531 static int smu_baco_set_state(void *handle, int state) 3532 { 3533 struct smu_context *smu = handle; 3534 int ret = 0; 3535 3536 if (!smu->pm_enabled) 3537 return -EOPNOTSUPP; 3538 3539 if (state == 0) { 3540 if (smu->ppt_funcs->baco_exit) 3541 ret = smu->ppt_funcs->baco_exit(smu); 3542 } else if (state == 1) { 3543 if (smu->ppt_funcs->baco_enter) 3544 ret = smu->ppt_funcs->baco_enter(smu); 3545 } else { 3546 return -EINVAL; 3547 } 3548 3549 if (ret) 3550 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3551 (state)?"enter":"exit"); 3552 3553 return ret; 3554 } 3555 3556 bool smu_mode1_reset_is_support(struct smu_context *smu) 3557 { 3558 bool ret = false; 3559 3560 if (!smu->pm_enabled) 3561 return false; 3562 3563 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3564 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3565 3566 return ret; 3567 } 3568 3569 bool smu_link_reset_is_support(struct smu_context *smu) 3570 { 3571 if (!smu->pm_enabled) 3572 return false; 3573 3574 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__LINK_RESET); 3575 } 3576 3577 int smu_mode1_reset(struct smu_context *smu) 3578 { 3579 int ret = 0; 3580 3581 if (!smu->pm_enabled) 3582 return -EOPNOTSUPP; 3583 3584 if (smu->ppt_funcs->mode1_reset) 3585 ret = smu->ppt_funcs->mode1_reset(smu); 3586 3587 return ret; 3588 } 3589 3590 static int smu_mode2_reset(void *handle) 3591 { 3592 struct smu_context *smu = handle; 3593 int ret = 0; 3594 3595 if (!smu->pm_enabled) 3596 return -EOPNOTSUPP; 3597 3598 if (smu->ppt_funcs->mode2_reset) 3599 ret = smu->ppt_funcs->mode2_reset(smu); 3600 3601 if (ret) 3602 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3603 3604 return ret; 3605 } 3606 3607 int smu_link_reset(struct smu_context *smu) 3608 { 3609 int ret = 0; 3610 3611 if (!smu->pm_enabled) 3612 return -EOPNOTSUPP; 3613 3614 if (smu->ppt_funcs->link_reset) 3615 ret = smu->ppt_funcs->link_reset(smu); 3616 3617 return ret; 3618 } 3619 3620 static int smu_enable_gfx_features(void *handle) 3621 { 3622 struct smu_context *smu = handle; 3623 int ret = 0; 3624 3625 if (!smu->pm_enabled) 3626 return -EOPNOTSUPP; 3627 3628 if (smu->ppt_funcs->enable_gfx_features) 3629 ret = smu->ppt_funcs->enable_gfx_features(smu); 3630 3631 if (ret) 3632 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3633 3634 return ret; 3635 } 3636 3637 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3638 struct pp_smu_nv_clock_table *max_clocks) 3639 { 3640 struct smu_context *smu = handle; 3641 int ret = 0; 3642 3643 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3644 return -EOPNOTSUPP; 3645 3646 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3647 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3648 3649 return ret; 3650 } 3651 3652 static int smu_get_uclk_dpm_states(void *handle, 3653 unsigned int *clock_values_in_khz, 3654 unsigned int *num_states) 3655 { 3656 struct smu_context *smu = handle; 3657 int ret = 0; 3658 3659 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3660 return -EOPNOTSUPP; 3661 3662 if (smu->ppt_funcs->get_uclk_dpm_states) 3663 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3664 3665 return ret; 3666 } 3667 3668 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3669 { 3670 struct smu_context *smu = handle; 3671 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3672 3673 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3674 return -EOPNOTSUPP; 3675 3676 if (smu->ppt_funcs->get_current_power_state) 3677 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3678 3679 return pm_state; 3680 } 3681 3682 static int smu_get_dpm_clock_table(void *handle, 3683 struct dpm_clocks *clock_table) 3684 { 3685 struct smu_context *smu = handle; 3686 int ret = 0; 3687 3688 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3689 return -EOPNOTSUPP; 3690 3691 if (smu->ppt_funcs->get_dpm_clock_table) 3692 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3693 3694 return ret; 3695 } 3696 3697 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3698 { 3699 struct smu_context *smu = handle; 3700 struct smu_table_context *smu_table = &smu->smu_table; 3701 struct smu_driver_table *driver_tables = smu_table->driver_tables; 3702 struct smu_driver_table *gpu_metrics_table; 3703 3704 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3705 return -EOPNOTSUPP; 3706 3707 if (!smu->ppt_funcs->get_gpu_metrics) 3708 return -EOPNOTSUPP; 3709 3710 gpu_metrics_table = &driver_tables[SMU_DRIVER_TABLE_GPU_METRICS]; 3711 3712 /* If cached table is valid, return it */ 3713 if (smu_driver_table_is_valid(gpu_metrics_table)) { 3714 *table = gpu_metrics_table->cache.buffer; 3715 return gpu_metrics_table->cache.size; 3716 } 3717 3718 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3719 } 3720 3721 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3722 size_t size) 3723 { 3724 struct smu_context *smu = handle; 3725 3726 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3727 return -EOPNOTSUPP; 3728 3729 if (!smu->ppt_funcs->get_pm_metrics) 3730 return -EOPNOTSUPP; 3731 3732 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3733 } 3734 3735 static int smu_enable_mgpu_fan_boost(void *handle) 3736 { 3737 struct smu_context *smu = handle; 3738 int ret = 0; 3739 3740 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3741 return -EOPNOTSUPP; 3742 3743 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3744 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3745 3746 return ret; 3747 } 3748 3749 static int smu_gfx_state_change_set(void *handle, 3750 uint32_t state) 3751 { 3752 struct smu_context *smu = handle; 3753 int ret = 0; 3754 3755 if (smu->ppt_funcs->gfx_state_change_set) 3756 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3757 3758 return ret; 3759 } 3760 3761 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3762 { 3763 int ret = 0; 3764 3765 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3766 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3767 3768 return ret; 3769 } 3770 3771 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3772 { 3773 int ret = -EOPNOTSUPP; 3774 3775 if (smu->ppt_funcs && 3776 smu->ppt_funcs->get_ecc_info) 3777 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3778 3779 return ret; 3780 3781 } 3782 3783 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3784 { 3785 struct smu_context *smu = handle; 3786 struct smu_table_context *smu_table = &smu->smu_table; 3787 struct smu_table *memory_pool = &smu_table->memory_pool; 3788 3789 if (!addr || !size) 3790 return -EINVAL; 3791 3792 *addr = NULL; 3793 *size = 0; 3794 if (memory_pool->bo) { 3795 *addr = memory_pool->cpu_addr; 3796 *size = memory_pool->size; 3797 } 3798 3799 return 0; 3800 } 3801 3802 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3803 size_t *size) 3804 { 3805 size_t offset = *size; 3806 int level; 3807 3808 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3809 if (level == policy->current_level) 3810 offset += sysfs_emit_at(sysbuf, offset, 3811 "%d : %s*\n", level, 3812 policy->desc->get_desc(policy, level)); 3813 else 3814 offset += sysfs_emit_at(sysbuf, offset, 3815 "%d : %s\n", level, 3816 policy->desc->get_desc(policy, level)); 3817 } 3818 3819 *size = offset; 3820 } 3821 3822 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3823 enum pp_pm_policy p_type, char *sysbuf) 3824 { 3825 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3826 struct smu_dpm_policy_ctxt *policy_ctxt; 3827 struct smu_dpm_policy *dpm_policy; 3828 size_t offset = 0; 3829 3830 policy_ctxt = dpm_ctxt->dpm_policies; 3831 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3832 !policy_ctxt->policy_mask) 3833 return -EOPNOTSUPP; 3834 3835 if (p_type == PP_PM_POLICY_NONE) 3836 return -EINVAL; 3837 3838 dpm_policy = smu_get_pm_policy(smu, p_type); 3839 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3840 return -ENOENT; 3841 3842 if (!sysbuf) 3843 return -EINVAL; 3844 3845 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3846 3847 return offset; 3848 } 3849 3850 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3851 enum pp_pm_policy p_type) 3852 { 3853 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3854 struct smu_dpm_policy_ctxt *policy_ctxt; 3855 int i; 3856 3857 policy_ctxt = dpm_ctxt->dpm_policies; 3858 if (!policy_ctxt) 3859 return NULL; 3860 3861 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3862 if (policy_ctxt->policies[i].policy_type == p_type) 3863 return &policy_ctxt->policies[i]; 3864 } 3865 3866 return NULL; 3867 } 3868 3869 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3870 int level) 3871 { 3872 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3873 struct smu_dpm_policy *dpm_policy = NULL; 3874 struct smu_dpm_policy_ctxt *policy_ctxt; 3875 int ret = -EOPNOTSUPP; 3876 3877 policy_ctxt = dpm_ctxt->dpm_policies; 3878 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3879 !policy_ctxt->policy_mask) 3880 return ret; 3881 3882 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3883 return -EINVAL; 3884 3885 dpm_policy = smu_get_pm_policy(smu, p_type); 3886 3887 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3888 return ret; 3889 3890 if (dpm_policy->current_level == level) 3891 return 0; 3892 3893 ret = dpm_policy->set_policy(smu, level); 3894 3895 if (!ret) 3896 dpm_policy->current_level = level; 3897 3898 return ret; 3899 } 3900 3901 static ssize_t smu_sys_get_temp_metrics(void *handle, enum smu_temp_metric_type type, void *table) 3902 { 3903 struct smu_context *smu = handle; 3904 struct smu_table_context *smu_table = &smu->smu_table; 3905 struct smu_driver_table *driver_tables = smu_table->driver_tables; 3906 enum smu_driver_table_id table_id; 3907 struct smu_driver_table *temp_table; 3908 3909 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3910 return -EOPNOTSUPP; 3911 3912 if (!smu->smu_temp.temp_funcs || !smu->smu_temp.temp_funcs->get_temp_metrics) 3913 return -EOPNOTSUPP; 3914 3915 table_id = smu_metrics_get_temp_table_id(type); 3916 3917 if (table_id == SMU_DRIVER_TABLE_COUNT) 3918 return -EINVAL; 3919 3920 temp_table = &driver_tables[table_id]; 3921 3922 /* If the request is to get size alone, return the cached table size */ 3923 if (!table && temp_table->cache.size) 3924 return temp_table->cache.size; 3925 3926 if (smu_driver_table_is_valid(temp_table)) { 3927 memcpy(table, temp_table->cache.buffer, temp_table->cache.size); 3928 return temp_table->cache.size; 3929 } 3930 3931 return smu->smu_temp.temp_funcs->get_temp_metrics(smu, type, table); 3932 } 3933 3934 static bool smu_temp_metrics_is_supported(void *handle, enum smu_temp_metric_type type) 3935 { 3936 struct smu_context *smu = handle; 3937 bool ret = false; 3938 3939 if (!smu->pm_enabled) 3940 return false; 3941 3942 if (smu->smu_temp.temp_funcs && smu->smu_temp.temp_funcs->temp_metrics_is_supported) 3943 ret = smu->smu_temp.temp_funcs->temp_metrics_is_supported(smu, type); 3944 3945 return ret; 3946 } 3947 3948 static ssize_t smu_sys_get_xcp_metrics(void *handle, int xcp_id, void *table) 3949 { 3950 struct smu_context *smu = handle; 3951 3952 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3953 return -EOPNOTSUPP; 3954 3955 if (!smu->adev->xcp_mgr || !smu->ppt_funcs->get_xcp_metrics) 3956 return -EOPNOTSUPP; 3957 3958 return smu->ppt_funcs->get_xcp_metrics(smu, xcp_id, table); 3959 } 3960 3961 static const struct amd_pm_funcs swsmu_pm_funcs = { 3962 /* export for sysfs */ 3963 .set_fan_control_mode = smu_set_fan_control_mode, 3964 .get_fan_control_mode = smu_get_fan_control_mode, 3965 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3966 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3967 .force_clock_level = smu_force_ppclk_levels, 3968 .emit_clock_levels = smu_emit_ppclk_levels, 3969 .force_performance_level = smu_force_performance_level, 3970 .read_sensor = smu_read_sensor, 3971 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3972 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3973 .get_performance_level = smu_get_performance_level, 3974 .get_current_power_state = smu_get_current_power_state, 3975 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3976 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3977 .get_pp_num_states = smu_get_power_num_states, 3978 .get_pp_table = smu_sys_get_pp_table, 3979 .set_pp_table = smu_sys_set_pp_table, 3980 .switch_power_profile = smu_switch_power_profile, 3981 .pause_power_profile = smu_pause_power_profile, 3982 /* export to amdgpu */ 3983 .dispatch_tasks = smu_handle_dpm_task, 3984 .load_firmware = smu_load_microcode, 3985 .set_powergating_by_smu = smu_dpm_set_power_gate, 3986 .set_power_limit = smu_set_power_limit, 3987 .get_power_limit = smu_get_power_limit, 3988 .get_power_profile_mode = smu_get_power_profile_mode, 3989 .set_power_profile_mode = smu_set_power_profile_mode, 3990 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3991 .set_mp1_state = smu_set_mp1_state, 3992 .gfx_state_change_set = smu_gfx_state_change_set, 3993 /* export to DC */ 3994 .get_sclk = smu_get_sclk, 3995 .get_mclk = smu_get_mclk, 3996 .display_configuration_change = smu_display_configuration_change, 3997 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3998 .display_clock_voltage_request = smu_display_clock_voltage_request, 3999 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 4000 .set_active_display_count = smu_set_display_count, 4001 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 4002 .get_asic_baco_capability = smu_get_baco_capability, 4003 .set_asic_baco_state = smu_baco_set_state, 4004 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 4005 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 4006 .asic_reset_mode_2 = smu_mode2_reset, 4007 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 4008 .set_df_cstate = smu_set_df_cstate, 4009 .set_xgmi_pstate = smu_set_xgmi_pstate, 4010 .get_gpu_metrics = smu_sys_get_gpu_metrics, 4011 .get_pm_metrics = smu_sys_get_pm_metrics, 4012 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 4013 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 4014 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 4015 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 4016 .get_dpm_clock_table = smu_get_dpm_clock_table, 4017 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 4018 .get_xcp_metrics = smu_sys_get_xcp_metrics, 4019 .get_temp_metrics = smu_sys_get_temp_metrics, 4020 .temp_metrics_is_supported = smu_temp_metrics_is_supported, 4021 }; 4022 4023 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 4024 uint64_t event_arg) 4025 { 4026 int ret = -EINVAL; 4027 4028 if (smu->ppt_funcs->wait_for_event) 4029 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 4030 4031 return ret; 4032 } 4033 4034 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 4035 { 4036 4037 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 4038 return -EOPNOTSUPP; 4039 4040 /* Confirm the buffer allocated is of correct size */ 4041 if (size != smu->stb_context.stb_buf_size) 4042 return -EINVAL; 4043 4044 /* 4045 * No need to lock smu mutex as we access STB directly through MMIO 4046 * and not going through SMU messaging route (for now at least). 4047 * For registers access rely on implementation internal locking. 4048 */ 4049 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 4050 } 4051 4052 #if defined(CONFIG_DEBUG_FS) 4053 4054 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 4055 { 4056 struct amdgpu_device *adev = filp->f_inode->i_private; 4057 struct smu_context *smu = adev->powerplay.pp_handle; 4058 unsigned char *buf; 4059 int r; 4060 4061 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 4062 if (!buf) 4063 return -ENOMEM; 4064 4065 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 4066 if (r) 4067 goto out; 4068 4069 filp->private_data = buf; 4070 4071 return 0; 4072 4073 out: 4074 kvfree(buf); 4075 return r; 4076 } 4077 4078 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 4079 loff_t *pos) 4080 { 4081 struct amdgpu_device *adev = filp->f_inode->i_private; 4082 struct smu_context *smu = adev->powerplay.pp_handle; 4083 4084 4085 if (!filp->private_data) 4086 return -EINVAL; 4087 4088 return simple_read_from_buffer(buf, 4089 size, 4090 pos, filp->private_data, 4091 smu->stb_context.stb_buf_size); 4092 } 4093 4094 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 4095 { 4096 kvfree(filp->private_data); 4097 filp->private_data = NULL; 4098 4099 return 0; 4100 } 4101 4102 /* 4103 * We have to define not only read method but also 4104 * open and release because .read takes up to PAGE_SIZE 4105 * data each time so and so is invoked multiple times. 4106 * We allocate the STB buffer in .open and release it 4107 * in .release 4108 */ 4109 static const struct file_operations smu_stb_debugfs_fops = { 4110 .owner = THIS_MODULE, 4111 .open = smu_stb_debugfs_open, 4112 .read = smu_stb_debugfs_read, 4113 .release = smu_stb_debugfs_release, 4114 .llseek = default_llseek, 4115 }; 4116 4117 #endif 4118 4119 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 4120 { 4121 #if defined(CONFIG_DEBUG_FS) 4122 4123 struct smu_context *smu = adev->powerplay.pp_handle; 4124 4125 if (!smu || (!smu->stb_context.stb_buf_size)) 4126 return; 4127 4128 debugfs_create_file_size("amdgpu_smu_stb_dump", 4129 S_IRUSR, 4130 adev_to_drm(adev)->primary->debugfs_root, 4131 adev, 4132 &smu_stb_debugfs_fops, 4133 smu->stb_context.stb_buf_size); 4134 #endif 4135 } 4136 4137 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 4138 { 4139 int ret = 0; 4140 4141 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 4142 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 4143 4144 return ret; 4145 } 4146 4147 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 4148 { 4149 int ret = 0; 4150 4151 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 4152 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 4153 4154 return ret; 4155 } 4156 4157 int smu_send_rma_reason(struct smu_context *smu) 4158 { 4159 int ret = 0; 4160 4161 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 4162 ret = smu->ppt_funcs->send_rma_reason(smu); 4163 4164 return ret; 4165 } 4166 4167 /** 4168 * smu_reset_sdma_is_supported - Check if SDMA reset is supported by SMU 4169 * @smu: smu_context pointer 4170 * 4171 * This function checks if the SMU supports resetting the SDMA engine. 4172 * It returns true if supported, false otherwise. 4173 */ 4174 bool smu_reset_sdma_is_supported(struct smu_context *smu) 4175 { 4176 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__SDMA_RESET); 4177 } 4178 4179 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask) 4180 { 4181 int ret = 0; 4182 4183 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma) 4184 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask); 4185 4186 return ret; 4187 } 4188 4189 bool smu_reset_vcn_is_supported(struct smu_context *smu) 4190 { 4191 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__VCN_RESET); 4192 } 4193 4194 int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask) 4195 { 4196 if (smu->ppt_funcs && smu->ppt_funcs->dpm_reset_vcn) 4197 smu->ppt_funcs->dpm_reset_vcn(smu, inst_mask); 4198 4199 return 0; 4200 } 4201