1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 76 static int smu_sys_get_pp_feature_mask(void *handle, 77 char *buf) 78 { 79 struct smu_context *smu = handle; 80 81 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 82 return -EOPNOTSUPP; 83 84 return smu_get_pp_feature_mask(smu, buf); 85 } 86 87 static int smu_sys_set_pp_feature_mask(void *handle, 88 uint64_t new_mask) 89 { 90 struct smu_context *smu = handle; 91 92 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 93 return -EOPNOTSUPP; 94 95 return smu_set_pp_feature_mask(smu, new_mask); 96 } 97 98 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 99 { 100 if (!smu->ppt_funcs->set_gfx_off_residency) 101 return -EINVAL; 102 103 return smu_set_gfx_off_residency(smu, value); 104 } 105 106 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 107 { 108 if (!smu->ppt_funcs->get_gfx_off_residency) 109 return -EINVAL; 110 111 return smu_get_gfx_off_residency(smu, value); 112 } 113 114 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 115 { 116 if (!smu->ppt_funcs->get_gfx_off_entrycount) 117 return -EINVAL; 118 119 return smu_get_gfx_off_entrycount(smu, value); 120 } 121 122 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 123 { 124 if (!smu->ppt_funcs->get_gfx_off_status) 125 return -EINVAL; 126 127 *value = smu_get_gfx_off_status(smu); 128 129 return 0; 130 } 131 132 int smu_set_soft_freq_range(struct smu_context *smu, 133 enum smu_clk_type clk_type, 134 uint32_t min, 135 uint32_t max) 136 { 137 int ret = 0; 138 139 if (smu->ppt_funcs->set_soft_freq_limited_range) 140 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 141 clk_type, 142 min, 143 max); 144 145 return ret; 146 } 147 148 int smu_get_dpm_freq_range(struct smu_context *smu, 149 enum smu_clk_type clk_type, 150 uint32_t *min, 151 uint32_t *max) 152 { 153 int ret = -ENOTSUPP; 154 155 if (!min && !max) 156 return -EINVAL; 157 158 if (smu->ppt_funcs->get_dpm_ultimate_freq) 159 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 160 clk_type, 161 min, 162 max); 163 164 return ret; 165 } 166 167 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 168 { 169 int ret = 0; 170 struct amdgpu_device *adev = smu->adev; 171 172 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 173 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 174 if (ret) 175 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 176 } 177 return ret; 178 } 179 180 static u32 smu_get_mclk(void *handle, bool low) 181 { 182 struct smu_context *smu = handle; 183 uint32_t clk_freq; 184 int ret = 0; 185 186 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 187 low ? &clk_freq : NULL, 188 !low ? &clk_freq : NULL); 189 if (ret) 190 return 0; 191 return clk_freq * 100; 192 } 193 194 static u32 smu_get_sclk(void *handle, bool low) 195 { 196 struct smu_context *smu = handle; 197 uint32_t clk_freq; 198 int ret = 0; 199 200 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 201 low ? &clk_freq : NULL, 202 !low ? &clk_freq : NULL); 203 if (ret) 204 return 0; 205 return clk_freq * 100; 206 } 207 208 static int smu_set_gfx_imu_enable(struct smu_context *smu) 209 { 210 struct amdgpu_device *adev = smu->adev; 211 212 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 213 return 0; 214 215 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 216 return 0; 217 218 return smu_set_gfx_power_up_by_imu(smu); 219 } 220 221 static bool is_vcn_enabled(struct amdgpu_device *adev) 222 { 223 int i; 224 225 for (i = 0; i < adev->num_ip_blocks; i++) { 226 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 227 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 228 !adev->ip_blocks[i].status.valid) 229 return false; 230 } 231 232 return true; 233 } 234 235 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 236 bool enable) 237 { 238 struct smu_power_context *smu_power = &smu->smu_power; 239 struct smu_power_gate *power_gate = &smu_power->power_gate; 240 int ret = 0; 241 242 /* 243 * don't poweron vcn/jpeg when they are skipped. 244 */ 245 if (!is_vcn_enabled(smu->adev)) 246 return 0; 247 248 if (!smu->ppt_funcs->dpm_set_vcn_enable) 249 return 0; 250 251 if (atomic_read(&power_gate->vcn_gated) ^ enable) 252 return 0; 253 254 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 255 if (!ret) 256 atomic_set(&power_gate->vcn_gated, !enable); 257 258 return ret; 259 } 260 261 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 262 bool enable) 263 { 264 struct smu_power_context *smu_power = &smu->smu_power; 265 struct smu_power_gate *power_gate = &smu_power->power_gate; 266 int ret = 0; 267 268 if (!is_vcn_enabled(smu->adev)) 269 return 0; 270 271 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 272 return 0; 273 274 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 275 return 0; 276 277 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 278 if (!ret) 279 atomic_set(&power_gate->jpeg_gated, !enable); 280 281 return ret; 282 } 283 284 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 285 bool enable) 286 { 287 struct smu_power_context *smu_power = &smu->smu_power; 288 struct smu_power_gate *power_gate = &smu_power->power_gate; 289 int ret = 0; 290 291 if (!smu->ppt_funcs->dpm_set_vpe_enable) 292 return 0; 293 294 if (atomic_read(&power_gate->vpe_gated) ^ enable) 295 return 0; 296 297 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 298 if (!ret) 299 atomic_set(&power_gate->vpe_gated, !enable); 300 301 return ret; 302 } 303 304 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 305 bool enable) 306 { 307 struct smu_power_context *smu_power = &smu->smu_power; 308 struct smu_power_gate *power_gate = &smu_power->power_gate; 309 int ret = 0; 310 311 if (!smu->adev->enable_umsch_mm) 312 return 0; 313 314 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 315 return 0; 316 317 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 318 return 0; 319 320 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 321 if (!ret) 322 atomic_set(&power_gate->umsch_mm_gated, !enable); 323 324 return ret; 325 } 326 327 static int smu_set_mall_enable(struct smu_context *smu) 328 { 329 int ret = 0; 330 331 if (!smu->ppt_funcs->set_mall_enable) 332 return 0; 333 334 ret = smu->ppt_funcs->set_mall_enable(smu); 335 336 return ret; 337 } 338 339 /** 340 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 341 * 342 * @handle: smu_context pointer 343 * @block_type: the IP block to power gate/ungate 344 * @gate: to power gate if true, ungate otherwise 345 * 346 * This API uses no smu->mutex lock protection due to: 347 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 348 * This is guarded to be race condition free by the caller. 349 * 2. Or get called on user setting request of power_dpm_force_performance_level. 350 * Under this case, the smu->mutex lock protection is already enforced on 351 * the parent API smu_force_performance_level of the call path. 352 */ 353 static int smu_dpm_set_power_gate(void *handle, 354 uint32_t block_type, 355 bool gate) 356 { 357 struct smu_context *smu = handle; 358 int ret = 0; 359 360 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 361 dev_WARN(smu->adev->dev, 362 "SMU uninitialized but power %s requested for %u!\n", 363 gate ? "gate" : "ungate", block_type); 364 return -EOPNOTSUPP; 365 } 366 367 switch (block_type) { 368 /* 369 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 370 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 371 */ 372 case AMD_IP_BLOCK_TYPE_UVD: 373 case AMD_IP_BLOCK_TYPE_VCN: 374 ret = smu_dpm_set_vcn_enable(smu, !gate); 375 if (ret) 376 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 377 gate ? "gate" : "ungate"); 378 break; 379 case AMD_IP_BLOCK_TYPE_GFX: 380 ret = smu_gfx_off_control(smu, gate); 381 if (ret) 382 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 383 gate ? "enable" : "disable"); 384 break; 385 case AMD_IP_BLOCK_TYPE_SDMA: 386 ret = smu_powergate_sdma(smu, gate); 387 if (ret) 388 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 389 gate ? "gate" : "ungate"); 390 break; 391 case AMD_IP_BLOCK_TYPE_JPEG: 392 ret = smu_dpm_set_jpeg_enable(smu, !gate); 393 if (ret) 394 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 395 gate ? "gate" : "ungate"); 396 break; 397 case AMD_IP_BLOCK_TYPE_VPE: 398 ret = smu_dpm_set_vpe_enable(smu, !gate); 399 if (ret) 400 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 401 gate ? "gate" : "ungate"); 402 break; 403 default: 404 dev_err(smu->adev->dev, "Unsupported block type!\n"); 405 return -EINVAL; 406 } 407 408 return ret; 409 } 410 411 /** 412 * smu_set_user_clk_dependencies - set user profile clock dependencies 413 * 414 * @smu: smu_context pointer 415 * @clk: enum smu_clk_type type 416 * 417 * Enable/Disable the clock dependency for the @clk type. 418 */ 419 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 420 { 421 if (smu->adev->in_suspend) 422 return; 423 424 if (clk == SMU_MCLK) { 425 smu->user_dpm_profile.clk_dependency = 0; 426 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 427 } else if (clk == SMU_FCLK) { 428 /* MCLK takes precedence over FCLK */ 429 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 430 return; 431 432 smu->user_dpm_profile.clk_dependency = 0; 433 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 434 } else if (clk == SMU_SOCCLK) { 435 /* MCLK takes precedence over SOCCLK */ 436 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 437 return; 438 439 smu->user_dpm_profile.clk_dependency = 0; 440 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 441 } else 442 /* Add clk dependencies here, if any */ 443 return; 444 } 445 446 /** 447 * smu_restore_dpm_user_profile - reinstate user dpm profile 448 * 449 * @smu: smu_context pointer 450 * 451 * Restore the saved user power configurations include power limit, 452 * clock frequencies, fan control mode and fan speed. 453 */ 454 static void smu_restore_dpm_user_profile(struct smu_context *smu) 455 { 456 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 457 int ret = 0; 458 459 if (!smu->adev->in_suspend) 460 return; 461 462 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 463 return; 464 465 /* Enable restore flag */ 466 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 467 468 /* set the user dpm power limit */ 469 if (smu->user_dpm_profile.power_limit) { 470 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 471 if (ret) 472 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 473 } 474 475 /* set the user dpm clock configurations */ 476 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 477 enum smu_clk_type clk_type; 478 479 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 480 /* 481 * Iterate over smu clk type and force the saved user clk 482 * configs, skip if clock dependency is enabled 483 */ 484 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 485 smu->user_dpm_profile.clk_mask[clk_type]) { 486 ret = smu_force_smuclk_levels(smu, clk_type, 487 smu->user_dpm_profile.clk_mask[clk_type]); 488 if (ret) 489 dev_err(smu->adev->dev, 490 "Failed to set clock type = %d\n", clk_type); 491 } 492 } 493 } 494 495 /* set the user dpm fan configurations */ 496 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 497 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 498 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 499 if (ret != -EOPNOTSUPP) { 500 smu->user_dpm_profile.fan_speed_pwm = 0; 501 smu->user_dpm_profile.fan_speed_rpm = 0; 502 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 503 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 504 } 505 506 if (smu->user_dpm_profile.fan_speed_pwm) { 507 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 508 if (ret != -EOPNOTSUPP) 509 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 510 } 511 512 if (smu->user_dpm_profile.fan_speed_rpm) { 513 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 514 if (ret != -EOPNOTSUPP) 515 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 516 } 517 } 518 519 /* Restore user customized OD settings */ 520 if (smu->user_dpm_profile.user_od) { 521 if (smu->ppt_funcs->restore_user_od_settings) { 522 ret = smu->ppt_funcs->restore_user_od_settings(smu); 523 if (ret) 524 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 525 } 526 } 527 528 /* Disable restore flag */ 529 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 530 } 531 532 static int smu_get_power_num_states(void *handle, 533 struct pp_states_info *state_info) 534 { 535 if (!state_info) 536 return -EINVAL; 537 538 /* not support power state */ 539 memset(state_info, 0, sizeof(struct pp_states_info)); 540 state_info->nums = 1; 541 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 542 543 return 0; 544 } 545 546 bool is_support_sw_smu(struct amdgpu_device *adev) 547 { 548 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 549 if (adev->asic_type == CHIP_VEGA20) 550 return false; 551 552 if (amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) 553 return true; 554 555 return false; 556 } 557 558 bool is_support_cclk_dpm(struct amdgpu_device *adev) 559 { 560 struct smu_context *smu = adev->powerplay.pp_handle; 561 562 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 563 return false; 564 565 return true; 566 } 567 568 569 static int smu_sys_get_pp_table(void *handle, 570 char **table) 571 { 572 struct smu_context *smu = handle; 573 struct smu_table_context *smu_table = &smu->smu_table; 574 575 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 576 return -EOPNOTSUPP; 577 578 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 579 return -EINVAL; 580 581 if (smu_table->hardcode_pptable) 582 *table = smu_table->hardcode_pptable; 583 else 584 *table = smu_table->power_play_table; 585 586 return smu_table->power_play_table_size; 587 } 588 589 static int smu_sys_set_pp_table(void *handle, 590 const char *buf, 591 size_t size) 592 { 593 struct smu_context *smu = handle; 594 struct smu_table_context *smu_table = &smu->smu_table; 595 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 596 int ret = 0; 597 598 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 599 return -EOPNOTSUPP; 600 601 if (header->usStructureSize != size) { 602 dev_err(smu->adev->dev, "pp table size not matched !\n"); 603 return -EIO; 604 } 605 606 if (!smu_table->hardcode_pptable) { 607 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 608 if (!smu_table->hardcode_pptable) 609 return -ENOMEM; 610 } 611 612 memcpy(smu_table->hardcode_pptable, buf, size); 613 smu_table->power_play_table = smu_table->hardcode_pptable; 614 smu_table->power_play_table_size = size; 615 616 /* 617 * Special hw_fini action(for Navi1x, the DPMs disablement will be 618 * skipped) may be needed for custom pptable uploading. 619 */ 620 smu->uploading_custom_pp_table = true; 621 622 ret = smu_reset(smu); 623 if (ret) 624 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 625 626 smu->uploading_custom_pp_table = false; 627 628 return ret; 629 } 630 631 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 632 { 633 struct smu_feature *feature = &smu->smu_feature; 634 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 635 int ret = 0; 636 637 /* 638 * With SCPM enabled, the allowed featuremasks setting(via 639 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 640 * That means there is no way to let PMFW knows the settings below. 641 * Thus, we just assume all the features are allowed under 642 * such scenario. 643 */ 644 if (smu->adev->scpm_enabled) { 645 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 646 return 0; 647 } 648 649 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 650 651 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 652 SMU_FEATURE_MAX/32); 653 if (ret) 654 return ret; 655 656 bitmap_or(feature->allowed, feature->allowed, 657 (unsigned long *)allowed_feature_mask, 658 feature->feature_num); 659 660 return ret; 661 } 662 663 static int smu_set_funcs(struct amdgpu_device *adev) 664 { 665 struct smu_context *smu = adev->powerplay.pp_handle; 666 667 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 668 smu->od_enabled = true; 669 670 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 671 case IP_VERSION(11, 0, 0): 672 case IP_VERSION(11, 0, 5): 673 case IP_VERSION(11, 0, 9): 674 navi10_set_ppt_funcs(smu); 675 break; 676 case IP_VERSION(11, 0, 7): 677 case IP_VERSION(11, 0, 11): 678 case IP_VERSION(11, 0, 12): 679 case IP_VERSION(11, 0, 13): 680 sienna_cichlid_set_ppt_funcs(smu); 681 break; 682 case IP_VERSION(12, 0, 0): 683 case IP_VERSION(12, 0, 1): 684 renoir_set_ppt_funcs(smu); 685 break; 686 case IP_VERSION(11, 5, 0): 687 vangogh_set_ppt_funcs(smu); 688 break; 689 case IP_VERSION(13, 0, 1): 690 case IP_VERSION(13, 0, 3): 691 case IP_VERSION(13, 0, 8): 692 yellow_carp_set_ppt_funcs(smu); 693 break; 694 case IP_VERSION(13, 0, 4): 695 case IP_VERSION(13, 0, 11): 696 smu_v13_0_4_set_ppt_funcs(smu); 697 break; 698 case IP_VERSION(13, 0, 5): 699 smu_v13_0_5_set_ppt_funcs(smu); 700 break; 701 case IP_VERSION(11, 0, 8): 702 cyan_skillfish_set_ppt_funcs(smu); 703 break; 704 case IP_VERSION(11, 0, 2): 705 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 706 arcturus_set_ppt_funcs(smu); 707 /* OD is not supported on Arcturus */ 708 smu->od_enabled = false; 709 break; 710 case IP_VERSION(13, 0, 2): 711 aldebaran_set_ppt_funcs(smu); 712 /* Enable pp_od_clk_voltage node */ 713 smu->od_enabled = true; 714 break; 715 case IP_VERSION(13, 0, 0): 716 case IP_VERSION(13, 0, 10): 717 smu_v13_0_0_set_ppt_funcs(smu); 718 break; 719 case IP_VERSION(13, 0, 6): 720 case IP_VERSION(13, 0, 14): 721 smu_v13_0_6_set_ppt_funcs(smu); 722 /* Enable pp_od_clk_voltage node */ 723 smu->od_enabled = true; 724 break; 725 case IP_VERSION(13, 0, 7): 726 smu_v13_0_7_set_ppt_funcs(smu); 727 break; 728 case IP_VERSION(14, 0, 0): 729 case IP_VERSION(14, 0, 1): 730 case IP_VERSION(14, 0, 4): 731 smu_v14_0_0_set_ppt_funcs(smu); 732 break; 733 case IP_VERSION(14, 0, 2): 734 case IP_VERSION(14, 0, 3): 735 smu_v14_0_2_set_ppt_funcs(smu); 736 break; 737 default: 738 return -EINVAL; 739 } 740 741 return 0; 742 } 743 744 static int smu_early_init(void *handle) 745 { 746 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 747 struct smu_context *smu; 748 int r; 749 750 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 751 if (!smu) 752 return -ENOMEM; 753 754 smu->adev = adev; 755 smu->pm_enabled = !!amdgpu_dpm; 756 smu->is_apu = false; 757 smu->smu_baco.state = SMU_BACO_STATE_NONE; 758 smu->smu_baco.platform_support = false; 759 smu->smu_baco.maco_support = false; 760 smu->user_dpm_profile.fan_mode = -1; 761 762 mutex_init(&smu->message_lock); 763 764 adev->powerplay.pp_handle = smu; 765 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 766 767 r = smu_set_funcs(adev); 768 if (r) 769 return r; 770 return smu_init_microcode(smu); 771 } 772 773 static int smu_set_default_dpm_table(struct smu_context *smu) 774 { 775 struct amdgpu_device *adev = smu->adev; 776 struct smu_power_context *smu_power = &smu->smu_power; 777 struct smu_power_gate *power_gate = &smu_power->power_gate; 778 int vcn_gate, jpeg_gate; 779 int ret = 0; 780 781 if (!smu->ppt_funcs->set_default_dpm_table) 782 return 0; 783 784 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 785 vcn_gate = atomic_read(&power_gate->vcn_gated); 786 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 787 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 788 789 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 790 ret = smu_dpm_set_vcn_enable(smu, true); 791 if (ret) 792 return ret; 793 } 794 795 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 796 ret = smu_dpm_set_jpeg_enable(smu, true); 797 if (ret) 798 goto err_out; 799 } 800 801 ret = smu->ppt_funcs->set_default_dpm_table(smu); 802 if (ret) 803 dev_err(smu->adev->dev, 804 "Failed to setup default dpm clock tables!\n"); 805 806 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 807 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 808 err_out: 809 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 810 smu_dpm_set_vcn_enable(smu, !vcn_gate); 811 812 return ret; 813 } 814 815 static int smu_apply_default_config_table_settings(struct smu_context *smu) 816 { 817 struct amdgpu_device *adev = smu->adev; 818 int ret = 0; 819 820 ret = smu_get_default_config_table_settings(smu, 821 &adev->pm.config_table); 822 if (ret) 823 return ret; 824 825 return smu_set_config_table(smu, &adev->pm.config_table); 826 } 827 828 static int smu_late_init(void *handle) 829 { 830 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 831 struct smu_context *smu = adev->powerplay.pp_handle; 832 int ret = 0; 833 834 smu_set_fine_grain_gfx_freq_parameters(smu); 835 836 if (!smu->pm_enabled) 837 return 0; 838 839 ret = smu_post_init(smu); 840 if (ret) { 841 dev_err(adev->dev, "Failed to post smu init!\n"); 842 return ret; 843 } 844 845 /* 846 * Explicitly notify PMFW the power mode the system in. Since 847 * the PMFW may boot the ASIC with a different mode. 848 * For those supporting ACDC switch via gpio, PMFW will 849 * handle the switch automatically. Driver involvement 850 * is unnecessary. 851 */ 852 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 853 smu_set_ac_dc(smu); 854 855 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 856 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 857 return 0; 858 859 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 860 ret = smu_set_default_od_settings(smu); 861 if (ret) { 862 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 863 return ret; 864 } 865 } 866 867 ret = smu_populate_umd_state_clk(smu); 868 if (ret) { 869 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 870 return ret; 871 } 872 873 ret = smu_get_asic_power_limits(smu, 874 &smu->current_power_limit, 875 &smu->default_power_limit, 876 &smu->max_power_limit, 877 &smu->min_power_limit); 878 if (ret) { 879 dev_err(adev->dev, "Failed to get asic power limits!\n"); 880 return ret; 881 } 882 883 if (!amdgpu_sriov_vf(adev)) 884 smu_get_unique_id(smu); 885 886 smu_get_fan_parameters(smu); 887 888 smu_handle_task(smu, 889 smu->smu_dpm.dpm_level, 890 AMD_PP_TASK_COMPLETE_INIT); 891 892 ret = smu_apply_default_config_table_settings(smu); 893 if (ret && (ret != -EOPNOTSUPP)) { 894 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 895 return ret; 896 } 897 898 smu_restore_dpm_user_profile(smu); 899 900 return 0; 901 } 902 903 static int smu_init_fb_allocations(struct smu_context *smu) 904 { 905 struct amdgpu_device *adev = smu->adev; 906 struct smu_table_context *smu_table = &smu->smu_table; 907 struct smu_table *tables = smu_table->tables; 908 struct smu_table *driver_table = &(smu_table->driver_table); 909 uint32_t max_table_size = 0; 910 int ret, i; 911 912 /* VRAM allocation for tool table */ 913 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 914 ret = amdgpu_bo_create_kernel(adev, 915 tables[SMU_TABLE_PMSTATUSLOG].size, 916 tables[SMU_TABLE_PMSTATUSLOG].align, 917 tables[SMU_TABLE_PMSTATUSLOG].domain, 918 &tables[SMU_TABLE_PMSTATUSLOG].bo, 919 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 920 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 921 if (ret) { 922 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 923 return ret; 924 } 925 } 926 927 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 928 /* VRAM allocation for driver table */ 929 for (i = 0; i < SMU_TABLE_COUNT; i++) { 930 if (tables[i].size == 0) 931 continue; 932 933 /* If one of the tables has VRAM domain restriction, keep it in 934 * VRAM 935 */ 936 if ((tables[i].domain & 937 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 938 AMDGPU_GEM_DOMAIN_VRAM) 939 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 940 941 if (i == SMU_TABLE_PMSTATUSLOG) 942 continue; 943 944 if (max_table_size < tables[i].size) 945 max_table_size = tables[i].size; 946 } 947 948 driver_table->size = max_table_size; 949 driver_table->align = PAGE_SIZE; 950 951 ret = amdgpu_bo_create_kernel(adev, 952 driver_table->size, 953 driver_table->align, 954 driver_table->domain, 955 &driver_table->bo, 956 &driver_table->mc_address, 957 &driver_table->cpu_addr); 958 if (ret) { 959 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 960 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 961 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 962 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 963 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 964 } 965 966 return ret; 967 } 968 969 static int smu_fini_fb_allocations(struct smu_context *smu) 970 { 971 struct smu_table_context *smu_table = &smu->smu_table; 972 struct smu_table *tables = smu_table->tables; 973 struct smu_table *driver_table = &(smu_table->driver_table); 974 975 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 976 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 977 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 978 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 979 980 amdgpu_bo_free_kernel(&driver_table->bo, 981 &driver_table->mc_address, 982 &driver_table->cpu_addr); 983 984 return 0; 985 } 986 987 /** 988 * smu_alloc_memory_pool - allocate memory pool in the system memory 989 * 990 * @smu: amdgpu_device pointer 991 * 992 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 993 * and DramLogSetDramAddr can notify it changed. 994 * 995 * Returns 0 on success, error on failure. 996 */ 997 static int smu_alloc_memory_pool(struct smu_context *smu) 998 { 999 struct amdgpu_device *adev = smu->adev; 1000 struct smu_table_context *smu_table = &smu->smu_table; 1001 struct smu_table *memory_pool = &smu_table->memory_pool; 1002 uint64_t pool_size = smu->pool_size; 1003 int ret = 0; 1004 1005 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1006 return ret; 1007 1008 memory_pool->size = pool_size; 1009 memory_pool->align = PAGE_SIZE; 1010 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 1011 1012 switch (pool_size) { 1013 case SMU_MEMORY_POOL_SIZE_256_MB: 1014 case SMU_MEMORY_POOL_SIZE_512_MB: 1015 case SMU_MEMORY_POOL_SIZE_1_GB: 1016 case SMU_MEMORY_POOL_SIZE_2_GB: 1017 ret = amdgpu_bo_create_kernel(adev, 1018 memory_pool->size, 1019 memory_pool->align, 1020 memory_pool->domain, 1021 &memory_pool->bo, 1022 &memory_pool->mc_address, 1023 &memory_pool->cpu_addr); 1024 if (ret) 1025 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1026 break; 1027 default: 1028 break; 1029 } 1030 1031 return ret; 1032 } 1033 1034 static int smu_free_memory_pool(struct smu_context *smu) 1035 { 1036 struct smu_table_context *smu_table = &smu->smu_table; 1037 struct smu_table *memory_pool = &smu_table->memory_pool; 1038 1039 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1040 return 0; 1041 1042 amdgpu_bo_free_kernel(&memory_pool->bo, 1043 &memory_pool->mc_address, 1044 &memory_pool->cpu_addr); 1045 1046 memset(memory_pool, 0, sizeof(struct smu_table)); 1047 1048 return 0; 1049 } 1050 1051 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1052 { 1053 struct smu_table_context *smu_table = &smu->smu_table; 1054 struct smu_table *dummy_read_1_table = 1055 &smu_table->dummy_read_1_table; 1056 struct amdgpu_device *adev = smu->adev; 1057 int ret = 0; 1058 1059 if (!dummy_read_1_table->size) 1060 return 0; 1061 1062 ret = amdgpu_bo_create_kernel(adev, 1063 dummy_read_1_table->size, 1064 dummy_read_1_table->align, 1065 dummy_read_1_table->domain, 1066 &dummy_read_1_table->bo, 1067 &dummy_read_1_table->mc_address, 1068 &dummy_read_1_table->cpu_addr); 1069 if (ret) 1070 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1071 1072 return ret; 1073 } 1074 1075 static void smu_free_dummy_read_table(struct smu_context *smu) 1076 { 1077 struct smu_table_context *smu_table = &smu->smu_table; 1078 struct smu_table *dummy_read_1_table = 1079 &smu_table->dummy_read_1_table; 1080 1081 1082 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1083 &dummy_read_1_table->mc_address, 1084 &dummy_read_1_table->cpu_addr); 1085 1086 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1087 } 1088 1089 static int smu_smc_table_sw_init(struct smu_context *smu) 1090 { 1091 int ret; 1092 1093 /** 1094 * Create smu_table structure, and init smc tables such as 1095 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1096 */ 1097 ret = smu_init_smc_tables(smu); 1098 if (ret) { 1099 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1100 return ret; 1101 } 1102 1103 /** 1104 * Create smu_power_context structure, and allocate smu_dpm_context and 1105 * context size to fill the smu_power_context data. 1106 */ 1107 ret = smu_init_power(smu); 1108 if (ret) { 1109 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1110 return ret; 1111 } 1112 1113 /* 1114 * allocate vram bos to store smc table contents. 1115 */ 1116 ret = smu_init_fb_allocations(smu); 1117 if (ret) 1118 return ret; 1119 1120 ret = smu_alloc_memory_pool(smu); 1121 if (ret) 1122 return ret; 1123 1124 ret = smu_alloc_dummy_read_table(smu); 1125 if (ret) 1126 return ret; 1127 1128 ret = smu_i2c_init(smu); 1129 if (ret) 1130 return ret; 1131 1132 return 0; 1133 } 1134 1135 static int smu_smc_table_sw_fini(struct smu_context *smu) 1136 { 1137 int ret; 1138 1139 smu_i2c_fini(smu); 1140 1141 smu_free_dummy_read_table(smu); 1142 1143 ret = smu_free_memory_pool(smu); 1144 if (ret) 1145 return ret; 1146 1147 ret = smu_fini_fb_allocations(smu); 1148 if (ret) 1149 return ret; 1150 1151 ret = smu_fini_power(smu); 1152 if (ret) { 1153 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1154 return ret; 1155 } 1156 1157 ret = smu_fini_smc_tables(smu); 1158 if (ret) { 1159 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1160 return ret; 1161 } 1162 1163 return 0; 1164 } 1165 1166 static void smu_throttling_logging_work_fn(struct work_struct *work) 1167 { 1168 struct smu_context *smu = container_of(work, struct smu_context, 1169 throttling_logging_work); 1170 1171 smu_log_thermal_throttling(smu); 1172 } 1173 1174 static void smu_interrupt_work_fn(struct work_struct *work) 1175 { 1176 struct smu_context *smu = container_of(work, struct smu_context, 1177 interrupt_work); 1178 1179 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1180 smu->ppt_funcs->interrupt_work(smu); 1181 } 1182 1183 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1184 { 1185 struct smu_context *smu = 1186 container_of(work, struct smu_context, swctf_delayed_work.work); 1187 struct smu_temperature_range *range = 1188 &smu->thermal_range; 1189 struct amdgpu_device *adev = smu->adev; 1190 uint32_t hotspot_tmp, size; 1191 1192 /* 1193 * If the hotspot temperature is confirmed as below SW CTF setting point 1194 * after the delay enforced, nothing will be done. 1195 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1196 */ 1197 if (range->software_shutdown_temp && 1198 smu->ppt_funcs->read_sensor && 1199 !smu->ppt_funcs->read_sensor(smu, 1200 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1201 &hotspot_tmp, 1202 &size) && 1203 hotspot_tmp / 1000 < range->software_shutdown_temp) 1204 return; 1205 1206 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1207 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1208 orderly_poweroff(true); 1209 } 1210 1211 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1212 { 1213 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1214 struct smu_dpm_policy_ctxt *policy_ctxt; 1215 struct smu_dpm_policy *policy; 1216 1217 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1218 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1219 if (policy) 1220 policy->current_level = XGMI_PLPD_DEFAULT; 1221 return; 1222 } 1223 1224 /* PMFW put PLPD into default policy after enabling the feature */ 1225 if (smu_feature_is_enabled(smu, 1226 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1227 if (policy) 1228 policy->current_level = XGMI_PLPD_DEFAULT; 1229 } else { 1230 policy_ctxt = dpm_ctxt->dpm_policies; 1231 if (policy_ctxt) 1232 policy_ctxt->policy_mask &= 1233 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1234 } 1235 } 1236 1237 static bool smu_is_workload_profile_available(struct smu_context *smu, 1238 u32 profile) 1239 { 1240 if (profile >= PP_SMC_POWER_PROFILE_COUNT) 1241 return false; 1242 return smu->workload_map && smu->workload_map[profile].valid_mapping; 1243 } 1244 1245 static int smu_sw_init(void *handle) 1246 { 1247 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1248 struct smu_context *smu = adev->powerplay.pp_handle; 1249 int ret; 1250 1251 smu->pool_size = adev->pm.smu_prv_buffer_size; 1252 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1253 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1254 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1255 1256 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1257 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1258 atomic64_set(&smu->throttle_int_counter, 0); 1259 smu->watermarks_bitmap = 0; 1260 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1261 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1262 smu->user_dpm_profile.user_workload_mask = 0; 1263 1264 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1265 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1266 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1267 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1268 1269 smu->workload_priority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1270 smu->workload_priority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1271 smu->workload_priority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1272 smu->workload_priority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1273 smu->workload_priority[PP_SMC_POWER_PROFILE_VR] = 4; 1274 smu->workload_priority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1275 smu->workload_priority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1276 1277 if (smu->is_apu || 1278 !smu_is_workload_profile_available(smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D)) { 1279 smu->driver_workload_mask = 1280 1 << smu->workload_priority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1281 } else { 1282 smu->driver_workload_mask = 1283 1 << smu->workload_priority[PP_SMC_POWER_PROFILE_FULLSCREEN3D]; 1284 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1285 } 1286 1287 smu->workload_mask = smu->driver_workload_mask | 1288 smu->user_dpm_profile.user_workload_mask; 1289 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1290 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1291 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1292 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1293 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1294 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1295 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1296 smu->display_config = &adev->pm.pm_display_cfg; 1297 1298 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1299 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1300 1301 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1302 smu_swctf_delayed_work_handler); 1303 1304 ret = smu_smc_table_sw_init(smu); 1305 if (ret) { 1306 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1307 return ret; 1308 } 1309 1310 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1311 ret = smu_get_vbios_bootup_values(smu); 1312 if (ret) { 1313 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1314 return ret; 1315 } 1316 1317 ret = smu_init_pptable_microcode(smu); 1318 if (ret) { 1319 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1320 return ret; 1321 } 1322 1323 ret = smu_register_irq_handler(smu); 1324 if (ret) { 1325 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1326 return ret; 1327 } 1328 1329 /* If there is no way to query fan control mode, fan control is not supported */ 1330 if (!smu->ppt_funcs->get_fan_control_mode) 1331 smu->adev->pm.no_fan = true; 1332 1333 return 0; 1334 } 1335 1336 static int smu_sw_fini(void *handle) 1337 { 1338 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1339 struct smu_context *smu = adev->powerplay.pp_handle; 1340 int ret; 1341 1342 ret = smu_smc_table_sw_fini(smu); 1343 if (ret) { 1344 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1345 return ret; 1346 } 1347 1348 smu_fini_microcode(smu); 1349 1350 return 0; 1351 } 1352 1353 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1354 { 1355 struct amdgpu_device *adev = smu->adev; 1356 struct smu_temperature_range *range = 1357 &smu->thermal_range; 1358 int ret = 0; 1359 1360 if (!smu->ppt_funcs->get_thermal_temperature_range) 1361 return 0; 1362 1363 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1364 if (ret) 1365 return ret; 1366 1367 adev->pm.dpm.thermal.min_temp = range->min; 1368 adev->pm.dpm.thermal.max_temp = range->max; 1369 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1370 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1371 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1372 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1373 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1374 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1375 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1376 1377 return ret; 1378 } 1379 1380 /** 1381 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1382 * 1383 * @smu: smu_context pointer 1384 * 1385 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1386 * Returns 0 on success, error on failure. 1387 */ 1388 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1389 { 1390 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1391 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1392 struct amdgpu_device *adev = smu->adev; 1393 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1394 uint64_t start, end; 1395 int ret, i, j; 1396 1397 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1398 if (ret) { 1399 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1400 return ret; 1401 } 1402 1403 /* 1404 * The exclusion ranges array we got might be filled with holes and duplicate 1405 * entries. For example: 1406 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1407 * We need to do some sortups to eliminate those holes and duplicate entries. 1408 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1409 */ 1410 for (i = 0; i < num_of_wbrf_ranges; i++) { 1411 start = wifi_bands[i].start; 1412 end = wifi_bands[i].end; 1413 1414 /* get the last valid entry to fill the intermediate hole */ 1415 if (!start && !end) { 1416 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1417 if (wifi_bands[j].start && wifi_bands[j].end) 1418 break; 1419 1420 /* no valid entry left */ 1421 if (j <= i) 1422 break; 1423 1424 start = wifi_bands[i].start = wifi_bands[j].start; 1425 end = wifi_bands[i].end = wifi_bands[j].end; 1426 wifi_bands[j].start = 0; 1427 wifi_bands[j].end = 0; 1428 num_of_wbrf_ranges = j; 1429 } 1430 1431 /* eliminate duplicate entries */ 1432 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1433 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1434 wifi_bands[j].start = 0; 1435 wifi_bands[j].end = 0; 1436 } 1437 } 1438 } 1439 1440 /* Send the sorted wifi_bands to PMFW */ 1441 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1442 /* Try to set the wifi_bands again */ 1443 if (unlikely(ret == -EBUSY)) { 1444 mdelay(5); 1445 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1446 } 1447 1448 return ret; 1449 } 1450 1451 /** 1452 * smu_wbrf_event_handler - handle notify events 1453 * 1454 * @nb: notifier block 1455 * @action: event type 1456 * @_arg: event data 1457 * 1458 * Calls relevant amdgpu function in response to wbrf event 1459 * notification from kernel. 1460 */ 1461 static int smu_wbrf_event_handler(struct notifier_block *nb, 1462 unsigned long action, void *_arg) 1463 { 1464 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1465 1466 switch (action) { 1467 case WBRF_CHANGED: 1468 schedule_delayed_work(&smu->wbrf_delayed_work, 1469 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1470 break; 1471 default: 1472 return NOTIFY_DONE; 1473 } 1474 1475 return NOTIFY_OK; 1476 } 1477 1478 /** 1479 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1480 * 1481 * @work: struct work_struct pointer 1482 * 1483 * Flood is over and driver will consume the latest exclusion ranges. 1484 */ 1485 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1486 { 1487 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1488 1489 smu_wbrf_handle_exclusion_ranges(smu); 1490 } 1491 1492 /** 1493 * smu_wbrf_support_check - check wbrf support 1494 * 1495 * @smu: smu_context pointer 1496 * 1497 * Verifies the ACPI interface whether wbrf is supported. 1498 */ 1499 static void smu_wbrf_support_check(struct smu_context *smu) 1500 { 1501 struct amdgpu_device *adev = smu->adev; 1502 1503 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1504 acpi_amd_wbrf_supported_consumer(adev->dev); 1505 1506 if (smu->wbrf_supported) 1507 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1508 } 1509 1510 /** 1511 * smu_wbrf_init - init driver wbrf support 1512 * 1513 * @smu: smu_context pointer 1514 * 1515 * Verifies the AMD ACPI interfaces and registers with the wbrf 1516 * notifier chain if wbrf feature is supported. 1517 * Returns 0 on success, error on failure. 1518 */ 1519 static int smu_wbrf_init(struct smu_context *smu) 1520 { 1521 int ret; 1522 1523 if (!smu->wbrf_supported) 1524 return 0; 1525 1526 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1527 1528 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1529 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1530 if (ret) 1531 return ret; 1532 1533 /* 1534 * Some wifiband exclusion ranges may be already there 1535 * before our driver loaded. To make sure our driver 1536 * is awared of those exclusion ranges. 1537 */ 1538 schedule_delayed_work(&smu->wbrf_delayed_work, 1539 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1540 1541 return 0; 1542 } 1543 1544 /** 1545 * smu_wbrf_fini - tear down driver wbrf support 1546 * 1547 * @smu: smu_context pointer 1548 * 1549 * Unregisters with the wbrf notifier chain. 1550 */ 1551 static void smu_wbrf_fini(struct smu_context *smu) 1552 { 1553 if (!smu->wbrf_supported) 1554 return; 1555 1556 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1557 1558 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1559 } 1560 1561 static int smu_smc_hw_setup(struct smu_context *smu) 1562 { 1563 struct smu_feature *feature = &smu->smu_feature; 1564 struct amdgpu_device *adev = smu->adev; 1565 uint8_t pcie_gen = 0, pcie_width = 0; 1566 uint64_t features_supported; 1567 int ret = 0; 1568 1569 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1570 case IP_VERSION(11, 0, 7): 1571 case IP_VERSION(11, 0, 11): 1572 case IP_VERSION(11, 5, 0): 1573 case IP_VERSION(11, 0, 12): 1574 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1575 dev_info(adev->dev, "dpm has been enabled\n"); 1576 ret = smu_system_features_control(smu, true); 1577 if (ret) 1578 dev_err(adev->dev, "Failed system features control!\n"); 1579 return ret; 1580 } 1581 break; 1582 default: 1583 break; 1584 } 1585 1586 ret = smu_init_display_count(smu, 0); 1587 if (ret) { 1588 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1589 return ret; 1590 } 1591 1592 ret = smu_set_driver_table_location(smu); 1593 if (ret) { 1594 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1595 return ret; 1596 } 1597 1598 /* 1599 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1600 */ 1601 ret = smu_set_tool_table_location(smu); 1602 if (ret) { 1603 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1604 return ret; 1605 } 1606 1607 /* 1608 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1609 * pool location. 1610 */ 1611 ret = smu_notify_memory_pool_location(smu); 1612 if (ret) { 1613 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1614 return ret; 1615 } 1616 1617 /* 1618 * It is assumed the pptable used before runpm is same as 1619 * the one used afterwards. Thus, we can reuse the stored 1620 * copy and do not need to resetup the pptable again. 1621 */ 1622 if (!adev->in_runpm) { 1623 ret = smu_setup_pptable(smu); 1624 if (ret) { 1625 dev_err(adev->dev, "Failed to setup pptable!\n"); 1626 return ret; 1627 } 1628 } 1629 1630 /* smu_dump_pptable(smu); */ 1631 1632 /* 1633 * With SCPM enabled, PSP is responsible for the PPTable transferring 1634 * (to SMU). Driver involvement is not needed and permitted. 1635 */ 1636 if (!adev->scpm_enabled) { 1637 /* 1638 * Copy pptable bo in the vram to smc with SMU MSGs such as 1639 * SetDriverDramAddr and TransferTableDram2Smu. 1640 */ 1641 ret = smu_write_pptable(smu); 1642 if (ret) { 1643 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1644 return ret; 1645 } 1646 } 1647 1648 /* issue Run*Btc msg */ 1649 ret = smu_run_btc(smu); 1650 if (ret) 1651 return ret; 1652 1653 /* Enable UclkShadow on wbrf supported */ 1654 if (smu->wbrf_supported) { 1655 ret = smu_enable_uclk_shadow(smu, true); 1656 if (ret) { 1657 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1658 return ret; 1659 } 1660 } 1661 1662 /* 1663 * With SCPM enabled, these actions(and relevant messages) are 1664 * not needed and permitted. 1665 */ 1666 if (!adev->scpm_enabled) { 1667 ret = smu_feature_set_allowed_mask(smu); 1668 if (ret) { 1669 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1670 return ret; 1671 } 1672 } 1673 1674 ret = smu_system_features_control(smu, true); 1675 if (ret) { 1676 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1677 return ret; 1678 } 1679 1680 smu_init_xgmi_plpd_mode(smu); 1681 1682 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1683 if (ret) { 1684 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1685 return ret; 1686 } 1687 bitmap_copy(feature->supported, 1688 (unsigned long *)&features_supported, 1689 feature->feature_num); 1690 1691 if (!smu_is_dpm_running(smu)) 1692 dev_info(adev->dev, "dpm has been disabled\n"); 1693 1694 /* 1695 * Set initialized values (get from vbios) to dpm tables context such as 1696 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1697 * type of clks. 1698 */ 1699 ret = smu_set_default_dpm_table(smu); 1700 if (ret) { 1701 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1702 return ret; 1703 } 1704 1705 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1706 pcie_gen = 3; 1707 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1708 pcie_gen = 2; 1709 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1710 pcie_gen = 1; 1711 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1712 pcie_gen = 0; 1713 1714 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1715 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1716 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1717 */ 1718 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1719 pcie_width = 6; 1720 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1721 pcie_width = 5; 1722 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1723 pcie_width = 4; 1724 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1725 pcie_width = 3; 1726 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1727 pcie_width = 2; 1728 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1729 pcie_width = 1; 1730 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1731 if (ret) { 1732 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1733 return ret; 1734 } 1735 1736 ret = smu_get_thermal_temperature_range(smu); 1737 if (ret) { 1738 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1739 return ret; 1740 } 1741 1742 ret = smu_enable_thermal_alert(smu); 1743 if (ret) { 1744 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1745 return ret; 1746 } 1747 1748 ret = smu_notify_display_change(smu); 1749 if (ret) { 1750 dev_err(adev->dev, "Failed to notify display change!\n"); 1751 return ret; 1752 } 1753 1754 /* 1755 * Set min deep sleep dce fclk with bootup value from vbios via 1756 * SetMinDeepSleepDcefclk MSG. 1757 */ 1758 ret = smu_set_min_dcef_deep_sleep(smu, 1759 smu->smu_table.boot_values.dcefclk / 100); 1760 if (ret) { 1761 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1762 return ret; 1763 } 1764 1765 /* Init wbrf support. Properly setup the notifier */ 1766 ret = smu_wbrf_init(smu); 1767 if (ret) 1768 dev_err(adev->dev, "Error during wbrf init call\n"); 1769 1770 return ret; 1771 } 1772 1773 static int smu_start_smc_engine(struct smu_context *smu) 1774 { 1775 struct amdgpu_device *adev = smu->adev; 1776 int ret = 0; 1777 1778 smu->smc_fw_state = SMU_FW_INIT; 1779 1780 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1781 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1782 if (smu->ppt_funcs->load_microcode) { 1783 ret = smu->ppt_funcs->load_microcode(smu); 1784 if (ret) 1785 return ret; 1786 } 1787 } 1788 } 1789 1790 if (smu->ppt_funcs->check_fw_status) { 1791 ret = smu->ppt_funcs->check_fw_status(smu); 1792 if (ret) { 1793 dev_err(adev->dev, "SMC is not ready\n"); 1794 return ret; 1795 } 1796 } 1797 1798 /* 1799 * Send msg GetDriverIfVersion to check if the return value is equal 1800 * with DRIVER_IF_VERSION of smc header. 1801 */ 1802 ret = smu_check_fw_version(smu); 1803 if (ret) 1804 return ret; 1805 1806 return ret; 1807 } 1808 1809 static int smu_hw_init(void *handle) 1810 { 1811 int ret; 1812 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1813 struct smu_context *smu = adev->powerplay.pp_handle; 1814 1815 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1816 smu->pm_enabled = false; 1817 return 0; 1818 } 1819 1820 ret = smu_start_smc_engine(smu); 1821 if (ret) { 1822 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1823 return ret; 1824 } 1825 1826 /* 1827 * Check whether wbrf is supported. This needs to be done 1828 * before SMU setup starts since part of SMU configuration 1829 * relies on this. 1830 */ 1831 smu_wbrf_support_check(smu); 1832 1833 if (smu->is_apu) { 1834 ret = smu_set_gfx_imu_enable(smu); 1835 if (ret) 1836 return ret; 1837 smu_dpm_set_vcn_enable(smu, true); 1838 smu_dpm_set_jpeg_enable(smu, true); 1839 smu_dpm_set_vpe_enable(smu, true); 1840 smu_dpm_set_umsch_mm_enable(smu, true); 1841 smu_set_mall_enable(smu); 1842 smu_set_gfx_cgpg(smu, true); 1843 } 1844 1845 if (!smu->pm_enabled) 1846 return 0; 1847 1848 ret = smu_get_driver_allowed_feature_mask(smu); 1849 if (ret) 1850 return ret; 1851 1852 ret = smu_smc_hw_setup(smu); 1853 if (ret) { 1854 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1855 return ret; 1856 } 1857 1858 /* 1859 * Move maximum sustainable clock retrieving here considering 1860 * 1. It is not needed on resume(from S3). 1861 * 2. DAL settings come between .hw_init and .late_init of SMU. 1862 * And DAL needs to know the maximum sustainable clocks. Thus 1863 * it cannot be put in .late_init(). 1864 */ 1865 ret = smu_init_max_sustainable_clocks(smu); 1866 if (ret) { 1867 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1868 return ret; 1869 } 1870 1871 adev->pm.dpm_enabled = true; 1872 1873 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1874 1875 return 0; 1876 } 1877 1878 static int smu_disable_dpms(struct smu_context *smu) 1879 { 1880 struct amdgpu_device *adev = smu->adev; 1881 int ret = 0; 1882 bool use_baco = !smu->is_apu && 1883 ((amdgpu_in_reset(adev) && 1884 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1885 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1886 1887 /* 1888 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1889 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1890 */ 1891 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1892 case IP_VERSION(13, 0, 0): 1893 case IP_VERSION(13, 0, 7): 1894 case IP_VERSION(13, 0, 10): 1895 case IP_VERSION(14, 0, 2): 1896 case IP_VERSION(14, 0, 3): 1897 return 0; 1898 default: 1899 break; 1900 } 1901 1902 /* 1903 * For custom pptable uploading, skip the DPM features 1904 * disable process on Navi1x ASICs. 1905 * - As the gfx related features are under control of 1906 * RLC on those ASICs. RLC reinitialization will be 1907 * needed to reenable them. That will cost much more 1908 * efforts. 1909 * 1910 * - SMU firmware can handle the DPM reenablement 1911 * properly. 1912 */ 1913 if (smu->uploading_custom_pp_table) { 1914 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1915 case IP_VERSION(11, 0, 0): 1916 case IP_VERSION(11, 0, 5): 1917 case IP_VERSION(11, 0, 9): 1918 case IP_VERSION(11, 0, 7): 1919 case IP_VERSION(11, 0, 11): 1920 case IP_VERSION(11, 5, 0): 1921 case IP_VERSION(11, 0, 12): 1922 case IP_VERSION(11, 0, 13): 1923 return 0; 1924 default: 1925 break; 1926 } 1927 } 1928 1929 /* 1930 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1931 * on BACO in. Driver involvement is unnecessary. 1932 */ 1933 if (use_baco) { 1934 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1935 case IP_VERSION(11, 0, 7): 1936 case IP_VERSION(11, 0, 0): 1937 case IP_VERSION(11, 0, 5): 1938 case IP_VERSION(11, 0, 9): 1939 case IP_VERSION(13, 0, 7): 1940 return 0; 1941 default: 1942 break; 1943 } 1944 } 1945 1946 /* 1947 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 1948 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1949 */ 1950 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 1951 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 1952 return 0; 1953 1954 /* 1955 * For gpu reset, runpm and hibernation through BACO, 1956 * BACO feature has to be kept enabled. 1957 */ 1958 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1959 ret = smu_disable_all_features_with_exception(smu, 1960 SMU_FEATURE_BACO_BIT); 1961 if (ret) 1962 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1963 } else { 1964 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1965 if (!adev->scpm_enabled) { 1966 ret = smu_system_features_control(smu, false); 1967 if (ret) 1968 dev_err(adev->dev, "Failed to disable smu features.\n"); 1969 } 1970 } 1971 1972 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1973 * otherwise SMU will hang while interacting with RLC if RLC is halted 1974 * this is a WA for Vangogh asic which fix the SMU hang issue. 1975 */ 1976 ret = smu_notify_rlc_state(smu, false); 1977 if (ret) { 1978 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1979 return ret; 1980 } 1981 1982 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1983 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1984 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1985 adev->gfx.rlc.funcs->stop(adev); 1986 1987 return ret; 1988 } 1989 1990 static int smu_smc_hw_cleanup(struct smu_context *smu) 1991 { 1992 struct amdgpu_device *adev = smu->adev; 1993 int ret = 0; 1994 1995 smu_wbrf_fini(smu); 1996 1997 cancel_work_sync(&smu->throttling_logging_work); 1998 cancel_work_sync(&smu->interrupt_work); 1999 2000 ret = smu_disable_thermal_alert(smu); 2001 if (ret) { 2002 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 2003 return ret; 2004 } 2005 2006 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2007 2008 ret = smu_disable_dpms(smu); 2009 if (ret) { 2010 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2011 return ret; 2012 } 2013 2014 return 0; 2015 } 2016 2017 static int smu_reset_mp1_state(struct smu_context *smu) 2018 { 2019 struct amdgpu_device *adev = smu->adev; 2020 int ret = 0; 2021 2022 if ((!adev->in_runpm) && (!adev->in_suspend) && 2023 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 2024 IP_VERSION(13, 0, 10) && 2025 !amdgpu_device_has_display_hardware(adev)) 2026 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2027 2028 return ret; 2029 } 2030 2031 static int smu_hw_fini(void *handle) 2032 { 2033 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2034 struct smu_context *smu = adev->powerplay.pp_handle; 2035 int ret; 2036 2037 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2038 return 0; 2039 2040 smu_dpm_set_vcn_enable(smu, false); 2041 smu_dpm_set_jpeg_enable(smu, false); 2042 smu_dpm_set_vpe_enable(smu, false); 2043 smu_dpm_set_umsch_mm_enable(smu, false); 2044 2045 adev->vcn.cur_state = AMD_PG_STATE_GATE; 2046 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2047 2048 if (!smu->pm_enabled) 2049 return 0; 2050 2051 adev->pm.dpm_enabled = false; 2052 2053 ret = smu_smc_hw_cleanup(smu); 2054 if (ret) 2055 return ret; 2056 2057 ret = smu_reset_mp1_state(smu); 2058 if (ret) 2059 return ret; 2060 2061 return 0; 2062 } 2063 2064 static void smu_late_fini(void *handle) 2065 { 2066 struct amdgpu_device *adev = handle; 2067 struct smu_context *smu = adev->powerplay.pp_handle; 2068 2069 kfree(smu); 2070 } 2071 2072 static int smu_reset(struct smu_context *smu) 2073 { 2074 struct amdgpu_device *adev = smu->adev; 2075 int ret; 2076 2077 ret = smu_hw_fini(adev); 2078 if (ret) 2079 return ret; 2080 2081 ret = smu_hw_init(adev); 2082 if (ret) 2083 return ret; 2084 2085 ret = smu_late_init(adev); 2086 if (ret) 2087 return ret; 2088 2089 return 0; 2090 } 2091 2092 static int smu_suspend(void *handle) 2093 { 2094 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2095 struct smu_context *smu = adev->powerplay.pp_handle; 2096 int ret; 2097 uint64_t count; 2098 2099 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2100 return 0; 2101 2102 if (!smu->pm_enabled) 2103 return 0; 2104 2105 adev->pm.dpm_enabled = false; 2106 2107 ret = smu_smc_hw_cleanup(smu); 2108 if (ret) 2109 return ret; 2110 2111 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2112 2113 smu_set_gfx_cgpg(smu, false); 2114 2115 /* 2116 * pwfw resets entrycount when device is suspended, so we save the 2117 * last value to be used when we resume to keep it consistent 2118 */ 2119 ret = smu_get_entrycount_gfxoff(smu, &count); 2120 if (!ret) 2121 adev->gfx.gfx_off_entrycount = count; 2122 2123 return 0; 2124 } 2125 2126 static int smu_resume(void *handle) 2127 { 2128 int ret; 2129 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2130 struct smu_context *smu = adev->powerplay.pp_handle; 2131 2132 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2133 return 0; 2134 2135 if (!smu->pm_enabled) 2136 return 0; 2137 2138 dev_info(adev->dev, "SMU is resuming...\n"); 2139 2140 ret = smu_start_smc_engine(smu); 2141 if (ret) { 2142 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2143 return ret; 2144 } 2145 2146 ret = smu_smc_hw_setup(smu); 2147 if (ret) { 2148 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2149 return ret; 2150 } 2151 2152 ret = smu_set_gfx_imu_enable(smu); 2153 if (ret) 2154 return ret; 2155 2156 smu_set_gfx_cgpg(smu, true); 2157 2158 smu->disable_uclk_switch = 0; 2159 2160 adev->pm.dpm_enabled = true; 2161 2162 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2163 2164 return 0; 2165 } 2166 2167 static int smu_display_configuration_change(void *handle, 2168 const struct amd_pp_display_configuration *display_config) 2169 { 2170 struct smu_context *smu = handle; 2171 2172 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2173 return -EOPNOTSUPP; 2174 2175 if (!display_config) 2176 return -EINVAL; 2177 2178 smu_set_min_dcef_deep_sleep(smu, 2179 display_config->min_dcef_deep_sleep_set_clk / 100); 2180 2181 return 0; 2182 } 2183 2184 static int smu_set_clockgating_state(void *handle, 2185 enum amd_clockgating_state state) 2186 { 2187 return 0; 2188 } 2189 2190 static int smu_set_powergating_state(void *handle, 2191 enum amd_powergating_state state) 2192 { 2193 return 0; 2194 } 2195 2196 static int smu_enable_umd_pstate(void *handle, 2197 enum amd_dpm_forced_level *level) 2198 { 2199 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2200 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2201 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2202 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2203 2204 struct smu_context *smu = (struct smu_context*)(handle); 2205 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2206 2207 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2208 return -EINVAL; 2209 2210 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2211 /* enter umd pstate, save current level, disable gfx cg*/ 2212 if (*level & profile_mode_mask) { 2213 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2214 smu_gpo_control(smu, false); 2215 smu_gfx_ulv_control(smu, false); 2216 smu_deep_sleep_control(smu, false); 2217 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2218 } 2219 } else { 2220 /* exit umd pstate, restore level, enable gfx cg*/ 2221 if (!(*level & profile_mode_mask)) { 2222 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2223 *level = smu_dpm_ctx->saved_dpm_level; 2224 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2225 smu_deep_sleep_control(smu, true); 2226 smu_gfx_ulv_control(smu, true); 2227 smu_gpo_control(smu, true); 2228 } 2229 } 2230 2231 return 0; 2232 } 2233 2234 static int smu_bump_power_profile_mode(struct smu_context *smu, 2235 long *param, 2236 uint32_t param_size) 2237 { 2238 int ret = 0; 2239 2240 if (smu->ppt_funcs->set_power_profile_mode) 2241 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2242 2243 return ret; 2244 } 2245 2246 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2247 enum amd_dpm_forced_level level, 2248 bool skip_display_settings, 2249 bool init) 2250 { 2251 int ret = 0; 2252 int index = 0; 2253 long workload[1]; 2254 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2255 2256 if (!skip_display_settings) { 2257 ret = smu_display_config_changed(smu); 2258 if (ret) { 2259 dev_err(smu->adev->dev, "Failed to change display config!"); 2260 return ret; 2261 } 2262 } 2263 2264 ret = smu_apply_clocks_adjust_rules(smu); 2265 if (ret) { 2266 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2267 return ret; 2268 } 2269 2270 if (!skip_display_settings) { 2271 ret = smu_notify_smc_display_config(smu); 2272 if (ret) { 2273 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2274 return ret; 2275 } 2276 } 2277 2278 if (smu_dpm_ctx->dpm_level != level) { 2279 ret = smu_asic_set_performance_level(smu, level); 2280 if (ret) { 2281 dev_err(smu->adev->dev, "Failed to set performance level!"); 2282 return ret; 2283 } 2284 2285 /* update the saved copy */ 2286 smu_dpm_ctx->dpm_level = level; 2287 } 2288 2289 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2290 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2291 index = fls(smu->workload_mask); 2292 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2293 workload[0] = smu->workload_setting[index]; 2294 2295 if (init || smu->power_profile_mode != workload[0]) 2296 smu_bump_power_profile_mode(smu, workload, 0); 2297 } 2298 2299 return ret; 2300 } 2301 2302 static int smu_handle_task(struct smu_context *smu, 2303 enum amd_dpm_forced_level level, 2304 enum amd_pp_task task_id) 2305 { 2306 int ret = 0; 2307 2308 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2309 return -EOPNOTSUPP; 2310 2311 switch (task_id) { 2312 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2313 ret = smu_pre_display_config_changed(smu); 2314 if (ret) 2315 return ret; 2316 ret = smu_adjust_power_state_dynamic(smu, level, false, false); 2317 break; 2318 case AMD_PP_TASK_COMPLETE_INIT: 2319 ret = smu_adjust_power_state_dynamic(smu, level, true, true); 2320 break; 2321 case AMD_PP_TASK_READJUST_POWER_STATE: 2322 ret = smu_adjust_power_state_dynamic(smu, level, true, false); 2323 break; 2324 default: 2325 break; 2326 } 2327 2328 return ret; 2329 } 2330 2331 static int smu_handle_dpm_task(void *handle, 2332 enum amd_pp_task task_id, 2333 enum amd_pm_state_type *user_state) 2334 { 2335 struct smu_context *smu = handle; 2336 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2337 2338 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2339 2340 } 2341 2342 static int smu_switch_power_profile(void *handle, 2343 enum PP_SMC_POWER_PROFILE type, 2344 bool en) 2345 { 2346 struct smu_context *smu = handle; 2347 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2348 long workload[1]; 2349 uint32_t index; 2350 2351 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2352 return -EOPNOTSUPP; 2353 2354 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2355 return -EINVAL; 2356 2357 if (!en) { 2358 smu->driver_workload_mask &= ~(1 << smu->workload_priority[type]); 2359 index = fls(smu->workload_mask); 2360 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2361 workload[0] = smu->workload_setting[index]; 2362 } else { 2363 smu->driver_workload_mask |= (1 << smu->workload_priority[type]); 2364 index = fls(smu->workload_mask); 2365 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2366 workload[0] = smu->workload_setting[index]; 2367 } 2368 2369 smu->workload_mask = smu->driver_workload_mask | 2370 smu->user_dpm_profile.user_workload_mask; 2371 2372 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2373 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2374 smu_bump_power_profile_mode(smu, workload, 0); 2375 2376 return 0; 2377 } 2378 2379 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2380 { 2381 struct smu_context *smu = handle; 2382 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2383 2384 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2385 return -EOPNOTSUPP; 2386 2387 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2388 return -EINVAL; 2389 2390 return smu_dpm_ctx->dpm_level; 2391 } 2392 2393 static int smu_force_performance_level(void *handle, 2394 enum amd_dpm_forced_level level) 2395 { 2396 struct smu_context *smu = handle; 2397 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2398 int ret = 0; 2399 2400 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2401 return -EOPNOTSUPP; 2402 2403 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2404 return -EINVAL; 2405 2406 ret = smu_enable_umd_pstate(smu, &level); 2407 if (ret) 2408 return ret; 2409 2410 ret = smu_handle_task(smu, level, 2411 AMD_PP_TASK_READJUST_POWER_STATE); 2412 2413 /* reset user dpm clock state */ 2414 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2415 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2416 smu->user_dpm_profile.clk_dependency = 0; 2417 } 2418 2419 return ret; 2420 } 2421 2422 static int smu_set_display_count(void *handle, uint32_t count) 2423 { 2424 struct smu_context *smu = handle; 2425 2426 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2427 return -EOPNOTSUPP; 2428 2429 return smu_init_display_count(smu, count); 2430 } 2431 2432 static int smu_force_smuclk_levels(struct smu_context *smu, 2433 enum smu_clk_type clk_type, 2434 uint32_t mask) 2435 { 2436 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2437 int ret = 0; 2438 2439 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2440 return -EOPNOTSUPP; 2441 2442 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2443 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2444 return -EINVAL; 2445 } 2446 2447 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2448 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2449 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2450 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2451 smu_set_user_clk_dependencies(smu, clk_type); 2452 } 2453 } 2454 2455 return ret; 2456 } 2457 2458 static int smu_force_ppclk_levels(void *handle, 2459 enum pp_clock_type type, 2460 uint32_t mask) 2461 { 2462 struct smu_context *smu = handle; 2463 enum smu_clk_type clk_type; 2464 2465 switch (type) { 2466 case PP_SCLK: 2467 clk_type = SMU_SCLK; break; 2468 case PP_MCLK: 2469 clk_type = SMU_MCLK; break; 2470 case PP_PCIE: 2471 clk_type = SMU_PCIE; break; 2472 case PP_SOCCLK: 2473 clk_type = SMU_SOCCLK; break; 2474 case PP_FCLK: 2475 clk_type = SMU_FCLK; break; 2476 case PP_DCEFCLK: 2477 clk_type = SMU_DCEFCLK; break; 2478 case PP_VCLK: 2479 clk_type = SMU_VCLK; break; 2480 case PP_VCLK1: 2481 clk_type = SMU_VCLK1; break; 2482 case PP_DCLK: 2483 clk_type = SMU_DCLK; break; 2484 case PP_DCLK1: 2485 clk_type = SMU_DCLK1; break; 2486 case OD_SCLK: 2487 clk_type = SMU_OD_SCLK; break; 2488 case OD_MCLK: 2489 clk_type = SMU_OD_MCLK; break; 2490 case OD_VDDC_CURVE: 2491 clk_type = SMU_OD_VDDC_CURVE; break; 2492 case OD_RANGE: 2493 clk_type = SMU_OD_RANGE; break; 2494 default: 2495 return -EINVAL; 2496 } 2497 2498 return smu_force_smuclk_levels(smu, clk_type, mask); 2499 } 2500 2501 /* 2502 * On system suspending or resetting, the dpm_enabled 2503 * flag will be cleared. So that those SMU services which 2504 * are not supported will be gated. 2505 * However, the mp1 state setting should still be granted 2506 * even if the dpm_enabled cleared. 2507 */ 2508 static int smu_set_mp1_state(void *handle, 2509 enum pp_mp1_state mp1_state) 2510 { 2511 struct smu_context *smu = handle; 2512 int ret = 0; 2513 2514 if (!smu->pm_enabled) 2515 return -EOPNOTSUPP; 2516 2517 if (smu->ppt_funcs && 2518 smu->ppt_funcs->set_mp1_state) 2519 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2520 2521 return ret; 2522 } 2523 2524 static int smu_set_df_cstate(void *handle, 2525 enum pp_df_cstate state) 2526 { 2527 struct smu_context *smu = handle; 2528 int ret = 0; 2529 2530 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2531 return -EOPNOTSUPP; 2532 2533 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2534 return 0; 2535 2536 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2537 if (ret) 2538 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2539 2540 return ret; 2541 } 2542 2543 int smu_write_watermarks_table(struct smu_context *smu) 2544 { 2545 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2546 return -EOPNOTSUPP; 2547 2548 return smu_set_watermarks_table(smu, NULL); 2549 } 2550 2551 static int smu_set_watermarks_for_clock_ranges(void *handle, 2552 struct pp_smu_wm_range_sets *clock_ranges) 2553 { 2554 struct smu_context *smu = handle; 2555 2556 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2557 return -EOPNOTSUPP; 2558 2559 if (smu->disable_watermark) 2560 return 0; 2561 2562 return smu_set_watermarks_table(smu, clock_ranges); 2563 } 2564 2565 int smu_set_ac_dc(struct smu_context *smu) 2566 { 2567 int ret = 0; 2568 2569 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2570 return -EOPNOTSUPP; 2571 2572 /* controlled by firmware */ 2573 if (smu->dc_controlled_by_gpio) 2574 return 0; 2575 2576 ret = smu_set_power_source(smu, 2577 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2578 SMU_POWER_SOURCE_DC); 2579 if (ret) 2580 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2581 smu->adev->pm.ac_power ? "AC" : "DC"); 2582 2583 return ret; 2584 } 2585 2586 const struct amd_ip_funcs smu_ip_funcs = { 2587 .name = "smu", 2588 .early_init = smu_early_init, 2589 .late_init = smu_late_init, 2590 .sw_init = smu_sw_init, 2591 .sw_fini = smu_sw_fini, 2592 .hw_init = smu_hw_init, 2593 .hw_fini = smu_hw_fini, 2594 .late_fini = smu_late_fini, 2595 .suspend = smu_suspend, 2596 .resume = smu_resume, 2597 .is_idle = NULL, 2598 .check_soft_reset = NULL, 2599 .wait_for_idle = NULL, 2600 .soft_reset = NULL, 2601 .set_clockgating_state = smu_set_clockgating_state, 2602 .set_powergating_state = smu_set_powergating_state, 2603 }; 2604 2605 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2606 .type = AMD_IP_BLOCK_TYPE_SMC, 2607 .major = 11, 2608 .minor = 0, 2609 .rev = 0, 2610 .funcs = &smu_ip_funcs, 2611 }; 2612 2613 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2614 .type = AMD_IP_BLOCK_TYPE_SMC, 2615 .major = 12, 2616 .minor = 0, 2617 .rev = 0, 2618 .funcs = &smu_ip_funcs, 2619 }; 2620 2621 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2622 .type = AMD_IP_BLOCK_TYPE_SMC, 2623 .major = 13, 2624 .minor = 0, 2625 .rev = 0, 2626 .funcs = &smu_ip_funcs, 2627 }; 2628 2629 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2630 .type = AMD_IP_BLOCK_TYPE_SMC, 2631 .major = 14, 2632 .minor = 0, 2633 .rev = 0, 2634 .funcs = &smu_ip_funcs, 2635 }; 2636 2637 static int smu_load_microcode(void *handle) 2638 { 2639 struct smu_context *smu = handle; 2640 struct amdgpu_device *adev = smu->adev; 2641 int ret = 0; 2642 2643 if (!smu->pm_enabled) 2644 return -EOPNOTSUPP; 2645 2646 /* This should be used for non PSP loading */ 2647 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2648 return 0; 2649 2650 if (smu->ppt_funcs->load_microcode) { 2651 ret = smu->ppt_funcs->load_microcode(smu); 2652 if (ret) { 2653 dev_err(adev->dev, "Load microcode failed\n"); 2654 return ret; 2655 } 2656 } 2657 2658 if (smu->ppt_funcs->check_fw_status) { 2659 ret = smu->ppt_funcs->check_fw_status(smu); 2660 if (ret) { 2661 dev_err(adev->dev, "SMC is not ready\n"); 2662 return ret; 2663 } 2664 } 2665 2666 return ret; 2667 } 2668 2669 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2670 { 2671 int ret = 0; 2672 2673 if (smu->ppt_funcs->set_gfx_cgpg) 2674 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2675 2676 return ret; 2677 } 2678 2679 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2680 { 2681 struct smu_context *smu = handle; 2682 int ret = 0; 2683 2684 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2685 return -EOPNOTSUPP; 2686 2687 if (!smu->ppt_funcs->set_fan_speed_rpm) 2688 return -EOPNOTSUPP; 2689 2690 if (speed == U32_MAX) 2691 return -EINVAL; 2692 2693 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2694 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2695 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2696 smu->user_dpm_profile.fan_speed_rpm = speed; 2697 2698 /* Override custom PWM setting as they cannot co-exist */ 2699 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2700 smu->user_dpm_profile.fan_speed_pwm = 0; 2701 } 2702 2703 return ret; 2704 } 2705 2706 /** 2707 * smu_get_power_limit - Request one of the SMU Power Limits 2708 * 2709 * @handle: pointer to smu context 2710 * @limit: requested limit is written back to this variable 2711 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2712 * @pp_power_type: &pp_power_type type of power 2713 * Return: 0 on success, <0 on error 2714 * 2715 */ 2716 int smu_get_power_limit(void *handle, 2717 uint32_t *limit, 2718 enum pp_power_limit_level pp_limit_level, 2719 enum pp_power_type pp_power_type) 2720 { 2721 struct smu_context *smu = handle; 2722 struct amdgpu_device *adev = smu->adev; 2723 enum smu_ppt_limit_level limit_level; 2724 uint32_t limit_type; 2725 int ret = 0; 2726 2727 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2728 return -EOPNOTSUPP; 2729 2730 switch (pp_power_type) { 2731 case PP_PWR_TYPE_SUSTAINED: 2732 limit_type = SMU_DEFAULT_PPT_LIMIT; 2733 break; 2734 case PP_PWR_TYPE_FAST: 2735 limit_type = SMU_FAST_PPT_LIMIT; 2736 break; 2737 default: 2738 return -EOPNOTSUPP; 2739 } 2740 2741 switch (pp_limit_level) { 2742 case PP_PWR_LIMIT_CURRENT: 2743 limit_level = SMU_PPT_LIMIT_CURRENT; 2744 break; 2745 case PP_PWR_LIMIT_DEFAULT: 2746 limit_level = SMU_PPT_LIMIT_DEFAULT; 2747 break; 2748 case PP_PWR_LIMIT_MAX: 2749 limit_level = SMU_PPT_LIMIT_MAX; 2750 break; 2751 case PP_PWR_LIMIT_MIN: 2752 limit_level = SMU_PPT_LIMIT_MIN; 2753 break; 2754 default: 2755 return -EOPNOTSUPP; 2756 } 2757 2758 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2759 if (smu->ppt_funcs->get_ppt_limit) 2760 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2761 } else { 2762 switch (limit_level) { 2763 case SMU_PPT_LIMIT_CURRENT: 2764 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2765 case IP_VERSION(13, 0, 2): 2766 case IP_VERSION(13, 0, 6): 2767 case IP_VERSION(13, 0, 14): 2768 case IP_VERSION(11, 0, 7): 2769 case IP_VERSION(11, 0, 11): 2770 case IP_VERSION(11, 0, 12): 2771 case IP_VERSION(11, 0, 13): 2772 ret = smu_get_asic_power_limits(smu, 2773 &smu->current_power_limit, 2774 NULL, NULL, NULL); 2775 break; 2776 default: 2777 break; 2778 } 2779 *limit = smu->current_power_limit; 2780 break; 2781 case SMU_PPT_LIMIT_DEFAULT: 2782 *limit = smu->default_power_limit; 2783 break; 2784 case SMU_PPT_LIMIT_MAX: 2785 *limit = smu->max_power_limit; 2786 break; 2787 case SMU_PPT_LIMIT_MIN: 2788 *limit = smu->min_power_limit; 2789 break; 2790 default: 2791 return -EINVAL; 2792 } 2793 } 2794 2795 return ret; 2796 } 2797 2798 static int smu_set_power_limit(void *handle, uint32_t limit) 2799 { 2800 struct smu_context *smu = handle; 2801 uint32_t limit_type = limit >> 24; 2802 int ret = 0; 2803 2804 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2805 return -EOPNOTSUPP; 2806 2807 limit &= (1<<24)-1; 2808 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2809 if (smu->ppt_funcs->set_power_limit) 2810 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2811 2812 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2813 dev_err(smu->adev->dev, 2814 "New power limit (%d) is out of range [%d,%d]\n", 2815 limit, smu->min_power_limit, smu->max_power_limit); 2816 return -EINVAL; 2817 } 2818 2819 if (!limit) 2820 limit = smu->current_power_limit; 2821 2822 if (smu->ppt_funcs->set_power_limit) { 2823 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2824 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2825 smu->user_dpm_profile.power_limit = limit; 2826 } 2827 2828 return ret; 2829 } 2830 2831 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2832 { 2833 int ret = 0; 2834 2835 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2836 return -EOPNOTSUPP; 2837 2838 if (smu->ppt_funcs->print_clk_levels) 2839 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2840 2841 return ret; 2842 } 2843 2844 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2845 { 2846 enum smu_clk_type clk_type; 2847 2848 switch (type) { 2849 case PP_SCLK: 2850 clk_type = SMU_SCLK; break; 2851 case PP_MCLK: 2852 clk_type = SMU_MCLK; break; 2853 case PP_PCIE: 2854 clk_type = SMU_PCIE; break; 2855 case PP_SOCCLK: 2856 clk_type = SMU_SOCCLK; break; 2857 case PP_FCLK: 2858 clk_type = SMU_FCLK; break; 2859 case PP_DCEFCLK: 2860 clk_type = SMU_DCEFCLK; break; 2861 case PP_VCLK: 2862 clk_type = SMU_VCLK; break; 2863 case PP_VCLK1: 2864 clk_type = SMU_VCLK1; break; 2865 case PP_DCLK: 2866 clk_type = SMU_DCLK; break; 2867 case PP_DCLK1: 2868 clk_type = SMU_DCLK1; break; 2869 case OD_SCLK: 2870 clk_type = SMU_OD_SCLK; break; 2871 case OD_MCLK: 2872 clk_type = SMU_OD_MCLK; break; 2873 case OD_VDDC_CURVE: 2874 clk_type = SMU_OD_VDDC_CURVE; break; 2875 case OD_RANGE: 2876 clk_type = SMU_OD_RANGE; break; 2877 case OD_VDDGFX_OFFSET: 2878 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2879 case OD_CCLK: 2880 clk_type = SMU_OD_CCLK; break; 2881 case OD_FAN_CURVE: 2882 clk_type = SMU_OD_FAN_CURVE; break; 2883 case OD_ACOUSTIC_LIMIT: 2884 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2885 case OD_ACOUSTIC_TARGET: 2886 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2887 case OD_FAN_TARGET_TEMPERATURE: 2888 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2889 case OD_FAN_MINIMUM_PWM: 2890 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2891 default: 2892 clk_type = SMU_CLK_COUNT; break; 2893 } 2894 2895 return clk_type; 2896 } 2897 2898 static int smu_print_ppclk_levels(void *handle, 2899 enum pp_clock_type type, 2900 char *buf) 2901 { 2902 struct smu_context *smu = handle; 2903 enum smu_clk_type clk_type; 2904 2905 clk_type = smu_convert_to_smuclk(type); 2906 if (clk_type == SMU_CLK_COUNT) 2907 return -EINVAL; 2908 2909 return smu_print_smuclk_levels(smu, clk_type, buf); 2910 } 2911 2912 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2913 { 2914 struct smu_context *smu = handle; 2915 enum smu_clk_type clk_type; 2916 2917 clk_type = smu_convert_to_smuclk(type); 2918 if (clk_type == SMU_CLK_COUNT) 2919 return -EINVAL; 2920 2921 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2922 return -EOPNOTSUPP; 2923 2924 if (!smu->ppt_funcs->emit_clk_levels) 2925 return -ENOENT; 2926 2927 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2928 2929 } 2930 2931 static int smu_od_edit_dpm_table(void *handle, 2932 enum PP_OD_DPM_TABLE_COMMAND type, 2933 long *input, uint32_t size) 2934 { 2935 struct smu_context *smu = handle; 2936 int ret = 0; 2937 2938 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2939 return -EOPNOTSUPP; 2940 2941 if (smu->ppt_funcs->od_edit_dpm_table) { 2942 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2943 } 2944 2945 return ret; 2946 } 2947 2948 static int smu_read_sensor(void *handle, 2949 int sensor, 2950 void *data, 2951 int *size_arg) 2952 { 2953 struct smu_context *smu = handle; 2954 struct smu_umd_pstate_table *pstate_table = 2955 &smu->pstate_table; 2956 int ret = 0; 2957 uint32_t *size, size_val; 2958 2959 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2960 return -EOPNOTSUPP; 2961 2962 if (!data || !size_arg) 2963 return -EINVAL; 2964 2965 size_val = *size_arg; 2966 size = &size_val; 2967 2968 if (smu->ppt_funcs->read_sensor) 2969 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2970 goto unlock; 2971 2972 switch (sensor) { 2973 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2974 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2975 *size = 4; 2976 break; 2977 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2978 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2979 *size = 4; 2980 break; 2981 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2982 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2983 *size = 4; 2984 break; 2985 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2986 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2987 *size = 4; 2988 break; 2989 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2990 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2991 *size = 8; 2992 break; 2993 case AMDGPU_PP_SENSOR_UVD_POWER: 2994 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2995 *size = 4; 2996 break; 2997 case AMDGPU_PP_SENSOR_VCE_POWER: 2998 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2999 *size = 4; 3000 break; 3001 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3002 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 3003 *size = 4; 3004 break; 3005 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3006 *(uint32_t *)data = 0; 3007 *size = 4; 3008 break; 3009 default: 3010 *size = 0; 3011 ret = -EOPNOTSUPP; 3012 break; 3013 } 3014 3015 unlock: 3016 // assign uint32_t to int 3017 *size_arg = size_val; 3018 3019 return ret; 3020 } 3021 3022 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3023 { 3024 int ret = -EOPNOTSUPP; 3025 struct smu_context *smu = handle; 3026 3027 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3028 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3029 3030 return ret; 3031 } 3032 3033 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3034 { 3035 int ret = -EOPNOTSUPP; 3036 struct smu_context *smu = handle; 3037 3038 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3039 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3040 3041 return ret; 3042 } 3043 3044 static int smu_get_power_profile_mode(void *handle, char *buf) 3045 { 3046 struct smu_context *smu = handle; 3047 3048 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3049 !smu->ppt_funcs->get_power_profile_mode) 3050 return -EOPNOTSUPP; 3051 if (!buf) 3052 return -EINVAL; 3053 3054 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3055 } 3056 3057 static int smu_set_power_profile_mode(void *handle, 3058 long *param, 3059 uint32_t param_size) 3060 { 3061 struct smu_context *smu = handle; 3062 int ret; 3063 3064 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3065 !smu->ppt_funcs->set_power_profile_mode) 3066 return -EOPNOTSUPP; 3067 3068 if (smu->user_dpm_profile.user_workload_mask & 3069 (1 << smu->workload_priority[param[param_size]])) 3070 return 0; 3071 3072 smu->user_dpm_profile.user_workload_mask = 3073 (1 << smu->workload_priority[param[param_size]]); 3074 smu->workload_mask = smu->user_dpm_profile.user_workload_mask | 3075 smu->driver_workload_mask; 3076 ret = smu_bump_power_profile_mode(smu, param, param_size); 3077 3078 return ret; 3079 } 3080 3081 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3082 { 3083 struct smu_context *smu = handle; 3084 3085 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3086 return -EOPNOTSUPP; 3087 3088 if (!smu->ppt_funcs->get_fan_control_mode) 3089 return -EOPNOTSUPP; 3090 3091 if (!fan_mode) 3092 return -EINVAL; 3093 3094 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3095 3096 return 0; 3097 } 3098 3099 static int smu_set_fan_control_mode(void *handle, u32 value) 3100 { 3101 struct smu_context *smu = handle; 3102 int ret = 0; 3103 3104 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3105 return -EOPNOTSUPP; 3106 3107 if (!smu->ppt_funcs->set_fan_control_mode) 3108 return -EOPNOTSUPP; 3109 3110 if (value == U32_MAX) 3111 return -EINVAL; 3112 3113 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3114 if (ret) 3115 goto out; 3116 3117 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3118 smu->user_dpm_profile.fan_mode = value; 3119 3120 /* reset user dpm fan speed */ 3121 if (value != AMD_FAN_CTRL_MANUAL) { 3122 smu->user_dpm_profile.fan_speed_pwm = 0; 3123 smu->user_dpm_profile.fan_speed_rpm = 0; 3124 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3125 } 3126 } 3127 3128 out: 3129 return ret; 3130 } 3131 3132 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3133 { 3134 struct smu_context *smu = handle; 3135 int ret = 0; 3136 3137 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3138 return -EOPNOTSUPP; 3139 3140 if (!smu->ppt_funcs->get_fan_speed_pwm) 3141 return -EOPNOTSUPP; 3142 3143 if (!speed) 3144 return -EINVAL; 3145 3146 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3147 3148 return ret; 3149 } 3150 3151 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3152 { 3153 struct smu_context *smu = handle; 3154 int ret = 0; 3155 3156 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3157 return -EOPNOTSUPP; 3158 3159 if (!smu->ppt_funcs->set_fan_speed_pwm) 3160 return -EOPNOTSUPP; 3161 3162 if (speed == U32_MAX) 3163 return -EINVAL; 3164 3165 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3166 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3167 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3168 smu->user_dpm_profile.fan_speed_pwm = speed; 3169 3170 /* Override custom RPM setting as they cannot co-exist */ 3171 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3172 smu->user_dpm_profile.fan_speed_rpm = 0; 3173 } 3174 3175 return ret; 3176 } 3177 3178 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3179 { 3180 struct smu_context *smu = handle; 3181 int ret = 0; 3182 3183 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3184 return -EOPNOTSUPP; 3185 3186 if (!smu->ppt_funcs->get_fan_speed_rpm) 3187 return -EOPNOTSUPP; 3188 3189 if (!speed) 3190 return -EINVAL; 3191 3192 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3193 3194 return ret; 3195 } 3196 3197 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3198 { 3199 struct smu_context *smu = handle; 3200 3201 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3202 return -EOPNOTSUPP; 3203 3204 return smu_set_min_dcef_deep_sleep(smu, clk); 3205 } 3206 3207 static int smu_get_clock_by_type_with_latency(void *handle, 3208 enum amd_pp_clock_type type, 3209 struct pp_clock_levels_with_latency *clocks) 3210 { 3211 struct smu_context *smu = handle; 3212 enum smu_clk_type clk_type; 3213 int ret = 0; 3214 3215 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3216 return -EOPNOTSUPP; 3217 3218 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3219 switch (type) { 3220 case amd_pp_sys_clock: 3221 clk_type = SMU_GFXCLK; 3222 break; 3223 case amd_pp_mem_clock: 3224 clk_type = SMU_MCLK; 3225 break; 3226 case amd_pp_dcef_clock: 3227 clk_type = SMU_DCEFCLK; 3228 break; 3229 case amd_pp_disp_clock: 3230 clk_type = SMU_DISPCLK; 3231 break; 3232 default: 3233 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3234 return -EINVAL; 3235 } 3236 3237 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3238 } 3239 3240 return ret; 3241 } 3242 3243 static int smu_display_clock_voltage_request(void *handle, 3244 struct pp_display_clock_request *clock_req) 3245 { 3246 struct smu_context *smu = handle; 3247 int ret = 0; 3248 3249 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3250 return -EOPNOTSUPP; 3251 3252 if (smu->ppt_funcs->display_clock_voltage_request) 3253 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3254 3255 return ret; 3256 } 3257 3258 3259 static int smu_display_disable_memory_clock_switch(void *handle, 3260 bool disable_memory_clock_switch) 3261 { 3262 struct smu_context *smu = handle; 3263 int ret = -EINVAL; 3264 3265 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3266 return -EOPNOTSUPP; 3267 3268 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3269 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3270 3271 return ret; 3272 } 3273 3274 static int smu_set_xgmi_pstate(void *handle, 3275 uint32_t pstate) 3276 { 3277 struct smu_context *smu = handle; 3278 int ret = 0; 3279 3280 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3281 return -EOPNOTSUPP; 3282 3283 if (smu->ppt_funcs->set_xgmi_pstate) 3284 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3285 3286 if (ret) 3287 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3288 3289 return ret; 3290 } 3291 3292 static int smu_get_baco_capability(void *handle) 3293 { 3294 struct smu_context *smu = handle; 3295 3296 if (!smu->pm_enabled) 3297 return false; 3298 3299 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3300 return false; 3301 3302 return smu->ppt_funcs->get_bamaco_support(smu); 3303 } 3304 3305 static int smu_baco_set_state(void *handle, int state) 3306 { 3307 struct smu_context *smu = handle; 3308 int ret = 0; 3309 3310 if (!smu->pm_enabled) 3311 return -EOPNOTSUPP; 3312 3313 if (state == 0) { 3314 if (smu->ppt_funcs->baco_exit) 3315 ret = smu->ppt_funcs->baco_exit(smu); 3316 } else if (state == 1) { 3317 if (smu->ppt_funcs->baco_enter) 3318 ret = smu->ppt_funcs->baco_enter(smu); 3319 } else { 3320 return -EINVAL; 3321 } 3322 3323 if (ret) 3324 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3325 (state)?"enter":"exit"); 3326 3327 return ret; 3328 } 3329 3330 bool smu_mode1_reset_is_support(struct smu_context *smu) 3331 { 3332 bool ret = false; 3333 3334 if (!smu->pm_enabled) 3335 return false; 3336 3337 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3338 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3339 3340 return ret; 3341 } 3342 3343 bool smu_mode2_reset_is_support(struct smu_context *smu) 3344 { 3345 bool ret = false; 3346 3347 if (!smu->pm_enabled) 3348 return false; 3349 3350 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3351 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3352 3353 return ret; 3354 } 3355 3356 int smu_mode1_reset(struct smu_context *smu) 3357 { 3358 int ret = 0; 3359 3360 if (!smu->pm_enabled) 3361 return -EOPNOTSUPP; 3362 3363 if (smu->ppt_funcs->mode1_reset) 3364 ret = smu->ppt_funcs->mode1_reset(smu); 3365 3366 return ret; 3367 } 3368 3369 static int smu_mode2_reset(void *handle) 3370 { 3371 struct smu_context *smu = handle; 3372 int ret = 0; 3373 3374 if (!smu->pm_enabled) 3375 return -EOPNOTSUPP; 3376 3377 if (smu->ppt_funcs->mode2_reset) 3378 ret = smu->ppt_funcs->mode2_reset(smu); 3379 3380 if (ret) 3381 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3382 3383 return ret; 3384 } 3385 3386 static int smu_enable_gfx_features(void *handle) 3387 { 3388 struct smu_context *smu = handle; 3389 int ret = 0; 3390 3391 if (!smu->pm_enabled) 3392 return -EOPNOTSUPP; 3393 3394 if (smu->ppt_funcs->enable_gfx_features) 3395 ret = smu->ppt_funcs->enable_gfx_features(smu); 3396 3397 if (ret) 3398 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3399 3400 return ret; 3401 } 3402 3403 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3404 struct pp_smu_nv_clock_table *max_clocks) 3405 { 3406 struct smu_context *smu = handle; 3407 int ret = 0; 3408 3409 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3410 return -EOPNOTSUPP; 3411 3412 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3413 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3414 3415 return ret; 3416 } 3417 3418 static int smu_get_uclk_dpm_states(void *handle, 3419 unsigned int *clock_values_in_khz, 3420 unsigned int *num_states) 3421 { 3422 struct smu_context *smu = handle; 3423 int ret = 0; 3424 3425 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3426 return -EOPNOTSUPP; 3427 3428 if (smu->ppt_funcs->get_uclk_dpm_states) 3429 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3430 3431 return ret; 3432 } 3433 3434 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3435 { 3436 struct smu_context *smu = handle; 3437 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3438 3439 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3440 return -EOPNOTSUPP; 3441 3442 if (smu->ppt_funcs->get_current_power_state) 3443 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3444 3445 return pm_state; 3446 } 3447 3448 static int smu_get_dpm_clock_table(void *handle, 3449 struct dpm_clocks *clock_table) 3450 { 3451 struct smu_context *smu = handle; 3452 int ret = 0; 3453 3454 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3455 return -EOPNOTSUPP; 3456 3457 if (smu->ppt_funcs->get_dpm_clock_table) 3458 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3459 3460 return ret; 3461 } 3462 3463 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3464 { 3465 struct smu_context *smu = handle; 3466 3467 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3468 return -EOPNOTSUPP; 3469 3470 if (!smu->ppt_funcs->get_gpu_metrics) 3471 return -EOPNOTSUPP; 3472 3473 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3474 } 3475 3476 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3477 size_t size) 3478 { 3479 struct smu_context *smu = handle; 3480 3481 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3482 return -EOPNOTSUPP; 3483 3484 if (!smu->ppt_funcs->get_pm_metrics) 3485 return -EOPNOTSUPP; 3486 3487 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3488 } 3489 3490 static int smu_enable_mgpu_fan_boost(void *handle) 3491 { 3492 struct smu_context *smu = handle; 3493 int ret = 0; 3494 3495 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3496 return -EOPNOTSUPP; 3497 3498 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3499 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3500 3501 return ret; 3502 } 3503 3504 static int smu_gfx_state_change_set(void *handle, 3505 uint32_t state) 3506 { 3507 struct smu_context *smu = handle; 3508 int ret = 0; 3509 3510 if (smu->ppt_funcs->gfx_state_change_set) 3511 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3512 3513 return ret; 3514 } 3515 3516 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3517 { 3518 int ret = 0; 3519 3520 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3521 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3522 3523 return ret; 3524 } 3525 3526 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3527 { 3528 int ret = -EOPNOTSUPP; 3529 3530 if (smu->ppt_funcs && 3531 smu->ppt_funcs->get_ecc_info) 3532 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3533 3534 return ret; 3535 3536 } 3537 3538 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3539 { 3540 struct smu_context *smu = handle; 3541 struct smu_table_context *smu_table = &smu->smu_table; 3542 struct smu_table *memory_pool = &smu_table->memory_pool; 3543 3544 if (!addr || !size) 3545 return -EINVAL; 3546 3547 *addr = NULL; 3548 *size = 0; 3549 if (memory_pool->bo) { 3550 *addr = memory_pool->cpu_addr; 3551 *size = memory_pool->size; 3552 } 3553 3554 return 0; 3555 } 3556 3557 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3558 size_t *size) 3559 { 3560 size_t offset = *size; 3561 int level; 3562 3563 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3564 if (level == policy->current_level) 3565 offset += sysfs_emit_at(sysbuf, offset, 3566 "%d : %s*\n", level, 3567 policy->desc->get_desc(policy, level)); 3568 else 3569 offset += sysfs_emit_at(sysbuf, offset, 3570 "%d : %s\n", level, 3571 policy->desc->get_desc(policy, level)); 3572 } 3573 3574 *size = offset; 3575 } 3576 3577 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3578 enum pp_pm_policy p_type, char *sysbuf) 3579 { 3580 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3581 struct smu_dpm_policy_ctxt *policy_ctxt; 3582 struct smu_dpm_policy *dpm_policy; 3583 size_t offset = 0; 3584 3585 policy_ctxt = dpm_ctxt->dpm_policies; 3586 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3587 !policy_ctxt->policy_mask) 3588 return -EOPNOTSUPP; 3589 3590 if (p_type == PP_PM_POLICY_NONE) 3591 return -EINVAL; 3592 3593 dpm_policy = smu_get_pm_policy(smu, p_type); 3594 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3595 return -ENOENT; 3596 3597 if (!sysbuf) 3598 return -EINVAL; 3599 3600 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3601 3602 return offset; 3603 } 3604 3605 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3606 enum pp_pm_policy p_type) 3607 { 3608 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3609 struct smu_dpm_policy_ctxt *policy_ctxt; 3610 int i; 3611 3612 policy_ctxt = dpm_ctxt->dpm_policies; 3613 if (!policy_ctxt) 3614 return NULL; 3615 3616 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3617 if (policy_ctxt->policies[i].policy_type == p_type) 3618 return &policy_ctxt->policies[i]; 3619 } 3620 3621 return NULL; 3622 } 3623 3624 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3625 int level) 3626 { 3627 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3628 struct smu_dpm_policy *dpm_policy = NULL; 3629 struct smu_dpm_policy_ctxt *policy_ctxt; 3630 int ret = -EOPNOTSUPP; 3631 3632 policy_ctxt = dpm_ctxt->dpm_policies; 3633 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3634 !policy_ctxt->policy_mask) 3635 return ret; 3636 3637 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3638 return -EINVAL; 3639 3640 dpm_policy = smu_get_pm_policy(smu, p_type); 3641 3642 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3643 return ret; 3644 3645 if (dpm_policy->current_level == level) 3646 return 0; 3647 3648 ret = dpm_policy->set_policy(smu, level); 3649 3650 if (!ret) 3651 dpm_policy->current_level = level; 3652 3653 return ret; 3654 } 3655 3656 static const struct amd_pm_funcs swsmu_pm_funcs = { 3657 /* export for sysfs */ 3658 .set_fan_control_mode = smu_set_fan_control_mode, 3659 .get_fan_control_mode = smu_get_fan_control_mode, 3660 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3661 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3662 .force_clock_level = smu_force_ppclk_levels, 3663 .print_clock_levels = smu_print_ppclk_levels, 3664 .emit_clock_levels = smu_emit_ppclk_levels, 3665 .force_performance_level = smu_force_performance_level, 3666 .read_sensor = smu_read_sensor, 3667 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3668 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3669 .get_performance_level = smu_get_performance_level, 3670 .get_current_power_state = smu_get_current_power_state, 3671 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3672 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3673 .get_pp_num_states = smu_get_power_num_states, 3674 .get_pp_table = smu_sys_get_pp_table, 3675 .set_pp_table = smu_sys_set_pp_table, 3676 .switch_power_profile = smu_switch_power_profile, 3677 /* export to amdgpu */ 3678 .dispatch_tasks = smu_handle_dpm_task, 3679 .load_firmware = smu_load_microcode, 3680 .set_powergating_by_smu = smu_dpm_set_power_gate, 3681 .set_power_limit = smu_set_power_limit, 3682 .get_power_limit = smu_get_power_limit, 3683 .get_power_profile_mode = smu_get_power_profile_mode, 3684 .set_power_profile_mode = smu_set_power_profile_mode, 3685 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3686 .set_mp1_state = smu_set_mp1_state, 3687 .gfx_state_change_set = smu_gfx_state_change_set, 3688 /* export to DC */ 3689 .get_sclk = smu_get_sclk, 3690 .get_mclk = smu_get_mclk, 3691 .display_configuration_change = smu_display_configuration_change, 3692 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3693 .display_clock_voltage_request = smu_display_clock_voltage_request, 3694 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3695 .set_active_display_count = smu_set_display_count, 3696 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3697 .get_asic_baco_capability = smu_get_baco_capability, 3698 .set_asic_baco_state = smu_baco_set_state, 3699 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3700 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3701 .asic_reset_mode_2 = smu_mode2_reset, 3702 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3703 .set_df_cstate = smu_set_df_cstate, 3704 .set_xgmi_pstate = smu_set_xgmi_pstate, 3705 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3706 .get_pm_metrics = smu_sys_get_pm_metrics, 3707 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3708 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3709 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3710 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3711 .get_dpm_clock_table = smu_get_dpm_clock_table, 3712 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3713 }; 3714 3715 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3716 uint64_t event_arg) 3717 { 3718 int ret = -EINVAL; 3719 3720 if (smu->ppt_funcs->wait_for_event) 3721 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3722 3723 return ret; 3724 } 3725 3726 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3727 { 3728 3729 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3730 return -EOPNOTSUPP; 3731 3732 /* Confirm the buffer allocated is of correct size */ 3733 if (size != smu->stb_context.stb_buf_size) 3734 return -EINVAL; 3735 3736 /* 3737 * No need to lock smu mutex as we access STB directly through MMIO 3738 * and not going through SMU messaging route (for now at least). 3739 * For registers access rely on implementation internal locking. 3740 */ 3741 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3742 } 3743 3744 #if defined(CONFIG_DEBUG_FS) 3745 3746 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3747 { 3748 struct amdgpu_device *adev = filp->f_inode->i_private; 3749 struct smu_context *smu = adev->powerplay.pp_handle; 3750 unsigned char *buf; 3751 int r; 3752 3753 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3754 if (!buf) 3755 return -ENOMEM; 3756 3757 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3758 if (r) 3759 goto out; 3760 3761 filp->private_data = buf; 3762 3763 return 0; 3764 3765 out: 3766 kvfree(buf); 3767 return r; 3768 } 3769 3770 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3771 loff_t *pos) 3772 { 3773 struct amdgpu_device *adev = filp->f_inode->i_private; 3774 struct smu_context *smu = adev->powerplay.pp_handle; 3775 3776 3777 if (!filp->private_data) 3778 return -EINVAL; 3779 3780 return simple_read_from_buffer(buf, 3781 size, 3782 pos, filp->private_data, 3783 smu->stb_context.stb_buf_size); 3784 } 3785 3786 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3787 { 3788 kvfree(filp->private_data); 3789 filp->private_data = NULL; 3790 3791 return 0; 3792 } 3793 3794 /* 3795 * We have to define not only read method but also 3796 * open and release because .read takes up to PAGE_SIZE 3797 * data each time so and so is invoked multiple times. 3798 * We allocate the STB buffer in .open and release it 3799 * in .release 3800 */ 3801 static const struct file_operations smu_stb_debugfs_fops = { 3802 .owner = THIS_MODULE, 3803 .open = smu_stb_debugfs_open, 3804 .read = smu_stb_debugfs_read, 3805 .release = smu_stb_debugfs_release, 3806 .llseek = default_llseek, 3807 }; 3808 3809 #endif 3810 3811 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3812 { 3813 #if defined(CONFIG_DEBUG_FS) 3814 3815 struct smu_context *smu = adev->powerplay.pp_handle; 3816 3817 if (!smu || (!smu->stb_context.stb_buf_size)) 3818 return; 3819 3820 debugfs_create_file_size("amdgpu_smu_stb_dump", 3821 S_IRUSR, 3822 adev_to_drm(adev)->primary->debugfs_root, 3823 adev, 3824 &smu_stb_debugfs_fops, 3825 smu->stb_context.stb_buf_size); 3826 #endif 3827 } 3828 3829 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3830 { 3831 int ret = 0; 3832 3833 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3834 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3835 3836 return ret; 3837 } 3838 3839 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3840 { 3841 int ret = 0; 3842 3843 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3844 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3845 3846 return ret; 3847 } 3848 3849 int smu_send_rma_reason(struct smu_context *smu) 3850 { 3851 int ret = 0; 3852 3853 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3854 ret = smu->ppt_funcs->send_rma_reason(smu); 3855 3856 return ret; 3857 } 3858