1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "amd_pcie.h" 40 41 /* 42 * DO NOT use these for err/warn/info/debug messages. 43 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 44 * They are more MGPU friendly. 45 */ 46 #undef pr_err 47 #undef pr_warn 48 #undef pr_info 49 #undef pr_debug 50 51 static const struct amd_pm_funcs swsmu_pm_funcs; 52 static int smu_force_smuclk_levels(struct smu_context *smu, 53 enum smu_clk_type clk_type, 54 uint32_t mask); 55 static int smu_handle_task(struct smu_context *smu, 56 enum amd_dpm_forced_level level, 57 enum amd_pp_task task_id, 58 bool lock_needed); 59 static int smu_reset(struct smu_context *smu); 60 static int smu_set_fan_speed_percent(void *handle, u32 speed); 61 static int smu_set_fan_control_mode(struct smu_context *smu, int value); 62 static int smu_set_power_limit(void *handle, uint32_t limit); 63 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 64 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 65 66 static int smu_sys_get_pp_feature_mask(void *handle, 67 char *buf) 68 { 69 struct smu_context *smu = handle; 70 int size = 0; 71 72 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 73 return -EOPNOTSUPP; 74 75 mutex_lock(&smu->mutex); 76 77 size = smu_get_pp_feature_mask(smu, buf); 78 79 mutex_unlock(&smu->mutex); 80 81 return size; 82 } 83 84 static int smu_sys_set_pp_feature_mask(void *handle, 85 uint64_t new_mask) 86 { 87 struct smu_context *smu = handle; 88 int ret = 0; 89 90 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 91 return -EOPNOTSUPP; 92 93 mutex_lock(&smu->mutex); 94 95 ret = smu_set_pp_feature_mask(smu, new_mask); 96 97 mutex_unlock(&smu->mutex); 98 99 return ret; 100 } 101 102 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 103 { 104 int ret = 0; 105 struct smu_context *smu = &adev->smu; 106 107 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status) 108 *value = smu_get_gfx_off_status(smu); 109 else 110 ret = -EINVAL; 111 112 return ret; 113 } 114 115 int smu_set_soft_freq_range(struct smu_context *smu, 116 enum smu_clk_type clk_type, 117 uint32_t min, 118 uint32_t max) 119 { 120 int ret = 0; 121 122 mutex_lock(&smu->mutex); 123 124 if (smu->ppt_funcs->set_soft_freq_limited_range) 125 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 126 clk_type, 127 min, 128 max); 129 130 mutex_unlock(&smu->mutex); 131 132 return ret; 133 } 134 135 int smu_get_dpm_freq_range(struct smu_context *smu, 136 enum smu_clk_type clk_type, 137 uint32_t *min, 138 uint32_t *max) 139 { 140 int ret = 0; 141 142 if (!min && !max) 143 return -EINVAL; 144 145 mutex_lock(&smu->mutex); 146 147 if (smu->ppt_funcs->get_dpm_ultimate_freq) 148 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 149 clk_type, 150 min, 151 max); 152 153 mutex_unlock(&smu->mutex); 154 155 return ret; 156 } 157 158 static u32 smu_get_mclk(void *handle, bool low) 159 { 160 struct smu_context *smu = handle; 161 uint32_t clk_freq; 162 int ret = 0; 163 164 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 165 low ? &clk_freq : NULL, 166 !low ? &clk_freq : NULL); 167 if (ret) 168 return 0; 169 return clk_freq * 100; 170 } 171 172 static u32 smu_get_sclk(void *handle, bool low) 173 { 174 struct smu_context *smu = handle; 175 uint32_t clk_freq; 176 int ret = 0; 177 178 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 179 low ? &clk_freq : NULL, 180 !low ? &clk_freq : NULL); 181 if (ret) 182 return 0; 183 return clk_freq * 100; 184 } 185 186 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, 187 bool enable) 188 { 189 struct smu_power_context *smu_power = &smu->smu_power; 190 struct smu_power_gate *power_gate = &smu_power->power_gate; 191 int ret = 0; 192 193 if (!smu->ppt_funcs->dpm_set_vcn_enable) 194 return 0; 195 196 if (atomic_read(&power_gate->vcn_gated) ^ enable) 197 return 0; 198 199 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 200 if (!ret) 201 atomic_set(&power_gate->vcn_gated, !enable); 202 203 return ret; 204 } 205 206 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 207 bool enable) 208 { 209 struct smu_power_context *smu_power = &smu->smu_power; 210 struct smu_power_gate *power_gate = &smu_power->power_gate; 211 int ret = 0; 212 213 mutex_lock(&power_gate->vcn_gate_lock); 214 215 ret = smu_dpm_set_vcn_enable_locked(smu, enable); 216 217 mutex_unlock(&power_gate->vcn_gate_lock); 218 219 return ret; 220 } 221 222 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu, 223 bool enable) 224 { 225 struct smu_power_context *smu_power = &smu->smu_power; 226 struct smu_power_gate *power_gate = &smu_power->power_gate; 227 int ret = 0; 228 229 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 230 return 0; 231 232 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 233 return 0; 234 235 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 236 if (!ret) 237 atomic_set(&power_gate->jpeg_gated, !enable); 238 239 return ret; 240 } 241 242 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 243 bool enable) 244 { 245 struct smu_power_context *smu_power = &smu->smu_power; 246 struct smu_power_gate *power_gate = &smu_power->power_gate; 247 int ret = 0; 248 249 mutex_lock(&power_gate->jpeg_gate_lock); 250 251 ret = smu_dpm_set_jpeg_enable_locked(smu, enable); 252 253 mutex_unlock(&power_gate->jpeg_gate_lock); 254 255 return ret; 256 } 257 258 /** 259 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 260 * 261 * @handle: smu_context pointer 262 * @block_type: the IP block to power gate/ungate 263 * @gate: to power gate if true, ungate otherwise 264 * 265 * This API uses no smu->mutex lock protection due to: 266 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 267 * This is guarded to be race condition free by the caller. 268 * 2. Or get called on user setting request of power_dpm_force_performance_level. 269 * Under this case, the smu->mutex lock protection is already enforced on 270 * the parent API smu_force_performance_level of the call path. 271 */ 272 static int smu_dpm_set_power_gate(void *handle, 273 uint32_t block_type, 274 bool gate) 275 { 276 struct smu_context *smu = handle; 277 int ret = 0; 278 279 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 280 return -EOPNOTSUPP; 281 282 switch (block_type) { 283 /* 284 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 285 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 286 */ 287 case AMD_IP_BLOCK_TYPE_UVD: 288 case AMD_IP_BLOCK_TYPE_VCN: 289 ret = smu_dpm_set_vcn_enable(smu, !gate); 290 if (ret) 291 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 292 gate ? "gate" : "ungate"); 293 break; 294 case AMD_IP_BLOCK_TYPE_GFX: 295 ret = smu_gfx_off_control(smu, gate); 296 if (ret) 297 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 298 gate ? "enable" : "disable"); 299 break; 300 case AMD_IP_BLOCK_TYPE_SDMA: 301 ret = smu_powergate_sdma(smu, gate); 302 if (ret) 303 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 304 gate ? "gate" : "ungate"); 305 break; 306 case AMD_IP_BLOCK_TYPE_JPEG: 307 ret = smu_dpm_set_jpeg_enable(smu, !gate); 308 if (ret) 309 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 310 gate ? "gate" : "ungate"); 311 break; 312 default: 313 dev_err(smu->adev->dev, "Unsupported block type!\n"); 314 return -EINVAL; 315 } 316 317 return ret; 318 } 319 320 /** 321 * smu_set_user_clk_dependencies - set user profile clock dependencies 322 * 323 * @smu: smu_context pointer 324 * @clk: enum smu_clk_type type 325 * 326 * Enable/Disable the clock dependency for the @clk type. 327 */ 328 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 329 { 330 if (smu->adev->in_suspend) 331 return; 332 333 if (clk == SMU_MCLK) { 334 smu->user_dpm_profile.clk_dependency = 0; 335 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 336 } else if (clk == SMU_FCLK) { 337 /* MCLK takes precedence over FCLK */ 338 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 339 return; 340 341 smu->user_dpm_profile.clk_dependency = 0; 342 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 343 } else if (clk == SMU_SOCCLK) { 344 /* MCLK takes precedence over SOCCLK */ 345 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 346 return; 347 348 smu->user_dpm_profile.clk_dependency = 0; 349 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 350 } else 351 /* Add clk dependencies here, if any */ 352 return; 353 } 354 355 /** 356 * smu_restore_dpm_user_profile - reinstate user dpm profile 357 * 358 * @smu: smu_context pointer 359 * 360 * Restore the saved user power configurations include power limit, 361 * clock frequencies, fan control mode and fan speed. 362 */ 363 static void smu_restore_dpm_user_profile(struct smu_context *smu) 364 { 365 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 366 int ret = 0; 367 368 if (!smu->adev->in_suspend) 369 return; 370 371 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 372 return; 373 374 /* Enable restore flag */ 375 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 376 377 /* set the user dpm power limit */ 378 if (smu->user_dpm_profile.power_limit) { 379 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 380 if (ret) 381 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 382 } 383 384 /* set the user dpm clock configurations */ 385 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 386 enum smu_clk_type clk_type; 387 388 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 389 /* 390 * Iterate over smu clk type and force the saved user clk 391 * configs, skip if clock dependency is enabled 392 */ 393 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 394 smu->user_dpm_profile.clk_mask[clk_type]) { 395 ret = smu_force_smuclk_levels(smu, clk_type, 396 smu->user_dpm_profile.clk_mask[clk_type]); 397 if (ret) 398 dev_err(smu->adev->dev, 399 "Failed to set clock type = %d\n", clk_type); 400 } 401 } 402 } 403 404 /* set the user dpm fan configurations */ 405 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL) { 406 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 407 if (ret) { 408 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 409 return; 410 } 411 412 if (!ret && smu->user_dpm_profile.fan_speed_percent) { 413 ret = smu_set_fan_speed_percent(smu, smu->user_dpm_profile.fan_speed_percent); 414 if (ret) 415 dev_err(smu->adev->dev, "Failed to set manual fan speed\n"); 416 } 417 } 418 419 /* Disable restore flag */ 420 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 421 } 422 423 static int smu_get_power_num_states(void *handle, 424 struct pp_states_info *state_info) 425 { 426 if (!state_info) 427 return -EINVAL; 428 429 /* not support power state */ 430 memset(state_info, 0, sizeof(struct pp_states_info)); 431 state_info->nums = 1; 432 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 433 434 return 0; 435 } 436 437 bool is_support_sw_smu(struct amdgpu_device *adev) 438 { 439 if (adev->asic_type >= CHIP_ARCTURUS) 440 return true; 441 442 return false; 443 } 444 445 bool is_support_cclk_dpm(struct amdgpu_device *adev) 446 { 447 struct smu_context *smu = &adev->smu; 448 449 if (!is_support_sw_smu(adev)) 450 return false; 451 452 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 453 return false; 454 455 return true; 456 } 457 458 459 static int smu_sys_get_pp_table(void *handle, 460 char **table) 461 { 462 struct smu_context *smu = handle; 463 struct smu_table_context *smu_table = &smu->smu_table; 464 uint32_t powerplay_table_size; 465 466 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 467 return -EOPNOTSUPP; 468 469 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 470 return -EINVAL; 471 472 mutex_lock(&smu->mutex); 473 474 if (smu_table->hardcode_pptable) 475 *table = smu_table->hardcode_pptable; 476 else 477 *table = smu_table->power_play_table; 478 479 powerplay_table_size = smu_table->power_play_table_size; 480 481 mutex_unlock(&smu->mutex); 482 483 return powerplay_table_size; 484 } 485 486 static int smu_sys_set_pp_table(void *handle, 487 const char *buf, 488 size_t size) 489 { 490 struct smu_context *smu = handle; 491 struct smu_table_context *smu_table = &smu->smu_table; 492 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 493 int ret = 0; 494 495 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 496 return -EOPNOTSUPP; 497 498 if (header->usStructureSize != size) { 499 dev_err(smu->adev->dev, "pp table size not matched !\n"); 500 return -EIO; 501 } 502 503 mutex_lock(&smu->mutex); 504 if (!smu_table->hardcode_pptable) 505 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 506 if (!smu_table->hardcode_pptable) { 507 ret = -ENOMEM; 508 goto failed; 509 } 510 511 memcpy(smu_table->hardcode_pptable, buf, size); 512 smu_table->power_play_table = smu_table->hardcode_pptable; 513 smu_table->power_play_table_size = size; 514 515 /* 516 * Special hw_fini action(for Navi1x, the DPMs disablement will be 517 * skipped) may be needed for custom pptable uploading. 518 */ 519 smu->uploading_custom_pp_table = true; 520 521 ret = smu_reset(smu); 522 if (ret) 523 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 524 525 smu->uploading_custom_pp_table = false; 526 527 failed: 528 mutex_unlock(&smu->mutex); 529 return ret; 530 } 531 532 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 533 { 534 struct smu_feature *feature = &smu->smu_feature; 535 int ret = 0; 536 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 537 538 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 539 540 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 541 SMU_FEATURE_MAX/32); 542 if (ret) 543 return ret; 544 545 bitmap_or(feature->allowed, feature->allowed, 546 (unsigned long *)allowed_feature_mask, 547 feature->feature_num); 548 549 return ret; 550 } 551 552 static int smu_set_funcs(struct amdgpu_device *adev) 553 { 554 struct smu_context *smu = &adev->smu; 555 556 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 557 smu->od_enabled = true; 558 559 switch (adev->asic_type) { 560 case CHIP_NAVI10: 561 case CHIP_NAVI14: 562 case CHIP_NAVI12: 563 navi10_set_ppt_funcs(smu); 564 break; 565 case CHIP_ARCTURUS: 566 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 567 arcturus_set_ppt_funcs(smu); 568 /* OD is not supported on Arcturus */ 569 smu->od_enabled =false; 570 break; 571 case CHIP_SIENNA_CICHLID: 572 case CHIP_NAVY_FLOUNDER: 573 case CHIP_DIMGREY_CAVEFISH: 574 case CHIP_BEIGE_GOBY: 575 sienna_cichlid_set_ppt_funcs(smu); 576 break; 577 case CHIP_ALDEBARAN: 578 aldebaran_set_ppt_funcs(smu); 579 /* Enable pp_od_clk_voltage node */ 580 smu->od_enabled = true; 581 break; 582 case CHIP_RENOIR: 583 renoir_set_ppt_funcs(smu); 584 break; 585 case CHIP_VANGOGH: 586 vangogh_set_ppt_funcs(smu); 587 break; 588 case CHIP_YELLOW_CARP: 589 yellow_carp_set_ppt_funcs(smu); 590 break; 591 default: 592 return -EINVAL; 593 } 594 595 return 0; 596 } 597 598 static int smu_early_init(void *handle) 599 { 600 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 601 struct smu_context *smu = &adev->smu; 602 603 smu->adev = adev; 604 smu->pm_enabled = !!amdgpu_dpm; 605 smu->is_apu = false; 606 mutex_init(&smu->mutex); 607 mutex_init(&smu->smu_baco.mutex); 608 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 609 smu->smu_baco.platform_support = false; 610 611 adev->powerplay.pp_handle = smu; 612 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 613 614 return smu_set_funcs(adev); 615 } 616 617 static int smu_set_default_dpm_table(struct smu_context *smu) 618 { 619 struct smu_power_context *smu_power = &smu->smu_power; 620 struct smu_power_gate *power_gate = &smu_power->power_gate; 621 int vcn_gate, jpeg_gate; 622 int ret = 0; 623 624 if (!smu->ppt_funcs->set_default_dpm_table) 625 return 0; 626 627 mutex_lock(&power_gate->vcn_gate_lock); 628 mutex_lock(&power_gate->jpeg_gate_lock); 629 630 vcn_gate = atomic_read(&power_gate->vcn_gated); 631 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 632 633 ret = smu_dpm_set_vcn_enable_locked(smu, true); 634 if (ret) 635 goto err0_out; 636 637 ret = smu_dpm_set_jpeg_enable_locked(smu, true); 638 if (ret) 639 goto err1_out; 640 641 ret = smu->ppt_funcs->set_default_dpm_table(smu); 642 if (ret) 643 dev_err(smu->adev->dev, 644 "Failed to setup default dpm clock tables!\n"); 645 646 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate); 647 err1_out: 648 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate); 649 err0_out: 650 mutex_unlock(&power_gate->jpeg_gate_lock); 651 mutex_unlock(&power_gate->vcn_gate_lock); 652 653 return ret; 654 } 655 656 657 static int smu_late_init(void *handle) 658 { 659 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 660 struct smu_context *smu = &adev->smu; 661 int ret = 0; 662 663 smu_set_fine_grain_gfx_freq_parameters(smu); 664 665 if (!smu->pm_enabled) 666 return 0; 667 668 ret = smu_post_init(smu); 669 if (ret) { 670 dev_err(adev->dev, "Failed to post smu init!\n"); 671 return ret; 672 } 673 674 if (adev->asic_type == CHIP_YELLOW_CARP) 675 return 0; 676 677 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 678 ret = smu_set_default_od_settings(smu); 679 if (ret) { 680 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 681 return ret; 682 } 683 } 684 685 ret = smu_populate_umd_state_clk(smu); 686 if (ret) { 687 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 688 return ret; 689 } 690 691 ret = smu_get_asic_power_limits(smu); 692 if (ret) { 693 dev_err(adev->dev, "Failed to get asic power limits!\n"); 694 return ret; 695 } 696 697 if (!amdgpu_sriov_vf(adev)) 698 smu_get_unique_id(smu); 699 700 smu_get_fan_parameters(smu); 701 702 smu_handle_task(&adev->smu, 703 smu->smu_dpm.dpm_level, 704 AMD_PP_TASK_COMPLETE_INIT, 705 false); 706 707 smu_restore_dpm_user_profile(smu); 708 709 return 0; 710 } 711 712 static int smu_init_fb_allocations(struct smu_context *smu) 713 { 714 struct amdgpu_device *adev = smu->adev; 715 struct smu_table_context *smu_table = &smu->smu_table; 716 struct smu_table *tables = smu_table->tables; 717 struct smu_table *driver_table = &(smu_table->driver_table); 718 uint32_t max_table_size = 0; 719 int ret, i; 720 721 /* VRAM allocation for tool table */ 722 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 723 ret = amdgpu_bo_create_kernel(adev, 724 tables[SMU_TABLE_PMSTATUSLOG].size, 725 tables[SMU_TABLE_PMSTATUSLOG].align, 726 tables[SMU_TABLE_PMSTATUSLOG].domain, 727 &tables[SMU_TABLE_PMSTATUSLOG].bo, 728 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 729 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 730 if (ret) { 731 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 732 return ret; 733 } 734 } 735 736 /* VRAM allocation for driver table */ 737 for (i = 0; i < SMU_TABLE_COUNT; i++) { 738 if (tables[i].size == 0) 739 continue; 740 741 if (i == SMU_TABLE_PMSTATUSLOG) 742 continue; 743 744 if (max_table_size < tables[i].size) 745 max_table_size = tables[i].size; 746 } 747 748 driver_table->size = max_table_size; 749 driver_table->align = PAGE_SIZE; 750 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 751 752 ret = amdgpu_bo_create_kernel(adev, 753 driver_table->size, 754 driver_table->align, 755 driver_table->domain, 756 &driver_table->bo, 757 &driver_table->mc_address, 758 &driver_table->cpu_addr); 759 if (ret) { 760 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 761 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 762 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 763 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 764 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 765 } 766 767 return ret; 768 } 769 770 static int smu_fini_fb_allocations(struct smu_context *smu) 771 { 772 struct smu_table_context *smu_table = &smu->smu_table; 773 struct smu_table *tables = smu_table->tables; 774 struct smu_table *driver_table = &(smu_table->driver_table); 775 776 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 777 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 778 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 779 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 780 781 amdgpu_bo_free_kernel(&driver_table->bo, 782 &driver_table->mc_address, 783 &driver_table->cpu_addr); 784 785 return 0; 786 } 787 788 /** 789 * smu_alloc_memory_pool - allocate memory pool in the system memory 790 * 791 * @smu: amdgpu_device pointer 792 * 793 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 794 * and DramLogSetDramAddr can notify it changed. 795 * 796 * Returns 0 on success, error on failure. 797 */ 798 static int smu_alloc_memory_pool(struct smu_context *smu) 799 { 800 struct amdgpu_device *adev = smu->adev; 801 struct smu_table_context *smu_table = &smu->smu_table; 802 struct smu_table *memory_pool = &smu_table->memory_pool; 803 uint64_t pool_size = smu->pool_size; 804 int ret = 0; 805 806 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 807 return ret; 808 809 memory_pool->size = pool_size; 810 memory_pool->align = PAGE_SIZE; 811 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 812 813 switch (pool_size) { 814 case SMU_MEMORY_POOL_SIZE_256_MB: 815 case SMU_MEMORY_POOL_SIZE_512_MB: 816 case SMU_MEMORY_POOL_SIZE_1_GB: 817 case SMU_MEMORY_POOL_SIZE_2_GB: 818 ret = amdgpu_bo_create_kernel(adev, 819 memory_pool->size, 820 memory_pool->align, 821 memory_pool->domain, 822 &memory_pool->bo, 823 &memory_pool->mc_address, 824 &memory_pool->cpu_addr); 825 if (ret) 826 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 827 break; 828 default: 829 break; 830 } 831 832 return ret; 833 } 834 835 static int smu_free_memory_pool(struct smu_context *smu) 836 { 837 struct smu_table_context *smu_table = &smu->smu_table; 838 struct smu_table *memory_pool = &smu_table->memory_pool; 839 840 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 841 return 0; 842 843 amdgpu_bo_free_kernel(&memory_pool->bo, 844 &memory_pool->mc_address, 845 &memory_pool->cpu_addr); 846 847 memset(memory_pool, 0, sizeof(struct smu_table)); 848 849 return 0; 850 } 851 852 static int smu_alloc_dummy_read_table(struct smu_context *smu) 853 { 854 struct smu_table_context *smu_table = &smu->smu_table; 855 struct smu_table *dummy_read_1_table = 856 &smu_table->dummy_read_1_table; 857 struct amdgpu_device *adev = smu->adev; 858 int ret = 0; 859 860 dummy_read_1_table->size = 0x40000; 861 dummy_read_1_table->align = PAGE_SIZE; 862 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 863 864 ret = amdgpu_bo_create_kernel(adev, 865 dummy_read_1_table->size, 866 dummy_read_1_table->align, 867 dummy_read_1_table->domain, 868 &dummy_read_1_table->bo, 869 &dummy_read_1_table->mc_address, 870 &dummy_read_1_table->cpu_addr); 871 if (ret) 872 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 873 874 return ret; 875 } 876 877 static void smu_free_dummy_read_table(struct smu_context *smu) 878 { 879 struct smu_table_context *smu_table = &smu->smu_table; 880 struct smu_table *dummy_read_1_table = 881 &smu_table->dummy_read_1_table; 882 883 884 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 885 &dummy_read_1_table->mc_address, 886 &dummy_read_1_table->cpu_addr); 887 888 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 889 } 890 891 static int smu_smc_table_sw_init(struct smu_context *smu) 892 { 893 int ret; 894 895 /** 896 * Create smu_table structure, and init smc tables such as 897 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 898 */ 899 ret = smu_init_smc_tables(smu); 900 if (ret) { 901 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 902 return ret; 903 } 904 905 /** 906 * Create smu_power_context structure, and allocate smu_dpm_context and 907 * context size to fill the smu_power_context data. 908 */ 909 ret = smu_init_power(smu); 910 if (ret) { 911 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 912 return ret; 913 } 914 915 /* 916 * allocate vram bos to store smc table contents. 917 */ 918 ret = smu_init_fb_allocations(smu); 919 if (ret) 920 return ret; 921 922 ret = smu_alloc_memory_pool(smu); 923 if (ret) 924 return ret; 925 926 ret = smu_alloc_dummy_read_table(smu); 927 if (ret) 928 return ret; 929 930 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 931 if (ret) 932 return ret; 933 934 return 0; 935 } 936 937 static int smu_smc_table_sw_fini(struct smu_context *smu) 938 { 939 int ret; 940 941 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 942 943 smu_free_dummy_read_table(smu); 944 945 ret = smu_free_memory_pool(smu); 946 if (ret) 947 return ret; 948 949 ret = smu_fini_fb_allocations(smu); 950 if (ret) 951 return ret; 952 953 ret = smu_fini_power(smu); 954 if (ret) { 955 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 956 return ret; 957 } 958 959 ret = smu_fini_smc_tables(smu); 960 if (ret) { 961 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 962 return ret; 963 } 964 965 return 0; 966 } 967 968 static void smu_throttling_logging_work_fn(struct work_struct *work) 969 { 970 struct smu_context *smu = container_of(work, struct smu_context, 971 throttling_logging_work); 972 973 smu_log_thermal_throttling(smu); 974 } 975 976 static void smu_interrupt_work_fn(struct work_struct *work) 977 { 978 struct smu_context *smu = container_of(work, struct smu_context, 979 interrupt_work); 980 981 mutex_lock(&smu->mutex); 982 983 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 984 smu->ppt_funcs->interrupt_work(smu); 985 986 mutex_unlock(&smu->mutex); 987 } 988 989 static int smu_sw_init(void *handle) 990 { 991 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 992 struct smu_context *smu = &adev->smu; 993 int ret; 994 995 smu->pool_size = adev->pm.smu_prv_buffer_size; 996 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 997 mutex_init(&smu->smu_feature.mutex); 998 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 999 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 1000 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1001 1002 mutex_init(&smu->sensor_lock); 1003 mutex_init(&smu->metrics_lock); 1004 mutex_init(&smu->message_lock); 1005 1006 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1007 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1008 atomic64_set(&smu->throttle_int_counter, 0); 1009 smu->watermarks_bitmap = 0; 1010 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1011 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1012 1013 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1014 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1015 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock); 1016 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock); 1017 1018 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1019 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1020 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1021 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1022 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1023 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1024 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1025 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1026 1027 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1028 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1029 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1030 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1031 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1032 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1033 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1034 smu->display_config = &adev->pm.pm_display_cfg; 1035 1036 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1037 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1038 1039 ret = smu_init_microcode(smu); 1040 if (ret) { 1041 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1042 return ret; 1043 } 1044 1045 ret = smu_smc_table_sw_init(smu); 1046 if (ret) { 1047 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1048 return ret; 1049 } 1050 1051 ret = smu_register_irq_handler(smu); 1052 if (ret) { 1053 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1054 return ret; 1055 } 1056 1057 /* If there is no way to query fan control mode, fan control is not supported */ 1058 if (!smu->ppt_funcs->get_fan_control_mode) 1059 smu->adev->pm.no_fan = true; 1060 1061 return 0; 1062 } 1063 1064 static int smu_sw_fini(void *handle) 1065 { 1066 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1067 struct smu_context *smu = &adev->smu; 1068 int ret; 1069 1070 ret = smu_smc_table_sw_fini(smu); 1071 if (ret) { 1072 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1073 return ret; 1074 } 1075 1076 smu_fini_microcode(smu); 1077 1078 return 0; 1079 } 1080 1081 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1082 { 1083 struct amdgpu_device *adev = smu->adev; 1084 struct smu_temperature_range *range = 1085 &smu->thermal_range; 1086 int ret = 0; 1087 1088 if (!smu->ppt_funcs->get_thermal_temperature_range) 1089 return 0; 1090 1091 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1092 if (ret) 1093 return ret; 1094 1095 adev->pm.dpm.thermal.min_temp = range->min; 1096 adev->pm.dpm.thermal.max_temp = range->max; 1097 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1098 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1099 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1100 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1101 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1102 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1103 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1104 1105 return ret; 1106 } 1107 1108 static int smu_smc_hw_setup(struct smu_context *smu) 1109 { 1110 struct amdgpu_device *adev = smu->adev; 1111 uint32_t pcie_gen = 0, pcie_width = 0; 1112 int ret = 0; 1113 1114 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1115 dev_info(adev->dev, "dpm has been enabled\n"); 1116 /* this is needed specifically */ 1117 if ((adev->asic_type >= CHIP_SIENNA_CICHLID) && 1118 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 1119 ret = smu_system_features_control(smu, true); 1120 return ret; 1121 } 1122 1123 ret = smu_init_display_count(smu, 0); 1124 if (ret) { 1125 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1126 return ret; 1127 } 1128 1129 ret = smu_set_driver_table_location(smu); 1130 if (ret) { 1131 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1132 return ret; 1133 } 1134 1135 /* 1136 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1137 */ 1138 ret = smu_set_tool_table_location(smu); 1139 if (ret) { 1140 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1141 return ret; 1142 } 1143 1144 /* 1145 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1146 * pool location. 1147 */ 1148 ret = smu_notify_memory_pool_location(smu); 1149 if (ret) { 1150 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1151 return ret; 1152 } 1153 1154 /* smu_dump_pptable(smu); */ 1155 /* 1156 * Copy pptable bo in the vram to smc with SMU MSGs such as 1157 * SetDriverDramAddr and TransferTableDram2Smu. 1158 */ 1159 ret = smu_write_pptable(smu); 1160 if (ret) { 1161 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1162 return ret; 1163 } 1164 1165 /* issue Run*Btc msg */ 1166 ret = smu_run_btc(smu); 1167 if (ret) 1168 return ret; 1169 1170 ret = smu_feature_set_allowed_mask(smu); 1171 if (ret) { 1172 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1173 return ret; 1174 } 1175 1176 ret = smu_system_features_control(smu, true); 1177 if (ret) { 1178 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1179 return ret; 1180 } 1181 1182 if (!smu_is_dpm_running(smu)) 1183 dev_info(adev->dev, "dpm has been disabled\n"); 1184 1185 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1186 pcie_gen = 3; 1187 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1188 pcie_gen = 2; 1189 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1190 pcie_gen = 1; 1191 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1192 pcie_gen = 0; 1193 1194 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1195 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1196 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1197 */ 1198 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1199 pcie_width = 6; 1200 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1201 pcie_width = 5; 1202 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1203 pcie_width = 4; 1204 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1205 pcie_width = 3; 1206 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1207 pcie_width = 2; 1208 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1209 pcie_width = 1; 1210 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1211 if (ret) { 1212 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1213 return ret; 1214 } 1215 1216 ret = smu_get_thermal_temperature_range(smu); 1217 if (ret) { 1218 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1219 return ret; 1220 } 1221 1222 ret = smu_enable_thermal_alert(smu); 1223 if (ret) { 1224 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1225 return ret; 1226 } 1227 1228 /* 1229 * Set initialized values (get from vbios) to dpm tables context such as 1230 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1231 * type of clks. 1232 */ 1233 ret = smu_set_default_dpm_table(smu); 1234 if (ret) { 1235 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1236 return ret; 1237 } 1238 1239 ret = smu_notify_display_change(smu); 1240 if (ret) 1241 return ret; 1242 1243 /* 1244 * Set min deep sleep dce fclk with bootup value from vbios via 1245 * SetMinDeepSleepDcefclk MSG. 1246 */ 1247 ret = smu_set_min_dcef_deep_sleep(smu, 1248 smu->smu_table.boot_values.dcefclk / 100); 1249 if (ret) 1250 return ret; 1251 1252 return ret; 1253 } 1254 1255 static int smu_start_smc_engine(struct smu_context *smu) 1256 { 1257 struct amdgpu_device *adev = smu->adev; 1258 int ret = 0; 1259 1260 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1261 if (adev->asic_type < CHIP_NAVI10) { 1262 if (smu->ppt_funcs->load_microcode) { 1263 ret = smu->ppt_funcs->load_microcode(smu); 1264 if (ret) 1265 return ret; 1266 } 1267 } 1268 } 1269 1270 if (smu->ppt_funcs->check_fw_status) { 1271 ret = smu->ppt_funcs->check_fw_status(smu); 1272 if (ret) { 1273 dev_err(adev->dev, "SMC is not ready\n"); 1274 return ret; 1275 } 1276 } 1277 1278 /* 1279 * Send msg GetDriverIfVersion to check if the return value is equal 1280 * with DRIVER_IF_VERSION of smc header. 1281 */ 1282 ret = smu_check_fw_version(smu); 1283 if (ret) 1284 return ret; 1285 1286 return ret; 1287 } 1288 1289 static int smu_hw_init(void *handle) 1290 { 1291 int ret; 1292 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1293 struct smu_context *smu = &adev->smu; 1294 1295 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1296 smu->pm_enabled = false; 1297 return 0; 1298 } 1299 1300 ret = smu_start_smc_engine(smu); 1301 if (ret) { 1302 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1303 return ret; 1304 } 1305 1306 if (smu->is_apu) { 1307 smu_powergate_sdma(&adev->smu, false); 1308 smu_dpm_set_vcn_enable(smu, true); 1309 smu_dpm_set_jpeg_enable(smu, true); 1310 smu_set_gfx_cgpg(&adev->smu, true); 1311 } 1312 1313 if (!smu->pm_enabled) 1314 return 0; 1315 1316 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1317 ret = smu_get_vbios_bootup_values(smu); 1318 if (ret) { 1319 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1320 return ret; 1321 } 1322 1323 ret = smu_setup_pptable(smu); 1324 if (ret) { 1325 dev_err(adev->dev, "Failed to setup pptable!\n"); 1326 return ret; 1327 } 1328 1329 ret = smu_get_driver_allowed_feature_mask(smu); 1330 if (ret) 1331 return ret; 1332 1333 ret = smu_smc_hw_setup(smu); 1334 if (ret) { 1335 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1336 return ret; 1337 } 1338 1339 /* 1340 * Move maximum sustainable clock retrieving here considering 1341 * 1. It is not needed on resume(from S3). 1342 * 2. DAL settings come between .hw_init and .late_init of SMU. 1343 * And DAL needs to know the maximum sustainable clocks. Thus 1344 * it cannot be put in .late_init(). 1345 */ 1346 ret = smu_init_max_sustainable_clocks(smu); 1347 if (ret) { 1348 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1349 return ret; 1350 } 1351 1352 adev->pm.dpm_enabled = true; 1353 1354 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1355 1356 return 0; 1357 } 1358 1359 static int smu_disable_dpms(struct smu_context *smu) 1360 { 1361 struct amdgpu_device *adev = smu->adev; 1362 int ret = 0; 1363 bool use_baco = !smu->is_apu && 1364 ((amdgpu_in_reset(adev) && 1365 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1366 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1367 1368 /* 1369 * For custom pptable uploading, skip the DPM features 1370 * disable process on Navi1x ASICs. 1371 * - As the gfx related features are under control of 1372 * RLC on those ASICs. RLC reinitialization will be 1373 * needed to reenable them. That will cost much more 1374 * efforts. 1375 * 1376 * - SMU firmware can handle the DPM reenablement 1377 * properly. 1378 */ 1379 if (smu->uploading_custom_pp_table && 1380 (adev->asic_type >= CHIP_NAVI10) && 1381 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 1382 return 0; 1383 1384 /* 1385 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1386 * on BACO in. Driver involvement is unnecessary. 1387 */ 1388 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 1389 use_baco) 1390 return 0; 1391 1392 /* 1393 * For gpu reset, runpm and hibernation through BACO, 1394 * BACO feature has to be kept enabled. 1395 */ 1396 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1397 ret = smu_disable_all_features_with_exception(smu, 1398 SMU_FEATURE_BACO_BIT); 1399 if (ret) 1400 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1401 } else { 1402 ret = smu_system_features_control(smu, false); 1403 if (ret) 1404 dev_err(adev->dev, "Failed to disable smu features.\n"); 1405 } 1406 1407 if (adev->asic_type >= CHIP_NAVI10 && 1408 adev->gfx.rlc.funcs->stop) 1409 adev->gfx.rlc.funcs->stop(adev); 1410 1411 return ret; 1412 } 1413 1414 static int smu_smc_hw_cleanup(struct smu_context *smu) 1415 { 1416 struct amdgpu_device *adev = smu->adev; 1417 int ret = 0; 1418 1419 cancel_work_sync(&smu->throttling_logging_work); 1420 cancel_work_sync(&smu->interrupt_work); 1421 1422 ret = smu_disable_thermal_alert(smu); 1423 if (ret) { 1424 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1425 return ret; 1426 } 1427 1428 ret = smu_disable_dpms(smu); 1429 if (ret) { 1430 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1431 return ret; 1432 } 1433 1434 return 0; 1435 } 1436 1437 static int smu_hw_fini(void *handle) 1438 { 1439 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1440 struct smu_context *smu = &adev->smu; 1441 1442 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1443 return 0; 1444 1445 if (smu->is_apu) { 1446 smu_powergate_sdma(&adev->smu, true); 1447 smu_dpm_set_vcn_enable(smu, false); 1448 smu_dpm_set_jpeg_enable(smu, false); 1449 } 1450 1451 if (!smu->pm_enabled) 1452 return 0; 1453 1454 adev->pm.dpm_enabled = false; 1455 1456 return smu_smc_hw_cleanup(smu); 1457 } 1458 1459 static int smu_reset(struct smu_context *smu) 1460 { 1461 struct amdgpu_device *adev = smu->adev; 1462 int ret; 1463 1464 amdgpu_gfx_off_ctrl(smu->adev, false); 1465 1466 ret = smu_hw_fini(adev); 1467 if (ret) 1468 return ret; 1469 1470 ret = smu_hw_init(adev); 1471 if (ret) 1472 return ret; 1473 1474 ret = smu_late_init(adev); 1475 if (ret) 1476 return ret; 1477 1478 amdgpu_gfx_off_ctrl(smu->adev, true); 1479 1480 return 0; 1481 } 1482 1483 static int smu_suspend(void *handle) 1484 { 1485 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1486 struct smu_context *smu = &adev->smu; 1487 int ret; 1488 1489 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1490 return 0; 1491 1492 if (!smu->pm_enabled) 1493 return 0; 1494 1495 adev->pm.dpm_enabled = false; 1496 1497 ret = smu_smc_hw_cleanup(smu); 1498 if (ret) 1499 return ret; 1500 1501 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1502 1503 /* skip CGPG when in S0ix */ 1504 if (smu->is_apu && !adev->in_s0ix) 1505 smu_set_gfx_cgpg(&adev->smu, false); 1506 1507 return 0; 1508 } 1509 1510 static int smu_resume(void *handle) 1511 { 1512 int ret; 1513 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1514 struct smu_context *smu = &adev->smu; 1515 1516 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1517 return 0; 1518 1519 if (!smu->pm_enabled) 1520 return 0; 1521 1522 dev_info(adev->dev, "SMU is resuming...\n"); 1523 1524 ret = smu_start_smc_engine(smu); 1525 if (ret) { 1526 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1527 return ret; 1528 } 1529 1530 ret = smu_smc_hw_setup(smu); 1531 if (ret) { 1532 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1533 return ret; 1534 } 1535 1536 if (smu->is_apu) 1537 smu_set_gfx_cgpg(&adev->smu, true); 1538 1539 smu->disable_uclk_switch = 0; 1540 1541 adev->pm.dpm_enabled = true; 1542 1543 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1544 1545 return 0; 1546 } 1547 1548 static int smu_display_configuration_change(void *handle, 1549 const struct amd_pp_display_configuration *display_config) 1550 { 1551 struct smu_context *smu = handle; 1552 int index = 0; 1553 int num_of_active_display = 0; 1554 1555 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1556 return -EOPNOTSUPP; 1557 1558 if (!display_config) 1559 return -EINVAL; 1560 1561 mutex_lock(&smu->mutex); 1562 1563 smu_set_min_dcef_deep_sleep(smu, 1564 display_config->min_dcef_deep_sleep_set_clk / 100); 1565 1566 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1567 if (display_config->displays[index].controller_id != 0) 1568 num_of_active_display++; 1569 } 1570 1571 mutex_unlock(&smu->mutex); 1572 1573 return 0; 1574 } 1575 1576 static int smu_set_clockgating_state(void *handle, 1577 enum amd_clockgating_state state) 1578 { 1579 return 0; 1580 } 1581 1582 static int smu_set_powergating_state(void *handle, 1583 enum amd_powergating_state state) 1584 { 1585 return 0; 1586 } 1587 1588 static int smu_enable_umd_pstate(void *handle, 1589 enum amd_dpm_forced_level *level) 1590 { 1591 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1592 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1593 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1594 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1595 1596 struct smu_context *smu = (struct smu_context*)(handle); 1597 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1598 1599 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1600 return -EINVAL; 1601 1602 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1603 /* enter umd pstate, save current level, disable gfx cg*/ 1604 if (*level & profile_mode_mask) { 1605 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1606 smu_dpm_ctx->enable_umd_pstate = true; 1607 smu_gpo_control(smu, false); 1608 amdgpu_device_ip_set_powergating_state(smu->adev, 1609 AMD_IP_BLOCK_TYPE_GFX, 1610 AMD_PG_STATE_UNGATE); 1611 amdgpu_device_ip_set_clockgating_state(smu->adev, 1612 AMD_IP_BLOCK_TYPE_GFX, 1613 AMD_CG_STATE_UNGATE); 1614 smu_gfx_ulv_control(smu, false); 1615 smu_deep_sleep_control(smu, false); 1616 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1617 } 1618 } else { 1619 /* exit umd pstate, restore level, enable gfx cg*/ 1620 if (!(*level & profile_mode_mask)) { 1621 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1622 *level = smu_dpm_ctx->saved_dpm_level; 1623 smu_dpm_ctx->enable_umd_pstate = false; 1624 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1625 smu_deep_sleep_control(smu, true); 1626 smu_gfx_ulv_control(smu, true); 1627 amdgpu_device_ip_set_clockgating_state(smu->adev, 1628 AMD_IP_BLOCK_TYPE_GFX, 1629 AMD_CG_STATE_GATE); 1630 amdgpu_device_ip_set_powergating_state(smu->adev, 1631 AMD_IP_BLOCK_TYPE_GFX, 1632 AMD_PG_STATE_GATE); 1633 smu_gpo_control(smu, true); 1634 } 1635 } 1636 1637 return 0; 1638 } 1639 1640 static int smu_bump_power_profile_mode(struct smu_context *smu, 1641 long *param, 1642 uint32_t param_size) 1643 { 1644 int ret = 0; 1645 1646 if (smu->ppt_funcs->set_power_profile_mode) 1647 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1648 1649 return ret; 1650 } 1651 1652 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1653 enum amd_dpm_forced_level level, 1654 bool skip_display_settings) 1655 { 1656 int ret = 0; 1657 int index = 0; 1658 long workload; 1659 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1660 1661 if (!skip_display_settings) { 1662 ret = smu_display_config_changed(smu); 1663 if (ret) { 1664 dev_err(smu->adev->dev, "Failed to change display config!"); 1665 return ret; 1666 } 1667 } 1668 1669 ret = smu_apply_clocks_adjust_rules(smu); 1670 if (ret) { 1671 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1672 return ret; 1673 } 1674 1675 if (!skip_display_settings) { 1676 ret = smu_notify_smc_display_config(smu); 1677 if (ret) { 1678 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1679 return ret; 1680 } 1681 } 1682 1683 if (smu_dpm_ctx->dpm_level != level) { 1684 ret = smu_asic_set_performance_level(smu, level); 1685 if (ret) { 1686 dev_err(smu->adev->dev, "Failed to set performance level!"); 1687 return ret; 1688 } 1689 1690 /* update the saved copy */ 1691 smu_dpm_ctx->dpm_level = level; 1692 } 1693 1694 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1695 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1696 index = fls(smu->workload_mask); 1697 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1698 workload = smu->workload_setting[index]; 1699 1700 if (smu->power_profile_mode != workload) 1701 smu_bump_power_profile_mode(smu, &workload, 0); 1702 } 1703 1704 return ret; 1705 } 1706 1707 static int smu_handle_task(struct smu_context *smu, 1708 enum amd_dpm_forced_level level, 1709 enum amd_pp_task task_id, 1710 bool lock_needed) 1711 { 1712 int ret = 0; 1713 1714 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1715 return -EOPNOTSUPP; 1716 1717 if (lock_needed) 1718 mutex_lock(&smu->mutex); 1719 1720 switch (task_id) { 1721 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1722 ret = smu_pre_display_config_changed(smu); 1723 if (ret) 1724 goto out; 1725 ret = smu_adjust_power_state_dynamic(smu, level, false); 1726 break; 1727 case AMD_PP_TASK_COMPLETE_INIT: 1728 case AMD_PP_TASK_READJUST_POWER_STATE: 1729 ret = smu_adjust_power_state_dynamic(smu, level, true); 1730 break; 1731 default: 1732 break; 1733 } 1734 1735 out: 1736 if (lock_needed) 1737 mutex_unlock(&smu->mutex); 1738 1739 return ret; 1740 } 1741 1742 static int smu_handle_dpm_task(void *handle, 1743 enum amd_pp_task task_id, 1744 enum amd_pm_state_type *user_state) 1745 { 1746 struct smu_context *smu = handle; 1747 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1748 1749 return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true); 1750 1751 } 1752 1753 static int smu_switch_power_profile(void *handle, 1754 enum PP_SMC_POWER_PROFILE type, 1755 bool en) 1756 { 1757 struct smu_context *smu = handle; 1758 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1759 long workload; 1760 uint32_t index; 1761 1762 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1763 return -EOPNOTSUPP; 1764 1765 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1766 return -EINVAL; 1767 1768 mutex_lock(&smu->mutex); 1769 1770 if (!en) { 1771 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1772 index = fls(smu->workload_mask); 1773 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1774 workload = smu->workload_setting[index]; 1775 } else { 1776 smu->workload_mask |= (1 << smu->workload_prority[type]); 1777 index = fls(smu->workload_mask); 1778 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1779 workload = smu->workload_setting[index]; 1780 } 1781 1782 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1783 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1784 smu_bump_power_profile_mode(smu, &workload, 0); 1785 1786 mutex_unlock(&smu->mutex); 1787 1788 return 0; 1789 } 1790 1791 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1792 { 1793 struct smu_context *smu = handle; 1794 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1795 enum amd_dpm_forced_level level; 1796 1797 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1798 return -EOPNOTSUPP; 1799 1800 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1801 return -EINVAL; 1802 1803 mutex_lock(&(smu->mutex)); 1804 level = smu_dpm_ctx->dpm_level; 1805 mutex_unlock(&(smu->mutex)); 1806 1807 return level; 1808 } 1809 1810 static int smu_force_performance_level(void *handle, 1811 enum amd_dpm_forced_level level) 1812 { 1813 struct smu_context *smu = handle; 1814 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1815 int ret = 0; 1816 1817 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1818 return -EOPNOTSUPP; 1819 1820 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1821 return -EINVAL; 1822 1823 mutex_lock(&smu->mutex); 1824 1825 ret = smu_enable_umd_pstate(smu, &level); 1826 if (ret) { 1827 mutex_unlock(&smu->mutex); 1828 return ret; 1829 } 1830 1831 ret = smu_handle_task(smu, level, 1832 AMD_PP_TASK_READJUST_POWER_STATE, 1833 false); 1834 1835 mutex_unlock(&smu->mutex); 1836 1837 /* reset user dpm clock state */ 1838 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1839 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1840 smu->user_dpm_profile.clk_dependency = 0; 1841 } 1842 1843 return ret; 1844 } 1845 1846 static int smu_set_display_count(void *handle, uint32_t count) 1847 { 1848 struct smu_context *smu = handle; 1849 int ret = 0; 1850 1851 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1852 return -EOPNOTSUPP; 1853 1854 mutex_lock(&smu->mutex); 1855 ret = smu_init_display_count(smu, count); 1856 mutex_unlock(&smu->mutex); 1857 1858 return ret; 1859 } 1860 1861 static int smu_force_smuclk_levels(struct smu_context *smu, 1862 enum smu_clk_type clk_type, 1863 uint32_t mask) 1864 { 1865 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1866 int ret = 0; 1867 1868 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1869 return -EOPNOTSUPP; 1870 1871 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1872 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1873 return -EINVAL; 1874 } 1875 1876 mutex_lock(&smu->mutex); 1877 1878 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1879 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1880 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1881 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1882 smu_set_user_clk_dependencies(smu, clk_type); 1883 } 1884 } 1885 1886 mutex_unlock(&smu->mutex); 1887 1888 return ret; 1889 } 1890 1891 static int smu_force_ppclk_levels(void *handle, 1892 enum pp_clock_type type, 1893 uint32_t mask) 1894 { 1895 struct smu_context *smu = handle; 1896 enum smu_clk_type clk_type; 1897 1898 switch (type) { 1899 case PP_SCLK: 1900 clk_type = SMU_SCLK; break; 1901 case PP_MCLK: 1902 clk_type = SMU_MCLK; break; 1903 case PP_PCIE: 1904 clk_type = SMU_PCIE; break; 1905 case PP_SOCCLK: 1906 clk_type = SMU_SOCCLK; break; 1907 case PP_FCLK: 1908 clk_type = SMU_FCLK; break; 1909 case PP_DCEFCLK: 1910 clk_type = SMU_DCEFCLK; break; 1911 case PP_VCLK: 1912 clk_type = SMU_VCLK; break; 1913 case PP_DCLK: 1914 clk_type = SMU_DCLK; break; 1915 case OD_SCLK: 1916 clk_type = SMU_OD_SCLK; break; 1917 case OD_MCLK: 1918 clk_type = SMU_OD_MCLK; break; 1919 case OD_VDDC_CURVE: 1920 clk_type = SMU_OD_VDDC_CURVE; break; 1921 case OD_RANGE: 1922 clk_type = SMU_OD_RANGE; break; 1923 default: 1924 return -EINVAL; 1925 } 1926 1927 return smu_force_smuclk_levels(smu, clk_type, mask); 1928 } 1929 1930 /* 1931 * On system suspending or resetting, the dpm_enabled 1932 * flag will be cleared. So that those SMU services which 1933 * are not supported will be gated. 1934 * However, the mp1 state setting should still be granted 1935 * even if the dpm_enabled cleared. 1936 */ 1937 static int smu_set_mp1_state(void *handle, 1938 enum pp_mp1_state mp1_state) 1939 { 1940 struct smu_context *smu = handle; 1941 int ret = 0; 1942 1943 if (!smu->pm_enabled) 1944 return -EOPNOTSUPP; 1945 1946 mutex_lock(&smu->mutex); 1947 1948 if (smu->ppt_funcs && 1949 smu->ppt_funcs->set_mp1_state) 1950 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 1951 1952 mutex_unlock(&smu->mutex); 1953 1954 return ret; 1955 } 1956 1957 static int smu_set_df_cstate(void *handle, 1958 enum pp_df_cstate state) 1959 { 1960 struct smu_context *smu = handle; 1961 int ret = 0; 1962 1963 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1964 return -EOPNOTSUPP; 1965 1966 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 1967 return 0; 1968 1969 mutex_lock(&smu->mutex); 1970 1971 ret = smu->ppt_funcs->set_df_cstate(smu, state); 1972 if (ret) 1973 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 1974 1975 mutex_unlock(&smu->mutex); 1976 1977 return ret; 1978 } 1979 1980 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 1981 { 1982 int ret = 0; 1983 1984 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1985 return -EOPNOTSUPP; 1986 1987 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 1988 return 0; 1989 1990 mutex_lock(&smu->mutex); 1991 1992 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 1993 if (ret) 1994 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 1995 1996 mutex_unlock(&smu->mutex); 1997 1998 return ret; 1999 } 2000 2001 int smu_write_watermarks_table(struct smu_context *smu) 2002 { 2003 int ret = 0; 2004 2005 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2006 return -EOPNOTSUPP; 2007 2008 mutex_lock(&smu->mutex); 2009 2010 ret = smu_set_watermarks_table(smu, NULL); 2011 2012 mutex_unlock(&smu->mutex); 2013 2014 return ret; 2015 } 2016 2017 static int smu_set_watermarks_for_clock_ranges(void *handle, 2018 struct pp_smu_wm_range_sets *clock_ranges) 2019 { 2020 struct smu_context *smu = handle; 2021 int ret = 0; 2022 2023 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2024 return -EOPNOTSUPP; 2025 2026 if (smu->disable_watermark) 2027 return 0; 2028 2029 mutex_lock(&smu->mutex); 2030 2031 ret = smu_set_watermarks_table(smu, clock_ranges); 2032 2033 mutex_unlock(&smu->mutex); 2034 2035 return ret; 2036 } 2037 2038 int smu_set_ac_dc(struct smu_context *smu) 2039 { 2040 int ret = 0; 2041 2042 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2043 return -EOPNOTSUPP; 2044 2045 /* controlled by firmware */ 2046 if (smu->dc_controlled_by_gpio) 2047 return 0; 2048 2049 mutex_lock(&smu->mutex); 2050 ret = smu_set_power_source(smu, 2051 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2052 SMU_POWER_SOURCE_DC); 2053 if (ret) 2054 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2055 smu->adev->pm.ac_power ? "AC" : "DC"); 2056 mutex_unlock(&smu->mutex); 2057 2058 return ret; 2059 } 2060 2061 const struct amd_ip_funcs smu_ip_funcs = { 2062 .name = "smu", 2063 .early_init = smu_early_init, 2064 .late_init = smu_late_init, 2065 .sw_init = smu_sw_init, 2066 .sw_fini = smu_sw_fini, 2067 .hw_init = smu_hw_init, 2068 .hw_fini = smu_hw_fini, 2069 .suspend = smu_suspend, 2070 .resume = smu_resume, 2071 .is_idle = NULL, 2072 .check_soft_reset = NULL, 2073 .wait_for_idle = NULL, 2074 .soft_reset = NULL, 2075 .set_clockgating_state = smu_set_clockgating_state, 2076 .set_powergating_state = smu_set_powergating_state, 2077 .enable_umd_pstate = smu_enable_umd_pstate, 2078 }; 2079 2080 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2081 { 2082 .type = AMD_IP_BLOCK_TYPE_SMC, 2083 .major = 11, 2084 .minor = 0, 2085 .rev = 0, 2086 .funcs = &smu_ip_funcs, 2087 }; 2088 2089 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2090 { 2091 .type = AMD_IP_BLOCK_TYPE_SMC, 2092 .major = 12, 2093 .minor = 0, 2094 .rev = 0, 2095 .funcs = &smu_ip_funcs, 2096 }; 2097 2098 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2099 { 2100 .type = AMD_IP_BLOCK_TYPE_SMC, 2101 .major = 13, 2102 .minor = 0, 2103 .rev = 0, 2104 .funcs = &smu_ip_funcs, 2105 }; 2106 2107 static int smu_load_microcode(void *handle) 2108 { 2109 struct smu_context *smu = handle; 2110 struct amdgpu_device *adev = smu->adev; 2111 int ret = 0; 2112 2113 if (!smu->pm_enabled) 2114 return -EOPNOTSUPP; 2115 2116 /* This should be used for non PSP loading */ 2117 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2118 return 0; 2119 2120 if (smu->ppt_funcs->load_microcode) { 2121 ret = smu->ppt_funcs->load_microcode(smu); 2122 if (ret) { 2123 dev_err(adev->dev, "Load microcode failed\n"); 2124 return ret; 2125 } 2126 } 2127 2128 if (smu->ppt_funcs->check_fw_status) { 2129 ret = smu->ppt_funcs->check_fw_status(smu); 2130 if (ret) { 2131 dev_err(adev->dev, "SMC is not ready\n"); 2132 return ret; 2133 } 2134 } 2135 2136 return ret; 2137 } 2138 2139 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2140 { 2141 int ret = 0; 2142 2143 mutex_lock(&smu->mutex); 2144 2145 if (smu->ppt_funcs->set_gfx_cgpg) 2146 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2147 2148 mutex_unlock(&smu->mutex); 2149 2150 return ret; 2151 } 2152 2153 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2154 { 2155 struct smu_context *smu = handle; 2156 u32 percent; 2157 int ret = 0; 2158 2159 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2160 return -EOPNOTSUPP; 2161 2162 mutex_lock(&smu->mutex); 2163 2164 if (smu->ppt_funcs->set_fan_speed_percent) { 2165 percent = speed * 100 / smu->fan_max_rpm; 2166 ret = smu->ppt_funcs->set_fan_speed_percent(smu, percent); 2167 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2168 smu->user_dpm_profile.fan_speed_percent = percent; 2169 } 2170 2171 mutex_unlock(&smu->mutex); 2172 2173 return ret; 2174 } 2175 2176 int smu_get_power_limit(struct smu_context *smu, 2177 uint32_t *limit, 2178 enum smu_ppt_limit_level limit_level) 2179 { 2180 uint32_t limit_type = *limit >> 24; 2181 int ret = 0; 2182 2183 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2184 return -EOPNOTSUPP; 2185 2186 mutex_lock(&smu->mutex); 2187 2188 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2189 if (smu->ppt_funcs->get_ppt_limit) 2190 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2191 } else { 2192 switch (limit_level) { 2193 case SMU_PPT_LIMIT_CURRENT: 2194 *limit = smu->current_power_limit; 2195 break; 2196 case SMU_PPT_LIMIT_DEFAULT: 2197 *limit = smu->default_power_limit; 2198 break; 2199 case SMU_PPT_LIMIT_MAX: 2200 *limit = smu->max_power_limit; 2201 break; 2202 default: 2203 break; 2204 } 2205 } 2206 2207 mutex_unlock(&smu->mutex); 2208 2209 return ret; 2210 } 2211 2212 static int smu_set_power_limit(void *handle, uint32_t limit) 2213 { 2214 struct smu_context *smu = handle; 2215 uint32_t limit_type = limit >> 24; 2216 int ret = 0; 2217 2218 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2219 return -EOPNOTSUPP; 2220 2221 mutex_lock(&smu->mutex); 2222 2223 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2224 if (smu->ppt_funcs->set_power_limit) { 2225 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2226 goto out; 2227 } 2228 2229 if (limit > smu->max_power_limit) { 2230 dev_err(smu->adev->dev, 2231 "New power limit (%d) is over the max allowed %d\n", 2232 limit, smu->max_power_limit); 2233 ret = -EINVAL; 2234 goto out; 2235 } 2236 2237 if (!limit) 2238 limit = smu->current_power_limit; 2239 2240 if (smu->ppt_funcs->set_power_limit) { 2241 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2242 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2243 smu->user_dpm_profile.power_limit = limit; 2244 } 2245 2246 out: 2247 mutex_unlock(&smu->mutex); 2248 2249 return ret; 2250 } 2251 2252 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2253 { 2254 int ret = 0; 2255 2256 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2257 return -EOPNOTSUPP; 2258 2259 mutex_lock(&smu->mutex); 2260 2261 if (smu->ppt_funcs->print_clk_levels) 2262 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2263 2264 mutex_unlock(&smu->mutex); 2265 2266 return ret; 2267 } 2268 2269 static int smu_print_ppclk_levels(void *handle, 2270 enum pp_clock_type type, 2271 char *buf) 2272 { 2273 struct smu_context *smu = handle; 2274 enum smu_clk_type clk_type; 2275 2276 switch (type) { 2277 case PP_SCLK: 2278 clk_type = SMU_SCLK; break; 2279 case PP_MCLK: 2280 clk_type = SMU_MCLK; break; 2281 case PP_PCIE: 2282 clk_type = SMU_PCIE; break; 2283 case PP_SOCCLK: 2284 clk_type = SMU_SOCCLK; break; 2285 case PP_FCLK: 2286 clk_type = SMU_FCLK; break; 2287 case PP_DCEFCLK: 2288 clk_type = SMU_DCEFCLK; break; 2289 case PP_VCLK: 2290 clk_type = SMU_VCLK; break; 2291 case PP_DCLK: 2292 clk_type = SMU_DCLK; break; 2293 case OD_SCLK: 2294 clk_type = SMU_OD_SCLK; break; 2295 case OD_MCLK: 2296 clk_type = SMU_OD_MCLK; break; 2297 case OD_VDDC_CURVE: 2298 clk_type = SMU_OD_VDDC_CURVE; break; 2299 case OD_RANGE: 2300 clk_type = SMU_OD_RANGE; break; 2301 case OD_VDDGFX_OFFSET: 2302 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2303 case OD_CCLK: 2304 clk_type = SMU_OD_CCLK; break; 2305 default: 2306 return -EINVAL; 2307 } 2308 2309 return smu_print_smuclk_levels(smu, clk_type, buf); 2310 } 2311 2312 static int smu_od_edit_dpm_table(void *handle, 2313 enum PP_OD_DPM_TABLE_COMMAND type, 2314 long *input, uint32_t size) 2315 { 2316 struct smu_context *smu = handle; 2317 int ret = 0; 2318 2319 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2320 return -EOPNOTSUPP; 2321 2322 mutex_lock(&smu->mutex); 2323 2324 if (smu->ppt_funcs->od_edit_dpm_table) { 2325 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2326 } 2327 2328 mutex_unlock(&smu->mutex); 2329 2330 return ret; 2331 } 2332 2333 static int smu_read_sensor(void *handle, 2334 int sensor, 2335 void *data, 2336 int *size_arg) 2337 { 2338 struct smu_context *smu = handle; 2339 struct smu_umd_pstate_table *pstate_table = 2340 &smu->pstate_table; 2341 int ret = 0; 2342 uint32_t *size, size_val; 2343 2344 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2345 return -EOPNOTSUPP; 2346 2347 if (!data || !size_arg) 2348 return -EINVAL; 2349 2350 size_val = *size_arg; 2351 size = &size_val; 2352 2353 mutex_lock(&smu->mutex); 2354 2355 if (smu->ppt_funcs->read_sensor) 2356 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2357 goto unlock; 2358 2359 switch (sensor) { 2360 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2361 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2362 *size = 4; 2363 break; 2364 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2365 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2366 *size = 4; 2367 break; 2368 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2369 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2370 *size = 8; 2371 break; 2372 case AMDGPU_PP_SENSOR_UVD_POWER: 2373 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2374 *size = 4; 2375 break; 2376 case AMDGPU_PP_SENSOR_VCE_POWER: 2377 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2378 *size = 4; 2379 break; 2380 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2381 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2382 *size = 4; 2383 break; 2384 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2385 *(uint32_t *)data = 0; 2386 *size = 4; 2387 break; 2388 default: 2389 *size = 0; 2390 ret = -EOPNOTSUPP; 2391 break; 2392 } 2393 2394 unlock: 2395 mutex_unlock(&smu->mutex); 2396 2397 // assign uint32_t to int 2398 *size_arg = size_val; 2399 2400 return ret; 2401 } 2402 2403 static int smu_get_power_profile_mode(void *handle, char *buf) 2404 { 2405 struct smu_context *smu = handle; 2406 int ret = 0; 2407 2408 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2409 return -EOPNOTSUPP; 2410 2411 mutex_lock(&smu->mutex); 2412 2413 if (smu->ppt_funcs->get_power_profile_mode) 2414 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf); 2415 2416 mutex_unlock(&smu->mutex); 2417 2418 return ret; 2419 } 2420 2421 static int smu_set_power_profile_mode(void *handle, 2422 long *param, 2423 uint32_t param_size) 2424 { 2425 struct smu_context *smu = handle; 2426 int ret = 0; 2427 2428 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2429 return -EOPNOTSUPP; 2430 2431 mutex_lock(&smu->mutex); 2432 2433 smu_bump_power_profile_mode(smu, param, param_size); 2434 2435 mutex_unlock(&smu->mutex); 2436 2437 return ret; 2438 } 2439 2440 2441 static u32 smu_get_fan_control_mode(void *handle) 2442 { 2443 struct smu_context *smu = handle; 2444 u32 ret = 0; 2445 2446 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2447 return AMD_FAN_CTRL_NONE; 2448 2449 mutex_lock(&smu->mutex); 2450 2451 if (smu->ppt_funcs->get_fan_control_mode) 2452 ret = smu->ppt_funcs->get_fan_control_mode(smu); 2453 2454 mutex_unlock(&smu->mutex); 2455 2456 return ret; 2457 } 2458 2459 static int smu_set_fan_control_mode(struct smu_context *smu, int value) 2460 { 2461 int ret = 0; 2462 2463 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2464 return -EOPNOTSUPP; 2465 2466 mutex_lock(&smu->mutex); 2467 2468 if (smu->ppt_funcs->set_fan_control_mode) { 2469 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2470 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2471 smu->user_dpm_profile.fan_mode = value; 2472 } 2473 2474 mutex_unlock(&smu->mutex); 2475 2476 /* reset user dpm fan speed */ 2477 if (!ret && value != AMD_FAN_CTRL_MANUAL && 2478 !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2479 smu->user_dpm_profile.fan_speed_percent = 0; 2480 2481 return ret; 2482 } 2483 2484 static void smu_pp_set_fan_control_mode(void *handle, u32 value) 2485 { 2486 struct smu_context *smu = handle; 2487 2488 smu_set_fan_control_mode(smu, value); 2489 } 2490 2491 2492 static int smu_get_fan_speed_percent(void *handle, u32 *speed) 2493 { 2494 struct smu_context *smu = handle; 2495 int ret = 0; 2496 uint32_t percent; 2497 2498 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2499 return -EOPNOTSUPP; 2500 2501 mutex_lock(&smu->mutex); 2502 2503 if (smu->ppt_funcs->get_fan_speed_percent) { 2504 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent); 2505 if (!ret) { 2506 *speed = percent > 100 ? 100 : percent; 2507 } 2508 } 2509 2510 mutex_unlock(&smu->mutex); 2511 2512 2513 return ret; 2514 } 2515 2516 static int smu_set_fan_speed_percent(void *handle, u32 speed) 2517 { 2518 struct smu_context *smu = handle; 2519 int ret = 0; 2520 2521 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2522 return -EOPNOTSUPP; 2523 2524 mutex_lock(&smu->mutex); 2525 2526 if (smu->ppt_funcs->set_fan_speed_percent) { 2527 if (speed > 100) 2528 speed = 100; 2529 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed); 2530 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2531 smu->user_dpm_profile.fan_speed_percent = speed; 2532 } 2533 2534 mutex_unlock(&smu->mutex); 2535 2536 return ret; 2537 } 2538 2539 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2540 { 2541 struct smu_context *smu = handle; 2542 int ret = 0; 2543 u32 percent; 2544 2545 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2546 return -EOPNOTSUPP; 2547 2548 mutex_lock(&smu->mutex); 2549 2550 if (smu->ppt_funcs->get_fan_speed_percent) { 2551 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent); 2552 *speed = percent * smu->fan_max_rpm / 100; 2553 } 2554 2555 mutex_unlock(&smu->mutex); 2556 2557 return ret; 2558 } 2559 2560 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2561 { 2562 struct smu_context *smu = handle; 2563 int ret = 0; 2564 2565 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2566 return -EOPNOTSUPP; 2567 2568 mutex_lock(&smu->mutex); 2569 2570 ret = smu_set_min_dcef_deep_sleep(smu, clk); 2571 2572 mutex_unlock(&smu->mutex); 2573 2574 return ret; 2575 } 2576 2577 static int smu_get_clock_by_type_with_latency(void *handle, 2578 enum amd_pp_clock_type type, 2579 struct pp_clock_levels_with_latency *clocks) 2580 { 2581 struct smu_context *smu = handle; 2582 enum smu_clk_type clk_type; 2583 int ret = 0; 2584 2585 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2586 return -EOPNOTSUPP; 2587 2588 mutex_lock(&smu->mutex); 2589 2590 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2591 switch (type) { 2592 case amd_pp_sys_clock: 2593 clk_type = SMU_GFXCLK; 2594 break; 2595 case amd_pp_mem_clock: 2596 clk_type = SMU_MCLK; 2597 break; 2598 case amd_pp_dcef_clock: 2599 clk_type = SMU_DCEFCLK; 2600 break; 2601 case amd_pp_disp_clock: 2602 clk_type = SMU_DISPCLK; 2603 break; 2604 default: 2605 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2606 mutex_unlock(&smu->mutex); 2607 return -EINVAL; 2608 } 2609 2610 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2611 } 2612 2613 mutex_unlock(&smu->mutex); 2614 2615 return ret; 2616 } 2617 2618 static int smu_display_clock_voltage_request(void *handle, 2619 struct pp_display_clock_request *clock_req) 2620 { 2621 struct smu_context *smu = handle; 2622 int ret = 0; 2623 2624 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2625 return -EOPNOTSUPP; 2626 2627 mutex_lock(&smu->mutex); 2628 2629 if (smu->ppt_funcs->display_clock_voltage_request) 2630 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2631 2632 mutex_unlock(&smu->mutex); 2633 2634 return ret; 2635 } 2636 2637 2638 static int smu_display_disable_memory_clock_switch(void *handle, 2639 bool disable_memory_clock_switch) 2640 { 2641 struct smu_context *smu = handle; 2642 int ret = -EINVAL; 2643 2644 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2645 return -EOPNOTSUPP; 2646 2647 mutex_lock(&smu->mutex); 2648 2649 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2650 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2651 2652 mutex_unlock(&smu->mutex); 2653 2654 return ret; 2655 } 2656 2657 static int smu_set_xgmi_pstate(void *handle, 2658 uint32_t pstate) 2659 { 2660 struct smu_context *smu = handle; 2661 int ret = 0; 2662 2663 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2664 return -EOPNOTSUPP; 2665 2666 mutex_lock(&smu->mutex); 2667 2668 if (smu->ppt_funcs->set_xgmi_pstate) 2669 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2670 2671 mutex_unlock(&smu->mutex); 2672 2673 if(ret) 2674 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2675 2676 return ret; 2677 } 2678 2679 static int smu_get_baco_capability(void *handle, bool *cap) 2680 { 2681 struct smu_context *smu = handle; 2682 int ret = 0; 2683 2684 *cap = false; 2685 2686 if (!smu->pm_enabled) 2687 return 0; 2688 2689 mutex_lock(&smu->mutex); 2690 2691 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2692 *cap = smu->ppt_funcs->baco_is_support(smu); 2693 2694 mutex_unlock(&smu->mutex); 2695 2696 return ret; 2697 } 2698 2699 static int smu_baco_set_state(void *handle, int state) 2700 { 2701 struct smu_context *smu = handle; 2702 int ret = 0; 2703 2704 if (!smu->pm_enabled) 2705 return -EOPNOTSUPP; 2706 2707 if (state == 0) { 2708 mutex_lock(&smu->mutex); 2709 2710 if (smu->ppt_funcs->baco_exit) 2711 ret = smu->ppt_funcs->baco_exit(smu); 2712 2713 mutex_unlock(&smu->mutex); 2714 } else if (state == 1) { 2715 mutex_lock(&smu->mutex); 2716 2717 if (smu->ppt_funcs->baco_enter) 2718 ret = smu->ppt_funcs->baco_enter(smu); 2719 2720 mutex_unlock(&smu->mutex); 2721 2722 } else { 2723 return -EINVAL; 2724 } 2725 2726 if (ret) 2727 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2728 (state)?"enter":"exit"); 2729 2730 return ret; 2731 } 2732 2733 bool smu_mode1_reset_is_support(struct smu_context *smu) 2734 { 2735 bool ret = false; 2736 2737 if (!smu->pm_enabled) 2738 return false; 2739 2740 mutex_lock(&smu->mutex); 2741 2742 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2743 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2744 2745 mutex_unlock(&smu->mutex); 2746 2747 return ret; 2748 } 2749 2750 bool smu_mode2_reset_is_support(struct smu_context *smu) 2751 { 2752 bool ret = false; 2753 2754 if (!smu->pm_enabled) 2755 return false; 2756 2757 mutex_lock(&smu->mutex); 2758 2759 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2760 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2761 2762 mutex_unlock(&smu->mutex); 2763 2764 return ret; 2765 } 2766 2767 int smu_mode1_reset(struct smu_context *smu) 2768 { 2769 int ret = 0; 2770 2771 if (!smu->pm_enabled) 2772 return -EOPNOTSUPP; 2773 2774 mutex_lock(&smu->mutex); 2775 2776 if (smu->ppt_funcs->mode1_reset) 2777 ret = smu->ppt_funcs->mode1_reset(smu); 2778 2779 mutex_unlock(&smu->mutex); 2780 2781 return ret; 2782 } 2783 2784 static int smu_mode2_reset(void *handle) 2785 { 2786 struct smu_context *smu = handle; 2787 int ret = 0; 2788 2789 if (!smu->pm_enabled) 2790 return -EOPNOTSUPP; 2791 2792 mutex_lock(&smu->mutex); 2793 2794 if (smu->ppt_funcs->mode2_reset) 2795 ret = smu->ppt_funcs->mode2_reset(smu); 2796 2797 mutex_unlock(&smu->mutex); 2798 2799 if (ret) 2800 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2801 2802 return ret; 2803 } 2804 2805 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2806 struct pp_smu_nv_clock_table *max_clocks) 2807 { 2808 struct smu_context *smu = handle; 2809 int ret = 0; 2810 2811 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2812 return -EOPNOTSUPP; 2813 2814 mutex_lock(&smu->mutex); 2815 2816 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2817 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2818 2819 mutex_unlock(&smu->mutex); 2820 2821 return ret; 2822 } 2823 2824 static int smu_get_uclk_dpm_states(void *handle, 2825 unsigned int *clock_values_in_khz, 2826 unsigned int *num_states) 2827 { 2828 struct smu_context *smu = handle; 2829 int ret = 0; 2830 2831 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2832 return -EOPNOTSUPP; 2833 2834 mutex_lock(&smu->mutex); 2835 2836 if (smu->ppt_funcs->get_uclk_dpm_states) 2837 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2838 2839 mutex_unlock(&smu->mutex); 2840 2841 return ret; 2842 } 2843 2844 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2845 { 2846 struct smu_context *smu = handle; 2847 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2848 2849 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2850 return -EOPNOTSUPP; 2851 2852 mutex_lock(&smu->mutex); 2853 2854 if (smu->ppt_funcs->get_current_power_state) 2855 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2856 2857 mutex_unlock(&smu->mutex); 2858 2859 return pm_state; 2860 } 2861 2862 static int smu_get_dpm_clock_table(void *handle, 2863 struct dpm_clocks *clock_table) 2864 { 2865 struct smu_context *smu = handle; 2866 int ret = 0; 2867 2868 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2869 return -EOPNOTSUPP; 2870 2871 mutex_lock(&smu->mutex); 2872 2873 if (smu->ppt_funcs->get_dpm_clock_table) 2874 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2875 2876 mutex_unlock(&smu->mutex); 2877 2878 return ret; 2879 } 2880 2881 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2882 { 2883 struct smu_context *smu = handle; 2884 ssize_t size; 2885 2886 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2887 return -EOPNOTSUPP; 2888 2889 if (!smu->ppt_funcs->get_gpu_metrics) 2890 return -EOPNOTSUPP; 2891 2892 mutex_lock(&smu->mutex); 2893 2894 size = smu->ppt_funcs->get_gpu_metrics(smu, table); 2895 2896 mutex_unlock(&smu->mutex); 2897 2898 return size; 2899 } 2900 2901 static int smu_enable_mgpu_fan_boost(void *handle) 2902 { 2903 struct smu_context *smu = handle; 2904 int ret = 0; 2905 2906 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2907 return -EOPNOTSUPP; 2908 2909 mutex_lock(&smu->mutex); 2910 2911 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2912 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2913 2914 mutex_unlock(&smu->mutex); 2915 2916 return ret; 2917 } 2918 2919 static int smu_gfx_state_change_set(void *handle, 2920 uint32_t state) 2921 { 2922 struct smu_context *smu = handle; 2923 int ret = 0; 2924 2925 mutex_lock(&smu->mutex); 2926 if (smu->ppt_funcs->gfx_state_change_set) 2927 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2928 mutex_unlock(&smu->mutex); 2929 2930 return ret; 2931 } 2932 2933 int smu_set_light_sbr(struct smu_context *smu, bool enable) 2934 { 2935 int ret = 0; 2936 2937 mutex_lock(&smu->mutex); 2938 if (smu->ppt_funcs->set_light_sbr) 2939 ret = smu->ppt_funcs->set_light_sbr(smu, enable); 2940 mutex_unlock(&smu->mutex); 2941 2942 return ret; 2943 } 2944 2945 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 2946 { 2947 struct smu_context *smu = handle; 2948 struct smu_table_context *smu_table = &smu->smu_table; 2949 struct smu_table *memory_pool = &smu_table->memory_pool; 2950 2951 if (!addr || !size) 2952 return -EINVAL; 2953 2954 *addr = NULL; 2955 *size = 0; 2956 mutex_lock(&smu->mutex); 2957 if (memory_pool->bo) { 2958 *addr = memory_pool->cpu_addr; 2959 *size = memory_pool->size; 2960 } 2961 mutex_unlock(&smu->mutex); 2962 2963 return 0; 2964 } 2965 2966 static const struct amd_pm_funcs swsmu_pm_funcs = { 2967 /* export for sysfs */ 2968 .set_fan_control_mode = smu_pp_set_fan_control_mode, 2969 .get_fan_control_mode = smu_get_fan_control_mode, 2970 .set_fan_speed_percent = smu_set_fan_speed_percent, 2971 .get_fan_speed_percent = smu_get_fan_speed_percent, 2972 .force_performance_level = smu_force_performance_level, 2973 .read_sensor = smu_read_sensor, 2974 .get_performance_level = smu_get_performance_level, 2975 .get_current_power_state = smu_get_current_power_state, 2976 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 2977 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 2978 .get_pp_num_states = smu_get_power_num_states, 2979 .get_pp_table = smu_sys_get_pp_table, 2980 .set_pp_table = smu_sys_set_pp_table, 2981 .switch_power_profile = smu_switch_power_profile, 2982 /* export to amdgpu */ 2983 .dispatch_tasks = smu_handle_dpm_task, 2984 .set_powergating_by_smu = smu_dpm_set_power_gate, 2985 .set_power_limit = smu_set_power_limit, 2986 .odn_edit_dpm_table = smu_od_edit_dpm_table, 2987 .set_mp1_state = smu_set_mp1_state, 2988 /* export to DC */ 2989 .get_sclk = smu_get_sclk, 2990 .get_mclk = smu_get_mclk, 2991 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 2992 .get_asic_baco_capability = smu_get_baco_capability, 2993 .set_asic_baco_state = smu_baco_set_state, 2994 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 2995 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 2996 .asic_reset_mode_2 = smu_mode2_reset, 2997 .set_df_cstate = smu_set_df_cstate, 2998 .set_xgmi_pstate = smu_set_xgmi_pstate, 2999 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3000 .set_power_profile_mode = smu_set_power_profile_mode, 3001 .get_power_profile_mode = smu_get_power_profile_mode, 3002 .force_clock_level = smu_force_ppclk_levels, 3003 .print_clock_levels = smu_print_ppclk_levels, 3004 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3005 .get_dpm_clock_table = smu_get_dpm_clock_table, 3006 .display_configuration_change = smu_display_configuration_change, 3007 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3008 .display_clock_voltage_request = smu_display_clock_voltage_request, 3009 .set_active_display_count = smu_set_display_count, 3010 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3011 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3012 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3013 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3014 .load_firmware = smu_load_microcode, 3015 .gfx_state_change_set = smu_gfx_state_change_set, 3016 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3017 }; 3018 3019 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 3020 uint64_t event_arg) 3021 { 3022 int ret = -EINVAL; 3023 struct smu_context *smu = &adev->smu; 3024 3025 if (smu->ppt_funcs->wait_for_event) { 3026 mutex_lock(&smu->mutex); 3027 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3028 mutex_unlock(&smu->mutex); 3029 } 3030 3031 return ret; 3032 } 3033