1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 76 static int smu_sys_get_pp_feature_mask(void *handle, 77 char *buf) 78 { 79 struct smu_context *smu = handle; 80 81 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 82 return -EOPNOTSUPP; 83 84 return smu_get_pp_feature_mask(smu, buf); 85 } 86 87 static int smu_sys_set_pp_feature_mask(void *handle, 88 uint64_t new_mask) 89 { 90 struct smu_context *smu = handle; 91 92 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 93 return -EOPNOTSUPP; 94 95 return smu_set_pp_feature_mask(smu, new_mask); 96 } 97 98 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 99 { 100 if (!smu->ppt_funcs->set_gfx_off_residency) 101 return -EINVAL; 102 103 return smu_set_gfx_off_residency(smu, value); 104 } 105 106 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 107 { 108 if (!smu->ppt_funcs->get_gfx_off_residency) 109 return -EINVAL; 110 111 return smu_get_gfx_off_residency(smu, value); 112 } 113 114 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 115 { 116 if (!smu->ppt_funcs->get_gfx_off_entrycount) 117 return -EINVAL; 118 119 return smu_get_gfx_off_entrycount(smu, value); 120 } 121 122 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 123 { 124 if (!smu->ppt_funcs->get_gfx_off_status) 125 return -EINVAL; 126 127 *value = smu_get_gfx_off_status(smu); 128 129 return 0; 130 } 131 132 int smu_set_soft_freq_range(struct smu_context *smu, 133 enum smu_clk_type clk_type, 134 uint32_t min, 135 uint32_t max) 136 { 137 int ret = 0; 138 139 if (smu->ppt_funcs->set_soft_freq_limited_range) 140 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 141 clk_type, 142 min, 143 max); 144 145 return ret; 146 } 147 148 int smu_get_dpm_freq_range(struct smu_context *smu, 149 enum smu_clk_type clk_type, 150 uint32_t *min, 151 uint32_t *max) 152 { 153 int ret = -ENOTSUPP; 154 155 if (!min && !max) 156 return -EINVAL; 157 158 if (smu->ppt_funcs->get_dpm_ultimate_freq) 159 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 160 clk_type, 161 min, 162 max); 163 164 return ret; 165 } 166 167 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 168 { 169 int ret = 0; 170 struct amdgpu_device *adev = smu->adev; 171 172 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 173 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 174 if (ret) 175 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 176 } 177 return ret; 178 } 179 180 static u32 smu_get_mclk(void *handle, bool low) 181 { 182 struct smu_context *smu = handle; 183 uint32_t clk_freq; 184 int ret = 0; 185 186 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 187 low ? &clk_freq : NULL, 188 !low ? &clk_freq : NULL); 189 if (ret) 190 return 0; 191 return clk_freq * 100; 192 } 193 194 static u32 smu_get_sclk(void *handle, bool low) 195 { 196 struct smu_context *smu = handle; 197 uint32_t clk_freq; 198 int ret = 0; 199 200 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 201 low ? &clk_freq : NULL, 202 !low ? &clk_freq : NULL); 203 if (ret) 204 return 0; 205 return clk_freq * 100; 206 } 207 208 static int smu_set_gfx_imu_enable(struct smu_context *smu) 209 { 210 struct amdgpu_device *adev = smu->adev; 211 212 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 213 return 0; 214 215 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 216 return 0; 217 218 return smu_set_gfx_power_up_by_imu(smu); 219 } 220 221 static bool is_vcn_enabled(struct amdgpu_device *adev) 222 { 223 int i; 224 225 for (i = 0; i < adev->num_ip_blocks; i++) { 226 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 227 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 228 !adev->ip_blocks[i].status.valid) 229 return false; 230 } 231 232 return true; 233 } 234 235 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 236 bool enable) 237 { 238 struct smu_power_context *smu_power = &smu->smu_power; 239 struct smu_power_gate *power_gate = &smu_power->power_gate; 240 int ret = 0; 241 242 /* 243 * don't poweron vcn/jpeg when they are skipped. 244 */ 245 if (!is_vcn_enabled(smu->adev)) 246 return 0; 247 248 if (!smu->ppt_funcs->dpm_set_vcn_enable) 249 return 0; 250 251 if (atomic_read(&power_gate->vcn_gated) ^ enable) 252 return 0; 253 254 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 255 if (!ret) 256 atomic_set(&power_gate->vcn_gated, !enable); 257 258 return ret; 259 } 260 261 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 262 bool enable) 263 { 264 struct smu_power_context *smu_power = &smu->smu_power; 265 struct smu_power_gate *power_gate = &smu_power->power_gate; 266 int ret = 0; 267 268 if (!is_vcn_enabled(smu->adev)) 269 return 0; 270 271 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 272 return 0; 273 274 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 275 return 0; 276 277 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 278 if (!ret) 279 atomic_set(&power_gate->jpeg_gated, !enable); 280 281 return ret; 282 } 283 284 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 285 bool enable) 286 { 287 struct smu_power_context *smu_power = &smu->smu_power; 288 struct smu_power_gate *power_gate = &smu_power->power_gate; 289 int ret = 0; 290 291 if (!smu->ppt_funcs->dpm_set_vpe_enable) 292 return 0; 293 294 if (atomic_read(&power_gate->vpe_gated) ^ enable) 295 return 0; 296 297 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 298 if (!ret) 299 atomic_set(&power_gate->vpe_gated, !enable); 300 301 return ret; 302 } 303 304 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 305 bool enable) 306 { 307 struct smu_power_context *smu_power = &smu->smu_power; 308 struct smu_power_gate *power_gate = &smu_power->power_gate; 309 int ret = 0; 310 311 if (!smu->adev->enable_umsch_mm) 312 return 0; 313 314 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 315 return 0; 316 317 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 318 return 0; 319 320 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 321 if (!ret) 322 atomic_set(&power_gate->umsch_mm_gated, !enable); 323 324 return ret; 325 } 326 327 /** 328 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 329 * 330 * @handle: smu_context pointer 331 * @block_type: the IP block to power gate/ungate 332 * @gate: to power gate if true, ungate otherwise 333 * 334 * This API uses no smu->mutex lock protection due to: 335 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 336 * This is guarded to be race condition free by the caller. 337 * 2. Or get called on user setting request of power_dpm_force_performance_level. 338 * Under this case, the smu->mutex lock protection is already enforced on 339 * the parent API smu_force_performance_level of the call path. 340 */ 341 static int smu_dpm_set_power_gate(void *handle, 342 uint32_t block_type, 343 bool gate) 344 { 345 struct smu_context *smu = handle; 346 int ret = 0; 347 348 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 349 dev_WARN(smu->adev->dev, 350 "SMU uninitialized but power %s requested for %u!\n", 351 gate ? "gate" : "ungate", block_type); 352 return -EOPNOTSUPP; 353 } 354 355 switch (block_type) { 356 /* 357 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 358 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 359 */ 360 case AMD_IP_BLOCK_TYPE_UVD: 361 case AMD_IP_BLOCK_TYPE_VCN: 362 ret = smu_dpm_set_vcn_enable(smu, !gate); 363 if (ret) 364 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 365 gate ? "gate" : "ungate"); 366 break; 367 case AMD_IP_BLOCK_TYPE_GFX: 368 ret = smu_gfx_off_control(smu, gate); 369 if (ret) 370 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 371 gate ? "enable" : "disable"); 372 break; 373 case AMD_IP_BLOCK_TYPE_SDMA: 374 ret = smu_powergate_sdma(smu, gate); 375 if (ret) 376 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 377 gate ? "gate" : "ungate"); 378 break; 379 case AMD_IP_BLOCK_TYPE_JPEG: 380 ret = smu_dpm_set_jpeg_enable(smu, !gate); 381 if (ret) 382 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 383 gate ? "gate" : "ungate"); 384 break; 385 case AMD_IP_BLOCK_TYPE_VPE: 386 ret = smu_dpm_set_vpe_enable(smu, !gate); 387 if (ret) 388 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 389 gate ? "gate" : "ungate"); 390 break; 391 default: 392 dev_err(smu->adev->dev, "Unsupported block type!\n"); 393 return -EINVAL; 394 } 395 396 return ret; 397 } 398 399 /** 400 * smu_set_user_clk_dependencies - set user profile clock dependencies 401 * 402 * @smu: smu_context pointer 403 * @clk: enum smu_clk_type type 404 * 405 * Enable/Disable the clock dependency for the @clk type. 406 */ 407 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 408 { 409 if (smu->adev->in_suspend) 410 return; 411 412 if (clk == SMU_MCLK) { 413 smu->user_dpm_profile.clk_dependency = 0; 414 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 415 } else if (clk == SMU_FCLK) { 416 /* MCLK takes precedence over FCLK */ 417 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 418 return; 419 420 smu->user_dpm_profile.clk_dependency = 0; 421 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 422 } else if (clk == SMU_SOCCLK) { 423 /* MCLK takes precedence over SOCCLK */ 424 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 425 return; 426 427 smu->user_dpm_profile.clk_dependency = 0; 428 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 429 } else 430 /* Add clk dependencies here, if any */ 431 return; 432 } 433 434 /** 435 * smu_restore_dpm_user_profile - reinstate user dpm profile 436 * 437 * @smu: smu_context pointer 438 * 439 * Restore the saved user power configurations include power limit, 440 * clock frequencies, fan control mode and fan speed. 441 */ 442 static void smu_restore_dpm_user_profile(struct smu_context *smu) 443 { 444 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 445 int ret = 0; 446 447 if (!smu->adev->in_suspend) 448 return; 449 450 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 451 return; 452 453 /* Enable restore flag */ 454 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 455 456 /* set the user dpm power limit */ 457 if (smu->user_dpm_profile.power_limit) { 458 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 459 if (ret) 460 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 461 } 462 463 /* set the user dpm clock configurations */ 464 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 465 enum smu_clk_type clk_type; 466 467 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 468 /* 469 * Iterate over smu clk type and force the saved user clk 470 * configs, skip if clock dependency is enabled 471 */ 472 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 473 smu->user_dpm_profile.clk_mask[clk_type]) { 474 ret = smu_force_smuclk_levels(smu, clk_type, 475 smu->user_dpm_profile.clk_mask[clk_type]); 476 if (ret) 477 dev_err(smu->adev->dev, 478 "Failed to set clock type = %d\n", clk_type); 479 } 480 } 481 } 482 483 /* set the user dpm fan configurations */ 484 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 485 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 486 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 487 if (ret != -EOPNOTSUPP) { 488 smu->user_dpm_profile.fan_speed_pwm = 0; 489 smu->user_dpm_profile.fan_speed_rpm = 0; 490 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 491 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 492 } 493 494 if (smu->user_dpm_profile.fan_speed_pwm) { 495 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 496 if (ret != -EOPNOTSUPP) 497 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 498 } 499 500 if (smu->user_dpm_profile.fan_speed_rpm) { 501 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 502 if (ret != -EOPNOTSUPP) 503 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 504 } 505 } 506 507 /* Restore user customized OD settings */ 508 if (smu->user_dpm_profile.user_od) { 509 if (smu->ppt_funcs->restore_user_od_settings) { 510 ret = smu->ppt_funcs->restore_user_od_settings(smu); 511 if (ret) 512 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 513 } 514 } 515 516 /* Disable restore flag */ 517 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 518 } 519 520 static int smu_get_power_num_states(void *handle, 521 struct pp_states_info *state_info) 522 { 523 if (!state_info) 524 return -EINVAL; 525 526 /* not support power state */ 527 memset(state_info, 0, sizeof(struct pp_states_info)); 528 state_info->nums = 1; 529 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 530 531 return 0; 532 } 533 534 bool is_support_sw_smu(struct amdgpu_device *adev) 535 { 536 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 537 if (adev->asic_type == CHIP_VEGA20) 538 return false; 539 540 if (amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) 541 return true; 542 543 return false; 544 } 545 546 bool is_support_cclk_dpm(struct amdgpu_device *adev) 547 { 548 struct smu_context *smu = adev->powerplay.pp_handle; 549 550 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 551 return false; 552 553 return true; 554 } 555 556 557 static int smu_sys_get_pp_table(void *handle, 558 char **table) 559 { 560 struct smu_context *smu = handle; 561 struct smu_table_context *smu_table = &smu->smu_table; 562 563 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 564 return -EOPNOTSUPP; 565 566 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 567 return -EINVAL; 568 569 if (smu_table->hardcode_pptable) 570 *table = smu_table->hardcode_pptable; 571 else 572 *table = smu_table->power_play_table; 573 574 return smu_table->power_play_table_size; 575 } 576 577 static int smu_sys_set_pp_table(void *handle, 578 const char *buf, 579 size_t size) 580 { 581 struct smu_context *smu = handle; 582 struct smu_table_context *smu_table = &smu->smu_table; 583 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 584 int ret = 0; 585 586 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 587 return -EOPNOTSUPP; 588 589 if (header->usStructureSize != size) { 590 dev_err(smu->adev->dev, "pp table size not matched !\n"); 591 return -EIO; 592 } 593 594 if (!smu_table->hardcode_pptable) { 595 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 596 if (!smu_table->hardcode_pptable) 597 return -ENOMEM; 598 } 599 600 memcpy(smu_table->hardcode_pptable, buf, size); 601 smu_table->power_play_table = smu_table->hardcode_pptable; 602 smu_table->power_play_table_size = size; 603 604 /* 605 * Special hw_fini action(for Navi1x, the DPMs disablement will be 606 * skipped) may be needed for custom pptable uploading. 607 */ 608 smu->uploading_custom_pp_table = true; 609 610 ret = smu_reset(smu); 611 if (ret) 612 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 613 614 smu->uploading_custom_pp_table = false; 615 616 return ret; 617 } 618 619 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 620 { 621 struct smu_feature *feature = &smu->smu_feature; 622 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 623 int ret = 0; 624 625 /* 626 * With SCPM enabled, the allowed featuremasks setting(via 627 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 628 * That means there is no way to let PMFW knows the settings below. 629 * Thus, we just assume all the features are allowed under 630 * such scenario. 631 */ 632 if (smu->adev->scpm_enabled) { 633 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 634 return 0; 635 } 636 637 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 638 639 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 640 SMU_FEATURE_MAX/32); 641 if (ret) 642 return ret; 643 644 bitmap_or(feature->allowed, feature->allowed, 645 (unsigned long *)allowed_feature_mask, 646 feature->feature_num); 647 648 return ret; 649 } 650 651 static int smu_set_funcs(struct amdgpu_device *adev) 652 { 653 struct smu_context *smu = adev->powerplay.pp_handle; 654 655 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 656 smu->od_enabled = true; 657 658 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 659 case IP_VERSION(11, 0, 0): 660 case IP_VERSION(11, 0, 5): 661 case IP_VERSION(11, 0, 9): 662 navi10_set_ppt_funcs(smu); 663 break; 664 case IP_VERSION(11, 0, 7): 665 case IP_VERSION(11, 0, 11): 666 case IP_VERSION(11, 0, 12): 667 case IP_VERSION(11, 0, 13): 668 sienna_cichlid_set_ppt_funcs(smu); 669 break; 670 case IP_VERSION(12, 0, 0): 671 case IP_VERSION(12, 0, 1): 672 renoir_set_ppt_funcs(smu); 673 break; 674 case IP_VERSION(11, 5, 0): 675 vangogh_set_ppt_funcs(smu); 676 break; 677 case IP_VERSION(13, 0, 1): 678 case IP_VERSION(13, 0, 3): 679 case IP_VERSION(13, 0, 8): 680 yellow_carp_set_ppt_funcs(smu); 681 break; 682 case IP_VERSION(13, 0, 4): 683 case IP_VERSION(13, 0, 11): 684 smu_v13_0_4_set_ppt_funcs(smu); 685 break; 686 case IP_VERSION(13, 0, 5): 687 smu_v13_0_5_set_ppt_funcs(smu); 688 break; 689 case IP_VERSION(11, 0, 8): 690 cyan_skillfish_set_ppt_funcs(smu); 691 break; 692 case IP_VERSION(11, 0, 2): 693 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 694 arcturus_set_ppt_funcs(smu); 695 /* OD is not supported on Arcturus */ 696 smu->od_enabled = false; 697 break; 698 case IP_VERSION(13, 0, 2): 699 aldebaran_set_ppt_funcs(smu); 700 /* Enable pp_od_clk_voltage node */ 701 smu->od_enabled = true; 702 break; 703 case IP_VERSION(13, 0, 0): 704 case IP_VERSION(13, 0, 10): 705 smu_v13_0_0_set_ppt_funcs(smu); 706 break; 707 case IP_VERSION(13, 0, 6): 708 case IP_VERSION(13, 0, 14): 709 smu_v13_0_6_set_ppt_funcs(smu); 710 /* Enable pp_od_clk_voltage node */ 711 smu->od_enabled = true; 712 break; 713 case IP_VERSION(13, 0, 7): 714 smu_v13_0_7_set_ppt_funcs(smu); 715 break; 716 case IP_VERSION(14, 0, 0): 717 case IP_VERSION(14, 0, 1): 718 smu_v14_0_0_set_ppt_funcs(smu); 719 break; 720 case IP_VERSION(14, 0, 2): 721 case IP_VERSION(14, 0, 3): 722 smu_v14_0_2_set_ppt_funcs(smu); 723 break; 724 default: 725 return -EINVAL; 726 } 727 728 return 0; 729 } 730 731 static int smu_early_init(void *handle) 732 { 733 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 734 struct smu_context *smu; 735 int r; 736 737 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 738 if (!smu) 739 return -ENOMEM; 740 741 smu->adev = adev; 742 smu->pm_enabled = !!amdgpu_dpm; 743 smu->is_apu = false; 744 smu->smu_baco.state = SMU_BACO_STATE_NONE; 745 smu->smu_baco.platform_support = false; 746 smu->smu_baco.maco_support = false; 747 smu->user_dpm_profile.fan_mode = -1; 748 749 mutex_init(&smu->message_lock); 750 751 adev->powerplay.pp_handle = smu; 752 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 753 754 r = smu_set_funcs(adev); 755 if (r) 756 return r; 757 return smu_init_microcode(smu); 758 } 759 760 static int smu_set_default_dpm_table(struct smu_context *smu) 761 { 762 struct amdgpu_device *adev = smu->adev; 763 struct smu_power_context *smu_power = &smu->smu_power; 764 struct smu_power_gate *power_gate = &smu_power->power_gate; 765 int vcn_gate, jpeg_gate; 766 int ret = 0; 767 768 if (!smu->ppt_funcs->set_default_dpm_table) 769 return 0; 770 771 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 772 vcn_gate = atomic_read(&power_gate->vcn_gated); 773 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 774 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 775 776 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 777 ret = smu_dpm_set_vcn_enable(smu, true); 778 if (ret) 779 return ret; 780 } 781 782 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 783 ret = smu_dpm_set_jpeg_enable(smu, true); 784 if (ret) 785 goto err_out; 786 } 787 788 ret = smu->ppt_funcs->set_default_dpm_table(smu); 789 if (ret) 790 dev_err(smu->adev->dev, 791 "Failed to setup default dpm clock tables!\n"); 792 793 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 794 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 795 err_out: 796 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 797 smu_dpm_set_vcn_enable(smu, !vcn_gate); 798 799 return ret; 800 } 801 802 static int smu_apply_default_config_table_settings(struct smu_context *smu) 803 { 804 struct amdgpu_device *adev = smu->adev; 805 int ret = 0; 806 807 ret = smu_get_default_config_table_settings(smu, 808 &adev->pm.config_table); 809 if (ret) 810 return ret; 811 812 return smu_set_config_table(smu, &adev->pm.config_table); 813 } 814 815 static int smu_late_init(void *handle) 816 { 817 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 818 struct smu_context *smu = adev->powerplay.pp_handle; 819 int ret = 0; 820 821 smu_set_fine_grain_gfx_freq_parameters(smu); 822 823 if (!smu->pm_enabled) 824 return 0; 825 826 ret = smu_post_init(smu); 827 if (ret) { 828 dev_err(adev->dev, "Failed to post smu init!\n"); 829 return ret; 830 } 831 832 /* 833 * Explicitly notify PMFW the power mode the system in. Since 834 * the PMFW may boot the ASIC with a different mode. 835 * For those supporting ACDC switch via gpio, PMFW will 836 * handle the switch automatically. Driver involvement 837 * is unnecessary. 838 */ 839 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 840 smu_set_ac_dc(smu); 841 842 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 843 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 844 return 0; 845 846 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 847 ret = smu_set_default_od_settings(smu); 848 if (ret) { 849 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 850 return ret; 851 } 852 } 853 854 ret = smu_populate_umd_state_clk(smu); 855 if (ret) { 856 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 857 return ret; 858 } 859 860 ret = smu_get_asic_power_limits(smu, 861 &smu->current_power_limit, 862 &smu->default_power_limit, 863 &smu->max_power_limit, 864 &smu->min_power_limit); 865 if (ret) { 866 dev_err(adev->dev, "Failed to get asic power limits!\n"); 867 return ret; 868 } 869 870 if (!amdgpu_sriov_vf(adev)) 871 smu_get_unique_id(smu); 872 873 smu_get_fan_parameters(smu); 874 875 smu_handle_task(smu, 876 smu->smu_dpm.dpm_level, 877 AMD_PP_TASK_COMPLETE_INIT); 878 879 ret = smu_apply_default_config_table_settings(smu); 880 if (ret && (ret != -EOPNOTSUPP)) { 881 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 882 return ret; 883 } 884 885 smu_restore_dpm_user_profile(smu); 886 887 return 0; 888 } 889 890 static int smu_init_fb_allocations(struct smu_context *smu) 891 { 892 struct amdgpu_device *adev = smu->adev; 893 struct smu_table_context *smu_table = &smu->smu_table; 894 struct smu_table *tables = smu_table->tables; 895 struct smu_table *driver_table = &(smu_table->driver_table); 896 uint32_t max_table_size = 0; 897 int ret, i; 898 899 /* VRAM allocation for tool table */ 900 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 901 ret = amdgpu_bo_create_kernel(adev, 902 tables[SMU_TABLE_PMSTATUSLOG].size, 903 tables[SMU_TABLE_PMSTATUSLOG].align, 904 tables[SMU_TABLE_PMSTATUSLOG].domain, 905 &tables[SMU_TABLE_PMSTATUSLOG].bo, 906 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 907 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 908 if (ret) { 909 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 910 return ret; 911 } 912 } 913 914 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 915 /* VRAM allocation for driver table */ 916 for (i = 0; i < SMU_TABLE_COUNT; i++) { 917 if (tables[i].size == 0) 918 continue; 919 920 /* If one of the tables has VRAM domain restriction, keep it in 921 * VRAM 922 */ 923 if ((tables[i].domain & 924 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 925 AMDGPU_GEM_DOMAIN_VRAM) 926 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 927 928 if (i == SMU_TABLE_PMSTATUSLOG) 929 continue; 930 931 if (max_table_size < tables[i].size) 932 max_table_size = tables[i].size; 933 } 934 935 driver_table->size = max_table_size; 936 driver_table->align = PAGE_SIZE; 937 938 ret = amdgpu_bo_create_kernel(adev, 939 driver_table->size, 940 driver_table->align, 941 driver_table->domain, 942 &driver_table->bo, 943 &driver_table->mc_address, 944 &driver_table->cpu_addr); 945 if (ret) { 946 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 947 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 948 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 949 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 950 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 951 } 952 953 return ret; 954 } 955 956 static int smu_fini_fb_allocations(struct smu_context *smu) 957 { 958 struct smu_table_context *smu_table = &smu->smu_table; 959 struct smu_table *tables = smu_table->tables; 960 struct smu_table *driver_table = &(smu_table->driver_table); 961 962 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 963 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 964 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 965 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 966 967 amdgpu_bo_free_kernel(&driver_table->bo, 968 &driver_table->mc_address, 969 &driver_table->cpu_addr); 970 971 return 0; 972 } 973 974 /** 975 * smu_alloc_memory_pool - allocate memory pool in the system memory 976 * 977 * @smu: amdgpu_device pointer 978 * 979 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 980 * and DramLogSetDramAddr can notify it changed. 981 * 982 * Returns 0 on success, error on failure. 983 */ 984 static int smu_alloc_memory_pool(struct smu_context *smu) 985 { 986 struct amdgpu_device *adev = smu->adev; 987 struct smu_table_context *smu_table = &smu->smu_table; 988 struct smu_table *memory_pool = &smu_table->memory_pool; 989 uint64_t pool_size = smu->pool_size; 990 int ret = 0; 991 992 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 993 return ret; 994 995 memory_pool->size = pool_size; 996 memory_pool->align = PAGE_SIZE; 997 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 998 999 switch (pool_size) { 1000 case SMU_MEMORY_POOL_SIZE_256_MB: 1001 case SMU_MEMORY_POOL_SIZE_512_MB: 1002 case SMU_MEMORY_POOL_SIZE_1_GB: 1003 case SMU_MEMORY_POOL_SIZE_2_GB: 1004 ret = amdgpu_bo_create_kernel(adev, 1005 memory_pool->size, 1006 memory_pool->align, 1007 memory_pool->domain, 1008 &memory_pool->bo, 1009 &memory_pool->mc_address, 1010 &memory_pool->cpu_addr); 1011 if (ret) 1012 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1013 break; 1014 default: 1015 break; 1016 } 1017 1018 return ret; 1019 } 1020 1021 static int smu_free_memory_pool(struct smu_context *smu) 1022 { 1023 struct smu_table_context *smu_table = &smu->smu_table; 1024 struct smu_table *memory_pool = &smu_table->memory_pool; 1025 1026 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1027 return 0; 1028 1029 amdgpu_bo_free_kernel(&memory_pool->bo, 1030 &memory_pool->mc_address, 1031 &memory_pool->cpu_addr); 1032 1033 memset(memory_pool, 0, sizeof(struct smu_table)); 1034 1035 return 0; 1036 } 1037 1038 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1039 { 1040 struct smu_table_context *smu_table = &smu->smu_table; 1041 struct smu_table *dummy_read_1_table = 1042 &smu_table->dummy_read_1_table; 1043 struct amdgpu_device *adev = smu->adev; 1044 int ret = 0; 1045 1046 if (!dummy_read_1_table->size) 1047 return 0; 1048 1049 ret = amdgpu_bo_create_kernel(adev, 1050 dummy_read_1_table->size, 1051 dummy_read_1_table->align, 1052 dummy_read_1_table->domain, 1053 &dummy_read_1_table->bo, 1054 &dummy_read_1_table->mc_address, 1055 &dummy_read_1_table->cpu_addr); 1056 if (ret) 1057 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1058 1059 return ret; 1060 } 1061 1062 static void smu_free_dummy_read_table(struct smu_context *smu) 1063 { 1064 struct smu_table_context *smu_table = &smu->smu_table; 1065 struct smu_table *dummy_read_1_table = 1066 &smu_table->dummy_read_1_table; 1067 1068 1069 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1070 &dummy_read_1_table->mc_address, 1071 &dummy_read_1_table->cpu_addr); 1072 1073 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1074 } 1075 1076 static int smu_smc_table_sw_init(struct smu_context *smu) 1077 { 1078 int ret; 1079 1080 /** 1081 * Create smu_table structure, and init smc tables such as 1082 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1083 */ 1084 ret = smu_init_smc_tables(smu); 1085 if (ret) { 1086 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1087 return ret; 1088 } 1089 1090 /** 1091 * Create smu_power_context structure, and allocate smu_dpm_context and 1092 * context size to fill the smu_power_context data. 1093 */ 1094 ret = smu_init_power(smu); 1095 if (ret) { 1096 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1097 return ret; 1098 } 1099 1100 /* 1101 * allocate vram bos to store smc table contents. 1102 */ 1103 ret = smu_init_fb_allocations(smu); 1104 if (ret) 1105 return ret; 1106 1107 ret = smu_alloc_memory_pool(smu); 1108 if (ret) 1109 return ret; 1110 1111 ret = smu_alloc_dummy_read_table(smu); 1112 if (ret) 1113 return ret; 1114 1115 ret = smu_i2c_init(smu); 1116 if (ret) 1117 return ret; 1118 1119 return 0; 1120 } 1121 1122 static int smu_smc_table_sw_fini(struct smu_context *smu) 1123 { 1124 int ret; 1125 1126 smu_i2c_fini(smu); 1127 1128 smu_free_dummy_read_table(smu); 1129 1130 ret = smu_free_memory_pool(smu); 1131 if (ret) 1132 return ret; 1133 1134 ret = smu_fini_fb_allocations(smu); 1135 if (ret) 1136 return ret; 1137 1138 ret = smu_fini_power(smu); 1139 if (ret) { 1140 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1141 return ret; 1142 } 1143 1144 ret = smu_fini_smc_tables(smu); 1145 if (ret) { 1146 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1147 return ret; 1148 } 1149 1150 return 0; 1151 } 1152 1153 static void smu_throttling_logging_work_fn(struct work_struct *work) 1154 { 1155 struct smu_context *smu = container_of(work, struct smu_context, 1156 throttling_logging_work); 1157 1158 smu_log_thermal_throttling(smu); 1159 } 1160 1161 static void smu_interrupt_work_fn(struct work_struct *work) 1162 { 1163 struct smu_context *smu = container_of(work, struct smu_context, 1164 interrupt_work); 1165 1166 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1167 smu->ppt_funcs->interrupt_work(smu); 1168 } 1169 1170 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1171 { 1172 struct smu_context *smu = 1173 container_of(work, struct smu_context, swctf_delayed_work.work); 1174 struct smu_temperature_range *range = 1175 &smu->thermal_range; 1176 struct amdgpu_device *adev = smu->adev; 1177 uint32_t hotspot_tmp, size; 1178 1179 /* 1180 * If the hotspot temperature is confirmed as below SW CTF setting point 1181 * after the delay enforced, nothing will be done. 1182 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1183 */ 1184 if (range->software_shutdown_temp && 1185 smu->ppt_funcs->read_sensor && 1186 !smu->ppt_funcs->read_sensor(smu, 1187 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1188 &hotspot_tmp, 1189 &size) && 1190 hotspot_tmp / 1000 < range->software_shutdown_temp) 1191 return; 1192 1193 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1194 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1195 orderly_poweroff(true); 1196 } 1197 1198 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1199 { 1200 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1201 struct smu_dpm_policy_ctxt *policy_ctxt; 1202 struct smu_dpm_policy *policy; 1203 1204 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1205 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1206 if (policy) 1207 policy->current_level = XGMI_PLPD_DEFAULT; 1208 return; 1209 } 1210 1211 /* PMFW put PLPD into default policy after enabling the feature */ 1212 if (smu_feature_is_enabled(smu, 1213 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1214 if (policy) 1215 policy->current_level = XGMI_PLPD_DEFAULT; 1216 } else { 1217 policy_ctxt = dpm_ctxt->dpm_policies; 1218 if (policy_ctxt) 1219 policy_ctxt->policy_mask &= 1220 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1221 } 1222 } 1223 1224 static int smu_sw_init(void *handle) 1225 { 1226 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1227 struct smu_context *smu = adev->powerplay.pp_handle; 1228 int ret; 1229 1230 smu->pool_size = adev->pm.smu_prv_buffer_size; 1231 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1232 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1233 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1234 1235 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1236 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1237 atomic64_set(&smu->throttle_int_counter, 0); 1238 smu->watermarks_bitmap = 0; 1239 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1240 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1241 1242 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1243 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1244 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1245 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1246 1247 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1248 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1249 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1250 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1251 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1252 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1253 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1254 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1255 1256 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1257 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1258 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1259 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1260 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1261 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1262 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1263 smu->display_config = &adev->pm.pm_display_cfg; 1264 1265 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1266 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1267 1268 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1269 smu_swctf_delayed_work_handler); 1270 1271 ret = smu_smc_table_sw_init(smu); 1272 if (ret) { 1273 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1274 return ret; 1275 } 1276 1277 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1278 ret = smu_get_vbios_bootup_values(smu); 1279 if (ret) { 1280 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1281 return ret; 1282 } 1283 1284 ret = smu_init_pptable_microcode(smu); 1285 if (ret) { 1286 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1287 return ret; 1288 } 1289 1290 ret = smu_register_irq_handler(smu); 1291 if (ret) { 1292 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1293 return ret; 1294 } 1295 1296 /* If there is no way to query fan control mode, fan control is not supported */ 1297 if (!smu->ppt_funcs->get_fan_control_mode) 1298 smu->adev->pm.no_fan = true; 1299 1300 return 0; 1301 } 1302 1303 static int smu_sw_fini(void *handle) 1304 { 1305 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1306 struct smu_context *smu = adev->powerplay.pp_handle; 1307 int ret; 1308 1309 ret = smu_smc_table_sw_fini(smu); 1310 if (ret) { 1311 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1312 return ret; 1313 } 1314 1315 smu_fini_microcode(smu); 1316 1317 return 0; 1318 } 1319 1320 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1321 { 1322 struct amdgpu_device *adev = smu->adev; 1323 struct smu_temperature_range *range = 1324 &smu->thermal_range; 1325 int ret = 0; 1326 1327 if (!smu->ppt_funcs->get_thermal_temperature_range) 1328 return 0; 1329 1330 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1331 if (ret) 1332 return ret; 1333 1334 adev->pm.dpm.thermal.min_temp = range->min; 1335 adev->pm.dpm.thermal.max_temp = range->max; 1336 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1337 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1338 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1339 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1340 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1341 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1342 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1343 1344 return ret; 1345 } 1346 1347 /** 1348 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1349 * 1350 * @smu: smu_context pointer 1351 * 1352 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1353 * Returns 0 on success, error on failure. 1354 */ 1355 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1356 { 1357 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1358 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1359 struct amdgpu_device *adev = smu->adev; 1360 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1361 uint64_t start, end; 1362 int ret, i, j; 1363 1364 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1365 if (ret) { 1366 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1367 return ret; 1368 } 1369 1370 /* 1371 * The exclusion ranges array we got might be filled with holes and duplicate 1372 * entries. For example: 1373 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1374 * We need to do some sortups to eliminate those holes and duplicate entries. 1375 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1376 */ 1377 for (i = 0; i < num_of_wbrf_ranges; i++) { 1378 start = wifi_bands[i].start; 1379 end = wifi_bands[i].end; 1380 1381 /* get the last valid entry to fill the intermediate hole */ 1382 if (!start && !end) { 1383 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1384 if (wifi_bands[j].start && wifi_bands[j].end) 1385 break; 1386 1387 /* no valid entry left */ 1388 if (j <= i) 1389 break; 1390 1391 start = wifi_bands[i].start = wifi_bands[j].start; 1392 end = wifi_bands[i].end = wifi_bands[j].end; 1393 wifi_bands[j].start = 0; 1394 wifi_bands[j].end = 0; 1395 num_of_wbrf_ranges = j; 1396 } 1397 1398 /* eliminate duplicate entries */ 1399 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1400 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1401 wifi_bands[j].start = 0; 1402 wifi_bands[j].end = 0; 1403 } 1404 } 1405 } 1406 1407 /* Send the sorted wifi_bands to PMFW */ 1408 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1409 /* Try to set the wifi_bands again */ 1410 if (unlikely(ret == -EBUSY)) { 1411 mdelay(5); 1412 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1413 } 1414 1415 return ret; 1416 } 1417 1418 /** 1419 * smu_wbrf_event_handler - handle notify events 1420 * 1421 * @nb: notifier block 1422 * @action: event type 1423 * @_arg: event data 1424 * 1425 * Calls relevant amdgpu function in response to wbrf event 1426 * notification from kernel. 1427 */ 1428 static int smu_wbrf_event_handler(struct notifier_block *nb, 1429 unsigned long action, void *_arg) 1430 { 1431 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1432 1433 switch (action) { 1434 case WBRF_CHANGED: 1435 schedule_delayed_work(&smu->wbrf_delayed_work, 1436 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1437 break; 1438 default: 1439 return NOTIFY_DONE; 1440 } 1441 1442 return NOTIFY_OK; 1443 } 1444 1445 /** 1446 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1447 * 1448 * @work: struct work_struct pointer 1449 * 1450 * Flood is over and driver will consume the latest exclusion ranges. 1451 */ 1452 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1453 { 1454 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1455 1456 smu_wbrf_handle_exclusion_ranges(smu); 1457 } 1458 1459 /** 1460 * smu_wbrf_support_check - check wbrf support 1461 * 1462 * @smu: smu_context pointer 1463 * 1464 * Verifies the ACPI interface whether wbrf is supported. 1465 */ 1466 static void smu_wbrf_support_check(struct smu_context *smu) 1467 { 1468 struct amdgpu_device *adev = smu->adev; 1469 1470 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1471 acpi_amd_wbrf_supported_consumer(adev->dev); 1472 1473 if (smu->wbrf_supported) 1474 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1475 } 1476 1477 /** 1478 * smu_wbrf_init - init driver wbrf support 1479 * 1480 * @smu: smu_context pointer 1481 * 1482 * Verifies the AMD ACPI interfaces and registers with the wbrf 1483 * notifier chain if wbrf feature is supported. 1484 * Returns 0 on success, error on failure. 1485 */ 1486 static int smu_wbrf_init(struct smu_context *smu) 1487 { 1488 int ret; 1489 1490 if (!smu->wbrf_supported) 1491 return 0; 1492 1493 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1494 1495 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1496 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1497 if (ret) 1498 return ret; 1499 1500 /* 1501 * Some wifiband exclusion ranges may be already there 1502 * before our driver loaded. To make sure our driver 1503 * is awared of those exclusion ranges. 1504 */ 1505 schedule_delayed_work(&smu->wbrf_delayed_work, 1506 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1507 1508 return 0; 1509 } 1510 1511 /** 1512 * smu_wbrf_fini - tear down driver wbrf support 1513 * 1514 * @smu: smu_context pointer 1515 * 1516 * Unregisters with the wbrf notifier chain. 1517 */ 1518 static void smu_wbrf_fini(struct smu_context *smu) 1519 { 1520 if (!smu->wbrf_supported) 1521 return; 1522 1523 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1524 1525 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1526 } 1527 1528 static int smu_smc_hw_setup(struct smu_context *smu) 1529 { 1530 struct smu_feature *feature = &smu->smu_feature; 1531 struct amdgpu_device *adev = smu->adev; 1532 uint8_t pcie_gen = 0, pcie_width = 0; 1533 uint64_t features_supported; 1534 int ret = 0; 1535 1536 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1537 case IP_VERSION(11, 0, 7): 1538 case IP_VERSION(11, 0, 11): 1539 case IP_VERSION(11, 5, 0): 1540 case IP_VERSION(11, 0, 12): 1541 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1542 dev_info(adev->dev, "dpm has been enabled\n"); 1543 ret = smu_system_features_control(smu, true); 1544 if (ret) 1545 dev_err(adev->dev, "Failed system features control!\n"); 1546 return ret; 1547 } 1548 break; 1549 default: 1550 break; 1551 } 1552 1553 ret = smu_init_display_count(smu, 0); 1554 if (ret) { 1555 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1556 return ret; 1557 } 1558 1559 ret = smu_set_driver_table_location(smu); 1560 if (ret) { 1561 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1562 return ret; 1563 } 1564 1565 /* 1566 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1567 */ 1568 ret = smu_set_tool_table_location(smu); 1569 if (ret) { 1570 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1571 return ret; 1572 } 1573 1574 /* 1575 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1576 * pool location. 1577 */ 1578 ret = smu_notify_memory_pool_location(smu); 1579 if (ret) { 1580 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1581 return ret; 1582 } 1583 1584 /* 1585 * It is assumed the pptable used before runpm is same as 1586 * the one used afterwards. Thus, we can reuse the stored 1587 * copy and do not need to resetup the pptable again. 1588 */ 1589 if (!adev->in_runpm) { 1590 ret = smu_setup_pptable(smu); 1591 if (ret) { 1592 dev_err(adev->dev, "Failed to setup pptable!\n"); 1593 return ret; 1594 } 1595 } 1596 1597 /* smu_dump_pptable(smu); */ 1598 1599 /* 1600 * With SCPM enabled, PSP is responsible for the PPTable transferring 1601 * (to SMU). Driver involvement is not needed and permitted. 1602 */ 1603 if (!adev->scpm_enabled) { 1604 /* 1605 * Copy pptable bo in the vram to smc with SMU MSGs such as 1606 * SetDriverDramAddr and TransferTableDram2Smu. 1607 */ 1608 ret = smu_write_pptable(smu); 1609 if (ret) { 1610 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1611 return ret; 1612 } 1613 } 1614 1615 /* issue Run*Btc msg */ 1616 ret = smu_run_btc(smu); 1617 if (ret) 1618 return ret; 1619 1620 /* Enable UclkShadow on wbrf supported */ 1621 if (smu->wbrf_supported) { 1622 ret = smu_enable_uclk_shadow(smu, true); 1623 if (ret) { 1624 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1625 return ret; 1626 } 1627 } 1628 1629 /* 1630 * With SCPM enabled, these actions(and relevant messages) are 1631 * not needed and permitted. 1632 */ 1633 if (!adev->scpm_enabled) { 1634 ret = smu_feature_set_allowed_mask(smu); 1635 if (ret) { 1636 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1637 return ret; 1638 } 1639 } 1640 1641 ret = smu_system_features_control(smu, true); 1642 if (ret) { 1643 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1644 return ret; 1645 } 1646 1647 smu_init_xgmi_plpd_mode(smu); 1648 1649 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1650 if (ret) { 1651 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1652 return ret; 1653 } 1654 bitmap_copy(feature->supported, 1655 (unsigned long *)&features_supported, 1656 feature->feature_num); 1657 1658 if (!smu_is_dpm_running(smu)) 1659 dev_info(adev->dev, "dpm has been disabled\n"); 1660 1661 /* 1662 * Set initialized values (get from vbios) to dpm tables context such as 1663 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1664 * type of clks. 1665 */ 1666 ret = smu_set_default_dpm_table(smu); 1667 if (ret) { 1668 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1669 return ret; 1670 } 1671 1672 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1673 pcie_gen = 3; 1674 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1675 pcie_gen = 2; 1676 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1677 pcie_gen = 1; 1678 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1679 pcie_gen = 0; 1680 1681 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1682 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1683 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1684 */ 1685 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1686 pcie_width = 6; 1687 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1688 pcie_width = 5; 1689 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1690 pcie_width = 4; 1691 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1692 pcie_width = 3; 1693 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1694 pcie_width = 2; 1695 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1696 pcie_width = 1; 1697 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1698 if (ret) { 1699 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1700 return ret; 1701 } 1702 1703 ret = smu_get_thermal_temperature_range(smu); 1704 if (ret) { 1705 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1706 return ret; 1707 } 1708 1709 ret = smu_enable_thermal_alert(smu); 1710 if (ret) { 1711 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1712 return ret; 1713 } 1714 1715 ret = smu_notify_display_change(smu); 1716 if (ret) { 1717 dev_err(adev->dev, "Failed to notify display change!\n"); 1718 return ret; 1719 } 1720 1721 /* 1722 * Set min deep sleep dce fclk with bootup value from vbios via 1723 * SetMinDeepSleepDcefclk MSG. 1724 */ 1725 ret = smu_set_min_dcef_deep_sleep(smu, 1726 smu->smu_table.boot_values.dcefclk / 100); 1727 if (ret) { 1728 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1729 return ret; 1730 } 1731 1732 /* Init wbrf support. Properly setup the notifier */ 1733 ret = smu_wbrf_init(smu); 1734 if (ret) 1735 dev_err(adev->dev, "Error during wbrf init call\n"); 1736 1737 return ret; 1738 } 1739 1740 static int smu_start_smc_engine(struct smu_context *smu) 1741 { 1742 struct amdgpu_device *adev = smu->adev; 1743 int ret = 0; 1744 1745 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1746 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1747 if (smu->ppt_funcs->load_microcode) { 1748 ret = smu->ppt_funcs->load_microcode(smu); 1749 if (ret) 1750 return ret; 1751 } 1752 } 1753 } 1754 1755 if (smu->ppt_funcs->check_fw_status) { 1756 ret = smu->ppt_funcs->check_fw_status(smu); 1757 if (ret) { 1758 dev_err(adev->dev, "SMC is not ready\n"); 1759 return ret; 1760 } 1761 } 1762 1763 /* 1764 * Send msg GetDriverIfVersion to check if the return value is equal 1765 * with DRIVER_IF_VERSION of smc header. 1766 */ 1767 ret = smu_check_fw_version(smu); 1768 if (ret) 1769 return ret; 1770 1771 return ret; 1772 } 1773 1774 static int smu_hw_init(void *handle) 1775 { 1776 int ret; 1777 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1778 struct smu_context *smu = adev->powerplay.pp_handle; 1779 1780 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1781 smu->pm_enabled = false; 1782 return 0; 1783 } 1784 1785 ret = smu_start_smc_engine(smu); 1786 if (ret) { 1787 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1788 return ret; 1789 } 1790 1791 /* 1792 * Check whether wbrf is supported. This needs to be done 1793 * before SMU setup starts since part of SMU configuration 1794 * relies on this. 1795 */ 1796 smu_wbrf_support_check(smu); 1797 1798 if (smu->is_apu) { 1799 ret = smu_set_gfx_imu_enable(smu); 1800 if (ret) 1801 return ret; 1802 smu_dpm_set_vcn_enable(smu, true); 1803 smu_dpm_set_jpeg_enable(smu, true); 1804 smu_dpm_set_vpe_enable(smu, true); 1805 smu_dpm_set_umsch_mm_enable(smu, true); 1806 smu_set_gfx_cgpg(smu, true); 1807 } 1808 1809 if (!smu->pm_enabled) 1810 return 0; 1811 1812 ret = smu_get_driver_allowed_feature_mask(smu); 1813 if (ret) 1814 return ret; 1815 1816 ret = smu_smc_hw_setup(smu); 1817 if (ret) { 1818 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1819 return ret; 1820 } 1821 1822 /* 1823 * Move maximum sustainable clock retrieving here considering 1824 * 1. It is not needed on resume(from S3). 1825 * 2. DAL settings come between .hw_init and .late_init of SMU. 1826 * And DAL needs to know the maximum sustainable clocks. Thus 1827 * it cannot be put in .late_init(). 1828 */ 1829 ret = smu_init_max_sustainable_clocks(smu); 1830 if (ret) { 1831 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1832 return ret; 1833 } 1834 1835 adev->pm.dpm_enabled = true; 1836 1837 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1838 1839 return 0; 1840 } 1841 1842 static int smu_disable_dpms(struct smu_context *smu) 1843 { 1844 struct amdgpu_device *adev = smu->adev; 1845 int ret = 0; 1846 bool use_baco = !smu->is_apu && 1847 ((amdgpu_in_reset(adev) && 1848 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1849 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1850 1851 /* 1852 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1853 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1854 */ 1855 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1856 case IP_VERSION(13, 0, 0): 1857 case IP_VERSION(13, 0, 7): 1858 case IP_VERSION(13, 0, 10): 1859 case IP_VERSION(14, 0, 2): 1860 case IP_VERSION(14, 0, 3): 1861 return 0; 1862 default: 1863 break; 1864 } 1865 1866 /* 1867 * For custom pptable uploading, skip the DPM features 1868 * disable process on Navi1x ASICs. 1869 * - As the gfx related features are under control of 1870 * RLC on those ASICs. RLC reinitialization will be 1871 * needed to reenable them. That will cost much more 1872 * efforts. 1873 * 1874 * - SMU firmware can handle the DPM reenablement 1875 * properly. 1876 */ 1877 if (smu->uploading_custom_pp_table) { 1878 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1879 case IP_VERSION(11, 0, 0): 1880 case IP_VERSION(11, 0, 5): 1881 case IP_VERSION(11, 0, 9): 1882 case IP_VERSION(11, 0, 7): 1883 case IP_VERSION(11, 0, 11): 1884 case IP_VERSION(11, 5, 0): 1885 case IP_VERSION(11, 0, 12): 1886 case IP_VERSION(11, 0, 13): 1887 return 0; 1888 default: 1889 break; 1890 } 1891 } 1892 1893 /* 1894 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1895 * on BACO in. Driver involvement is unnecessary. 1896 */ 1897 if (use_baco) { 1898 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1899 case IP_VERSION(11, 0, 7): 1900 case IP_VERSION(11, 0, 0): 1901 case IP_VERSION(11, 0, 5): 1902 case IP_VERSION(11, 0, 9): 1903 case IP_VERSION(13, 0, 7): 1904 return 0; 1905 default: 1906 break; 1907 } 1908 } 1909 1910 /* 1911 * For SMU 13.0.4/11 and 14.0.0, PMFW will handle the features disablement properly 1912 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1913 */ 1914 if (amdgpu_in_reset(adev) || adev->in_s0ix) { 1915 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1916 case IP_VERSION(13, 0, 4): 1917 case IP_VERSION(13, 0, 11): 1918 case IP_VERSION(14, 0, 0): 1919 case IP_VERSION(14, 0, 1): 1920 return 0; 1921 default: 1922 break; 1923 } 1924 } 1925 1926 /* 1927 * For gpu reset, runpm and hibernation through BACO, 1928 * BACO feature has to be kept enabled. 1929 */ 1930 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1931 ret = smu_disable_all_features_with_exception(smu, 1932 SMU_FEATURE_BACO_BIT); 1933 if (ret) 1934 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1935 } else { 1936 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1937 if (!adev->scpm_enabled) { 1938 ret = smu_system_features_control(smu, false); 1939 if (ret) 1940 dev_err(adev->dev, "Failed to disable smu features.\n"); 1941 } 1942 } 1943 1944 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1945 * otherwise SMU will hang while interacting with RLC if RLC is halted 1946 * this is a WA for Vangogh asic which fix the SMU hang issue. 1947 */ 1948 ret = smu_notify_rlc_state(smu, false); 1949 if (ret) { 1950 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1951 return ret; 1952 } 1953 1954 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1955 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1956 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1957 adev->gfx.rlc.funcs->stop(adev); 1958 1959 return ret; 1960 } 1961 1962 static int smu_smc_hw_cleanup(struct smu_context *smu) 1963 { 1964 struct amdgpu_device *adev = smu->adev; 1965 int ret = 0; 1966 1967 smu_wbrf_fini(smu); 1968 1969 cancel_work_sync(&smu->throttling_logging_work); 1970 cancel_work_sync(&smu->interrupt_work); 1971 1972 ret = smu_disable_thermal_alert(smu); 1973 if (ret) { 1974 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1975 return ret; 1976 } 1977 1978 cancel_delayed_work_sync(&smu->swctf_delayed_work); 1979 1980 ret = smu_disable_dpms(smu); 1981 if (ret) { 1982 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1983 return ret; 1984 } 1985 1986 return 0; 1987 } 1988 1989 static int smu_reset_mp1_state(struct smu_context *smu) 1990 { 1991 struct amdgpu_device *adev = smu->adev; 1992 int ret = 0; 1993 1994 if ((!adev->in_runpm) && (!adev->in_suspend) && 1995 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 1996 IP_VERSION(13, 0, 10) && 1997 !amdgpu_device_has_display_hardware(adev)) 1998 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 1999 2000 return ret; 2001 } 2002 2003 static int smu_hw_fini(void *handle) 2004 { 2005 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2006 struct smu_context *smu = adev->powerplay.pp_handle; 2007 int ret; 2008 2009 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2010 return 0; 2011 2012 smu_dpm_set_vcn_enable(smu, false); 2013 smu_dpm_set_jpeg_enable(smu, false); 2014 smu_dpm_set_vpe_enable(smu, false); 2015 smu_dpm_set_umsch_mm_enable(smu, false); 2016 2017 adev->vcn.cur_state = AMD_PG_STATE_GATE; 2018 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2019 2020 if (!smu->pm_enabled) 2021 return 0; 2022 2023 adev->pm.dpm_enabled = false; 2024 2025 ret = smu_smc_hw_cleanup(smu); 2026 if (ret) 2027 return ret; 2028 2029 ret = smu_reset_mp1_state(smu); 2030 if (ret) 2031 return ret; 2032 2033 return 0; 2034 } 2035 2036 static void smu_late_fini(void *handle) 2037 { 2038 struct amdgpu_device *adev = handle; 2039 struct smu_context *smu = adev->powerplay.pp_handle; 2040 2041 kfree(smu); 2042 } 2043 2044 static int smu_reset(struct smu_context *smu) 2045 { 2046 struct amdgpu_device *adev = smu->adev; 2047 int ret; 2048 2049 ret = smu_hw_fini(adev); 2050 if (ret) 2051 return ret; 2052 2053 ret = smu_hw_init(adev); 2054 if (ret) 2055 return ret; 2056 2057 ret = smu_late_init(adev); 2058 if (ret) 2059 return ret; 2060 2061 return 0; 2062 } 2063 2064 static int smu_suspend(void *handle) 2065 { 2066 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2067 struct smu_context *smu = adev->powerplay.pp_handle; 2068 int ret; 2069 uint64_t count; 2070 2071 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2072 return 0; 2073 2074 if (!smu->pm_enabled) 2075 return 0; 2076 2077 adev->pm.dpm_enabled = false; 2078 2079 ret = smu_smc_hw_cleanup(smu); 2080 if (ret) 2081 return ret; 2082 2083 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2084 2085 smu_set_gfx_cgpg(smu, false); 2086 2087 /* 2088 * pwfw resets entrycount when device is suspended, so we save the 2089 * last value to be used when we resume to keep it consistent 2090 */ 2091 ret = smu_get_entrycount_gfxoff(smu, &count); 2092 if (!ret) 2093 adev->gfx.gfx_off_entrycount = count; 2094 2095 return 0; 2096 } 2097 2098 static int smu_resume(void *handle) 2099 { 2100 int ret; 2101 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2102 struct smu_context *smu = adev->powerplay.pp_handle; 2103 2104 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2105 return 0; 2106 2107 if (!smu->pm_enabled) 2108 return 0; 2109 2110 dev_info(adev->dev, "SMU is resuming...\n"); 2111 2112 ret = smu_start_smc_engine(smu); 2113 if (ret) { 2114 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2115 return ret; 2116 } 2117 2118 ret = smu_smc_hw_setup(smu); 2119 if (ret) { 2120 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2121 return ret; 2122 } 2123 2124 ret = smu_set_gfx_imu_enable(smu); 2125 if (ret) 2126 return ret; 2127 2128 smu_set_gfx_cgpg(smu, true); 2129 2130 smu->disable_uclk_switch = 0; 2131 2132 adev->pm.dpm_enabled = true; 2133 2134 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2135 2136 return 0; 2137 } 2138 2139 static int smu_display_configuration_change(void *handle, 2140 const struct amd_pp_display_configuration *display_config) 2141 { 2142 struct smu_context *smu = handle; 2143 2144 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2145 return -EOPNOTSUPP; 2146 2147 if (!display_config) 2148 return -EINVAL; 2149 2150 smu_set_min_dcef_deep_sleep(smu, 2151 display_config->min_dcef_deep_sleep_set_clk / 100); 2152 2153 return 0; 2154 } 2155 2156 static int smu_set_clockgating_state(void *handle, 2157 enum amd_clockgating_state state) 2158 { 2159 return 0; 2160 } 2161 2162 static int smu_set_powergating_state(void *handle, 2163 enum amd_powergating_state state) 2164 { 2165 return 0; 2166 } 2167 2168 static int smu_enable_umd_pstate(void *handle, 2169 enum amd_dpm_forced_level *level) 2170 { 2171 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2172 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2173 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2174 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2175 2176 struct smu_context *smu = (struct smu_context*)(handle); 2177 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2178 2179 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2180 return -EINVAL; 2181 2182 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2183 /* enter umd pstate, save current level, disable gfx cg*/ 2184 if (*level & profile_mode_mask) { 2185 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2186 smu_gpo_control(smu, false); 2187 smu_gfx_ulv_control(smu, false); 2188 smu_deep_sleep_control(smu, false); 2189 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2190 } 2191 } else { 2192 /* exit umd pstate, restore level, enable gfx cg*/ 2193 if (!(*level & profile_mode_mask)) { 2194 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2195 *level = smu_dpm_ctx->saved_dpm_level; 2196 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2197 smu_deep_sleep_control(smu, true); 2198 smu_gfx_ulv_control(smu, true); 2199 smu_gpo_control(smu, true); 2200 } 2201 } 2202 2203 return 0; 2204 } 2205 2206 static int smu_bump_power_profile_mode(struct smu_context *smu, 2207 long *param, 2208 uint32_t param_size) 2209 { 2210 int ret = 0; 2211 2212 if (smu->ppt_funcs->set_power_profile_mode) 2213 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2214 2215 return ret; 2216 } 2217 2218 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2219 enum amd_dpm_forced_level level, 2220 bool skip_display_settings) 2221 { 2222 int ret = 0; 2223 int index = 0; 2224 long workload[1]; 2225 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2226 2227 if (!skip_display_settings) { 2228 ret = smu_display_config_changed(smu); 2229 if (ret) { 2230 dev_err(smu->adev->dev, "Failed to change display config!"); 2231 return ret; 2232 } 2233 } 2234 2235 ret = smu_apply_clocks_adjust_rules(smu); 2236 if (ret) { 2237 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2238 return ret; 2239 } 2240 2241 if (!skip_display_settings) { 2242 ret = smu_notify_smc_display_config(smu); 2243 if (ret) { 2244 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2245 return ret; 2246 } 2247 } 2248 2249 if (smu_dpm_ctx->dpm_level != level) { 2250 ret = smu_asic_set_performance_level(smu, level); 2251 if (ret) { 2252 dev_err(smu->adev->dev, "Failed to set performance level!"); 2253 return ret; 2254 } 2255 2256 /* update the saved copy */ 2257 smu_dpm_ctx->dpm_level = level; 2258 } 2259 2260 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2261 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2262 index = fls(smu->workload_mask); 2263 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2264 workload[0] = smu->workload_setting[index]; 2265 2266 if (smu->power_profile_mode != workload[0]) 2267 smu_bump_power_profile_mode(smu, workload, 0); 2268 } 2269 2270 return ret; 2271 } 2272 2273 static int smu_handle_task(struct smu_context *smu, 2274 enum amd_dpm_forced_level level, 2275 enum amd_pp_task task_id) 2276 { 2277 int ret = 0; 2278 2279 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2280 return -EOPNOTSUPP; 2281 2282 switch (task_id) { 2283 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2284 ret = smu_pre_display_config_changed(smu); 2285 if (ret) 2286 return ret; 2287 ret = smu_adjust_power_state_dynamic(smu, level, false); 2288 break; 2289 case AMD_PP_TASK_COMPLETE_INIT: 2290 case AMD_PP_TASK_READJUST_POWER_STATE: 2291 ret = smu_adjust_power_state_dynamic(smu, level, true); 2292 break; 2293 default: 2294 break; 2295 } 2296 2297 return ret; 2298 } 2299 2300 static int smu_handle_dpm_task(void *handle, 2301 enum amd_pp_task task_id, 2302 enum amd_pm_state_type *user_state) 2303 { 2304 struct smu_context *smu = handle; 2305 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2306 2307 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2308 2309 } 2310 2311 static int smu_switch_power_profile(void *handle, 2312 enum PP_SMC_POWER_PROFILE type, 2313 bool en) 2314 { 2315 struct smu_context *smu = handle; 2316 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2317 long workload[1]; 2318 uint32_t index; 2319 2320 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2321 return -EOPNOTSUPP; 2322 2323 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2324 return -EINVAL; 2325 2326 if (!en) { 2327 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 2328 index = fls(smu->workload_mask); 2329 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2330 workload[0] = smu->workload_setting[index]; 2331 } else { 2332 smu->workload_mask |= (1 << smu->workload_prority[type]); 2333 index = fls(smu->workload_mask); 2334 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2335 workload[0] = smu->workload_setting[index]; 2336 } 2337 2338 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2339 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2340 smu_bump_power_profile_mode(smu, workload, 0); 2341 2342 return 0; 2343 } 2344 2345 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2346 { 2347 struct smu_context *smu = handle; 2348 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2349 2350 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2351 return -EOPNOTSUPP; 2352 2353 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2354 return -EINVAL; 2355 2356 return smu_dpm_ctx->dpm_level; 2357 } 2358 2359 static int smu_force_performance_level(void *handle, 2360 enum amd_dpm_forced_level level) 2361 { 2362 struct smu_context *smu = handle; 2363 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2364 int ret = 0; 2365 2366 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2367 return -EOPNOTSUPP; 2368 2369 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2370 return -EINVAL; 2371 2372 ret = smu_enable_umd_pstate(smu, &level); 2373 if (ret) 2374 return ret; 2375 2376 ret = smu_handle_task(smu, level, 2377 AMD_PP_TASK_READJUST_POWER_STATE); 2378 2379 /* reset user dpm clock state */ 2380 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2381 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2382 smu->user_dpm_profile.clk_dependency = 0; 2383 } 2384 2385 return ret; 2386 } 2387 2388 static int smu_set_display_count(void *handle, uint32_t count) 2389 { 2390 struct smu_context *smu = handle; 2391 2392 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2393 return -EOPNOTSUPP; 2394 2395 return smu_init_display_count(smu, count); 2396 } 2397 2398 static int smu_force_smuclk_levels(struct smu_context *smu, 2399 enum smu_clk_type clk_type, 2400 uint32_t mask) 2401 { 2402 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2403 int ret = 0; 2404 2405 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2406 return -EOPNOTSUPP; 2407 2408 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2409 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2410 return -EINVAL; 2411 } 2412 2413 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2414 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2415 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2416 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2417 smu_set_user_clk_dependencies(smu, clk_type); 2418 } 2419 } 2420 2421 return ret; 2422 } 2423 2424 static int smu_force_ppclk_levels(void *handle, 2425 enum pp_clock_type type, 2426 uint32_t mask) 2427 { 2428 struct smu_context *smu = handle; 2429 enum smu_clk_type clk_type; 2430 2431 switch (type) { 2432 case PP_SCLK: 2433 clk_type = SMU_SCLK; break; 2434 case PP_MCLK: 2435 clk_type = SMU_MCLK; break; 2436 case PP_PCIE: 2437 clk_type = SMU_PCIE; break; 2438 case PP_SOCCLK: 2439 clk_type = SMU_SOCCLK; break; 2440 case PP_FCLK: 2441 clk_type = SMU_FCLK; break; 2442 case PP_DCEFCLK: 2443 clk_type = SMU_DCEFCLK; break; 2444 case PP_VCLK: 2445 clk_type = SMU_VCLK; break; 2446 case PP_VCLK1: 2447 clk_type = SMU_VCLK1; break; 2448 case PP_DCLK: 2449 clk_type = SMU_DCLK; break; 2450 case PP_DCLK1: 2451 clk_type = SMU_DCLK1; break; 2452 case OD_SCLK: 2453 clk_type = SMU_OD_SCLK; break; 2454 case OD_MCLK: 2455 clk_type = SMU_OD_MCLK; break; 2456 case OD_VDDC_CURVE: 2457 clk_type = SMU_OD_VDDC_CURVE; break; 2458 case OD_RANGE: 2459 clk_type = SMU_OD_RANGE; break; 2460 default: 2461 return -EINVAL; 2462 } 2463 2464 return smu_force_smuclk_levels(smu, clk_type, mask); 2465 } 2466 2467 /* 2468 * On system suspending or resetting, the dpm_enabled 2469 * flag will be cleared. So that those SMU services which 2470 * are not supported will be gated. 2471 * However, the mp1 state setting should still be granted 2472 * even if the dpm_enabled cleared. 2473 */ 2474 static int smu_set_mp1_state(void *handle, 2475 enum pp_mp1_state mp1_state) 2476 { 2477 struct smu_context *smu = handle; 2478 int ret = 0; 2479 2480 if (!smu->pm_enabled) 2481 return -EOPNOTSUPP; 2482 2483 if (smu->ppt_funcs && 2484 smu->ppt_funcs->set_mp1_state) 2485 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2486 2487 return ret; 2488 } 2489 2490 static int smu_set_df_cstate(void *handle, 2491 enum pp_df_cstate state) 2492 { 2493 struct smu_context *smu = handle; 2494 int ret = 0; 2495 2496 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2497 return -EOPNOTSUPP; 2498 2499 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2500 return 0; 2501 2502 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2503 if (ret) 2504 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2505 2506 return ret; 2507 } 2508 2509 int smu_write_watermarks_table(struct smu_context *smu) 2510 { 2511 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2512 return -EOPNOTSUPP; 2513 2514 return smu_set_watermarks_table(smu, NULL); 2515 } 2516 2517 static int smu_set_watermarks_for_clock_ranges(void *handle, 2518 struct pp_smu_wm_range_sets *clock_ranges) 2519 { 2520 struct smu_context *smu = handle; 2521 2522 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2523 return -EOPNOTSUPP; 2524 2525 if (smu->disable_watermark) 2526 return 0; 2527 2528 return smu_set_watermarks_table(smu, clock_ranges); 2529 } 2530 2531 int smu_set_ac_dc(struct smu_context *smu) 2532 { 2533 int ret = 0; 2534 2535 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2536 return -EOPNOTSUPP; 2537 2538 /* controlled by firmware */ 2539 if (smu->dc_controlled_by_gpio) 2540 return 0; 2541 2542 ret = smu_set_power_source(smu, 2543 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2544 SMU_POWER_SOURCE_DC); 2545 if (ret) 2546 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2547 smu->adev->pm.ac_power ? "AC" : "DC"); 2548 2549 return ret; 2550 } 2551 2552 const struct amd_ip_funcs smu_ip_funcs = { 2553 .name = "smu", 2554 .early_init = smu_early_init, 2555 .late_init = smu_late_init, 2556 .sw_init = smu_sw_init, 2557 .sw_fini = smu_sw_fini, 2558 .hw_init = smu_hw_init, 2559 .hw_fini = smu_hw_fini, 2560 .late_fini = smu_late_fini, 2561 .suspend = smu_suspend, 2562 .resume = smu_resume, 2563 .is_idle = NULL, 2564 .check_soft_reset = NULL, 2565 .wait_for_idle = NULL, 2566 .soft_reset = NULL, 2567 .set_clockgating_state = smu_set_clockgating_state, 2568 .set_powergating_state = smu_set_powergating_state, 2569 }; 2570 2571 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2572 .type = AMD_IP_BLOCK_TYPE_SMC, 2573 .major = 11, 2574 .minor = 0, 2575 .rev = 0, 2576 .funcs = &smu_ip_funcs, 2577 }; 2578 2579 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2580 .type = AMD_IP_BLOCK_TYPE_SMC, 2581 .major = 12, 2582 .minor = 0, 2583 .rev = 0, 2584 .funcs = &smu_ip_funcs, 2585 }; 2586 2587 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2588 .type = AMD_IP_BLOCK_TYPE_SMC, 2589 .major = 13, 2590 .minor = 0, 2591 .rev = 0, 2592 .funcs = &smu_ip_funcs, 2593 }; 2594 2595 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2596 .type = AMD_IP_BLOCK_TYPE_SMC, 2597 .major = 14, 2598 .minor = 0, 2599 .rev = 0, 2600 .funcs = &smu_ip_funcs, 2601 }; 2602 2603 static int smu_load_microcode(void *handle) 2604 { 2605 struct smu_context *smu = handle; 2606 struct amdgpu_device *adev = smu->adev; 2607 int ret = 0; 2608 2609 if (!smu->pm_enabled) 2610 return -EOPNOTSUPP; 2611 2612 /* This should be used for non PSP loading */ 2613 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2614 return 0; 2615 2616 if (smu->ppt_funcs->load_microcode) { 2617 ret = smu->ppt_funcs->load_microcode(smu); 2618 if (ret) { 2619 dev_err(adev->dev, "Load microcode failed\n"); 2620 return ret; 2621 } 2622 } 2623 2624 if (smu->ppt_funcs->check_fw_status) { 2625 ret = smu->ppt_funcs->check_fw_status(smu); 2626 if (ret) { 2627 dev_err(adev->dev, "SMC is not ready\n"); 2628 return ret; 2629 } 2630 } 2631 2632 return ret; 2633 } 2634 2635 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2636 { 2637 int ret = 0; 2638 2639 if (smu->ppt_funcs->set_gfx_cgpg) 2640 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2641 2642 return ret; 2643 } 2644 2645 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2646 { 2647 struct smu_context *smu = handle; 2648 int ret = 0; 2649 2650 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2651 return -EOPNOTSUPP; 2652 2653 if (!smu->ppt_funcs->set_fan_speed_rpm) 2654 return -EOPNOTSUPP; 2655 2656 if (speed == U32_MAX) 2657 return -EINVAL; 2658 2659 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2660 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2661 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2662 smu->user_dpm_profile.fan_speed_rpm = speed; 2663 2664 /* Override custom PWM setting as they cannot co-exist */ 2665 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2666 smu->user_dpm_profile.fan_speed_pwm = 0; 2667 } 2668 2669 return ret; 2670 } 2671 2672 /** 2673 * smu_get_power_limit - Request one of the SMU Power Limits 2674 * 2675 * @handle: pointer to smu context 2676 * @limit: requested limit is written back to this variable 2677 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2678 * @pp_power_type: &pp_power_type type of power 2679 * Return: 0 on success, <0 on error 2680 * 2681 */ 2682 int smu_get_power_limit(void *handle, 2683 uint32_t *limit, 2684 enum pp_power_limit_level pp_limit_level, 2685 enum pp_power_type pp_power_type) 2686 { 2687 struct smu_context *smu = handle; 2688 struct amdgpu_device *adev = smu->adev; 2689 enum smu_ppt_limit_level limit_level; 2690 uint32_t limit_type; 2691 int ret = 0; 2692 2693 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2694 return -EOPNOTSUPP; 2695 2696 switch (pp_power_type) { 2697 case PP_PWR_TYPE_SUSTAINED: 2698 limit_type = SMU_DEFAULT_PPT_LIMIT; 2699 break; 2700 case PP_PWR_TYPE_FAST: 2701 limit_type = SMU_FAST_PPT_LIMIT; 2702 break; 2703 default: 2704 return -EOPNOTSUPP; 2705 } 2706 2707 switch (pp_limit_level) { 2708 case PP_PWR_LIMIT_CURRENT: 2709 limit_level = SMU_PPT_LIMIT_CURRENT; 2710 break; 2711 case PP_PWR_LIMIT_DEFAULT: 2712 limit_level = SMU_PPT_LIMIT_DEFAULT; 2713 break; 2714 case PP_PWR_LIMIT_MAX: 2715 limit_level = SMU_PPT_LIMIT_MAX; 2716 break; 2717 case PP_PWR_LIMIT_MIN: 2718 limit_level = SMU_PPT_LIMIT_MIN; 2719 break; 2720 default: 2721 return -EOPNOTSUPP; 2722 } 2723 2724 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2725 if (smu->ppt_funcs->get_ppt_limit) 2726 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2727 } else { 2728 switch (limit_level) { 2729 case SMU_PPT_LIMIT_CURRENT: 2730 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2731 case IP_VERSION(13, 0, 2): 2732 case IP_VERSION(13, 0, 6): 2733 case IP_VERSION(13, 0, 14): 2734 case IP_VERSION(11, 0, 7): 2735 case IP_VERSION(11, 0, 11): 2736 case IP_VERSION(11, 0, 12): 2737 case IP_VERSION(11, 0, 13): 2738 ret = smu_get_asic_power_limits(smu, 2739 &smu->current_power_limit, 2740 NULL, NULL, NULL); 2741 break; 2742 default: 2743 break; 2744 } 2745 *limit = smu->current_power_limit; 2746 break; 2747 case SMU_PPT_LIMIT_DEFAULT: 2748 *limit = smu->default_power_limit; 2749 break; 2750 case SMU_PPT_LIMIT_MAX: 2751 *limit = smu->max_power_limit; 2752 break; 2753 case SMU_PPT_LIMIT_MIN: 2754 *limit = smu->min_power_limit; 2755 break; 2756 default: 2757 return -EINVAL; 2758 } 2759 } 2760 2761 return ret; 2762 } 2763 2764 static int smu_set_power_limit(void *handle, uint32_t limit) 2765 { 2766 struct smu_context *smu = handle; 2767 uint32_t limit_type = limit >> 24; 2768 int ret = 0; 2769 2770 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2771 return -EOPNOTSUPP; 2772 2773 limit &= (1<<24)-1; 2774 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2775 if (smu->ppt_funcs->set_power_limit) 2776 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2777 2778 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2779 dev_err(smu->adev->dev, 2780 "New power limit (%d) is out of range [%d,%d]\n", 2781 limit, smu->min_power_limit, smu->max_power_limit); 2782 return -EINVAL; 2783 } 2784 2785 if (!limit) 2786 limit = smu->current_power_limit; 2787 2788 if (smu->ppt_funcs->set_power_limit) { 2789 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2790 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2791 smu->user_dpm_profile.power_limit = limit; 2792 } 2793 2794 return ret; 2795 } 2796 2797 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2798 { 2799 int ret = 0; 2800 2801 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2802 return -EOPNOTSUPP; 2803 2804 if (smu->ppt_funcs->print_clk_levels) 2805 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2806 2807 return ret; 2808 } 2809 2810 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2811 { 2812 enum smu_clk_type clk_type; 2813 2814 switch (type) { 2815 case PP_SCLK: 2816 clk_type = SMU_SCLK; break; 2817 case PP_MCLK: 2818 clk_type = SMU_MCLK; break; 2819 case PP_PCIE: 2820 clk_type = SMU_PCIE; break; 2821 case PP_SOCCLK: 2822 clk_type = SMU_SOCCLK; break; 2823 case PP_FCLK: 2824 clk_type = SMU_FCLK; break; 2825 case PP_DCEFCLK: 2826 clk_type = SMU_DCEFCLK; break; 2827 case PP_VCLK: 2828 clk_type = SMU_VCLK; break; 2829 case PP_VCLK1: 2830 clk_type = SMU_VCLK1; break; 2831 case PP_DCLK: 2832 clk_type = SMU_DCLK; break; 2833 case PP_DCLK1: 2834 clk_type = SMU_DCLK1; break; 2835 case OD_SCLK: 2836 clk_type = SMU_OD_SCLK; break; 2837 case OD_MCLK: 2838 clk_type = SMU_OD_MCLK; break; 2839 case OD_VDDC_CURVE: 2840 clk_type = SMU_OD_VDDC_CURVE; break; 2841 case OD_RANGE: 2842 clk_type = SMU_OD_RANGE; break; 2843 case OD_VDDGFX_OFFSET: 2844 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2845 case OD_CCLK: 2846 clk_type = SMU_OD_CCLK; break; 2847 case OD_FAN_CURVE: 2848 clk_type = SMU_OD_FAN_CURVE; break; 2849 case OD_ACOUSTIC_LIMIT: 2850 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2851 case OD_ACOUSTIC_TARGET: 2852 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2853 case OD_FAN_TARGET_TEMPERATURE: 2854 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2855 case OD_FAN_MINIMUM_PWM: 2856 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2857 default: 2858 clk_type = SMU_CLK_COUNT; break; 2859 } 2860 2861 return clk_type; 2862 } 2863 2864 static int smu_print_ppclk_levels(void *handle, 2865 enum pp_clock_type type, 2866 char *buf) 2867 { 2868 struct smu_context *smu = handle; 2869 enum smu_clk_type clk_type; 2870 2871 clk_type = smu_convert_to_smuclk(type); 2872 if (clk_type == SMU_CLK_COUNT) 2873 return -EINVAL; 2874 2875 return smu_print_smuclk_levels(smu, clk_type, buf); 2876 } 2877 2878 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2879 { 2880 struct smu_context *smu = handle; 2881 enum smu_clk_type clk_type; 2882 2883 clk_type = smu_convert_to_smuclk(type); 2884 if (clk_type == SMU_CLK_COUNT) 2885 return -EINVAL; 2886 2887 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2888 return -EOPNOTSUPP; 2889 2890 if (!smu->ppt_funcs->emit_clk_levels) 2891 return -ENOENT; 2892 2893 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2894 2895 } 2896 2897 static int smu_od_edit_dpm_table(void *handle, 2898 enum PP_OD_DPM_TABLE_COMMAND type, 2899 long *input, uint32_t size) 2900 { 2901 struct smu_context *smu = handle; 2902 int ret = 0; 2903 2904 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2905 return -EOPNOTSUPP; 2906 2907 if (smu->ppt_funcs->od_edit_dpm_table) { 2908 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2909 } 2910 2911 return ret; 2912 } 2913 2914 static int smu_read_sensor(void *handle, 2915 int sensor, 2916 void *data, 2917 int *size_arg) 2918 { 2919 struct smu_context *smu = handle; 2920 struct smu_umd_pstate_table *pstate_table = 2921 &smu->pstate_table; 2922 int ret = 0; 2923 uint32_t *size, size_val; 2924 2925 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2926 return -EOPNOTSUPP; 2927 2928 if (!data || !size_arg) 2929 return -EINVAL; 2930 2931 size_val = *size_arg; 2932 size = &size_val; 2933 2934 if (smu->ppt_funcs->read_sensor) 2935 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2936 goto unlock; 2937 2938 switch (sensor) { 2939 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2940 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2941 *size = 4; 2942 break; 2943 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2944 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2945 *size = 4; 2946 break; 2947 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2948 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2949 *size = 4; 2950 break; 2951 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2952 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2953 *size = 4; 2954 break; 2955 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2956 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2957 *size = 8; 2958 break; 2959 case AMDGPU_PP_SENSOR_UVD_POWER: 2960 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2961 *size = 4; 2962 break; 2963 case AMDGPU_PP_SENSOR_VCE_POWER: 2964 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2965 *size = 4; 2966 break; 2967 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2968 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 2969 *size = 4; 2970 break; 2971 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2972 *(uint32_t *)data = 0; 2973 *size = 4; 2974 break; 2975 default: 2976 *size = 0; 2977 ret = -EOPNOTSUPP; 2978 break; 2979 } 2980 2981 unlock: 2982 // assign uint32_t to int 2983 *size_arg = size_val; 2984 2985 return ret; 2986 } 2987 2988 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 2989 { 2990 int ret = -EOPNOTSUPP; 2991 struct smu_context *smu = handle; 2992 2993 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 2994 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 2995 2996 return ret; 2997 } 2998 2999 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3000 { 3001 int ret = -EOPNOTSUPP; 3002 struct smu_context *smu = handle; 3003 3004 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3005 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3006 3007 return ret; 3008 } 3009 3010 static int smu_get_power_profile_mode(void *handle, char *buf) 3011 { 3012 struct smu_context *smu = handle; 3013 3014 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3015 !smu->ppt_funcs->get_power_profile_mode) 3016 return -EOPNOTSUPP; 3017 if (!buf) 3018 return -EINVAL; 3019 3020 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3021 } 3022 3023 static int smu_set_power_profile_mode(void *handle, 3024 long *param, 3025 uint32_t param_size) 3026 { 3027 struct smu_context *smu = handle; 3028 3029 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3030 !smu->ppt_funcs->set_power_profile_mode) 3031 return -EOPNOTSUPP; 3032 3033 return smu_bump_power_profile_mode(smu, param, param_size); 3034 } 3035 3036 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3037 { 3038 struct smu_context *smu = handle; 3039 3040 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3041 return -EOPNOTSUPP; 3042 3043 if (!smu->ppt_funcs->get_fan_control_mode) 3044 return -EOPNOTSUPP; 3045 3046 if (!fan_mode) 3047 return -EINVAL; 3048 3049 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3050 3051 return 0; 3052 } 3053 3054 static int smu_set_fan_control_mode(void *handle, u32 value) 3055 { 3056 struct smu_context *smu = handle; 3057 int ret = 0; 3058 3059 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3060 return -EOPNOTSUPP; 3061 3062 if (!smu->ppt_funcs->set_fan_control_mode) 3063 return -EOPNOTSUPP; 3064 3065 if (value == U32_MAX) 3066 return -EINVAL; 3067 3068 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3069 if (ret) 3070 goto out; 3071 3072 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3073 smu->user_dpm_profile.fan_mode = value; 3074 3075 /* reset user dpm fan speed */ 3076 if (value != AMD_FAN_CTRL_MANUAL) { 3077 smu->user_dpm_profile.fan_speed_pwm = 0; 3078 smu->user_dpm_profile.fan_speed_rpm = 0; 3079 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3080 } 3081 } 3082 3083 out: 3084 return ret; 3085 } 3086 3087 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3088 { 3089 struct smu_context *smu = handle; 3090 int ret = 0; 3091 3092 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3093 return -EOPNOTSUPP; 3094 3095 if (!smu->ppt_funcs->get_fan_speed_pwm) 3096 return -EOPNOTSUPP; 3097 3098 if (!speed) 3099 return -EINVAL; 3100 3101 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3102 3103 return ret; 3104 } 3105 3106 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3107 { 3108 struct smu_context *smu = handle; 3109 int ret = 0; 3110 3111 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3112 return -EOPNOTSUPP; 3113 3114 if (!smu->ppt_funcs->set_fan_speed_pwm) 3115 return -EOPNOTSUPP; 3116 3117 if (speed == U32_MAX) 3118 return -EINVAL; 3119 3120 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3121 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3122 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3123 smu->user_dpm_profile.fan_speed_pwm = speed; 3124 3125 /* Override custom RPM setting as they cannot co-exist */ 3126 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3127 smu->user_dpm_profile.fan_speed_rpm = 0; 3128 } 3129 3130 return ret; 3131 } 3132 3133 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3134 { 3135 struct smu_context *smu = handle; 3136 int ret = 0; 3137 3138 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3139 return -EOPNOTSUPP; 3140 3141 if (!smu->ppt_funcs->get_fan_speed_rpm) 3142 return -EOPNOTSUPP; 3143 3144 if (!speed) 3145 return -EINVAL; 3146 3147 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3148 3149 return ret; 3150 } 3151 3152 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3153 { 3154 struct smu_context *smu = handle; 3155 3156 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3157 return -EOPNOTSUPP; 3158 3159 return smu_set_min_dcef_deep_sleep(smu, clk); 3160 } 3161 3162 static int smu_get_clock_by_type_with_latency(void *handle, 3163 enum amd_pp_clock_type type, 3164 struct pp_clock_levels_with_latency *clocks) 3165 { 3166 struct smu_context *smu = handle; 3167 enum smu_clk_type clk_type; 3168 int ret = 0; 3169 3170 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3171 return -EOPNOTSUPP; 3172 3173 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3174 switch (type) { 3175 case amd_pp_sys_clock: 3176 clk_type = SMU_GFXCLK; 3177 break; 3178 case amd_pp_mem_clock: 3179 clk_type = SMU_MCLK; 3180 break; 3181 case amd_pp_dcef_clock: 3182 clk_type = SMU_DCEFCLK; 3183 break; 3184 case amd_pp_disp_clock: 3185 clk_type = SMU_DISPCLK; 3186 break; 3187 default: 3188 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3189 return -EINVAL; 3190 } 3191 3192 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3193 } 3194 3195 return ret; 3196 } 3197 3198 static int smu_display_clock_voltage_request(void *handle, 3199 struct pp_display_clock_request *clock_req) 3200 { 3201 struct smu_context *smu = handle; 3202 int ret = 0; 3203 3204 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3205 return -EOPNOTSUPP; 3206 3207 if (smu->ppt_funcs->display_clock_voltage_request) 3208 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3209 3210 return ret; 3211 } 3212 3213 3214 static int smu_display_disable_memory_clock_switch(void *handle, 3215 bool disable_memory_clock_switch) 3216 { 3217 struct smu_context *smu = handle; 3218 int ret = -EINVAL; 3219 3220 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3221 return -EOPNOTSUPP; 3222 3223 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3224 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3225 3226 return ret; 3227 } 3228 3229 static int smu_set_xgmi_pstate(void *handle, 3230 uint32_t pstate) 3231 { 3232 struct smu_context *smu = handle; 3233 int ret = 0; 3234 3235 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3236 return -EOPNOTSUPP; 3237 3238 if (smu->ppt_funcs->set_xgmi_pstate) 3239 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3240 3241 if (ret) 3242 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3243 3244 return ret; 3245 } 3246 3247 static int smu_get_baco_capability(void *handle) 3248 { 3249 struct smu_context *smu = handle; 3250 3251 if (!smu->pm_enabled) 3252 return false; 3253 3254 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3255 return false; 3256 3257 return smu->ppt_funcs->get_bamaco_support(smu); 3258 } 3259 3260 static int smu_baco_set_state(void *handle, int state) 3261 { 3262 struct smu_context *smu = handle; 3263 int ret = 0; 3264 3265 if (!smu->pm_enabled) 3266 return -EOPNOTSUPP; 3267 3268 if (state == 0) { 3269 if (smu->ppt_funcs->baco_exit) 3270 ret = smu->ppt_funcs->baco_exit(smu); 3271 } else if (state == 1) { 3272 if (smu->ppt_funcs->baco_enter) 3273 ret = smu->ppt_funcs->baco_enter(smu); 3274 } else { 3275 return -EINVAL; 3276 } 3277 3278 if (ret) 3279 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3280 (state)?"enter":"exit"); 3281 3282 return ret; 3283 } 3284 3285 bool smu_mode1_reset_is_support(struct smu_context *smu) 3286 { 3287 bool ret = false; 3288 3289 if (!smu->pm_enabled) 3290 return false; 3291 3292 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3293 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3294 3295 return ret; 3296 } 3297 3298 bool smu_mode2_reset_is_support(struct smu_context *smu) 3299 { 3300 bool ret = false; 3301 3302 if (!smu->pm_enabled) 3303 return false; 3304 3305 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3306 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3307 3308 return ret; 3309 } 3310 3311 int smu_mode1_reset(struct smu_context *smu) 3312 { 3313 int ret = 0; 3314 3315 if (!smu->pm_enabled) 3316 return -EOPNOTSUPP; 3317 3318 if (smu->ppt_funcs->mode1_reset) 3319 ret = smu->ppt_funcs->mode1_reset(smu); 3320 3321 return ret; 3322 } 3323 3324 static int smu_mode2_reset(void *handle) 3325 { 3326 struct smu_context *smu = handle; 3327 int ret = 0; 3328 3329 if (!smu->pm_enabled) 3330 return -EOPNOTSUPP; 3331 3332 if (smu->ppt_funcs->mode2_reset) 3333 ret = smu->ppt_funcs->mode2_reset(smu); 3334 3335 if (ret) 3336 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3337 3338 return ret; 3339 } 3340 3341 static int smu_enable_gfx_features(void *handle) 3342 { 3343 struct smu_context *smu = handle; 3344 int ret = 0; 3345 3346 if (!smu->pm_enabled) 3347 return -EOPNOTSUPP; 3348 3349 if (smu->ppt_funcs->enable_gfx_features) 3350 ret = smu->ppt_funcs->enable_gfx_features(smu); 3351 3352 if (ret) 3353 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3354 3355 return ret; 3356 } 3357 3358 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3359 struct pp_smu_nv_clock_table *max_clocks) 3360 { 3361 struct smu_context *smu = handle; 3362 int ret = 0; 3363 3364 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3365 return -EOPNOTSUPP; 3366 3367 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3368 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3369 3370 return ret; 3371 } 3372 3373 static int smu_get_uclk_dpm_states(void *handle, 3374 unsigned int *clock_values_in_khz, 3375 unsigned int *num_states) 3376 { 3377 struct smu_context *smu = handle; 3378 int ret = 0; 3379 3380 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3381 return -EOPNOTSUPP; 3382 3383 if (smu->ppt_funcs->get_uclk_dpm_states) 3384 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3385 3386 return ret; 3387 } 3388 3389 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3390 { 3391 struct smu_context *smu = handle; 3392 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3393 3394 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3395 return -EOPNOTSUPP; 3396 3397 if (smu->ppt_funcs->get_current_power_state) 3398 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3399 3400 return pm_state; 3401 } 3402 3403 static int smu_get_dpm_clock_table(void *handle, 3404 struct dpm_clocks *clock_table) 3405 { 3406 struct smu_context *smu = handle; 3407 int ret = 0; 3408 3409 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3410 return -EOPNOTSUPP; 3411 3412 if (smu->ppt_funcs->get_dpm_clock_table) 3413 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3414 3415 return ret; 3416 } 3417 3418 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3419 { 3420 struct smu_context *smu = handle; 3421 3422 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3423 return -EOPNOTSUPP; 3424 3425 if (!smu->ppt_funcs->get_gpu_metrics) 3426 return -EOPNOTSUPP; 3427 3428 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3429 } 3430 3431 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3432 size_t size) 3433 { 3434 struct smu_context *smu = handle; 3435 3436 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3437 return -EOPNOTSUPP; 3438 3439 if (!smu->ppt_funcs->get_pm_metrics) 3440 return -EOPNOTSUPP; 3441 3442 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3443 } 3444 3445 static int smu_enable_mgpu_fan_boost(void *handle) 3446 { 3447 struct smu_context *smu = handle; 3448 int ret = 0; 3449 3450 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3451 return -EOPNOTSUPP; 3452 3453 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3454 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3455 3456 return ret; 3457 } 3458 3459 static int smu_gfx_state_change_set(void *handle, 3460 uint32_t state) 3461 { 3462 struct smu_context *smu = handle; 3463 int ret = 0; 3464 3465 if (smu->ppt_funcs->gfx_state_change_set) 3466 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3467 3468 return ret; 3469 } 3470 3471 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3472 { 3473 int ret = 0; 3474 3475 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3476 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3477 3478 return ret; 3479 } 3480 3481 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3482 { 3483 int ret = -EOPNOTSUPP; 3484 3485 if (smu->ppt_funcs && 3486 smu->ppt_funcs->get_ecc_info) 3487 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3488 3489 return ret; 3490 3491 } 3492 3493 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3494 { 3495 struct smu_context *smu = handle; 3496 struct smu_table_context *smu_table = &smu->smu_table; 3497 struct smu_table *memory_pool = &smu_table->memory_pool; 3498 3499 if (!addr || !size) 3500 return -EINVAL; 3501 3502 *addr = NULL; 3503 *size = 0; 3504 if (memory_pool->bo) { 3505 *addr = memory_pool->cpu_addr; 3506 *size = memory_pool->size; 3507 } 3508 3509 return 0; 3510 } 3511 3512 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3513 size_t *size) 3514 { 3515 size_t offset = *size; 3516 int level; 3517 3518 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3519 if (level == policy->current_level) 3520 offset += sysfs_emit_at(sysbuf, offset, 3521 "%d : %s*\n", level, 3522 policy->desc->get_desc(policy, level)); 3523 else 3524 offset += sysfs_emit_at(sysbuf, offset, 3525 "%d : %s\n", level, 3526 policy->desc->get_desc(policy, level)); 3527 } 3528 3529 *size = offset; 3530 } 3531 3532 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3533 enum pp_pm_policy p_type, char *sysbuf) 3534 { 3535 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3536 struct smu_dpm_policy_ctxt *policy_ctxt; 3537 struct smu_dpm_policy *dpm_policy; 3538 size_t offset = 0; 3539 3540 policy_ctxt = dpm_ctxt->dpm_policies; 3541 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3542 !policy_ctxt->policy_mask) 3543 return -EOPNOTSUPP; 3544 3545 if (p_type == PP_PM_POLICY_NONE) 3546 return -EINVAL; 3547 3548 dpm_policy = smu_get_pm_policy(smu, p_type); 3549 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3550 return -ENOENT; 3551 3552 if (!sysbuf) 3553 return -EINVAL; 3554 3555 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3556 3557 return offset; 3558 } 3559 3560 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3561 enum pp_pm_policy p_type) 3562 { 3563 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3564 struct smu_dpm_policy_ctxt *policy_ctxt; 3565 int i; 3566 3567 policy_ctxt = dpm_ctxt->dpm_policies; 3568 if (!policy_ctxt) 3569 return NULL; 3570 3571 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3572 if (policy_ctxt->policies[i].policy_type == p_type) 3573 return &policy_ctxt->policies[i]; 3574 } 3575 3576 return NULL; 3577 } 3578 3579 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3580 int level) 3581 { 3582 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3583 struct smu_dpm_policy *dpm_policy = NULL; 3584 struct smu_dpm_policy_ctxt *policy_ctxt; 3585 int ret = -EOPNOTSUPP; 3586 3587 policy_ctxt = dpm_ctxt->dpm_policies; 3588 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3589 !policy_ctxt->policy_mask) 3590 return ret; 3591 3592 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3593 return -EINVAL; 3594 3595 dpm_policy = smu_get_pm_policy(smu, p_type); 3596 3597 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3598 return ret; 3599 3600 if (dpm_policy->current_level == level) 3601 return 0; 3602 3603 ret = dpm_policy->set_policy(smu, level); 3604 3605 if (!ret) 3606 dpm_policy->current_level = level; 3607 3608 return ret; 3609 } 3610 3611 static const struct amd_pm_funcs swsmu_pm_funcs = { 3612 /* export for sysfs */ 3613 .set_fan_control_mode = smu_set_fan_control_mode, 3614 .get_fan_control_mode = smu_get_fan_control_mode, 3615 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3616 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3617 .force_clock_level = smu_force_ppclk_levels, 3618 .print_clock_levels = smu_print_ppclk_levels, 3619 .emit_clock_levels = smu_emit_ppclk_levels, 3620 .force_performance_level = smu_force_performance_level, 3621 .read_sensor = smu_read_sensor, 3622 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3623 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3624 .get_performance_level = smu_get_performance_level, 3625 .get_current_power_state = smu_get_current_power_state, 3626 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3627 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3628 .get_pp_num_states = smu_get_power_num_states, 3629 .get_pp_table = smu_sys_get_pp_table, 3630 .set_pp_table = smu_sys_set_pp_table, 3631 .switch_power_profile = smu_switch_power_profile, 3632 /* export to amdgpu */ 3633 .dispatch_tasks = smu_handle_dpm_task, 3634 .load_firmware = smu_load_microcode, 3635 .set_powergating_by_smu = smu_dpm_set_power_gate, 3636 .set_power_limit = smu_set_power_limit, 3637 .get_power_limit = smu_get_power_limit, 3638 .get_power_profile_mode = smu_get_power_profile_mode, 3639 .set_power_profile_mode = smu_set_power_profile_mode, 3640 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3641 .set_mp1_state = smu_set_mp1_state, 3642 .gfx_state_change_set = smu_gfx_state_change_set, 3643 /* export to DC */ 3644 .get_sclk = smu_get_sclk, 3645 .get_mclk = smu_get_mclk, 3646 .display_configuration_change = smu_display_configuration_change, 3647 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3648 .display_clock_voltage_request = smu_display_clock_voltage_request, 3649 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3650 .set_active_display_count = smu_set_display_count, 3651 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3652 .get_asic_baco_capability = smu_get_baco_capability, 3653 .set_asic_baco_state = smu_baco_set_state, 3654 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3655 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3656 .asic_reset_mode_2 = smu_mode2_reset, 3657 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3658 .set_df_cstate = smu_set_df_cstate, 3659 .set_xgmi_pstate = smu_set_xgmi_pstate, 3660 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3661 .get_pm_metrics = smu_sys_get_pm_metrics, 3662 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3663 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3664 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3665 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3666 .get_dpm_clock_table = smu_get_dpm_clock_table, 3667 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3668 }; 3669 3670 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3671 uint64_t event_arg) 3672 { 3673 int ret = -EINVAL; 3674 3675 if (smu->ppt_funcs->wait_for_event) 3676 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3677 3678 return ret; 3679 } 3680 3681 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3682 { 3683 3684 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3685 return -EOPNOTSUPP; 3686 3687 /* Confirm the buffer allocated is of correct size */ 3688 if (size != smu->stb_context.stb_buf_size) 3689 return -EINVAL; 3690 3691 /* 3692 * No need to lock smu mutex as we access STB directly through MMIO 3693 * and not going through SMU messaging route (for now at least). 3694 * For registers access rely on implementation internal locking. 3695 */ 3696 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3697 } 3698 3699 #if defined(CONFIG_DEBUG_FS) 3700 3701 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3702 { 3703 struct amdgpu_device *adev = filp->f_inode->i_private; 3704 struct smu_context *smu = adev->powerplay.pp_handle; 3705 unsigned char *buf; 3706 int r; 3707 3708 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3709 if (!buf) 3710 return -ENOMEM; 3711 3712 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3713 if (r) 3714 goto out; 3715 3716 filp->private_data = buf; 3717 3718 return 0; 3719 3720 out: 3721 kvfree(buf); 3722 return r; 3723 } 3724 3725 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3726 loff_t *pos) 3727 { 3728 struct amdgpu_device *adev = filp->f_inode->i_private; 3729 struct smu_context *smu = adev->powerplay.pp_handle; 3730 3731 3732 if (!filp->private_data) 3733 return -EINVAL; 3734 3735 return simple_read_from_buffer(buf, 3736 size, 3737 pos, filp->private_data, 3738 smu->stb_context.stb_buf_size); 3739 } 3740 3741 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3742 { 3743 kvfree(filp->private_data); 3744 filp->private_data = NULL; 3745 3746 return 0; 3747 } 3748 3749 /* 3750 * We have to define not only read method but also 3751 * open and release because .read takes up to PAGE_SIZE 3752 * data each time so and so is invoked multiple times. 3753 * We allocate the STB buffer in .open and release it 3754 * in .release 3755 */ 3756 static const struct file_operations smu_stb_debugfs_fops = { 3757 .owner = THIS_MODULE, 3758 .open = smu_stb_debugfs_open, 3759 .read = smu_stb_debugfs_read, 3760 .release = smu_stb_debugfs_release, 3761 .llseek = default_llseek, 3762 }; 3763 3764 #endif 3765 3766 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3767 { 3768 #if defined(CONFIG_DEBUG_FS) 3769 3770 struct smu_context *smu = adev->powerplay.pp_handle; 3771 3772 if (!smu || (!smu->stb_context.stb_buf_size)) 3773 return; 3774 3775 debugfs_create_file_size("amdgpu_smu_stb_dump", 3776 S_IRUSR, 3777 adev_to_drm(adev)->primary->debugfs_root, 3778 adev, 3779 &smu_stb_debugfs_fops, 3780 smu->stb_context.stb_buf_size); 3781 #endif 3782 } 3783 3784 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3785 { 3786 int ret = 0; 3787 3788 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3789 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3790 3791 return ret; 3792 } 3793 3794 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3795 { 3796 int ret = 0; 3797 3798 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3799 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3800 3801 return ret; 3802 } 3803 3804 int smu_send_rma_reason(struct smu_context *smu) 3805 { 3806 int ret = 0; 3807 3808 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3809 ret = smu->ppt_funcs->send_rma_reason(smu); 3810 3811 return ret; 3812 } 3813