1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "smu_v15_0_0_ppt.h" 50 #include "smu_v15_0_8_ppt.h" 51 #include "amd_pcie.h" 52 53 /* 54 * DO NOT use these for err/warn/info/debug messages. 55 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 56 * They are more MGPU friendly. 57 */ 58 #undef pr_err 59 #undef pr_warn 60 #undef pr_info 61 #undef pr_debug 62 63 static const struct amd_pm_funcs swsmu_pm_funcs; 64 static int smu_force_smuclk_levels(struct smu_context *smu, 65 enum smu_clk_type clk_type, 66 uint32_t mask); 67 static int smu_handle_task(struct smu_context *smu, 68 enum amd_dpm_forced_level level, 69 enum amd_pp_task task_id); 70 static int smu_reset(struct smu_context *smu); 71 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 72 static int smu_set_fan_control_mode(void *handle, u32 value); 73 static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit); 74 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 75 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 76 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 77 static void smu_power_profile_mode_get(struct smu_context *smu, 78 enum PP_SMC_POWER_PROFILE profile_mode); 79 static void smu_power_profile_mode_put(struct smu_context *smu, 80 enum PP_SMC_POWER_PROFILE profile_mode); 81 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type); 82 static int smu_od_edit_dpm_table(void *handle, 83 enum PP_OD_DPM_TABLE_COMMAND type, 84 long *input, uint32_t size); 85 86 static int smu_sys_get_pp_feature_mask(void *handle, 87 char *buf) 88 { 89 struct smu_context *smu = handle; 90 91 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 92 return -EOPNOTSUPP; 93 94 return smu_get_pp_feature_mask(smu, buf); 95 } 96 97 static int smu_sys_set_pp_feature_mask(void *handle, 98 uint64_t new_mask) 99 { 100 struct smu_context *smu = handle; 101 102 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 103 return -EOPNOTSUPP; 104 105 return smu_set_pp_feature_mask(smu, new_mask); 106 } 107 108 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 109 { 110 if (!smu->ppt_funcs->set_gfx_off_residency) 111 return -EINVAL; 112 113 return smu_set_gfx_off_residency(smu, value); 114 } 115 116 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 117 { 118 if (!smu->ppt_funcs->get_gfx_off_residency) 119 return -EINVAL; 120 121 return smu_get_gfx_off_residency(smu, value); 122 } 123 124 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 125 { 126 if (!smu->ppt_funcs->get_gfx_off_entrycount) 127 return -EINVAL; 128 129 return smu_get_gfx_off_entrycount(smu, value); 130 } 131 132 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 133 { 134 if (!smu->ppt_funcs->get_gfx_off_status) 135 return -EINVAL; 136 137 *value = smu_get_gfx_off_status(smu); 138 139 return 0; 140 } 141 142 int smu_set_soft_freq_range(struct smu_context *smu, 143 enum pp_clock_type type, 144 uint32_t min, 145 uint32_t max) 146 { 147 enum smu_clk_type clk_type; 148 int ret = 0; 149 150 clk_type = smu_convert_to_smuclk(type); 151 if (clk_type == SMU_CLK_COUNT) 152 return -EINVAL; 153 154 if (smu->ppt_funcs->set_soft_freq_limited_range) 155 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 156 clk_type, 157 min, 158 max, 159 false); 160 161 return ret; 162 } 163 164 int smu_get_dpm_freq_range(struct smu_context *smu, 165 enum smu_clk_type clk_type, 166 uint32_t *min, 167 uint32_t *max) 168 { 169 int ret = -ENOTSUPP; 170 171 if (!min && !max) 172 return -EINVAL; 173 174 if (smu->ppt_funcs->get_dpm_ultimate_freq) 175 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 176 clk_type, 177 min, 178 max); 179 180 return ret; 181 } 182 183 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 184 { 185 int ret = 0; 186 struct amdgpu_device *adev = smu->adev; 187 188 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 189 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 190 if (ret) 191 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 192 } 193 return ret; 194 } 195 196 static u32 smu_get_mclk(void *handle, bool low) 197 { 198 struct smu_context *smu = handle; 199 uint32_t clk_freq; 200 int ret = 0; 201 202 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 203 low ? &clk_freq : NULL, 204 !low ? &clk_freq : NULL); 205 if (ret) 206 return 0; 207 return clk_freq * 100; 208 } 209 210 static u32 smu_get_sclk(void *handle, bool low) 211 { 212 struct smu_context *smu = handle; 213 uint32_t clk_freq; 214 int ret = 0; 215 216 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 217 low ? &clk_freq : NULL, 218 !low ? &clk_freq : NULL); 219 if (ret) 220 return 0; 221 return clk_freq * 100; 222 } 223 224 static int smu_set_gfx_imu_enable(struct smu_context *smu) 225 { 226 struct amdgpu_device *adev = smu->adev; 227 228 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 229 return 0; 230 231 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 232 return 0; 233 234 return smu_set_gfx_power_up_by_imu(smu); 235 } 236 237 static bool is_vcn_enabled(struct amdgpu_device *adev) 238 { 239 int i; 240 241 for (i = 0; i < adev->num_ip_blocks; i++) { 242 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 243 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 244 !adev->ip_blocks[i].status.valid) 245 return false; 246 } 247 248 return true; 249 } 250 251 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 252 bool enable, 253 int inst) 254 { 255 struct smu_power_context *smu_power = &smu->smu_power; 256 struct smu_power_gate *power_gate = &smu_power->power_gate; 257 int ret = 0; 258 259 /* 260 * don't poweron vcn/jpeg when they are skipped. 261 */ 262 if (!is_vcn_enabled(smu->adev)) 263 return 0; 264 265 if (!smu->ppt_funcs->dpm_set_vcn_enable) 266 return 0; 267 268 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable) 269 return 0; 270 271 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst); 272 if (!ret) 273 atomic_set(&power_gate->vcn_gated[inst], !enable); 274 275 return ret; 276 } 277 278 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 279 bool enable) 280 { 281 struct smu_power_context *smu_power = &smu->smu_power; 282 struct smu_power_gate *power_gate = &smu_power->power_gate; 283 int ret = 0; 284 285 if (!is_vcn_enabled(smu->adev)) 286 return 0; 287 288 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 289 return 0; 290 291 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 292 return 0; 293 294 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 295 if (!ret) 296 atomic_set(&power_gate->jpeg_gated, !enable); 297 298 return ret; 299 } 300 301 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 302 bool enable) 303 { 304 struct smu_power_context *smu_power = &smu->smu_power; 305 struct smu_power_gate *power_gate = &smu_power->power_gate; 306 int ret = 0; 307 308 if (!smu->ppt_funcs->dpm_set_vpe_enable) 309 return 0; 310 311 if (atomic_read(&power_gate->vpe_gated) ^ enable) 312 return 0; 313 314 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 315 if (!ret) 316 atomic_set(&power_gate->vpe_gated, !enable); 317 318 return ret; 319 } 320 321 static int smu_dpm_set_isp_enable(struct smu_context *smu, 322 bool enable) 323 { 324 struct smu_power_context *smu_power = &smu->smu_power; 325 struct smu_power_gate *power_gate = &smu_power->power_gate; 326 int ret; 327 328 if (!smu->ppt_funcs->dpm_set_isp_enable) 329 return 0; 330 331 if (atomic_read(&power_gate->isp_gated) ^ enable) 332 return 0; 333 334 ret = smu->ppt_funcs->dpm_set_isp_enable(smu, enable); 335 if (!ret) 336 atomic_set(&power_gate->isp_gated, !enable); 337 338 return ret; 339 } 340 341 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 342 bool enable) 343 { 344 struct smu_power_context *smu_power = &smu->smu_power; 345 struct smu_power_gate *power_gate = &smu_power->power_gate; 346 int ret = 0; 347 348 if (!smu->adev->enable_umsch_mm) 349 return 0; 350 351 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 352 return 0; 353 354 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 355 return 0; 356 357 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 358 if (!ret) 359 atomic_set(&power_gate->umsch_mm_gated, !enable); 360 361 return ret; 362 } 363 364 static int smu_set_mall_enable(struct smu_context *smu) 365 { 366 int ret = 0; 367 368 if (!smu->ppt_funcs->set_mall_enable) 369 return 0; 370 371 ret = smu->ppt_funcs->set_mall_enable(smu); 372 373 return ret; 374 } 375 376 /** 377 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 378 * 379 * @handle: smu_context pointer 380 * @block_type: the IP block to power gate/ungate 381 * @gate: to power gate if true, ungate otherwise 382 * @inst: the instance of the IP block to power gate/ungate 383 * 384 * This API uses no smu->mutex lock protection due to: 385 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 386 * This is guarded to be race condition free by the caller. 387 * 2. Or get called on user setting request of power_dpm_force_performance_level. 388 * Under this case, the smu->mutex lock protection is already enforced on 389 * the parent API smu_force_performance_level of the call path. 390 */ 391 static int smu_dpm_set_power_gate(void *handle, 392 uint32_t block_type, 393 bool gate, 394 int inst) 395 { 396 struct smu_context *smu = handle; 397 int ret = 0; 398 399 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 400 dev_WARN(smu->adev->dev, 401 "SMU uninitialized but power %s requested for %u!\n", 402 gate ? "gate" : "ungate", block_type); 403 return -EOPNOTSUPP; 404 } 405 406 switch (block_type) { 407 /* 408 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 409 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 410 */ 411 case AMD_IP_BLOCK_TYPE_UVD: 412 case AMD_IP_BLOCK_TYPE_VCN: 413 ret = smu_dpm_set_vcn_enable(smu, !gate, inst); 414 if (ret) 415 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n", 416 gate ? "gate" : "ungate", inst); 417 break; 418 case AMD_IP_BLOCK_TYPE_GFX: 419 ret = smu_gfx_off_control(smu, gate); 420 if (ret) 421 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 422 gate ? "enable" : "disable"); 423 break; 424 case AMD_IP_BLOCK_TYPE_SDMA: 425 ret = smu_powergate_sdma(smu, gate); 426 if (ret) 427 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 428 gate ? "gate" : "ungate"); 429 break; 430 case AMD_IP_BLOCK_TYPE_JPEG: 431 ret = smu_dpm_set_jpeg_enable(smu, !gate); 432 if (ret) 433 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 434 gate ? "gate" : "ungate"); 435 break; 436 case AMD_IP_BLOCK_TYPE_VPE: 437 ret = smu_dpm_set_vpe_enable(smu, !gate); 438 if (ret) 439 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 440 gate ? "gate" : "ungate"); 441 break; 442 case AMD_IP_BLOCK_TYPE_ISP: 443 ret = smu_dpm_set_isp_enable(smu, !gate); 444 if (ret) 445 dev_err(smu->adev->dev, "Failed to power %s ISP!\n", 446 gate ? "gate" : "ungate"); 447 break; 448 default: 449 dev_err(smu->adev->dev, "Unsupported block type!\n"); 450 return -EINVAL; 451 } 452 453 return ret; 454 } 455 456 /** 457 * smu_set_user_clk_dependencies - set user profile clock dependencies 458 * 459 * @smu: smu_context pointer 460 * @clk: enum smu_clk_type type 461 * 462 * Enable/Disable the clock dependency for the @clk type. 463 */ 464 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 465 { 466 if (smu->adev->in_suspend) 467 return; 468 469 if (clk == SMU_MCLK) { 470 smu->user_dpm_profile.clk_dependency = 0; 471 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 472 } else if (clk == SMU_FCLK) { 473 /* MCLK takes precedence over FCLK */ 474 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 475 return; 476 477 smu->user_dpm_profile.clk_dependency = 0; 478 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 479 } else if (clk == SMU_SOCCLK) { 480 /* MCLK takes precedence over SOCCLK */ 481 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 482 return; 483 484 smu->user_dpm_profile.clk_dependency = 0; 485 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 486 } else 487 /* Add clk dependencies here, if any */ 488 return; 489 } 490 491 /** 492 * smu_restore_dpm_user_profile - reinstate user dpm profile 493 * 494 * @smu: smu_context pointer 495 * 496 * Restore the saved user power configurations include power limit, 497 * clock frequencies, fan control mode and fan speed. 498 */ 499 static void smu_restore_dpm_user_profile(struct smu_context *smu) 500 { 501 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 502 int ret = 0; 503 504 if (!smu->adev->in_suspend) 505 return; 506 507 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 508 return; 509 510 /* Enable restore flag */ 511 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 512 513 /* set the user dpm power limits */ 514 for (int i = SMU_DEFAULT_PPT_LIMIT; i < SMU_LIMIT_TYPE_COUNT; i++) { 515 if (!smu->user_dpm_profile.power_limits[i]) 516 continue; 517 ret = smu_set_power_limit(smu, i, 518 smu->user_dpm_profile.power_limits[i]); 519 if (ret) 520 dev_err(smu->adev->dev, "Failed to set %d power limit value\n", i); 521 } 522 523 /* set the user dpm clock configurations */ 524 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 525 enum smu_clk_type clk_type; 526 527 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 528 /* 529 * Iterate over smu clk type and force the saved user clk 530 * configs, skip if clock dependency is enabled 531 */ 532 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 533 smu->user_dpm_profile.clk_mask[clk_type]) { 534 ret = smu_force_smuclk_levels(smu, clk_type, 535 smu->user_dpm_profile.clk_mask[clk_type]); 536 if (ret) 537 dev_err(smu->adev->dev, 538 "Failed to set clock type = %d\n", clk_type); 539 } 540 } 541 } 542 543 /* set the user dpm fan configurations */ 544 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 545 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 546 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 547 if (ret != -EOPNOTSUPP) { 548 smu->user_dpm_profile.fan_speed_pwm = 0; 549 smu->user_dpm_profile.fan_speed_rpm = 0; 550 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 551 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 552 } 553 554 if (smu->user_dpm_profile.fan_speed_pwm) { 555 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 556 if (ret != -EOPNOTSUPP) 557 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 558 } 559 560 if (smu->user_dpm_profile.fan_speed_rpm) { 561 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 562 if (ret != -EOPNOTSUPP) 563 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 564 } 565 } 566 567 /* Restore user customized OD settings */ 568 if (smu->user_dpm_profile.user_od) { 569 if (smu->ppt_funcs->restore_user_od_settings) { 570 ret = smu->ppt_funcs->restore_user_od_settings(smu); 571 if (ret) 572 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 573 } 574 } 575 576 /* Disable restore flag */ 577 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 578 } 579 580 static int smu_get_power_num_states(void *handle, 581 struct pp_states_info *state_info) 582 { 583 if (!state_info) 584 return -EINVAL; 585 586 /* not support power state */ 587 memset(state_info, 0, sizeof(struct pp_states_info)); 588 state_info->nums = 1; 589 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 590 591 return 0; 592 } 593 594 bool is_support_sw_smu(struct amdgpu_device *adev) 595 { 596 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 597 if (adev->asic_type == CHIP_VEGA20) 598 return false; 599 600 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && 601 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) 602 return true; 603 604 return false; 605 } 606 607 bool is_support_cclk_dpm(struct amdgpu_device *adev) 608 { 609 struct smu_context *smu = adev->powerplay.pp_handle; 610 611 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 612 return false; 613 614 return true; 615 } 616 617 int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, 618 uint32_t param, uint32_t *read_arg) 619 { 620 struct smu_context *smu = adev->powerplay.pp_handle; 621 int ret = -EOPNOTSUPP; 622 623 if (!smu) 624 return ret; 625 626 if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg) 627 ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg); 628 629 return ret; 630 } 631 632 int amdgpu_smu_ras_feature_is_enabled(struct amdgpu_device *adev, 633 enum smu_feature_mask mask) 634 { 635 struct smu_context *smu = adev->powerplay.pp_handle; 636 int ret = 0; 637 638 if (smu->ppt_funcs && smu->ppt_funcs->feature_is_enabled) 639 ret = smu->ppt_funcs->feature_is_enabled(smu, mask); 640 641 return ret; 642 } 643 644 static int smu_sys_get_pp_table(void *handle, 645 char **table) 646 { 647 struct smu_context *smu = handle; 648 struct smu_table_context *smu_table = &smu->smu_table; 649 650 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 651 return -EOPNOTSUPP; 652 653 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 654 return -EOPNOTSUPP; 655 656 if (smu_table->hardcode_pptable) 657 *table = smu_table->hardcode_pptable; 658 else 659 *table = smu_table->power_play_table; 660 661 return smu_table->power_play_table_size; 662 } 663 664 static int smu_sys_set_pp_table(void *handle, 665 const char *buf, 666 size_t size) 667 { 668 struct smu_context *smu = handle; 669 struct smu_table_context *smu_table = &smu->smu_table; 670 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 671 int ret = 0; 672 673 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 674 return -EOPNOTSUPP; 675 676 if (header->usStructureSize != size) { 677 dev_err(smu->adev->dev, "pp table size not matched !\n"); 678 return -EIO; 679 } 680 681 if (!smu_table->hardcode_pptable || smu_table->power_play_table_size < size) { 682 kfree(smu_table->hardcode_pptable); 683 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 684 if (!smu_table->hardcode_pptable) 685 return -ENOMEM; 686 } 687 688 memcpy(smu_table->hardcode_pptable, buf, size); 689 smu_table->power_play_table = smu_table->hardcode_pptable; 690 smu_table->power_play_table_size = size; 691 692 /* 693 * Special hw_fini action(for Navi1x, the DPMs disablement will be 694 * skipped) may be needed for custom pptable uploading. 695 */ 696 smu->uploading_custom_pp_table = true; 697 698 ret = smu_reset(smu); 699 if (ret) 700 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 701 702 smu->uploading_custom_pp_table = false; 703 704 return ret; 705 } 706 707 static int smu_init_driver_allowed_feature_mask(struct smu_context *smu) 708 { 709 /* 710 * With SCPM enabled, the allowed featuremasks setting(via 711 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 712 * That means there is no way to let PMFW knows the settings below. 713 * Thus, we just assume all the features are allowed under 714 * such scenario. 715 */ 716 if (smu->adev->scpm_enabled) { 717 smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); 718 return 0; 719 } 720 721 smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); 722 723 return smu_init_allowed_features(smu); 724 } 725 726 static int smu_set_funcs(struct amdgpu_device *adev) 727 { 728 struct smu_context *smu = adev->powerplay.pp_handle; 729 730 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 731 smu->od_enabled = true; 732 733 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 734 case IP_VERSION(11, 0, 0): 735 case IP_VERSION(11, 0, 5): 736 case IP_VERSION(11, 0, 9): 737 navi10_set_ppt_funcs(smu); 738 break; 739 case IP_VERSION(11, 0, 7): 740 case IP_VERSION(11, 0, 11): 741 case IP_VERSION(11, 0, 12): 742 case IP_VERSION(11, 0, 13): 743 sienna_cichlid_set_ppt_funcs(smu); 744 break; 745 case IP_VERSION(12, 0, 0): 746 case IP_VERSION(12, 0, 1): 747 renoir_set_ppt_funcs(smu); 748 break; 749 case IP_VERSION(11, 5, 0): 750 case IP_VERSION(11, 5, 2): 751 vangogh_set_ppt_funcs(smu); 752 break; 753 case IP_VERSION(13, 0, 1): 754 case IP_VERSION(13, 0, 3): 755 case IP_VERSION(13, 0, 8): 756 yellow_carp_set_ppt_funcs(smu); 757 break; 758 case IP_VERSION(13, 0, 4): 759 case IP_VERSION(13, 0, 11): 760 smu_v13_0_4_set_ppt_funcs(smu); 761 break; 762 case IP_VERSION(13, 0, 5): 763 smu_v13_0_5_set_ppt_funcs(smu); 764 break; 765 case IP_VERSION(11, 0, 8): 766 cyan_skillfish_set_ppt_funcs(smu); 767 break; 768 case IP_VERSION(11, 0, 2): 769 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 770 arcturus_set_ppt_funcs(smu); 771 /* OD is not supported on Arcturus */ 772 smu->od_enabled = false; 773 break; 774 case IP_VERSION(13, 0, 2): 775 aldebaran_set_ppt_funcs(smu); 776 /* Enable pp_od_clk_voltage node */ 777 smu->od_enabled = true; 778 break; 779 case IP_VERSION(13, 0, 0): 780 case IP_VERSION(13, 0, 10): 781 smu_v13_0_0_set_ppt_funcs(smu); 782 break; 783 case IP_VERSION(13, 0, 6): 784 case IP_VERSION(13, 0, 14): 785 case IP_VERSION(13, 0, 12): 786 smu_v13_0_6_set_ppt_funcs(smu); 787 /* Enable pp_od_clk_voltage node */ 788 smu->od_enabled = true; 789 break; 790 case IP_VERSION(13, 0, 7): 791 smu_v13_0_7_set_ppt_funcs(smu); 792 break; 793 case IP_VERSION(14, 0, 0): 794 case IP_VERSION(14, 0, 1): 795 case IP_VERSION(14, 0, 4): 796 case IP_VERSION(14, 0, 5): 797 smu_v14_0_0_set_ppt_funcs(smu); 798 break; 799 case IP_VERSION(14, 0, 2): 800 case IP_VERSION(14, 0, 3): 801 smu_v14_0_2_set_ppt_funcs(smu); 802 break; 803 case IP_VERSION(15, 0, 0): 804 case IP_VERSION(15, 0, 5): 805 smu_v15_0_0_set_ppt_funcs(smu); 806 break; 807 case IP_VERSION(15, 0, 8): 808 smu_v15_0_8_set_ppt_funcs(smu); 809 smu->od_enabled = true; 810 break; 811 default: 812 return -EINVAL; 813 } 814 815 return 0; 816 } 817 818 static int smu_early_init(struct amdgpu_ip_block *ip_block) 819 { 820 struct amdgpu_device *adev = ip_block->adev; 821 struct smu_context *smu; 822 int r; 823 824 smu = kzalloc_obj(struct smu_context); 825 if (!smu) 826 return -ENOMEM; 827 828 smu->adev = adev; 829 smu->pm_enabled = !!amdgpu_dpm; 830 smu->is_apu = false; 831 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 832 smu->smu_baco.platform_support = false; 833 smu->smu_baco.maco_support = false; 834 smu->user_dpm_profile.fan_mode = -1; 835 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN; 836 837 adev->powerplay.pp_handle = smu; 838 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 839 840 r = smu_set_funcs(adev); 841 if (r) 842 return r; 843 return smu_init_microcode(smu); 844 } 845 846 static int smu_set_default_dpm_table(struct smu_context *smu) 847 { 848 struct amdgpu_device *adev = smu->adev; 849 struct smu_power_context *smu_power = &smu->smu_power; 850 struct smu_power_gate *power_gate = &smu_power->power_gate; 851 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i; 852 int ret = 0; 853 854 if (!smu->ppt_funcs->set_default_dpm_table) 855 return 0; 856 857 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 858 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 859 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]); 860 } 861 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 862 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 863 864 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 865 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 866 ret = smu_dpm_set_vcn_enable(smu, true, i); 867 if (ret) 868 return ret; 869 } 870 } 871 872 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 873 ret = smu_dpm_set_jpeg_enable(smu, true); 874 if (ret) 875 goto err_out; 876 } 877 878 ret = smu->ppt_funcs->set_default_dpm_table(smu); 879 if (ret) 880 dev_err(smu->adev->dev, 881 "Failed to setup default dpm clock tables!\n"); 882 883 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 884 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 885 err_out: 886 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 887 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 888 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i); 889 } 890 891 return ret; 892 } 893 894 static int smu_apply_default_config_table_settings(struct smu_context *smu) 895 { 896 struct amdgpu_device *adev = smu->adev; 897 int ret = 0; 898 899 ret = smu_get_default_config_table_settings(smu, 900 &adev->pm.config_table); 901 if (ret) 902 return ret; 903 904 return smu_set_config_table(smu, &adev->pm.config_table); 905 } 906 907 static int smu_late_init(struct amdgpu_ip_block *ip_block) 908 { 909 struct amdgpu_device *adev = ip_block->adev; 910 struct smu_context *smu = adev->powerplay.pp_handle; 911 int ret = 0; 912 913 smu_set_fine_grain_gfx_freq_parameters(smu); 914 915 if (!smu->pm_enabled) 916 return 0; 917 918 ret = smu_post_init(smu); 919 if (ret) { 920 dev_err(adev->dev, "Failed to post smu init!\n"); 921 return ret; 922 } 923 924 /* 925 * Explicitly notify PMFW the power mode the system in. Since 926 * the PMFW may boot the ASIC with a different mode. 927 * For those supporting ACDC switch via gpio, PMFW will 928 * handle the switch automatically. Driver involvement 929 * is unnecessary. 930 */ 931 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 932 smu_set_ac_dc(smu); 933 934 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 935 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 936 return 0; 937 938 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 939 ret = smu_set_default_od_settings(smu); 940 if (ret) { 941 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 942 return ret; 943 } 944 } 945 946 ret = smu_populate_umd_state_clk(smu); 947 if (ret) { 948 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 949 return ret; 950 } 951 952 ret = smu_get_asic_power_limits(smu, 953 &smu->current_power_limit, 954 &smu->default_power_limit, 955 &smu->max_power_limit, 956 &smu->min_power_limit); 957 if (ret) { 958 dev_err(adev->dev, "Failed to get asic power limits!\n"); 959 return ret; 960 } 961 962 if (!amdgpu_sriov_vf(adev)) 963 smu_get_unique_id(smu); 964 965 smu_get_fan_parameters(smu); 966 967 smu_handle_task(smu, 968 smu->smu_dpm.dpm_level, 969 AMD_PP_TASK_COMPLETE_INIT); 970 971 ret = smu_apply_default_config_table_settings(smu); 972 if (ret && (ret != -EOPNOTSUPP)) { 973 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 974 return ret; 975 } 976 977 smu_restore_dpm_user_profile(smu); 978 979 return 0; 980 } 981 982 static int smu_init_fb_allocations(struct smu_context *smu) 983 { 984 struct amdgpu_device *adev = smu->adev; 985 struct smu_table_context *smu_table = &smu->smu_table; 986 struct smu_table *tables = smu_table->tables; 987 struct smu_table *driver_table = &(smu_table->driver_table); 988 uint32_t max_table_size = 0; 989 int ret, i; 990 991 /* VRAM allocation for tool table */ 992 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 993 ret = amdgpu_bo_create_kernel(adev, 994 tables[SMU_TABLE_PMSTATUSLOG].size, 995 tables[SMU_TABLE_PMSTATUSLOG].align, 996 tables[SMU_TABLE_PMSTATUSLOG].domain, 997 &tables[SMU_TABLE_PMSTATUSLOG].bo, 998 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 999 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1000 if (ret) { 1001 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 1002 return ret; 1003 } 1004 } 1005 1006 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 1007 /* VRAM allocation for driver table */ 1008 for (i = 0; i < SMU_TABLE_COUNT; i++) { 1009 if (tables[i].size == 0) 1010 continue; 1011 1012 /* If one of the tables has VRAM domain restriction, keep it in 1013 * VRAM 1014 */ 1015 if ((tables[i].domain & 1016 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 1017 AMDGPU_GEM_DOMAIN_VRAM) 1018 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 1019 1020 if (i == SMU_TABLE_PMSTATUSLOG) 1021 continue; 1022 1023 if (max_table_size < tables[i].size) 1024 max_table_size = tables[i].size; 1025 } 1026 1027 driver_table->size = max_table_size; 1028 driver_table->align = PAGE_SIZE; 1029 1030 ret = amdgpu_bo_create_kernel(adev, 1031 driver_table->size, 1032 driver_table->align, 1033 driver_table->domain, 1034 &driver_table->bo, 1035 &driver_table->mc_address, 1036 &driver_table->cpu_addr); 1037 if (ret) { 1038 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 1039 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 1040 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 1041 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1042 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1043 } 1044 1045 return ret; 1046 } 1047 1048 static int smu_fini_fb_allocations(struct smu_context *smu) 1049 { 1050 struct smu_table_context *smu_table = &smu->smu_table; 1051 struct smu_table *tables = smu_table->tables; 1052 struct smu_table *driver_table = &(smu_table->driver_table); 1053 1054 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 1055 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 1056 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1057 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1058 1059 amdgpu_bo_free_kernel(&driver_table->bo, 1060 &driver_table->mc_address, 1061 &driver_table->cpu_addr); 1062 1063 return 0; 1064 } 1065 1066 static void smu_update_gpu_addresses(struct smu_context *smu) 1067 { 1068 struct smu_table_context *smu_table = &smu->smu_table; 1069 struct smu_table *pm_status_table = smu_table->tables + SMU_TABLE_PMSTATUSLOG; 1070 struct smu_table *driver_table = &(smu_table->driver_table); 1071 struct smu_table *dummy_read_1_table = &smu_table->dummy_read_1_table; 1072 1073 if (pm_status_table->bo) 1074 pm_status_table->mc_address = amdgpu_bo_fb_aper_addr(pm_status_table->bo); 1075 if (driver_table->bo) 1076 driver_table->mc_address = amdgpu_bo_fb_aper_addr(driver_table->bo); 1077 if (dummy_read_1_table->bo) 1078 dummy_read_1_table->mc_address = amdgpu_bo_fb_aper_addr(dummy_read_1_table->bo); 1079 } 1080 1081 /** 1082 * smu_alloc_memory_pool - allocate memory pool in the system memory 1083 * 1084 * @smu: amdgpu_device pointer 1085 * 1086 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 1087 * and DramLogSetDramAddr can notify it changed. 1088 * 1089 * Returns 0 on success, error on failure. 1090 */ 1091 static int smu_alloc_memory_pool(struct smu_context *smu) 1092 { 1093 struct amdgpu_device *adev = smu->adev; 1094 struct smu_table_context *smu_table = &smu->smu_table; 1095 struct smu_table *memory_pool = &smu_table->memory_pool; 1096 uint64_t pool_size = smu->pool_size; 1097 int ret = 0; 1098 1099 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1100 return ret; 1101 1102 memory_pool->size = pool_size; 1103 memory_pool->align = PAGE_SIZE; 1104 memory_pool->domain = 1105 (adev->pm.smu_debug_mask & SMU_DEBUG_POOL_USE_VRAM) ? 1106 AMDGPU_GEM_DOMAIN_VRAM : 1107 AMDGPU_GEM_DOMAIN_GTT; 1108 1109 switch (pool_size) { 1110 case SMU_MEMORY_POOL_SIZE_256_MB: 1111 case SMU_MEMORY_POOL_SIZE_512_MB: 1112 case SMU_MEMORY_POOL_SIZE_1_GB: 1113 case SMU_MEMORY_POOL_SIZE_2_GB: 1114 ret = amdgpu_bo_create_kernel(adev, 1115 memory_pool->size, 1116 memory_pool->align, 1117 memory_pool->domain, 1118 &memory_pool->bo, 1119 &memory_pool->mc_address, 1120 &memory_pool->cpu_addr); 1121 if (ret) 1122 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1123 break; 1124 default: 1125 break; 1126 } 1127 1128 return ret; 1129 } 1130 1131 static int smu_free_memory_pool(struct smu_context *smu) 1132 { 1133 struct smu_table_context *smu_table = &smu->smu_table; 1134 struct smu_table *memory_pool = &smu_table->memory_pool; 1135 1136 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1137 return 0; 1138 1139 amdgpu_bo_free_kernel(&memory_pool->bo, 1140 &memory_pool->mc_address, 1141 &memory_pool->cpu_addr); 1142 1143 memset(memory_pool, 0, sizeof(struct smu_table)); 1144 1145 return 0; 1146 } 1147 1148 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1149 { 1150 struct smu_table_context *smu_table = &smu->smu_table; 1151 struct smu_table *dummy_read_1_table = 1152 &smu_table->dummy_read_1_table; 1153 struct amdgpu_device *adev = smu->adev; 1154 int ret = 0; 1155 1156 if (!dummy_read_1_table->size) 1157 return 0; 1158 1159 ret = amdgpu_bo_create_kernel(adev, 1160 dummy_read_1_table->size, 1161 dummy_read_1_table->align, 1162 dummy_read_1_table->domain, 1163 &dummy_read_1_table->bo, 1164 &dummy_read_1_table->mc_address, 1165 &dummy_read_1_table->cpu_addr); 1166 if (ret) 1167 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1168 1169 return ret; 1170 } 1171 1172 static void smu_free_dummy_read_table(struct smu_context *smu) 1173 { 1174 struct smu_table_context *smu_table = &smu->smu_table; 1175 struct smu_table *dummy_read_1_table = 1176 &smu_table->dummy_read_1_table; 1177 1178 1179 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1180 &dummy_read_1_table->mc_address, 1181 &dummy_read_1_table->cpu_addr); 1182 1183 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1184 } 1185 1186 static int smu_smc_table_sw_init(struct smu_context *smu) 1187 { 1188 int ret; 1189 1190 /** 1191 * Create smu_table structure, and init smc tables such as 1192 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1193 */ 1194 ret = smu_init_smc_tables(smu); 1195 if (ret) { 1196 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1197 return ret; 1198 } 1199 1200 /** 1201 * Create smu_power_context structure, and allocate smu_dpm_context and 1202 * context size to fill the smu_power_context data. 1203 */ 1204 ret = smu_init_power(smu); 1205 if (ret) { 1206 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1207 return ret; 1208 } 1209 1210 /* 1211 * allocate vram bos to store smc table contents. 1212 */ 1213 ret = smu_init_fb_allocations(smu); 1214 if (ret) 1215 return ret; 1216 1217 ret = smu_alloc_memory_pool(smu); 1218 if (ret) 1219 return ret; 1220 1221 ret = smu_alloc_dummy_read_table(smu); 1222 if (ret) 1223 return ret; 1224 1225 ret = smu_i2c_init(smu); 1226 if (ret) 1227 return ret; 1228 1229 return 0; 1230 } 1231 1232 static int smu_smc_table_sw_fini(struct smu_context *smu) 1233 { 1234 int ret; 1235 1236 smu_i2c_fini(smu); 1237 1238 smu_free_dummy_read_table(smu); 1239 1240 ret = smu_free_memory_pool(smu); 1241 if (ret) 1242 return ret; 1243 1244 ret = smu_fini_fb_allocations(smu); 1245 if (ret) 1246 return ret; 1247 1248 ret = smu_fini_power(smu); 1249 if (ret) { 1250 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1251 return ret; 1252 } 1253 1254 ret = smu_fini_smc_tables(smu); 1255 if (ret) { 1256 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1257 return ret; 1258 } 1259 1260 return 0; 1261 } 1262 1263 static void smu_throttling_logging_work_fn(struct work_struct *work) 1264 { 1265 struct smu_context *smu = container_of(work, struct smu_context, 1266 throttling_logging_work); 1267 1268 smu_log_thermal_throttling(smu); 1269 } 1270 1271 static void smu_interrupt_work_fn(struct work_struct *work) 1272 { 1273 struct smu_context *smu = container_of(work, struct smu_context, 1274 interrupt_work); 1275 1276 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1277 smu->ppt_funcs->interrupt_work(smu); 1278 } 1279 1280 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1281 { 1282 struct smu_context *smu = 1283 container_of(work, struct smu_context, swctf_delayed_work.work); 1284 struct smu_temperature_range *range = 1285 &smu->thermal_range; 1286 struct amdgpu_device *adev = smu->adev; 1287 uint32_t hotspot_tmp, size; 1288 1289 /* 1290 * If the hotspot temperature is confirmed as below SW CTF setting point 1291 * after the delay enforced, nothing will be done. 1292 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1293 */ 1294 if (range->software_shutdown_temp && 1295 smu->ppt_funcs->read_sensor && 1296 !smu->ppt_funcs->read_sensor(smu, 1297 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1298 &hotspot_tmp, 1299 &size) && 1300 hotspot_tmp / 1000 < range->software_shutdown_temp) 1301 return; 1302 1303 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1304 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1305 orderly_poweroff(true); 1306 } 1307 1308 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1309 { 1310 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1311 struct smu_dpm_policy_ctxt *policy_ctxt; 1312 struct smu_dpm_policy *policy; 1313 1314 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1315 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1316 if (policy) 1317 policy->current_level = XGMI_PLPD_DEFAULT; 1318 return; 1319 } 1320 1321 /* PMFW put PLPD into default policy after enabling the feature */ 1322 if (smu_feature_is_enabled(smu, 1323 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1324 if (policy) 1325 policy->current_level = XGMI_PLPD_DEFAULT; 1326 } else { 1327 policy_ctxt = dpm_ctxt->dpm_policies; 1328 if (policy_ctxt) 1329 policy_ctxt->policy_mask &= 1330 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1331 } 1332 } 1333 1334 static void smu_init_power_profile(struct smu_context *smu) 1335 { 1336 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) 1337 smu->power_profile_mode = 1338 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1339 smu_power_profile_mode_get(smu, smu->power_profile_mode); 1340 } 1341 1342 void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id) 1343 { 1344 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1345 1346 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT) 1347 return; 1348 1349 set_bit(fea_id, fea_cap->cap_map); 1350 } 1351 1352 bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id) 1353 { 1354 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1355 1356 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT) 1357 return false; 1358 1359 return test_bit(fea_id, fea_cap->cap_map); 1360 } 1361 1362 static void smu_feature_cap_init(struct smu_context *smu) 1363 { 1364 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1365 1366 bitmap_zero(fea_cap->cap_map, SMU_FEATURE_CAP_ID__COUNT); 1367 } 1368 1369 static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1370 { 1371 struct amdgpu_device *adev = ip_block->adev; 1372 struct smu_context *smu = adev->powerplay.pp_handle; 1373 int i, ret; 1374 1375 smu->pool_size = adev->pm.smu_prv_buffer_size; 1376 smu_feature_init(smu, SMU_FEATURE_NUM_DEFAULT); 1377 1378 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1379 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1380 atomic64_set(&smu->throttle_int_counter, 0); 1381 smu->watermarks_bitmap = 0; 1382 1383 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1384 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1); 1385 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1386 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1387 atomic_set(&smu->smu_power.power_gate.isp_gated, 1); 1388 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1389 1390 smu_init_power_profile(smu); 1391 smu->display_config = &adev->pm.pm_display_cfg; 1392 1393 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1394 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1395 1396 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1397 smu_swctf_delayed_work_handler); 1398 1399 smu_feature_cap_init(smu); 1400 1401 ret = smu_smc_table_sw_init(smu); 1402 if (ret) { 1403 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1404 return ret; 1405 } 1406 1407 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1408 ret = smu_get_vbios_bootup_values(smu); 1409 if (ret) { 1410 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1411 return ret; 1412 } 1413 1414 ret = smu_init_pptable_microcode(smu); 1415 if (ret) { 1416 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1417 return ret; 1418 } 1419 1420 ret = smu_register_irq_handler(smu); 1421 if (ret) { 1422 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1423 return ret; 1424 } 1425 1426 /* If there is no way to query fan control mode, fan control is not supported */ 1427 if (!smu->ppt_funcs->get_fan_control_mode) 1428 smu->adev->pm.no_fan = true; 1429 1430 return 0; 1431 } 1432 1433 static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1434 { 1435 struct amdgpu_device *adev = ip_block->adev; 1436 struct smu_context *smu = adev->powerplay.pp_handle; 1437 int ret; 1438 1439 ret = smu_smc_table_sw_fini(smu); 1440 if (ret) { 1441 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1442 return ret; 1443 } 1444 1445 if (smu->custom_profile_params) { 1446 kfree(smu->custom_profile_params); 1447 smu->custom_profile_params = NULL; 1448 } 1449 1450 smu_fini_microcode(smu); 1451 1452 return 0; 1453 } 1454 1455 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1456 { 1457 struct amdgpu_device *adev = smu->adev; 1458 struct smu_temperature_range *range = 1459 &smu->thermal_range; 1460 int ret = 0; 1461 1462 if (!smu->ppt_funcs->get_thermal_temperature_range) 1463 return 0; 1464 1465 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1466 if (ret) 1467 return ret; 1468 1469 adev->pm.dpm.thermal.min_temp = range->min; 1470 adev->pm.dpm.thermal.max_temp = range->max; 1471 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1472 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1473 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1474 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1475 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1476 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1477 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1478 1479 return ret; 1480 } 1481 1482 /** 1483 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1484 * 1485 * @smu: smu_context pointer 1486 * 1487 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1488 * Returns 0 on success, error on failure. 1489 */ 1490 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1491 { 1492 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1493 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1494 struct amdgpu_device *adev = smu->adev; 1495 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1496 uint64_t start, end; 1497 int ret, i, j; 1498 1499 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1500 if (ret) { 1501 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1502 return ret; 1503 } 1504 1505 /* 1506 * The exclusion ranges array we got might be filled with holes and duplicate 1507 * entries. For example: 1508 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1509 * We need to do some sortups to eliminate those holes and duplicate entries. 1510 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1511 */ 1512 for (i = 0; i < num_of_wbrf_ranges; i++) { 1513 start = wifi_bands[i].start; 1514 end = wifi_bands[i].end; 1515 1516 /* get the last valid entry to fill the intermediate hole */ 1517 if (!start && !end) { 1518 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1519 if (wifi_bands[j].start && wifi_bands[j].end) 1520 break; 1521 1522 /* no valid entry left */ 1523 if (j <= i) 1524 break; 1525 1526 start = wifi_bands[i].start = wifi_bands[j].start; 1527 end = wifi_bands[i].end = wifi_bands[j].end; 1528 wifi_bands[j].start = 0; 1529 wifi_bands[j].end = 0; 1530 num_of_wbrf_ranges = j; 1531 } 1532 1533 /* eliminate duplicate entries */ 1534 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1535 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1536 wifi_bands[j].start = 0; 1537 wifi_bands[j].end = 0; 1538 } 1539 } 1540 } 1541 1542 /* Send the sorted wifi_bands to PMFW */ 1543 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1544 /* Try to set the wifi_bands again */ 1545 if (unlikely(ret == -EBUSY)) { 1546 mdelay(5); 1547 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1548 } 1549 1550 return ret; 1551 } 1552 1553 /** 1554 * smu_wbrf_event_handler - handle notify events 1555 * 1556 * @nb: notifier block 1557 * @action: event type 1558 * @_arg: event data 1559 * 1560 * Calls relevant amdgpu function in response to wbrf event 1561 * notification from kernel. 1562 */ 1563 static int smu_wbrf_event_handler(struct notifier_block *nb, 1564 unsigned long action, void *_arg) 1565 { 1566 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1567 1568 switch (action) { 1569 case WBRF_CHANGED: 1570 schedule_delayed_work(&smu->wbrf_delayed_work, 1571 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1572 break; 1573 default: 1574 return NOTIFY_DONE; 1575 } 1576 1577 return NOTIFY_OK; 1578 } 1579 1580 /** 1581 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1582 * 1583 * @work: struct work_struct pointer 1584 * 1585 * Flood is over and driver will consume the latest exclusion ranges. 1586 */ 1587 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1588 { 1589 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1590 1591 smu_wbrf_handle_exclusion_ranges(smu); 1592 } 1593 1594 /** 1595 * smu_wbrf_support_check - check wbrf support 1596 * 1597 * @smu: smu_context pointer 1598 * 1599 * Verifies the ACPI interface whether wbrf is supported. 1600 */ 1601 static void smu_wbrf_support_check(struct smu_context *smu) 1602 { 1603 struct amdgpu_device *adev = smu->adev; 1604 1605 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1606 acpi_amd_wbrf_supported_consumer(adev->dev); 1607 1608 if (smu->wbrf_supported) 1609 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1610 } 1611 1612 /** 1613 * smu_wbrf_init - init driver wbrf support 1614 * 1615 * @smu: smu_context pointer 1616 * 1617 * Verifies the AMD ACPI interfaces and registers with the wbrf 1618 * notifier chain if wbrf feature is supported. 1619 * Returns 0 on success, error on failure. 1620 */ 1621 static int smu_wbrf_init(struct smu_context *smu) 1622 { 1623 int ret; 1624 1625 if (!smu->wbrf_supported) 1626 return 0; 1627 1628 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1629 1630 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1631 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1632 if (ret) 1633 return ret; 1634 1635 /* 1636 * Some wifiband exclusion ranges may be already there 1637 * before our driver loaded. To make sure our driver 1638 * is awared of those exclusion ranges. 1639 */ 1640 schedule_delayed_work(&smu->wbrf_delayed_work, 1641 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1642 1643 return 0; 1644 } 1645 1646 /** 1647 * smu_wbrf_fini - tear down driver wbrf support 1648 * 1649 * @smu: smu_context pointer 1650 * 1651 * Unregisters with the wbrf notifier chain. 1652 */ 1653 static void smu_wbrf_fini(struct smu_context *smu) 1654 { 1655 if (!smu->wbrf_supported) 1656 return; 1657 1658 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1659 1660 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1661 } 1662 1663 static int smu_smc_hw_setup(struct smu_context *smu) 1664 { 1665 struct amdgpu_device *adev = smu->adev; 1666 uint8_t pcie_gen = 0, pcie_width = 0; 1667 struct smu_feature_bits features_supported; 1668 int ret = 0; 1669 1670 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1671 case IP_VERSION(11, 0, 7): 1672 case IP_VERSION(11, 0, 11): 1673 case IP_VERSION(11, 5, 0): 1674 case IP_VERSION(11, 5, 2): 1675 case IP_VERSION(11, 0, 12): 1676 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1677 dev_info(adev->dev, "dpm has been enabled\n"); 1678 ret = smu_system_features_control(smu, true); 1679 if (ret) { 1680 dev_err(adev->dev, "Failed system features control!\n"); 1681 return ret; 1682 } 1683 1684 return smu_enable_thermal_alert(smu); 1685 } 1686 break; 1687 default: 1688 break; 1689 } 1690 1691 ret = smu_init_display_count(smu, 0); 1692 if (ret) { 1693 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1694 return ret; 1695 } 1696 1697 ret = smu_set_driver_table_location(smu); 1698 if (ret) { 1699 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1700 return ret; 1701 } 1702 1703 /* 1704 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1705 */ 1706 ret = smu_set_tool_table_location(smu); 1707 if (ret) { 1708 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1709 return ret; 1710 } 1711 1712 /* 1713 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1714 * pool location. 1715 */ 1716 ret = smu_notify_memory_pool_location(smu); 1717 if (ret) { 1718 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1719 return ret; 1720 } 1721 1722 /* 1723 * It is assumed the pptable used before runpm is same as 1724 * the one used afterwards. Thus, we can reuse the stored 1725 * copy and do not need to resetup the pptable again. 1726 */ 1727 if (!adev->in_runpm) { 1728 ret = smu_setup_pptable(smu); 1729 if (ret) { 1730 dev_err(adev->dev, "Failed to setup pptable!\n"); 1731 return ret; 1732 } 1733 } 1734 1735 /* smu_dump_pptable(smu); */ 1736 1737 /* 1738 * With SCPM enabled, PSP is responsible for the PPTable transferring 1739 * (to SMU). Driver involvement is not needed and permitted. 1740 */ 1741 if (!adev->scpm_enabled) { 1742 /* 1743 * Copy pptable bo in the vram to smc with SMU MSGs such as 1744 * SetDriverDramAddr and TransferTableDram2Smu. 1745 */ 1746 ret = smu_write_pptable(smu); 1747 if (ret) { 1748 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1749 return ret; 1750 } 1751 } 1752 1753 /* issue Run*Btc msg */ 1754 ret = smu_run_btc(smu); 1755 if (ret) 1756 return ret; 1757 1758 /* Enable UclkShadow on wbrf supported */ 1759 if (smu->wbrf_supported) { 1760 ret = smu_enable_uclk_shadow(smu, true); 1761 if (ret) { 1762 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1763 return ret; 1764 } 1765 } 1766 1767 /* 1768 * With SCPM enabled, these actions(and relevant messages) are 1769 * not needed and permitted. 1770 */ 1771 if (!adev->scpm_enabled) { 1772 ret = smu_feature_set_allowed_mask(smu); 1773 if (ret) { 1774 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1775 return ret; 1776 } 1777 } 1778 1779 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) 1780 pcie_gen = 4; 1781 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1782 pcie_gen = 3; 1783 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1784 pcie_gen = 2; 1785 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1786 pcie_gen = 1; 1787 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1788 pcie_gen = 0; 1789 1790 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1791 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1792 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1793 */ 1794 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) 1795 pcie_width = 7; 1796 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1797 pcie_width = 6; 1798 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1799 pcie_width = 5; 1800 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1801 pcie_width = 4; 1802 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1803 pcie_width = 3; 1804 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1805 pcie_width = 2; 1806 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1807 pcie_width = 1; 1808 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1809 if (ret) { 1810 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1811 return ret; 1812 } 1813 1814 ret = smu_system_features_control(smu, true); 1815 if (ret) { 1816 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1817 return ret; 1818 } 1819 1820 smu_init_xgmi_plpd_mode(smu); 1821 1822 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1823 if (ret) { 1824 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1825 return ret; 1826 } 1827 smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED, 1828 features_supported.bits); 1829 1830 if (!smu_is_dpm_running(smu)) 1831 dev_info(adev->dev, "dpm has been disabled\n"); 1832 1833 /* 1834 * Set initialized values (get from vbios) to dpm tables context such as 1835 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1836 * type of clks. 1837 */ 1838 ret = smu_set_default_dpm_table(smu); 1839 if (ret) { 1840 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1841 return ret; 1842 } 1843 1844 ret = smu_get_thermal_temperature_range(smu); 1845 if (ret) { 1846 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1847 return ret; 1848 } 1849 1850 ret = smu_enable_thermal_alert(smu); 1851 if (ret) { 1852 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1853 return ret; 1854 } 1855 1856 ret = smu_notify_display_change(smu); 1857 if (ret) { 1858 dev_err(adev->dev, "Failed to notify display change!\n"); 1859 return ret; 1860 } 1861 1862 /* 1863 * Set min deep sleep dce fclk with bootup value from vbios via 1864 * SetMinDeepSleepDcefclk MSG. 1865 */ 1866 ret = smu_set_min_dcef_deep_sleep(smu, 1867 smu->smu_table.boot_values.dcefclk / 100); 1868 if (ret) { 1869 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1870 return ret; 1871 } 1872 1873 /* Init wbrf support. Properly setup the notifier */ 1874 ret = smu_wbrf_init(smu); 1875 if (ret) 1876 dev_err(adev->dev, "Error during wbrf init call\n"); 1877 1878 return ret; 1879 } 1880 1881 static int smu_start_smc_engine(struct smu_context *smu) 1882 { 1883 struct amdgpu_device *adev = smu->adev; 1884 int ret = 0; 1885 1886 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 1887 smu_update_gpu_addresses(smu); 1888 1889 smu->smc_fw_state = SMU_FW_INIT; 1890 1891 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1892 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1893 if (smu->ppt_funcs->load_microcode) { 1894 ret = smu->ppt_funcs->load_microcode(smu); 1895 if (ret) 1896 return ret; 1897 } 1898 } 1899 } 1900 1901 if (smu->ppt_funcs->check_fw_status) { 1902 ret = smu->ppt_funcs->check_fw_status(smu); 1903 if (ret) { 1904 dev_err(adev->dev, "SMC is not ready\n"); 1905 return ret; 1906 } 1907 } 1908 1909 /* 1910 * Send msg GetDriverIfVersion to check if the return value is equal 1911 * with DRIVER_IF_VERSION of smc header. 1912 */ 1913 ret = smu_check_fw_version(smu); 1914 if (ret) 1915 return ret; 1916 1917 return ret; 1918 } 1919 1920 static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1921 { 1922 int i, ret; 1923 struct amdgpu_device *adev = ip_block->adev; 1924 struct smu_context *smu = adev->powerplay.pp_handle; 1925 1926 if (amdgpu_sriov_multi_vf_mode(adev)) { 1927 smu->pm_enabled = false; 1928 return 0; 1929 } 1930 1931 ret = smu_start_smc_engine(smu); 1932 if (ret) { 1933 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1934 return ret; 1935 } 1936 1937 /* 1938 * Check whether wbrf is supported. This needs to be done 1939 * before SMU setup starts since part of SMU configuration 1940 * relies on this. 1941 */ 1942 smu_wbrf_support_check(smu); 1943 1944 if (smu->is_apu) { 1945 ret = smu_set_gfx_imu_enable(smu); 1946 if (ret) 1947 return ret; 1948 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1949 smu_dpm_set_vcn_enable(smu, true, i); 1950 smu_dpm_set_jpeg_enable(smu, true); 1951 smu_dpm_set_umsch_mm_enable(smu, true); 1952 smu_set_mall_enable(smu); 1953 smu_set_gfx_cgpg(smu, true); 1954 } 1955 1956 if (!smu->pm_enabled) 1957 return 0; 1958 1959 ret = smu_init_driver_allowed_feature_mask(smu); 1960 if (ret) 1961 return ret; 1962 1963 ret = smu_smc_hw_setup(smu); 1964 if (ret) { 1965 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1966 return ret; 1967 } 1968 1969 /* 1970 * Move maximum sustainable clock retrieving here considering 1971 * 1. It is not needed on resume(from S3). 1972 * 2. DAL settings come between .hw_init and .late_init of SMU. 1973 * And DAL needs to know the maximum sustainable clocks. Thus 1974 * it cannot be put in .late_init(). 1975 */ 1976 ret = smu_init_max_sustainable_clocks(smu); 1977 if (ret) { 1978 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1979 return ret; 1980 } 1981 1982 adev->pm.dpm_enabled = true; 1983 1984 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1985 1986 return 0; 1987 } 1988 1989 static int smu_disable_dpms(struct smu_context *smu) 1990 { 1991 struct amdgpu_device *adev = smu->adev; 1992 int ret = 0; 1993 bool use_baco = !smu->is_apu && 1994 ((amdgpu_in_reset(adev) && 1995 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1996 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1997 1998 /* 1999 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 2000 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 2001 */ 2002 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2003 case IP_VERSION(13, 0, 0): 2004 case IP_VERSION(13, 0, 7): 2005 case IP_VERSION(13, 0, 10): 2006 case IP_VERSION(14, 0, 2): 2007 case IP_VERSION(14, 0, 3): 2008 return 0; 2009 default: 2010 break; 2011 } 2012 2013 /* 2014 * For custom pptable uploading, skip the DPM features 2015 * disable process on Navi1x ASICs. 2016 * - As the gfx related features are under control of 2017 * RLC on those ASICs. RLC reinitialization will be 2018 * needed to reenable them. That will cost much more 2019 * efforts. 2020 * 2021 * - SMU firmware can handle the DPM reenablement 2022 * properly. 2023 */ 2024 if (smu->uploading_custom_pp_table) { 2025 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2026 case IP_VERSION(11, 0, 0): 2027 case IP_VERSION(11, 0, 5): 2028 case IP_VERSION(11, 0, 9): 2029 case IP_VERSION(11, 0, 7): 2030 case IP_VERSION(11, 0, 11): 2031 case IP_VERSION(11, 5, 0): 2032 case IP_VERSION(11, 5, 2): 2033 case IP_VERSION(11, 0, 12): 2034 case IP_VERSION(11, 0, 13): 2035 return 0; 2036 default: 2037 break; 2038 } 2039 } 2040 2041 /* 2042 * For Sienna_Cichlid, PMFW will handle the features disablement properly 2043 * on BACO in. Driver involvement is unnecessary. 2044 */ 2045 if (use_baco) { 2046 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2047 case IP_VERSION(11, 0, 7): 2048 case IP_VERSION(11, 0, 0): 2049 case IP_VERSION(11, 0, 5): 2050 case IP_VERSION(11, 0, 9): 2051 case IP_VERSION(13, 0, 7): 2052 return 0; 2053 default: 2054 break; 2055 } 2056 } 2057 2058 /* 2059 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 2060 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 2061 */ 2062 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 2063 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 2064 return 0; 2065 2066 /* vangogh s0ix */ 2067 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) || 2068 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2)) && 2069 adev->in_s0ix) 2070 return 0; 2071 2072 /* 2073 * For gpu reset, runpm and hibernation through BACO, 2074 * BACO feature has to be kept enabled. 2075 */ 2076 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 2077 ret = smu_disable_all_features_with_exception(smu, 2078 SMU_FEATURE_BACO_BIT); 2079 if (ret) 2080 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 2081 } else { 2082 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 2083 if (!adev->scpm_enabled) { 2084 ret = smu_system_features_control(smu, false); 2085 if (ret) 2086 dev_err(adev->dev, "Failed to disable smu features.\n"); 2087 } 2088 } 2089 2090 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 2091 * otherwise SMU will hang while interacting with RLC if RLC is halted 2092 * this is a WA for Vangogh asic which fix the SMU hang issue. 2093 */ 2094 ret = smu_notify_rlc_state(smu, false); 2095 if (ret) { 2096 dev_err(adev->dev, "Fail to notify rlc status!\n"); 2097 return ret; 2098 } 2099 2100 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 2101 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 2102 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 2103 adev->gfx.rlc.funcs->stop(adev); 2104 2105 return ret; 2106 } 2107 2108 static int smu_smc_hw_cleanup(struct smu_context *smu) 2109 { 2110 struct amdgpu_device *adev = smu->adev; 2111 int ret = 0; 2112 2113 smu_wbrf_fini(smu); 2114 2115 cancel_work_sync(&smu->throttling_logging_work); 2116 cancel_work_sync(&smu->interrupt_work); 2117 2118 ret = smu_disable_thermal_alert(smu); 2119 if (ret) { 2120 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 2121 return ret; 2122 } 2123 2124 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2125 2126 ret = smu_disable_dpms(smu); 2127 if (ret) { 2128 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2129 return ret; 2130 } 2131 2132 return 0; 2133 } 2134 2135 static int smu_reset_mp1_state(struct smu_context *smu) 2136 { 2137 struct amdgpu_device *adev = smu->adev; 2138 int ret = 0; 2139 2140 if ((!adev->in_runpm) && (!adev->in_suspend) && 2141 (!amdgpu_in_reset(adev)) && !smu->is_apu && 2142 amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(13, 0, 0)) 2143 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2144 2145 return ret; 2146 } 2147 2148 static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2149 { 2150 struct amdgpu_device *adev = ip_block->adev; 2151 struct smu_context *smu = adev->powerplay.pp_handle; 2152 int i, ret; 2153 2154 if (amdgpu_sriov_multi_vf_mode(adev)) 2155 return 0; 2156 2157 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2158 smu_dpm_set_vcn_enable(smu, false, i); 2159 adev->vcn.inst[i].cur_state = AMD_PG_STATE_GATE; 2160 } 2161 smu_dpm_set_jpeg_enable(smu, false); 2162 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2163 smu_dpm_set_umsch_mm_enable(smu, false); 2164 2165 if (!smu->pm_enabled) 2166 return 0; 2167 2168 adev->pm.dpm_enabled = false; 2169 2170 ret = smu_smc_hw_cleanup(smu); 2171 if (ret) 2172 return ret; 2173 2174 ret = smu_reset_mp1_state(smu); 2175 if (ret) 2176 return ret; 2177 2178 return 0; 2179 } 2180 2181 static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2182 { 2183 struct amdgpu_device *adev = ip_block->adev; 2184 struct smu_context *smu = adev->powerplay.pp_handle; 2185 2186 kfree(smu); 2187 } 2188 2189 static int smu_reset(struct smu_context *smu) 2190 { 2191 struct amdgpu_device *adev = smu->adev; 2192 struct amdgpu_ip_block *ip_block; 2193 int ret; 2194 2195 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2196 if (!ip_block) 2197 return -EINVAL; 2198 2199 ret = smu_hw_fini(ip_block); 2200 if (ret) 2201 return ret; 2202 2203 ret = smu_hw_init(ip_block); 2204 if (ret) 2205 return ret; 2206 2207 ret = smu_late_init(ip_block); 2208 if (ret) 2209 return ret; 2210 2211 return 0; 2212 } 2213 2214 static int smu_suspend(struct amdgpu_ip_block *ip_block) 2215 { 2216 struct amdgpu_device *adev = ip_block->adev; 2217 struct smu_context *smu = adev->powerplay.pp_handle; 2218 int ret; 2219 uint64_t count; 2220 2221 if (amdgpu_sriov_multi_vf_mode(adev)) 2222 return 0; 2223 2224 if (!smu->pm_enabled) 2225 return 0; 2226 2227 adev->pm.dpm_enabled = false; 2228 2229 ret = smu_smc_hw_cleanup(smu); 2230 if (ret) 2231 return ret; 2232 2233 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2234 2235 smu_set_gfx_cgpg(smu, false); 2236 2237 /* 2238 * pwfw resets entrycount when device is suspended, so we save the 2239 * last value to be used when we resume to keep it consistent 2240 */ 2241 ret = smu_get_entrycount_gfxoff(smu, &count); 2242 if (!ret) 2243 adev->gfx.gfx_off_entrycount = count; 2244 2245 /* clear this on suspend so it will get reprogrammed on resume */ 2246 smu->workload_mask = 0; 2247 2248 return 0; 2249 } 2250 2251 static int smu_resume(struct amdgpu_ip_block *ip_block) 2252 { 2253 int ret; 2254 struct amdgpu_device *adev = ip_block->adev; 2255 struct smu_context *smu = adev->powerplay.pp_handle; 2256 2257 if (amdgpu_sriov_multi_vf_mode(adev)) 2258 return 0; 2259 2260 if (!smu->pm_enabled) 2261 return 0; 2262 2263 dev_info(adev->dev, "SMU is resuming...\n"); 2264 2265 ret = smu_start_smc_engine(smu); 2266 if (ret) { 2267 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2268 return ret; 2269 } 2270 2271 ret = smu_smc_hw_setup(smu); 2272 if (ret) { 2273 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2274 return ret; 2275 } 2276 2277 ret = smu_set_gfx_imu_enable(smu); 2278 if (ret) 2279 return ret; 2280 2281 smu_set_gfx_cgpg(smu, true); 2282 2283 smu->disable_uclk_switch = 0; 2284 2285 adev->pm.dpm_enabled = true; 2286 2287 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2288 2289 return 0; 2290 } 2291 2292 static int smu_display_configuration_change(void *handle, 2293 const struct amd_pp_display_configuration *display_config) 2294 { 2295 struct smu_context *smu = handle; 2296 2297 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2298 return -EOPNOTSUPP; 2299 2300 if (!display_config) 2301 return -EINVAL; 2302 2303 smu_set_min_dcef_deep_sleep(smu, 2304 display_config->min_dcef_deep_sleep_set_clk / 100); 2305 2306 return 0; 2307 } 2308 2309 static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2310 enum amd_clockgating_state state) 2311 { 2312 return 0; 2313 } 2314 2315 static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block, 2316 enum amd_powergating_state state) 2317 { 2318 return 0; 2319 } 2320 2321 static int smu_enable_umd_pstate(void *handle, 2322 enum amd_dpm_forced_level *level) 2323 { 2324 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2325 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2326 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2327 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2328 2329 struct smu_context *smu = (struct smu_context*)(handle); 2330 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2331 2332 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2333 return -EINVAL; 2334 2335 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2336 /* enter umd pstate, save current level, disable gfx cg*/ 2337 if (*level & profile_mode_mask) { 2338 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2339 smu_gpo_control(smu, false); 2340 smu_gfx_ulv_control(smu, false); 2341 smu_deep_sleep_control(smu, false); 2342 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2343 } 2344 } else { 2345 /* exit umd pstate, restore level, enable gfx cg*/ 2346 if (!(*level & profile_mode_mask)) { 2347 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2348 *level = smu_dpm_ctx->saved_dpm_level; 2349 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2350 smu_deep_sleep_control(smu, true); 2351 smu_gfx_ulv_control(smu, true); 2352 smu_gpo_control(smu, true); 2353 } 2354 } 2355 2356 return 0; 2357 } 2358 2359 static int smu_bump_power_profile_mode(struct smu_context *smu, 2360 long *custom_params, 2361 u32 custom_params_max_idx) 2362 { 2363 u32 workload_mask = 0; 2364 int i, ret = 0; 2365 2366 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2367 if (smu->workload_refcount[i]) 2368 workload_mask |= 1 << i; 2369 } 2370 2371 if (smu->workload_mask == workload_mask) 2372 return 0; 2373 2374 if (smu->ppt_funcs->set_power_profile_mode) 2375 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask, 2376 custom_params, 2377 custom_params_max_idx); 2378 2379 if (!ret) 2380 smu->workload_mask = workload_mask; 2381 2382 return ret; 2383 } 2384 2385 static void smu_power_profile_mode_get(struct smu_context *smu, 2386 enum PP_SMC_POWER_PROFILE profile_mode) 2387 { 2388 smu->workload_refcount[profile_mode]++; 2389 } 2390 2391 static void smu_power_profile_mode_put(struct smu_context *smu, 2392 enum PP_SMC_POWER_PROFILE profile_mode) 2393 { 2394 if (smu->workload_refcount[profile_mode]) 2395 smu->workload_refcount[profile_mode]--; 2396 } 2397 2398 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2399 enum amd_dpm_forced_level level, 2400 bool skip_display_settings) 2401 { 2402 int ret = 0; 2403 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2404 2405 if (!skip_display_settings) { 2406 ret = smu_display_config_changed(smu); 2407 if (ret) { 2408 dev_err(smu->adev->dev, "Failed to change display config!"); 2409 return ret; 2410 } 2411 } 2412 2413 ret = smu_apply_clocks_adjust_rules(smu); 2414 if (ret) { 2415 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2416 return ret; 2417 } 2418 2419 if (!skip_display_settings) { 2420 ret = smu_notify_smc_display_config(smu); 2421 if (ret) { 2422 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2423 return ret; 2424 } 2425 } 2426 2427 if (smu_dpm_ctx->dpm_level != level) { 2428 ret = smu_asic_set_performance_level(smu, level); 2429 if (ret) { 2430 if (ret == -EOPNOTSUPP) 2431 dev_info(smu->adev->dev, "set performance level %d not supported", 2432 level); 2433 else 2434 dev_err(smu->adev->dev, "Failed to set performance level %d", 2435 level); 2436 return ret; 2437 } 2438 2439 /* update the saved copy */ 2440 smu_dpm_ctx->dpm_level = level; 2441 } 2442 2443 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2444 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2445 smu_bump_power_profile_mode(smu, NULL, 0); 2446 2447 return ret; 2448 } 2449 2450 static int smu_handle_task(struct smu_context *smu, 2451 enum amd_dpm_forced_level level, 2452 enum amd_pp_task task_id) 2453 { 2454 int ret = 0; 2455 2456 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2457 return -EOPNOTSUPP; 2458 2459 switch (task_id) { 2460 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2461 ret = smu_pre_display_config_changed(smu); 2462 if (ret) 2463 return ret; 2464 ret = smu_adjust_power_state_dynamic(smu, level, false); 2465 break; 2466 case AMD_PP_TASK_COMPLETE_INIT: 2467 ret = smu_adjust_power_state_dynamic(smu, level, true); 2468 break; 2469 case AMD_PP_TASK_READJUST_POWER_STATE: 2470 ret = smu_adjust_power_state_dynamic(smu, level, true); 2471 break; 2472 default: 2473 break; 2474 } 2475 2476 return ret; 2477 } 2478 2479 static int smu_handle_dpm_task(void *handle, 2480 enum amd_pp_task task_id, 2481 enum amd_pm_state_type *user_state) 2482 { 2483 struct smu_context *smu = handle; 2484 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2485 2486 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2487 2488 } 2489 2490 static int smu_switch_power_profile(void *handle, 2491 enum PP_SMC_POWER_PROFILE type, 2492 bool enable) 2493 { 2494 struct smu_context *smu = handle; 2495 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2496 int ret; 2497 2498 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2499 return -EOPNOTSUPP; 2500 2501 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2502 return -EINVAL; 2503 2504 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2505 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2506 if (enable) 2507 smu_power_profile_mode_get(smu, type); 2508 else 2509 smu_power_profile_mode_put(smu, type); 2510 /* don't switch the active workload when paused */ 2511 if (smu->pause_workload) 2512 ret = 0; 2513 else 2514 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2515 if (ret) { 2516 if (enable) 2517 smu_power_profile_mode_put(smu, type); 2518 else 2519 smu_power_profile_mode_get(smu, type); 2520 return ret; 2521 } 2522 } 2523 2524 return 0; 2525 } 2526 2527 static int smu_pause_power_profile(void *handle, 2528 bool pause) 2529 { 2530 struct smu_context *smu = handle; 2531 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2532 u32 workload_mask = 1 << PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 2533 int ret; 2534 2535 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2536 return -EOPNOTSUPP; 2537 2538 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2539 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2540 smu->pause_workload = pause; 2541 2542 /* force to bootup default profile */ 2543 if (smu->pause_workload && smu->ppt_funcs->set_power_profile_mode) 2544 ret = smu->ppt_funcs->set_power_profile_mode(smu, 2545 workload_mask, 2546 NULL, 2547 0); 2548 else 2549 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2550 return ret; 2551 } 2552 2553 return 0; 2554 } 2555 2556 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2557 { 2558 struct smu_context *smu = handle; 2559 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2560 2561 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2562 return -EOPNOTSUPP; 2563 2564 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2565 return -EINVAL; 2566 2567 return smu_dpm_ctx->dpm_level; 2568 } 2569 2570 static int smu_force_performance_level(void *handle, 2571 enum amd_dpm_forced_level level) 2572 { 2573 struct smu_context *smu = handle; 2574 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2575 int ret = 0; 2576 2577 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2578 return -EOPNOTSUPP; 2579 2580 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2581 return -EINVAL; 2582 2583 ret = smu_enable_umd_pstate(smu, &level); 2584 if (ret) 2585 return ret; 2586 2587 ret = smu_handle_task(smu, level, 2588 AMD_PP_TASK_READJUST_POWER_STATE); 2589 2590 /* reset user dpm clock state */ 2591 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2592 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2593 smu->user_dpm_profile.clk_dependency = 0; 2594 } 2595 2596 return ret; 2597 } 2598 2599 static int smu_set_display_count(void *handle, uint32_t count) 2600 { 2601 struct smu_context *smu = handle; 2602 2603 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2604 return -EOPNOTSUPP; 2605 2606 return smu_init_display_count(smu, count); 2607 } 2608 2609 static int smu_force_smuclk_levels(struct smu_context *smu, 2610 enum smu_clk_type clk_type, 2611 uint32_t mask) 2612 { 2613 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2614 int ret = 0; 2615 2616 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2617 return -EOPNOTSUPP; 2618 2619 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2620 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2621 return -EINVAL; 2622 } 2623 2624 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2625 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2626 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2627 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2628 smu_set_user_clk_dependencies(smu, clk_type); 2629 } 2630 } 2631 2632 return ret; 2633 } 2634 2635 static int smu_force_ppclk_levels(void *handle, 2636 enum pp_clock_type type, 2637 uint32_t mask) 2638 { 2639 struct smu_context *smu = handle; 2640 enum smu_clk_type clk_type; 2641 2642 switch (type) { 2643 case PP_SCLK: 2644 clk_type = SMU_SCLK; break; 2645 case PP_MCLK: 2646 clk_type = SMU_MCLK; break; 2647 case PP_PCIE: 2648 clk_type = SMU_PCIE; break; 2649 case PP_SOCCLK: 2650 clk_type = SMU_SOCCLK; break; 2651 case PP_FCLK: 2652 clk_type = SMU_FCLK; break; 2653 case PP_DCEFCLK: 2654 clk_type = SMU_DCEFCLK; break; 2655 case PP_VCLK: 2656 clk_type = SMU_VCLK; break; 2657 case PP_VCLK1: 2658 clk_type = SMU_VCLK1; break; 2659 case PP_DCLK: 2660 clk_type = SMU_DCLK; break; 2661 case PP_DCLK1: 2662 clk_type = SMU_DCLK1; break; 2663 case OD_SCLK: 2664 clk_type = SMU_OD_SCLK; break; 2665 case OD_MCLK: 2666 clk_type = SMU_OD_MCLK; break; 2667 case OD_VDDC_CURVE: 2668 clk_type = SMU_OD_VDDC_CURVE; break; 2669 case OD_RANGE: 2670 clk_type = SMU_OD_RANGE; break; 2671 default: 2672 return -EINVAL; 2673 } 2674 2675 return smu_force_smuclk_levels(smu, clk_type, mask); 2676 } 2677 2678 /* 2679 * On system suspending or resetting, the dpm_enabled 2680 * flag will be cleared. So that those SMU services which 2681 * are not supported will be gated. 2682 * However, the mp1 state setting should still be granted 2683 * even if the dpm_enabled cleared. 2684 */ 2685 static int smu_set_mp1_state(void *handle, 2686 enum pp_mp1_state mp1_state) 2687 { 2688 struct smu_context *smu = handle; 2689 int ret = 0; 2690 2691 if (!smu->pm_enabled) 2692 return -EOPNOTSUPP; 2693 2694 if (smu->ppt_funcs && 2695 smu->ppt_funcs->set_mp1_state) 2696 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2697 2698 return ret; 2699 } 2700 2701 static int smu_set_df_cstate(void *handle, 2702 enum pp_df_cstate state) 2703 { 2704 struct smu_context *smu = handle; 2705 int ret = 0; 2706 2707 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2708 return -EOPNOTSUPP; 2709 2710 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2711 return 0; 2712 2713 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2714 if (ret) 2715 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2716 2717 return ret; 2718 } 2719 2720 int smu_write_watermarks_table(struct smu_context *smu) 2721 { 2722 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2723 return -EOPNOTSUPP; 2724 2725 return smu_set_watermarks_table(smu, NULL); 2726 } 2727 2728 static int smu_set_watermarks_for_clock_ranges(void *handle, 2729 struct pp_smu_wm_range_sets *clock_ranges) 2730 { 2731 struct smu_context *smu = handle; 2732 2733 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2734 return -EOPNOTSUPP; 2735 2736 if (smu->disable_watermark) 2737 return 0; 2738 2739 return smu_set_watermarks_table(smu, clock_ranges); 2740 } 2741 2742 int smu_set_ac_dc(struct smu_context *smu) 2743 { 2744 int ret = 0; 2745 2746 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2747 return -EOPNOTSUPP; 2748 2749 /* controlled by firmware */ 2750 if (smu->dc_controlled_by_gpio) 2751 return 0; 2752 2753 ret = smu_set_power_source(smu, 2754 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2755 SMU_POWER_SOURCE_DC); 2756 if (ret) 2757 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2758 smu->adev->pm.ac_power ? "AC" : "DC"); 2759 2760 return ret; 2761 } 2762 2763 const struct amd_ip_funcs smu_ip_funcs = { 2764 .name = "smu", 2765 .early_init = smu_early_init, 2766 .late_init = smu_late_init, 2767 .sw_init = smu_sw_init, 2768 .sw_fini = smu_sw_fini, 2769 .hw_init = smu_hw_init, 2770 .hw_fini = smu_hw_fini, 2771 .late_fini = smu_late_fini, 2772 .suspend = smu_suspend, 2773 .resume = smu_resume, 2774 .is_idle = NULL, 2775 .check_soft_reset = NULL, 2776 .wait_for_idle = NULL, 2777 .soft_reset = NULL, 2778 .set_clockgating_state = smu_set_clockgating_state, 2779 .set_powergating_state = smu_set_powergating_state, 2780 }; 2781 2782 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2783 .type = AMD_IP_BLOCK_TYPE_SMC, 2784 .major = 11, 2785 .minor = 0, 2786 .rev = 0, 2787 .funcs = &smu_ip_funcs, 2788 }; 2789 2790 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2791 .type = AMD_IP_BLOCK_TYPE_SMC, 2792 .major = 12, 2793 .minor = 0, 2794 .rev = 0, 2795 .funcs = &smu_ip_funcs, 2796 }; 2797 2798 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2799 .type = AMD_IP_BLOCK_TYPE_SMC, 2800 .major = 13, 2801 .minor = 0, 2802 .rev = 0, 2803 .funcs = &smu_ip_funcs, 2804 }; 2805 2806 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2807 .type = AMD_IP_BLOCK_TYPE_SMC, 2808 .major = 14, 2809 .minor = 0, 2810 .rev = 0, 2811 .funcs = &smu_ip_funcs, 2812 }; 2813 2814 const struct amdgpu_ip_block_version smu_v15_0_ip_block = { 2815 .type = AMD_IP_BLOCK_TYPE_SMC, 2816 .major = 15, 2817 .minor = 0, 2818 .rev = 0, 2819 .funcs = &smu_ip_funcs, 2820 }; 2821 2822 const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle) 2823 { 2824 struct smu_context *smu = (struct smu_context *)handle; 2825 const struct ras_smu_drv *tmp = NULL; 2826 int ret; 2827 2828 ret = smu_get_ras_smu_drv(smu, &tmp); 2829 2830 return ret ? NULL : tmp; 2831 } 2832 2833 static int smu_load_microcode(void *handle) 2834 { 2835 struct smu_context *smu = handle; 2836 struct amdgpu_device *adev = smu->adev; 2837 int ret = 0; 2838 2839 if (!smu->pm_enabled) 2840 return -EOPNOTSUPP; 2841 2842 /* This should be used for non PSP loading */ 2843 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2844 return 0; 2845 2846 if (smu->ppt_funcs->load_microcode) { 2847 ret = smu->ppt_funcs->load_microcode(smu); 2848 if (ret) { 2849 dev_err(adev->dev, "Load microcode failed\n"); 2850 return ret; 2851 } 2852 } 2853 2854 if (smu->ppt_funcs->check_fw_status) { 2855 ret = smu->ppt_funcs->check_fw_status(smu); 2856 if (ret) { 2857 dev_err(adev->dev, "SMC is not ready\n"); 2858 return ret; 2859 } 2860 } 2861 2862 return ret; 2863 } 2864 2865 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2866 { 2867 int ret = 0; 2868 2869 if (smu->ppt_funcs->set_gfx_cgpg) 2870 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2871 2872 return ret; 2873 } 2874 2875 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2876 { 2877 struct smu_context *smu = handle; 2878 int ret = 0; 2879 2880 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2881 return -EOPNOTSUPP; 2882 2883 if (!smu->ppt_funcs->set_fan_speed_rpm) 2884 return -EOPNOTSUPP; 2885 2886 if (speed == U32_MAX) 2887 return -EINVAL; 2888 2889 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2890 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2891 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2892 smu->user_dpm_profile.fan_speed_rpm = speed; 2893 2894 /* Override custom PWM setting as they cannot co-exist */ 2895 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2896 smu->user_dpm_profile.fan_speed_pwm = 0; 2897 } 2898 2899 return ret; 2900 } 2901 2902 /** 2903 * smu_get_power_limit - Request one of the SMU Power Limits 2904 * 2905 * @handle: pointer to smu context 2906 * @limit: requested limit is written back to this variable 2907 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2908 * @pp_power_type: &pp_power_type type of power 2909 * Return: 0 on success, <0 on error 2910 * 2911 */ 2912 int smu_get_power_limit(void *handle, 2913 uint32_t *limit, 2914 enum pp_power_limit_level pp_limit_level, 2915 enum pp_power_type pp_power_type) 2916 { 2917 struct smu_context *smu = handle; 2918 struct amdgpu_device *adev = smu->adev; 2919 enum smu_ppt_limit_level limit_level; 2920 uint32_t limit_type; 2921 int ret = 0; 2922 2923 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2924 return -EOPNOTSUPP; 2925 2926 if (!limit) 2927 return -EINVAL; 2928 2929 switch (pp_power_type) { 2930 case PP_PWR_TYPE_SUSTAINED: 2931 limit_type = SMU_DEFAULT_PPT_LIMIT; 2932 break; 2933 case PP_PWR_TYPE_FAST: 2934 limit_type = SMU_FAST_PPT_LIMIT; 2935 break; 2936 default: 2937 return -EOPNOTSUPP; 2938 } 2939 2940 switch (pp_limit_level) { 2941 case PP_PWR_LIMIT_CURRENT: 2942 limit_level = SMU_PPT_LIMIT_CURRENT; 2943 break; 2944 case PP_PWR_LIMIT_DEFAULT: 2945 limit_level = SMU_PPT_LIMIT_DEFAULT; 2946 break; 2947 case PP_PWR_LIMIT_MAX: 2948 limit_level = SMU_PPT_LIMIT_MAX; 2949 break; 2950 case PP_PWR_LIMIT_MIN: 2951 limit_level = SMU_PPT_LIMIT_MIN; 2952 break; 2953 default: 2954 return -EOPNOTSUPP; 2955 } 2956 2957 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2958 if (smu->ppt_funcs->get_ppt_limit) 2959 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2960 else 2961 return -EOPNOTSUPP; 2962 } else { 2963 switch (limit_level) { 2964 case SMU_PPT_LIMIT_CURRENT: 2965 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2966 case IP_VERSION(13, 0, 2): 2967 case IP_VERSION(13, 0, 6): 2968 case IP_VERSION(13, 0, 12): 2969 case IP_VERSION(13, 0, 14): 2970 case IP_VERSION(11, 0, 7): 2971 case IP_VERSION(11, 0, 11): 2972 case IP_VERSION(11, 0, 12): 2973 case IP_VERSION(11, 0, 13): 2974 case IP_VERSION(15, 0, 8): 2975 ret = smu_get_asic_power_limits(smu, 2976 &smu->current_power_limit, 2977 NULL, NULL, NULL); 2978 break; 2979 default: 2980 break; 2981 } 2982 *limit = smu->current_power_limit; 2983 break; 2984 case SMU_PPT_LIMIT_DEFAULT: 2985 *limit = smu->default_power_limit; 2986 break; 2987 case SMU_PPT_LIMIT_MAX: 2988 *limit = smu->max_power_limit; 2989 break; 2990 case SMU_PPT_LIMIT_MIN: 2991 *limit = smu->min_power_limit; 2992 break; 2993 default: 2994 return -EINVAL; 2995 } 2996 } 2997 2998 return ret; 2999 } 3000 3001 static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit) 3002 { 3003 struct smu_context *smu = handle; 3004 int ret = 0; 3005 3006 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3007 return -EOPNOTSUPP; 3008 3009 if (limit_type == SMU_DEFAULT_PPT_LIMIT) { 3010 if (!limit) 3011 limit = smu->current_power_limit; 3012 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 3013 dev_err(smu->adev->dev, 3014 "New power limit (%d) is out of range [%d,%d]\n", 3015 limit, smu->min_power_limit, smu->max_power_limit); 3016 return -EINVAL; 3017 } 3018 } 3019 3020 if (smu->ppt_funcs->set_power_limit) { 3021 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 3022 if (ret) 3023 return ret; 3024 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 3025 smu->user_dpm_profile.power_limits[limit_type] = limit; 3026 } 3027 3028 return 0; 3029 } 3030 3031 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 3032 { 3033 enum smu_clk_type clk_type; 3034 3035 switch (type) { 3036 case PP_SCLK: 3037 clk_type = SMU_SCLK; break; 3038 case PP_MCLK: 3039 clk_type = SMU_MCLK; break; 3040 case PP_PCIE: 3041 clk_type = SMU_PCIE; break; 3042 case PP_SOCCLK: 3043 clk_type = SMU_SOCCLK; break; 3044 case PP_FCLK: 3045 clk_type = SMU_FCLK; break; 3046 case PP_DCEFCLK: 3047 clk_type = SMU_DCEFCLK; break; 3048 case PP_VCLK: 3049 clk_type = SMU_VCLK; break; 3050 case PP_VCLK1: 3051 clk_type = SMU_VCLK1; break; 3052 case PP_DCLK: 3053 clk_type = SMU_DCLK; break; 3054 case PP_DCLK1: 3055 clk_type = SMU_DCLK1; break; 3056 case PP_ISPICLK: 3057 clk_type = SMU_ISPICLK; 3058 break; 3059 case PP_ISPXCLK: 3060 clk_type = SMU_ISPXCLK; 3061 break; 3062 case OD_SCLK: 3063 clk_type = SMU_OD_SCLK; break; 3064 case OD_MCLK: 3065 clk_type = SMU_OD_MCLK; break; 3066 case OD_FCLK: 3067 clk_type = SMU_OD_FCLK; break; 3068 case OD_VDDC_CURVE: 3069 clk_type = SMU_OD_VDDC_CURVE; break; 3070 case OD_RANGE: 3071 clk_type = SMU_OD_RANGE; break; 3072 case OD_VDDGFX_OFFSET: 3073 clk_type = SMU_OD_VDDGFX_OFFSET; break; 3074 case OD_CCLK: 3075 clk_type = SMU_OD_CCLK; break; 3076 case OD_FAN_CURVE: 3077 clk_type = SMU_OD_FAN_CURVE; break; 3078 case OD_ACOUSTIC_LIMIT: 3079 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 3080 case OD_ACOUSTIC_TARGET: 3081 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 3082 case OD_FAN_TARGET_TEMPERATURE: 3083 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 3084 case OD_FAN_MINIMUM_PWM: 3085 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 3086 case OD_FAN_ZERO_RPM_ENABLE: 3087 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 3088 case OD_FAN_ZERO_RPM_STOP_TEMP: 3089 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 3090 default: 3091 clk_type = SMU_CLK_COUNT; break; 3092 } 3093 3094 return clk_type; 3095 } 3096 3097 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 3098 { 3099 struct smu_context *smu = handle; 3100 enum smu_clk_type clk_type; 3101 3102 clk_type = smu_convert_to_smuclk(type); 3103 if (clk_type == SMU_CLK_COUNT) 3104 return -EINVAL; 3105 3106 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3107 return -EOPNOTSUPP; 3108 3109 if (!smu->ppt_funcs->emit_clk_levels) 3110 return -ENOENT; 3111 3112 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 3113 3114 } 3115 3116 static int smu_od_edit_dpm_table(void *handle, 3117 enum PP_OD_DPM_TABLE_COMMAND type, 3118 long *input, uint32_t size) 3119 { 3120 struct smu_context *smu = handle; 3121 int ret = 0; 3122 3123 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3124 return -EOPNOTSUPP; 3125 3126 if (smu->ppt_funcs->od_edit_dpm_table) { 3127 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 3128 } 3129 3130 return ret; 3131 } 3132 3133 static int smu_read_sensor(void *handle, 3134 int sensor, 3135 void *data, 3136 int *size_arg) 3137 { 3138 struct smu_context *smu = handle; 3139 struct amdgpu_device *adev = smu->adev; 3140 struct smu_umd_pstate_table *pstate_table = 3141 &smu->pstate_table; 3142 int i, ret = 0; 3143 uint32_t *size, size_val; 3144 3145 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3146 return -EOPNOTSUPP; 3147 3148 if (!data || !size_arg) 3149 return -EINVAL; 3150 3151 size_val = *size_arg; 3152 size = &size_val; 3153 3154 if (smu->ppt_funcs->read_sensor) 3155 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 3156 goto unlock; 3157 3158 switch (sensor) { 3159 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 3160 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 3161 *size = 4; 3162 break; 3163 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 3164 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 3165 *size = 4; 3166 break; 3167 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 3168 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 3169 *size = 4; 3170 break; 3171 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 3172 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3173 *size = 4; 3174 break; 3175 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: { 3176 struct smu_feature_bits feature_mask; 3177 uint32_t features[2]; 3178 3179 /* TBD: need to handle for > 64 bits */ 3180 ret = smu_feature_get_enabled_mask(smu, &feature_mask); 3181 if (!ret) { 3182 smu_feature_bits_to_arr32(&feature_mask, features, 64); 3183 *(uint64_t *)data = *(uint64_t *)features; 3184 } 3185 *size = 8; 3186 break; 3187 } 3188 case AMDGPU_PP_SENSOR_UVD_POWER: 3189 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3190 *size = 4; 3191 break; 3192 case AMDGPU_PP_SENSOR_VCE_POWER: 3193 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 3194 *size = 4; 3195 break; 3196 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3197 *(uint32_t *)data = 0; 3198 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 3199 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) { 3200 *(uint32_t *)data = 1; 3201 break; 3202 } 3203 } 3204 *size = 4; 3205 break; 3206 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3207 *(uint32_t *)data = 0; 3208 *size = 4; 3209 break; 3210 default: 3211 *size = 0; 3212 ret = -EOPNOTSUPP; 3213 break; 3214 } 3215 3216 unlock: 3217 // assign uint32_t to int 3218 *size_arg = size_val; 3219 3220 return ret; 3221 } 3222 3223 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3224 { 3225 int ret = -EOPNOTSUPP; 3226 struct smu_context *smu = handle; 3227 3228 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3229 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3230 3231 return ret; 3232 } 3233 3234 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3235 { 3236 int ret = -EOPNOTSUPP; 3237 struct smu_context *smu = handle; 3238 3239 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3240 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3241 3242 return ret; 3243 } 3244 3245 static int smu_get_power_profile_mode(void *handle, char *buf) 3246 { 3247 struct smu_context *smu = handle; 3248 3249 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3250 !smu->ppt_funcs->get_power_profile_mode) 3251 return -EOPNOTSUPP; 3252 if (!buf) 3253 return -EINVAL; 3254 3255 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3256 } 3257 3258 static int smu_set_power_profile_mode(void *handle, 3259 long *param, 3260 uint32_t param_size) 3261 { 3262 struct smu_context *smu = handle; 3263 bool custom = false; 3264 int ret = 0; 3265 3266 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3267 !smu->ppt_funcs->set_power_profile_mode) 3268 return -EOPNOTSUPP; 3269 3270 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) { 3271 custom = true; 3272 /* clear frontend mask so custom changes propogate */ 3273 smu->workload_mask = 0; 3274 } 3275 3276 if ((param[param_size] != smu->power_profile_mode) || custom) { 3277 /* clear the old user preference */ 3278 smu_power_profile_mode_put(smu, smu->power_profile_mode); 3279 /* set the new user preference */ 3280 smu_power_profile_mode_get(smu, param[param_size]); 3281 ret = smu_bump_power_profile_mode(smu, 3282 custom ? param : NULL, 3283 custom ? param_size : 0); 3284 if (ret) 3285 smu_power_profile_mode_put(smu, param[param_size]); 3286 else 3287 /* store the user's preference */ 3288 smu->power_profile_mode = param[param_size]; 3289 } 3290 3291 return ret; 3292 } 3293 3294 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3295 { 3296 struct smu_context *smu = handle; 3297 3298 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3299 return -EOPNOTSUPP; 3300 3301 if (!smu->ppt_funcs->get_fan_control_mode) 3302 return -EOPNOTSUPP; 3303 3304 if (!fan_mode) 3305 return -EINVAL; 3306 3307 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3308 3309 return 0; 3310 } 3311 3312 static int smu_set_fan_control_mode(void *handle, u32 value) 3313 { 3314 struct smu_context *smu = handle; 3315 int ret = 0; 3316 3317 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3318 return -EOPNOTSUPP; 3319 3320 if (!smu->ppt_funcs->set_fan_control_mode) 3321 return -EOPNOTSUPP; 3322 3323 if (value == U32_MAX) 3324 return -EINVAL; 3325 3326 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3327 if (ret) 3328 goto out; 3329 3330 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3331 smu->user_dpm_profile.fan_mode = value; 3332 3333 /* reset user dpm fan speed */ 3334 if (value != AMD_FAN_CTRL_MANUAL) { 3335 smu->user_dpm_profile.fan_speed_pwm = 0; 3336 smu->user_dpm_profile.fan_speed_rpm = 0; 3337 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3338 } 3339 } 3340 3341 out: 3342 return ret; 3343 } 3344 3345 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3346 { 3347 struct smu_context *smu = handle; 3348 int ret = 0; 3349 3350 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3351 return -EOPNOTSUPP; 3352 3353 if (!smu->ppt_funcs->get_fan_speed_pwm) 3354 return -EOPNOTSUPP; 3355 3356 if (!speed) 3357 return -EINVAL; 3358 3359 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3360 3361 return ret; 3362 } 3363 3364 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3365 { 3366 struct smu_context *smu = handle; 3367 int ret = 0; 3368 3369 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3370 return -EOPNOTSUPP; 3371 3372 if (!smu->ppt_funcs->set_fan_speed_pwm) 3373 return -EOPNOTSUPP; 3374 3375 if (speed == U32_MAX) 3376 return -EINVAL; 3377 3378 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3379 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3380 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3381 smu->user_dpm_profile.fan_speed_pwm = speed; 3382 3383 /* Override custom RPM setting as they cannot co-exist */ 3384 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3385 smu->user_dpm_profile.fan_speed_rpm = 0; 3386 } 3387 3388 return ret; 3389 } 3390 3391 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3392 { 3393 struct smu_context *smu = handle; 3394 int ret = 0; 3395 3396 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3397 return -EOPNOTSUPP; 3398 3399 if (!smu->ppt_funcs->get_fan_speed_rpm) 3400 return -EOPNOTSUPP; 3401 3402 if (!speed) 3403 return -EINVAL; 3404 3405 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3406 3407 return ret; 3408 } 3409 3410 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3411 { 3412 struct smu_context *smu = handle; 3413 3414 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3415 return -EOPNOTSUPP; 3416 3417 return smu_set_min_dcef_deep_sleep(smu, clk); 3418 } 3419 3420 static int smu_get_clock_by_type_with_latency(void *handle, 3421 enum amd_pp_clock_type type, 3422 struct pp_clock_levels_with_latency *clocks) 3423 { 3424 struct smu_context *smu = handle; 3425 enum smu_clk_type clk_type; 3426 int ret = 0; 3427 3428 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3429 return -EOPNOTSUPP; 3430 3431 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3432 switch (type) { 3433 case amd_pp_sys_clock: 3434 clk_type = SMU_GFXCLK; 3435 break; 3436 case amd_pp_mem_clock: 3437 clk_type = SMU_MCLK; 3438 break; 3439 case amd_pp_dcef_clock: 3440 clk_type = SMU_DCEFCLK; 3441 break; 3442 case amd_pp_disp_clock: 3443 clk_type = SMU_DISPCLK; 3444 break; 3445 default: 3446 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3447 return -EINVAL; 3448 } 3449 3450 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3451 } 3452 3453 return ret; 3454 } 3455 3456 static int smu_display_clock_voltage_request(void *handle, 3457 struct pp_display_clock_request *clock_req) 3458 { 3459 struct smu_context *smu = handle; 3460 int ret = 0; 3461 3462 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3463 return -EOPNOTSUPP; 3464 3465 if (smu->ppt_funcs->display_clock_voltage_request) 3466 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3467 3468 return ret; 3469 } 3470 3471 3472 static int smu_display_disable_memory_clock_switch(void *handle, 3473 bool disable_memory_clock_switch) 3474 { 3475 struct smu_context *smu = handle; 3476 int ret = -EINVAL; 3477 3478 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3479 return -EOPNOTSUPP; 3480 3481 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3482 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3483 3484 return ret; 3485 } 3486 3487 static int smu_set_xgmi_pstate(void *handle, 3488 uint32_t pstate) 3489 { 3490 struct smu_context *smu = handle; 3491 int ret = 0; 3492 3493 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3494 return -EOPNOTSUPP; 3495 3496 if (smu->ppt_funcs->set_xgmi_pstate) 3497 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3498 3499 if (ret) 3500 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3501 3502 return ret; 3503 } 3504 3505 static int smu_get_baco_capability(void *handle) 3506 { 3507 struct smu_context *smu = handle; 3508 3509 if (!smu->pm_enabled) 3510 return false; 3511 3512 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3513 return false; 3514 3515 return smu->ppt_funcs->get_bamaco_support(smu); 3516 } 3517 3518 static int smu_baco_set_state(void *handle, int state) 3519 { 3520 struct smu_context *smu = handle; 3521 int ret = 0; 3522 3523 if (!smu->pm_enabled) 3524 return -EOPNOTSUPP; 3525 3526 if (state == 0) { 3527 if (smu->ppt_funcs->baco_exit) 3528 ret = smu->ppt_funcs->baco_exit(smu); 3529 } else if (state == 1) { 3530 if (smu->ppt_funcs->baco_enter) 3531 ret = smu->ppt_funcs->baco_enter(smu); 3532 } else { 3533 return -EINVAL; 3534 } 3535 3536 if (ret) 3537 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3538 (state)?"enter":"exit"); 3539 3540 return ret; 3541 } 3542 3543 bool smu_mode1_reset_is_support(struct smu_context *smu) 3544 { 3545 bool ret = false; 3546 3547 if (!smu->pm_enabled) 3548 return false; 3549 3550 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3551 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3552 3553 return ret; 3554 } 3555 3556 bool smu_link_reset_is_support(struct smu_context *smu) 3557 { 3558 if (!smu->pm_enabled) 3559 return false; 3560 3561 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__LINK_RESET); 3562 } 3563 3564 int smu_mode1_reset(struct smu_context *smu) 3565 { 3566 int ret = 0; 3567 3568 if (!smu->pm_enabled) 3569 return -EOPNOTSUPP; 3570 3571 if (smu->ppt_funcs->mode1_reset) 3572 ret = smu->ppt_funcs->mode1_reset(smu); 3573 3574 return ret; 3575 } 3576 3577 static int smu_mode2_reset(void *handle) 3578 { 3579 struct smu_context *smu = handle; 3580 int ret = 0; 3581 3582 if (!smu->pm_enabled) 3583 return -EOPNOTSUPP; 3584 3585 if (smu->ppt_funcs->mode2_reset) 3586 ret = smu->ppt_funcs->mode2_reset(smu); 3587 3588 if (ret) 3589 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3590 3591 return ret; 3592 } 3593 3594 int smu_link_reset(struct smu_context *smu) 3595 { 3596 int ret = 0; 3597 3598 if (!smu->pm_enabled) 3599 return -EOPNOTSUPP; 3600 3601 if (smu->ppt_funcs->link_reset) 3602 ret = smu->ppt_funcs->link_reset(smu); 3603 3604 return ret; 3605 } 3606 3607 static int smu_enable_gfx_features(void *handle) 3608 { 3609 struct smu_context *smu = handle; 3610 int ret = 0; 3611 3612 if (!smu->pm_enabled) 3613 return -EOPNOTSUPP; 3614 3615 if (smu->ppt_funcs->enable_gfx_features) 3616 ret = smu->ppt_funcs->enable_gfx_features(smu); 3617 3618 if (ret) 3619 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3620 3621 return ret; 3622 } 3623 3624 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3625 struct pp_smu_nv_clock_table *max_clocks) 3626 { 3627 struct smu_context *smu = handle; 3628 int ret = 0; 3629 3630 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3631 return -EOPNOTSUPP; 3632 3633 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3634 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3635 3636 return ret; 3637 } 3638 3639 static int smu_get_uclk_dpm_states(void *handle, 3640 unsigned int *clock_values_in_khz, 3641 unsigned int *num_states) 3642 { 3643 struct smu_context *smu = handle; 3644 int ret = 0; 3645 3646 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3647 return -EOPNOTSUPP; 3648 3649 if (smu->ppt_funcs->get_uclk_dpm_states) 3650 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3651 3652 return ret; 3653 } 3654 3655 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3656 { 3657 struct smu_context *smu = handle; 3658 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3659 3660 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3661 return -EOPNOTSUPP; 3662 3663 if (smu->ppt_funcs->get_current_power_state) 3664 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3665 3666 return pm_state; 3667 } 3668 3669 static int smu_get_dpm_clock_table(void *handle, 3670 struct dpm_clocks *clock_table) 3671 { 3672 struct smu_context *smu = handle; 3673 int ret = 0; 3674 3675 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3676 return -EOPNOTSUPP; 3677 3678 if (smu->ppt_funcs->get_dpm_clock_table) 3679 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3680 3681 return ret; 3682 } 3683 3684 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3685 { 3686 struct smu_context *smu = handle; 3687 struct smu_table_context *smu_table = &smu->smu_table; 3688 struct smu_driver_table *driver_tables = smu_table->driver_tables; 3689 struct smu_driver_table *gpu_metrics_table; 3690 3691 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3692 return -EOPNOTSUPP; 3693 3694 if (!smu->ppt_funcs->get_gpu_metrics) 3695 return -EOPNOTSUPP; 3696 3697 gpu_metrics_table = &driver_tables[SMU_DRIVER_TABLE_GPU_METRICS]; 3698 3699 /* If cached table is valid, return it */ 3700 if (smu_driver_table_is_valid(gpu_metrics_table)) { 3701 *table = gpu_metrics_table->cache.buffer; 3702 return gpu_metrics_table->cache.size; 3703 } 3704 3705 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3706 } 3707 3708 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3709 size_t size) 3710 { 3711 struct smu_context *smu = handle; 3712 3713 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3714 return -EOPNOTSUPP; 3715 3716 if (!smu->ppt_funcs->get_pm_metrics) 3717 return -EOPNOTSUPP; 3718 3719 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3720 } 3721 3722 static int smu_enable_mgpu_fan_boost(void *handle) 3723 { 3724 struct smu_context *smu = handle; 3725 int ret = 0; 3726 3727 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3728 return -EOPNOTSUPP; 3729 3730 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3731 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3732 3733 return ret; 3734 } 3735 3736 static int smu_gfx_state_change_set(void *handle, 3737 uint32_t state) 3738 { 3739 struct smu_context *smu = handle; 3740 int ret = 0; 3741 3742 if (smu->ppt_funcs->gfx_state_change_set) 3743 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3744 3745 return ret; 3746 } 3747 3748 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3749 { 3750 int ret = 0; 3751 3752 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3753 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3754 3755 return ret; 3756 } 3757 3758 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3759 { 3760 int ret = -EOPNOTSUPP; 3761 3762 if (smu->ppt_funcs && 3763 smu->ppt_funcs->get_ecc_info) 3764 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3765 3766 return ret; 3767 3768 } 3769 3770 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3771 { 3772 struct smu_context *smu = handle; 3773 struct smu_table_context *smu_table = &smu->smu_table; 3774 struct smu_table *memory_pool = &smu_table->memory_pool; 3775 3776 if (!addr || !size) 3777 return -EINVAL; 3778 3779 *addr = NULL; 3780 *size = 0; 3781 if (memory_pool->bo) { 3782 *addr = memory_pool->cpu_addr; 3783 *size = memory_pool->size; 3784 } 3785 3786 return 0; 3787 } 3788 3789 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3790 size_t *size) 3791 { 3792 size_t offset = *size; 3793 int level; 3794 3795 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3796 if (level == policy->current_level) 3797 offset += sysfs_emit_at(sysbuf, offset, 3798 "%d : %s*\n", level, 3799 policy->desc->get_desc(policy, level)); 3800 else 3801 offset += sysfs_emit_at(sysbuf, offset, 3802 "%d : %s\n", level, 3803 policy->desc->get_desc(policy, level)); 3804 } 3805 3806 *size = offset; 3807 } 3808 3809 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3810 enum pp_pm_policy p_type, char *sysbuf) 3811 { 3812 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3813 struct smu_dpm_policy_ctxt *policy_ctxt; 3814 struct smu_dpm_policy *dpm_policy; 3815 size_t offset = 0; 3816 3817 policy_ctxt = dpm_ctxt->dpm_policies; 3818 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3819 !policy_ctxt->policy_mask) 3820 return -EOPNOTSUPP; 3821 3822 if (p_type == PP_PM_POLICY_NONE) 3823 return -EINVAL; 3824 3825 dpm_policy = smu_get_pm_policy(smu, p_type); 3826 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3827 return -ENOENT; 3828 3829 if (!sysbuf) 3830 return -EINVAL; 3831 3832 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3833 3834 return offset; 3835 } 3836 3837 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3838 enum pp_pm_policy p_type) 3839 { 3840 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3841 struct smu_dpm_policy_ctxt *policy_ctxt; 3842 int i; 3843 3844 policy_ctxt = dpm_ctxt->dpm_policies; 3845 if (!policy_ctxt) 3846 return NULL; 3847 3848 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3849 if (policy_ctxt->policies[i].policy_type == p_type) 3850 return &policy_ctxt->policies[i]; 3851 } 3852 3853 return NULL; 3854 } 3855 3856 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3857 int level) 3858 { 3859 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3860 struct smu_dpm_policy *dpm_policy = NULL; 3861 struct smu_dpm_policy_ctxt *policy_ctxt; 3862 int ret = -EOPNOTSUPP; 3863 3864 policy_ctxt = dpm_ctxt->dpm_policies; 3865 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3866 !policy_ctxt->policy_mask) 3867 return ret; 3868 3869 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3870 return -EINVAL; 3871 3872 dpm_policy = smu_get_pm_policy(smu, p_type); 3873 3874 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3875 return ret; 3876 3877 if (dpm_policy->current_level == level) 3878 return 0; 3879 3880 ret = dpm_policy->set_policy(smu, level); 3881 3882 if (!ret) 3883 dpm_policy->current_level = level; 3884 3885 return ret; 3886 } 3887 3888 static ssize_t smu_sys_get_temp_metrics(void *handle, enum smu_temp_metric_type type, void *table) 3889 { 3890 struct smu_context *smu = handle; 3891 struct smu_table_context *smu_table = &smu->smu_table; 3892 struct smu_driver_table *driver_tables = smu_table->driver_tables; 3893 enum smu_driver_table_id table_id; 3894 struct smu_driver_table *temp_table; 3895 3896 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3897 return -EOPNOTSUPP; 3898 3899 if (!smu->smu_temp.temp_funcs || !smu->smu_temp.temp_funcs->get_temp_metrics) 3900 return -EOPNOTSUPP; 3901 3902 table_id = smu_metrics_get_temp_table_id(type); 3903 3904 if (table_id == SMU_DRIVER_TABLE_COUNT) 3905 return -EINVAL; 3906 3907 temp_table = &driver_tables[table_id]; 3908 3909 /* If the request is to get size alone, return the cached table size */ 3910 if (!table && temp_table->cache.size) 3911 return temp_table->cache.size; 3912 3913 if (smu_driver_table_is_valid(temp_table)) { 3914 memcpy(table, temp_table->cache.buffer, temp_table->cache.size); 3915 return temp_table->cache.size; 3916 } 3917 3918 return smu->smu_temp.temp_funcs->get_temp_metrics(smu, type, table); 3919 } 3920 3921 static bool smu_temp_metrics_is_supported(void *handle, enum smu_temp_metric_type type) 3922 { 3923 struct smu_context *smu = handle; 3924 bool ret = false; 3925 3926 if (!smu->pm_enabled) 3927 return false; 3928 3929 if (smu->smu_temp.temp_funcs && smu->smu_temp.temp_funcs->temp_metrics_is_supported) 3930 ret = smu->smu_temp.temp_funcs->temp_metrics_is_supported(smu, type); 3931 3932 return ret; 3933 } 3934 3935 static ssize_t smu_sys_get_xcp_metrics(void *handle, int xcp_id, void *table) 3936 { 3937 struct smu_context *smu = handle; 3938 3939 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3940 return -EOPNOTSUPP; 3941 3942 if (!smu->adev->xcp_mgr || !smu->ppt_funcs->get_xcp_metrics) 3943 return -EOPNOTSUPP; 3944 3945 return smu->ppt_funcs->get_xcp_metrics(smu, xcp_id, table); 3946 } 3947 3948 static const struct amd_pm_funcs swsmu_pm_funcs = { 3949 /* export for sysfs */ 3950 .set_fan_control_mode = smu_set_fan_control_mode, 3951 .get_fan_control_mode = smu_get_fan_control_mode, 3952 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3953 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3954 .force_clock_level = smu_force_ppclk_levels, 3955 .emit_clock_levels = smu_emit_ppclk_levels, 3956 .force_performance_level = smu_force_performance_level, 3957 .read_sensor = smu_read_sensor, 3958 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3959 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3960 .get_performance_level = smu_get_performance_level, 3961 .get_current_power_state = smu_get_current_power_state, 3962 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3963 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3964 .get_pp_num_states = smu_get_power_num_states, 3965 .get_pp_table = smu_sys_get_pp_table, 3966 .set_pp_table = smu_sys_set_pp_table, 3967 .switch_power_profile = smu_switch_power_profile, 3968 .pause_power_profile = smu_pause_power_profile, 3969 /* export to amdgpu */ 3970 .dispatch_tasks = smu_handle_dpm_task, 3971 .load_firmware = smu_load_microcode, 3972 .set_powergating_by_smu = smu_dpm_set_power_gate, 3973 .set_power_limit = smu_set_power_limit, 3974 .get_power_limit = smu_get_power_limit, 3975 .get_power_profile_mode = smu_get_power_profile_mode, 3976 .set_power_profile_mode = smu_set_power_profile_mode, 3977 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3978 .set_mp1_state = smu_set_mp1_state, 3979 .gfx_state_change_set = smu_gfx_state_change_set, 3980 /* export to DC */ 3981 .get_sclk = smu_get_sclk, 3982 .get_mclk = smu_get_mclk, 3983 .display_configuration_change = smu_display_configuration_change, 3984 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3985 .display_clock_voltage_request = smu_display_clock_voltage_request, 3986 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3987 .set_active_display_count = smu_set_display_count, 3988 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3989 .get_asic_baco_capability = smu_get_baco_capability, 3990 .set_asic_baco_state = smu_baco_set_state, 3991 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3992 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3993 .asic_reset_mode_2 = smu_mode2_reset, 3994 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3995 .set_df_cstate = smu_set_df_cstate, 3996 .set_xgmi_pstate = smu_set_xgmi_pstate, 3997 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3998 .get_pm_metrics = smu_sys_get_pm_metrics, 3999 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 4000 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 4001 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 4002 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 4003 .get_dpm_clock_table = smu_get_dpm_clock_table, 4004 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 4005 .get_xcp_metrics = smu_sys_get_xcp_metrics, 4006 .get_temp_metrics = smu_sys_get_temp_metrics, 4007 .temp_metrics_is_supported = smu_temp_metrics_is_supported, 4008 }; 4009 4010 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 4011 uint64_t event_arg) 4012 { 4013 int ret = -EINVAL; 4014 4015 if (smu->ppt_funcs->wait_for_event) 4016 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 4017 4018 return ret; 4019 } 4020 4021 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 4022 { 4023 4024 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 4025 return -EOPNOTSUPP; 4026 4027 /* Confirm the buffer allocated is of correct size */ 4028 if (size != smu->stb_context.stb_buf_size) 4029 return -EINVAL; 4030 4031 /* 4032 * No need to lock smu mutex as we access STB directly through MMIO 4033 * and not going through SMU messaging route (for now at least). 4034 * For registers access rely on implementation internal locking. 4035 */ 4036 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 4037 } 4038 4039 #if defined(CONFIG_DEBUG_FS) 4040 4041 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 4042 { 4043 struct amdgpu_device *adev = filp->f_inode->i_private; 4044 struct smu_context *smu = adev->powerplay.pp_handle; 4045 unsigned char *buf; 4046 int r; 4047 4048 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 4049 if (!buf) 4050 return -ENOMEM; 4051 4052 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 4053 if (r) 4054 goto out; 4055 4056 filp->private_data = buf; 4057 4058 return 0; 4059 4060 out: 4061 kvfree(buf); 4062 return r; 4063 } 4064 4065 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 4066 loff_t *pos) 4067 { 4068 struct amdgpu_device *adev = filp->f_inode->i_private; 4069 struct smu_context *smu = adev->powerplay.pp_handle; 4070 4071 4072 if (!filp->private_data) 4073 return -EINVAL; 4074 4075 return simple_read_from_buffer(buf, 4076 size, 4077 pos, filp->private_data, 4078 smu->stb_context.stb_buf_size); 4079 } 4080 4081 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 4082 { 4083 kvfree(filp->private_data); 4084 filp->private_data = NULL; 4085 4086 return 0; 4087 } 4088 4089 /* 4090 * We have to define not only read method but also 4091 * open and release because .read takes up to PAGE_SIZE 4092 * data each time so and so is invoked multiple times. 4093 * We allocate the STB buffer in .open and release it 4094 * in .release 4095 */ 4096 static const struct file_operations smu_stb_debugfs_fops = { 4097 .owner = THIS_MODULE, 4098 .open = smu_stb_debugfs_open, 4099 .read = smu_stb_debugfs_read, 4100 .release = smu_stb_debugfs_release, 4101 .llseek = default_llseek, 4102 }; 4103 4104 #endif 4105 4106 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 4107 { 4108 #if defined(CONFIG_DEBUG_FS) 4109 4110 struct smu_context *smu = adev->powerplay.pp_handle; 4111 4112 if (!smu || (!smu->stb_context.stb_buf_size)) 4113 return; 4114 4115 debugfs_create_file_size("amdgpu_smu_stb_dump", 4116 S_IRUSR, 4117 adev_to_drm(adev)->primary->debugfs_root, 4118 adev, 4119 &smu_stb_debugfs_fops, 4120 smu->stb_context.stb_buf_size); 4121 #endif 4122 } 4123 4124 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 4125 { 4126 int ret = 0; 4127 4128 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 4129 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 4130 4131 return ret; 4132 } 4133 4134 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 4135 { 4136 int ret = 0; 4137 4138 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 4139 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 4140 4141 return ret; 4142 } 4143 4144 int smu_send_rma_reason(struct smu_context *smu) 4145 { 4146 int ret = 0; 4147 4148 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 4149 ret = smu->ppt_funcs->send_rma_reason(smu); 4150 4151 return ret; 4152 } 4153 4154 /** 4155 * smu_reset_sdma_is_supported - Check if SDMA reset is supported by SMU 4156 * @smu: smu_context pointer 4157 * 4158 * This function checks if the SMU supports resetting the SDMA engine. 4159 * It returns true if supported, false otherwise. 4160 */ 4161 bool smu_reset_sdma_is_supported(struct smu_context *smu) 4162 { 4163 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__SDMA_RESET); 4164 } 4165 4166 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask) 4167 { 4168 int ret = 0; 4169 4170 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma) 4171 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask); 4172 4173 return ret; 4174 } 4175 4176 bool smu_reset_vcn_is_supported(struct smu_context *smu) 4177 { 4178 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__VCN_RESET); 4179 } 4180 4181 int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask) 4182 { 4183 if (smu->ppt_funcs && smu->ppt_funcs->dpm_reset_vcn) 4184 smu->ppt_funcs->dpm_reset_vcn(smu, inst_mask); 4185 4186 return 0; 4187 } 4188