1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "smu_v13_0_0_ppt.h" 41 #include "smu_v13_0_4_ppt.h" 42 #include "smu_v13_0_5_ppt.h" 43 #include "smu_v13_0_7_ppt.h" 44 #include "amd_pcie.h" 45 46 /* 47 * DO NOT use these for err/warn/info/debug messages. 48 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 49 * They are more MGPU friendly. 50 */ 51 #undef pr_err 52 #undef pr_warn 53 #undef pr_info 54 #undef pr_debug 55 56 static const struct amd_pm_funcs swsmu_pm_funcs; 57 static int smu_force_smuclk_levels(struct smu_context *smu, 58 enum smu_clk_type clk_type, 59 uint32_t mask); 60 static int smu_handle_task(struct smu_context *smu, 61 enum amd_dpm_forced_level level, 62 enum amd_pp_task task_id); 63 static int smu_reset(struct smu_context *smu); 64 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 65 static int smu_set_fan_control_mode(void *handle, u32 value); 66 static int smu_set_power_limit(void *handle, uint32_t limit); 67 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 68 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 69 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 70 71 static int smu_sys_get_pp_feature_mask(void *handle, 72 char *buf) 73 { 74 struct smu_context *smu = handle; 75 76 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 77 return -EOPNOTSUPP; 78 79 return smu_get_pp_feature_mask(smu, buf); 80 } 81 82 static int smu_sys_set_pp_feature_mask(void *handle, 83 uint64_t new_mask) 84 { 85 struct smu_context *smu = handle; 86 87 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 88 return -EOPNOTSUPP; 89 90 return smu_set_pp_feature_mask(smu, new_mask); 91 } 92 93 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 94 { 95 if (!smu->ppt_funcs->set_gfx_off_residency) 96 return -EINVAL; 97 98 return smu_set_gfx_off_residency(smu, value); 99 } 100 101 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 102 { 103 if (!smu->ppt_funcs->get_gfx_off_residency) 104 return -EINVAL; 105 106 return smu_get_gfx_off_residency(smu, value); 107 } 108 109 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 110 { 111 if (!smu->ppt_funcs->get_gfx_off_entrycount) 112 return -EINVAL; 113 114 return smu_get_gfx_off_entrycount(smu, value); 115 } 116 117 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 118 { 119 if (!smu->ppt_funcs->get_gfx_off_status) 120 return -EINVAL; 121 122 *value = smu_get_gfx_off_status(smu); 123 124 return 0; 125 } 126 127 int smu_set_soft_freq_range(struct smu_context *smu, 128 enum smu_clk_type clk_type, 129 uint32_t min, 130 uint32_t max) 131 { 132 int ret = 0; 133 134 if (smu->ppt_funcs->set_soft_freq_limited_range) 135 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 136 clk_type, 137 min, 138 max); 139 140 return ret; 141 } 142 143 int smu_get_dpm_freq_range(struct smu_context *smu, 144 enum smu_clk_type clk_type, 145 uint32_t *min, 146 uint32_t *max) 147 { 148 int ret = -ENOTSUPP; 149 150 if (!min && !max) 151 return -EINVAL; 152 153 if (smu->ppt_funcs->get_dpm_ultimate_freq) 154 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 155 clk_type, 156 min, 157 max); 158 159 return ret; 160 } 161 162 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 163 { 164 if (!smu->ppt_funcs && !smu->ppt_funcs->set_gfx_power_up_by_imu) 165 return -EOPNOTSUPP; 166 167 return smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 168 } 169 170 static u32 smu_get_mclk(void *handle, bool low) 171 { 172 struct smu_context *smu = handle; 173 uint32_t clk_freq; 174 int ret = 0; 175 176 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 177 low ? &clk_freq : NULL, 178 !low ? &clk_freq : NULL); 179 if (ret) 180 return 0; 181 return clk_freq * 100; 182 } 183 184 static u32 smu_get_sclk(void *handle, bool low) 185 { 186 struct smu_context *smu = handle; 187 uint32_t clk_freq; 188 int ret = 0; 189 190 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 191 low ? &clk_freq : NULL, 192 !low ? &clk_freq : NULL); 193 if (ret) 194 return 0; 195 return clk_freq * 100; 196 } 197 198 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 199 bool enable) 200 { 201 struct smu_power_context *smu_power = &smu->smu_power; 202 struct smu_power_gate *power_gate = &smu_power->power_gate; 203 int ret = 0; 204 205 if (!smu->ppt_funcs->dpm_set_vcn_enable) 206 return 0; 207 208 if (atomic_read(&power_gate->vcn_gated) ^ enable) 209 return 0; 210 211 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 212 if (!ret) 213 atomic_set(&power_gate->vcn_gated, !enable); 214 215 return ret; 216 } 217 218 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 219 bool enable) 220 { 221 struct smu_power_context *smu_power = &smu->smu_power; 222 struct smu_power_gate *power_gate = &smu_power->power_gate; 223 int ret = 0; 224 225 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 226 return 0; 227 228 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 229 return 0; 230 231 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 232 if (!ret) 233 atomic_set(&power_gate->jpeg_gated, !enable); 234 235 return ret; 236 } 237 238 /** 239 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 240 * 241 * @handle: smu_context pointer 242 * @block_type: the IP block to power gate/ungate 243 * @gate: to power gate if true, ungate otherwise 244 * 245 * This API uses no smu->mutex lock protection due to: 246 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 247 * This is guarded to be race condition free by the caller. 248 * 2. Or get called on user setting request of power_dpm_force_performance_level. 249 * Under this case, the smu->mutex lock protection is already enforced on 250 * the parent API smu_force_performance_level of the call path. 251 */ 252 static int smu_dpm_set_power_gate(void *handle, 253 uint32_t block_type, 254 bool gate) 255 { 256 struct smu_context *smu = handle; 257 int ret = 0; 258 259 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 260 dev_WARN(smu->adev->dev, 261 "SMU uninitialized but power %s requested for %u!\n", 262 gate ? "gate" : "ungate", block_type); 263 return -EOPNOTSUPP; 264 } 265 266 switch (block_type) { 267 /* 268 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 269 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 270 */ 271 case AMD_IP_BLOCK_TYPE_UVD: 272 case AMD_IP_BLOCK_TYPE_VCN: 273 ret = smu_dpm_set_vcn_enable(smu, !gate); 274 if (ret) 275 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 276 gate ? "gate" : "ungate"); 277 break; 278 case AMD_IP_BLOCK_TYPE_GFX: 279 ret = smu_gfx_off_control(smu, gate); 280 if (ret) 281 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 282 gate ? "enable" : "disable"); 283 break; 284 case AMD_IP_BLOCK_TYPE_SDMA: 285 ret = smu_powergate_sdma(smu, gate); 286 if (ret) 287 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 288 gate ? "gate" : "ungate"); 289 break; 290 case AMD_IP_BLOCK_TYPE_JPEG: 291 ret = smu_dpm_set_jpeg_enable(smu, !gate); 292 if (ret) 293 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 294 gate ? "gate" : "ungate"); 295 break; 296 default: 297 dev_err(smu->adev->dev, "Unsupported block type!\n"); 298 return -EINVAL; 299 } 300 301 return ret; 302 } 303 304 /** 305 * smu_set_user_clk_dependencies - set user profile clock dependencies 306 * 307 * @smu: smu_context pointer 308 * @clk: enum smu_clk_type type 309 * 310 * Enable/Disable the clock dependency for the @clk type. 311 */ 312 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 313 { 314 if (smu->adev->in_suspend) 315 return; 316 317 if (clk == SMU_MCLK) { 318 smu->user_dpm_profile.clk_dependency = 0; 319 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 320 } else if (clk == SMU_FCLK) { 321 /* MCLK takes precedence over FCLK */ 322 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 323 return; 324 325 smu->user_dpm_profile.clk_dependency = 0; 326 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 327 } else if (clk == SMU_SOCCLK) { 328 /* MCLK takes precedence over SOCCLK */ 329 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 330 return; 331 332 smu->user_dpm_profile.clk_dependency = 0; 333 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 334 } else 335 /* Add clk dependencies here, if any */ 336 return; 337 } 338 339 /** 340 * smu_restore_dpm_user_profile - reinstate user dpm profile 341 * 342 * @smu: smu_context pointer 343 * 344 * Restore the saved user power configurations include power limit, 345 * clock frequencies, fan control mode and fan speed. 346 */ 347 static void smu_restore_dpm_user_profile(struct smu_context *smu) 348 { 349 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 350 int ret = 0; 351 352 if (!smu->adev->in_suspend) 353 return; 354 355 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 356 return; 357 358 /* Enable restore flag */ 359 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 360 361 /* set the user dpm power limit */ 362 if (smu->user_dpm_profile.power_limit) { 363 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 364 if (ret) 365 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 366 } 367 368 /* set the user dpm clock configurations */ 369 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 370 enum smu_clk_type clk_type; 371 372 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 373 /* 374 * Iterate over smu clk type and force the saved user clk 375 * configs, skip if clock dependency is enabled 376 */ 377 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 378 smu->user_dpm_profile.clk_mask[clk_type]) { 379 ret = smu_force_smuclk_levels(smu, clk_type, 380 smu->user_dpm_profile.clk_mask[clk_type]); 381 if (ret) 382 dev_err(smu->adev->dev, 383 "Failed to set clock type = %d\n", clk_type); 384 } 385 } 386 } 387 388 /* set the user dpm fan configurations */ 389 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 390 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 391 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 392 if (ret != -EOPNOTSUPP) { 393 smu->user_dpm_profile.fan_speed_pwm = 0; 394 smu->user_dpm_profile.fan_speed_rpm = 0; 395 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 396 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 397 } 398 399 if (smu->user_dpm_profile.fan_speed_pwm) { 400 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 401 if (ret != -EOPNOTSUPP) 402 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 403 } 404 405 if (smu->user_dpm_profile.fan_speed_rpm) { 406 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 407 if (ret != -EOPNOTSUPP) 408 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 409 } 410 } 411 412 /* Restore user customized OD settings */ 413 if (smu->user_dpm_profile.user_od) { 414 if (smu->ppt_funcs->restore_user_od_settings) { 415 ret = smu->ppt_funcs->restore_user_od_settings(smu); 416 if (ret) 417 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 418 } 419 } 420 421 /* Disable restore flag */ 422 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 423 } 424 425 static int smu_get_power_num_states(void *handle, 426 struct pp_states_info *state_info) 427 { 428 if (!state_info) 429 return -EINVAL; 430 431 /* not support power state */ 432 memset(state_info, 0, sizeof(struct pp_states_info)); 433 state_info->nums = 1; 434 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 435 436 return 0; 437 } 438 439 bool is_support_sw_smu(struct amdgpu_device *adev) 440 { 441 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 442 if (adev->asic_type == CHIP_VEGA20) 443 return false; 444 445 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 446 return true; 447 448 return false; 449 } 450 451 bool is_support_cclk_dpm(struct amdgpu_device *adev) 452 { 453 struct smu_context *smu = adev->powerplay.pp_handle; 454 455 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 456 return false; 457 458 return true; 459 } 460 461 462 static int smu_sys_get_pp_table(void *handle, 463 char **table) 464 { 465 struct smu_context *smu = handle; 466 struct smu_table_context *smu_table = &smu->smu_table; 467 468 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 469 return -EOPNOTSUPP; 470 471 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 472 return -EINVAL; 473 474 if (smu_table->hardcode_pptable) 475 *table = smu_table->hardcode_pptable; 476 else 477 *table = smu_table->power_play_table; 478 479 return smu_table->power_play_table_size; 480 } 481 482 static int smu_sys_set_pp_table(void *handle, 483 const char *buf, 484 size_t size) 485 { 486 struct smu_context *smu = handle; 487 struct smu_table_context *smu_table = &smu->smu_table; 488 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 489 int ret = 0; 490 491 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 492 return -EOPNOTSUPP; 493 494 if (header->usStructureSize != size) { 495 dev_err(smu->adev->dev, "pp table size not matched !\n"); 496 return -EIO; 497 } 498 499 if (!smu_table->hardcode_pptable) { 500 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 501 if (!smu_table->hardcode_pptable) 502 return -ENOMEM; 503 } 504 505 memcpy(smu_table->hardcode_pptable, buf, size); 506 smu_table->power_play_table = smu_table->hardcode_pptable; 507 smu_table->power_play_table_size = size; 508 509 /* 510 * Special hw_fini action(for Navi1x, the DPMs disablement will be 511 * skipped) may be needed for custom pptable uploading. 512 */ 513 smu->uploading_custom_pp_table = true; 514 515 ret = smu_reset(smu); 516 if (ret) 517 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 518 519 smu->uploading_custom_pp_table = false; 520 521 return ret; 522 } 523 524 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 525 { 526 struct smu_feature *feature = &smu->smu_feature; 527 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 528 int ret = 0; 529 530 /* 531 * With SCPM enabled, the allowed featuremasks setting(via 532 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 533 * That means there is no way to let PMFW knows the settings below. 534 * Thus, we just assume all the features are allowed under 535 * such scenario. 536 */ 537 if (smu->adev->scpm_enabled) { 538 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 539 return 0; 540 } 541 542 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 543 544 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 545 SMU_FEATURE_MAX/32); 546 if (ret) 547 return ret; 548 549 bitmap_or(feature->allowed, feature->allowed, 550 (unsigned long *)allowed_feature_mask, 551 feature->feature_num); 552 553 return ret; 554 } 555 556 static int smu_set_funcs(struct amdgpu_device *adev) 557 { 558 struct smu_context *smu = adev->powerplay.pp_handle; 559 560 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 561 smu->od_enabled = true; 562 563 switch (adev->ip_versions[MP1_HWIP][0]) { 564 case IP_VERSION(11, 0, 0): 565 case IP_VERSION(11, 0, 5): 566 case IP_VERSION(11, 0, 9): 567 navi10_set_ppt_funcs(smu); 568 break; 569 case IP_VERSION(11, 0, 7): 570 case IP_VERSION(11, 0, 11): 571 case IP_VERSION(11, 0, 12): 572 case IP_VERSION(11, 0, 13): 573 sienna_cichlid_set_ppt_funcs(smu); 574 break; 575 case IP_VERSION(12, 0, 0): 576 case IP_VERSION(12, 0, 1): 577 renoir_set_ppt_funcs(smu); 578 break; 579 case IP_VERSION(11, 5, 0): 580 vangogh_set_ppt_funcs(smu); 581 break; 582 case IP_VERSION(13, 0, 1): 583 case IP_VERSION(13, 0, 3): 584 case IP_VERSION(13, 0, 8): 585 yellow_carp_set_ppt_funcs(smu); 586 break; 587 case IP_VERSION(13, 0, 4): 588 smu_v13_0_4_set_ppt_funcs(smu); 589 break; 590 case IP_VERSION(13, 0, 5): 591 smu_v13_0_5_set_ppt_funcs(smu); 592 break; 593 case IP_VERSION(11, 0, 8): 594 cyan_skillfish_set_ppt_funcs(smu); 595 break; 596 case IP_VERSION(11, 0, 2): 597 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 598 arcturus_set_ppt_funcs(smu); 599 /* OD is not supported on Arcturus */ 600 smu->od_enabled =false; 601 break; 602 case IP_VERSION(13, 0, 2): 603 aldebaran_set_ppt_funcs(smu); 604 /* Enable pp_od_clk_voltage node */ 605 smu->od_enabled = true; 606 break; 607 case IP_VERSION(13, 0, 0): 608 case IP_VERSION(13, 0, 10): 609 smu_v13_0_0_set_ppt_funcs(smu); 610 break; 611 case IP_VERSION(13, 0, 7): 612 smu_v13_0_7_set_ppt_funcs(smu); 613 break; 614 default: 615 return -EINVAL; 616 } 617 618 return 0; 619 } 620 621 static int smu_early_init(void *handle) 622 { 623 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 624 struct smu_context *smu; 625 626 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 627 if (!smu) 628 return -ENOMEM; 629 630 smu->adev = adev; 631 smu->pm_enabled = !!amdgpu_dpm; 632 smu->is_apu = false; 633 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 634 smu->smu_baco.platform_support = false; 635 smu->user_dpm_profile.fan_mode = -1; 636 637 mutex_init(&smu->message_lock); 638 639 adev->powerplay.pp_handle = smu; 640 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 641 642 return smu_set_funcs(adev); 643 } 644 645 static int smu_set_default_dpm_table(struct smu_context *smu) 646 { 647 struct smu_power_context *smu_power = &smu->smu_power; 648 struct smu_power_gate *power_gate = &smu_power->power_gate; 649 int vcn_gate, jpeg_gate; 650 int ret = 0; 651 652 if (!smu->ppt_funcs->set_default_dpm_table) 653 return 0; 654 655 vcn_gate = atomic_read(&power_gate->vcn_gated); 656 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 657 658 ret = smu_dpm_set_vcn_enable(smu, true); 659 if (ret) 660 return ret; 661 662 ret = smu_dpm_set_jpeg_enable(smu, true); 663 if (ret) 664 goto err_out; 665 666 ret = smu->ppt_funcs->set_default_dpm_table(smu); 667 if (ret) 668 dev_err(smu->adev->dev, 669 "Failed to setup default dpm clock tables!\n"); 670 671 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 672 err_out: 673 smu_dpm_set_vcn_enable(smu, !vcn_gate); 674 return ret; 675 } 676 677 static int smu_apply_default_config_table_settings(struct smu_context *smu) 678 { 679 struct amdgpu_device *adev = smu->adev; 680 int ret = 0; 681 682 ret = smu_get_default_config_table_settings(smu, 683 &adev->pm.config_table); 684 if (ret) 685 return ret; 686 687 return smu_set_config_table(smu, &adev->pm.config_table); 688 } 689 690 static int smu_late_init(void *handle) 691 { 692 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 693 struct smu_context *smu = adev->powerplay.pp_handle; 694 int ret = 0; 695 696 smu_set_fine_grain_gfx_freq_parameters(smu); 697 698 if (!smu->pm_enabled) 699 return 0; 700 701 ret = smu_post_init(smu); 702 if (ret) { 703 dev_err(adev->dev, "Failed to post smu init!\n"); 704 return ret; 705 } 706 707 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 708 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 709 return 0; 710 711 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 712 ret = smu_set_default_od_settings(smu); 713 if (ret) { 714 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 715 return ret; 716 } 717 } 718 719 ret = smu_populate_umd_state_clk(smu); 720 if (ret) { 721 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 722 return ret; 723 } 724 725 ret = smu_get_asic_power_limits(smu, 726 &smu->current_power_limit, 727 &smu->default_power_limit, 728 &smu->max_power_limit); 729 if (ret) { 730 dev_err(adev->dev, "Failed to get asic power limits!\n"); 731 return ret; 732 } 733 734 if (!amdgpu_sriov_vf(adev)) 735 smu_get_unique_id(smu); 736 737 smu_get_fan_parameters(smu); 738 739 smu_handle_task(smu, 740 smu->smu_dpm.dpm_level, 741 AMD_PP_TASK_COMPLETE_INIT); 742 743 ret = smu_apply_default_config_table_settings(smu); 744 if (ret && (ret != -EOPNOTSUPP)) { 745 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 746 return ret; 747 } 748 749 smu_restore_dpm_user_profile(smu); 750 751 return 0; 752 } 753 754 static int smu_init_fb_allocations(struct smu_context *smu) 755 { 756 struct amdgpu_device *adev = smu->adev; 757 struct smu_table_context *smu_table = &smu->smu_table; 758 struct smu_table *tables = smu_table->tables; 759 struct smu_table *driver_table = &(smu_table->driver_table); 760 uint32_t max_table_size = 0; 761 int ret, i; 762 763 /* VRAM allocation for tool table */ 764 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 765 ret = amdgpu_bo_create_kernel(adev, 766 tables[SMU_TABLE_PMSTATUSLOG].size, 767 tables[SMU_TABLE_PMSTATUSLOG].align, 768 tables[SMU_TABLE_PMSTATUSLOG].domain, 769 &tables[SMU_TABLE_PMSTATUSLOG].bo, 770 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 771 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 772 if (ret) { 773 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 774 return ret; 775 } 776 } 777 778 /* VRAM allocation for driver table */ 779 for (i = 0; i < SMU_TABLE_COUNT; i++) { 780 if (tables[i].size == 0) 781 continue; 782 783 if (i == SMU_TABLE_PMSTATUSLOG) 784 continue; 785 786 if (max_table_size < tables[i].size) 787 max_table_size = tables[i].size; 788 } 789 790 driver_table->size = max_table_size; 791 driver_table->align = PAGE_SIZE; 792 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 793 794 ret = amdgpu_bo_create_kernel(adev, 795 driver_table->size, 796 driver_table->align, 797 driver_table->domain, 798 &driver_table->bo, 799 &driver_table->mc_address, 800 &driver_table->cpu_addr); 801 if (ret) { 802 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 803 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 804 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 805 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 806 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 807 } 808 809 return ret; 810 } 811 812 static int smu_fini_fb_allocations(struct smu_context *smu) 813 { 814 struct smu_table_context *smu_table = &smu->smu_table; 815 struct smu_table *tables = smu_table->tables; 816 struct smu_table *driver_table = &(smu_table->driver_table); 817 818 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 819 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 820 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 821 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 822 823 amdgpu_bo_free_kernel(&driver_table->bo, 824 &driver_table->mc_address, 825 &driver_table->cpu_addr); 826 827 return 0; 828 } 829 830 /** 831 * smu_alloc_memory_pool - allocate memory pool in the system memory 832 * 833 * @smu: amdgpu_device pointer 834 * 835 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 836 * and DramLogSetDramAddr can notify it changed. 837 * 838 * Returns 0 on success, error on failure. 839 */ 840 static int smu_alloc_memory_pool(struct smu_context *smu) 841 { 842 struct amdgpu_device *adev = smu->adev; 843 struct smu_table_context *smu_table = &smu->smu_table; 844 struct smu_table *memory_pool = &smu_table->memory_pool; 845 uint64_t pool_size = smu->pool_size; 846 int ret = 0; 847 848 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 849 return ret; 850 851 memory_pool->size = pool_size; 852 memory_pool->align = PAGE_SIZE; 853 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 854 855 switch (pool_size) { 856 case SMU_MEMORY_POOL_SIZE_256_MB: 857 case SMU_MEMORY_POOL_SIZE_512_MB: 858 case SMU_MEMORY_POOL_SIZE_1_GB: 859 case SMU_MEMORY_POOL_SIZE_2_GB: 860 ret = amdgpu_bo_create_kernel(adev, 861 memory_pool->size, 862 memory_pool->align, 863 memory_pool->domain, 864 &memory_pool->bo, 865 &memory_pool->mc_address, 866 &memory_pool->cpu_addr); 867 if (ret) 868 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 869 break; 870 default: 871 break; 872 } 873 874 return ret; 875 } 876 877 static int smu_free_memory_pool(struct smu_context *smu) 878 { 879 struct smu_table_context *smu_table = &smu->smu_table; 880 struct smu_table *memory_pool = &smu_table->memory_pool; 881 882 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 883 return 0; 884 885 amdgpu_bo_free_kernel(&memory_pool->bo, 886 &memory_pool->mc_address, 887 &memory_pool->cpu_addr); 888 889 memset(memory_pool, 0, sizeof(struct smu_table)); 890 891 return 0; 892 } 893 894 static int smu_alloc_dummy_read_table(struct smu_context *smu) 895 { 896 struct smu_table_context *smu_table = &smu->smu_table; 897 struct smu_table *dummy_read_1_table = 898 &smu_table->dummy_read_1_table; 899 struct amdgpu_device *adev = smu->adev; 900 int ret = 0; 901 902 dummy_read_1_table->size = 0x40000; 903 dummy_read_1_table->align = PAGE_SIZE; 904 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 905 906 ret = amdgpu_bo_create_kernel(adev, 907 dummy_read_1_table->size, 908 dummy_read_1_table->align, 909 dummy_read_1_table->domain, 910 &dummy_read_1_table->bo, 911 &dummy_read_1_table->mc_address, 912 &dummy_read_1_table->cpu_addr); 913 if (ret) 914 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 915 916 return ret; 917 } 918 919 static void smu_free_dummy_read_table(struct smu_context *smu) 920 { 921 struct smu_table_context *smu_table = &smu->smu_table; 922 struct smu_table *dummy_read_1_table = 923 &smu_table->dummy_read_1_table; 924 925 926 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 927 &dummy_read_1_table->mc_address, 928 &dummy_read_1_table->cpu_addr); 929 930 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 931 } 932 933 static int smu_smc_table_sw_init(struct smu_context *smu) 934 { 935 int ret; 936 937 /** 938 * Create smu_table structure, and init smc tables such as 939 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 940 */ 941 ret = smu_init_smc_tables(smu); 942 if (ret) { 943 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 944 return ret; 945 } 946 947 /** 948 * Create smu_power_context structure, and allocate smu_dpm_context and 949 * context size to fill the smu_power_context data. 950 */ 951 ret = smu_init_power(smu); 952 if (ret) { 953 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 954 return ret; 955 } 956 957 /* 958 * allocate vram bos to store smc table contents. 959 */ 960 ret = smu_init_fb_allocations(smu); 961 if (ret) 962 return ret; 963 964 ret = smu_alloc_memory_pool(smu); 965 if (ret) 966 return ret; 967 968 ret = smu_alloc_dummy_read_table(smu); 969 if (ret) 970 return ret; 971 972 ret = smu_i2c_init(smu); 973 if (ret) 974 return ret; 975 976 return 0; 977 } 978 979 static int smu_smc_table_sw_fini(struct smu_context *smu) 980 { 981 int ret; 982 983 smu_i2c_fini(smu); 984 985 smu_free_dummy_read_table(smu); 986 987 ret = smu_free_memory_pool(smu); 988 if (ret) 989 return ret; 990 991 ret = smu_fini_fb_allocations(smu); 992 if (ret) 993 return ret; 994 995 ret = smu_fini_power(smu); 996 if (ret) { 997 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 998 return ret; 999 } 1000 1001 ret = smu_fini_smc_tables(smu); 1002 if (ret) { 1003 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1004 return ret; 1005 } 1006 1007 return 0; 1008 } 1009 1010 static void smu_throttling_logging_work_fn(struct work_struct *work) 1011 { 1012 struct smu_context *smu = container_of(work, struct smu_context, 1013 throttling_logging_work); 1014 1015 smu_log_thermal_throttling(smu); 1016 } 1017 1018 static void smu_interrupt_work_fn(struct work_struct *work) 1019 { 1020 struct smu_context *smu = container_of(work, struct smu_context, 1021 interrupt_work); 1022 1023 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1024 smu->ppt_funcs->interrupt_work(smu); 1025 } 1026 1027 static int smu_sw_init(void *handle) 1028 { 1029 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1030 struct smu_context *smu = adev->powerplay.pp_handle; 1031 int ret; 1032 1033 smu->pool_size = adev->pm.smu_prv_buffer_size; 1034 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1035 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1036 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1037 1038 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1039 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1040 atomic64_set(&smu->throttle_int_counter, 0); 1041 smu->watermarks_bitmap = 0; 1042 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1043 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1044 1045 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1046 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1047 1048 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1049 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1050 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1051 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1052 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1053 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1054 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1055 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1056 1057 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1058 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1059 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1060 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1061 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1062 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1063 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1064 smu->display_config = &adev->pm.pm_display_cfg; 1065 1066 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1067 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1068 1069 ret = smu_init_microcode(smu); 1070 if (ret) { 1071 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1072 return ret; 1073 } 1074 1075 ret = smu_smc_table_sw_init(smu); 1076 if (ret) { 1077 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1078 return ret; 1079 } 1080 1081 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1082 ret = smu_get_vbios_bootup_values(smu); 1083 if (ret) { 1084 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1085 return ret; 1086 } 1087 1088 ret = smu_init_pptable_microcode(smu); 1089 if (ret) { 1090 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1091 return ret; 1092 } 1093 1094 ret = smu_register_irq_handler(smu); 1095 if (ret) { 1096 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1097 return ret; 1098 } 1099 1100 /* If there is no way to query fan control mode, fan control is not supported */ 1101 if (!smu->ppt_funcs->get_fan_control_mode) 1102 smu->adev->pm.no_fan = true; 1103 1104 return 0; 1105 } 1106 1107 static int smu_sw_fini(void *handle) 1108 { 1109 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1110 struct smu_context *smu = adev->powerplay.pp_handle; 1111 int ret; 1112 1113 ret = smu_smc_table_sw_fini(smu); 1114 if (ret) { 1115 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1116 return ret; 1117 } 1118 1119 smu_fini_microcode(smu); 1120 1121 return 0; 1122 } 1123 1124 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1125 { 1126 struct amdgpu_device *adev = smu->adev; 1127 struct smu_temperature_range *range = 1128 &smu->thermal_range; 1129 int ret = 0; 1130 1131 if (!smu->ppt_funcs->get_thermal_temperature_range) 1132 return 0; 1133 1134 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1135 if (ret) 1136 return ret; 1137 1138 adev->pm.dpm.thermal.min_temp = range->min; 1139 adev->pm.dpm.thermal.max_temp = range->max; 1140 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1141 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1142 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1143 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1144 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1145 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1146 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1147 1148 return ret; 1149 } 1150 1151 static int smu_smc_hw_setup(struct smu_context *smu) 1152 { 1153 struct smu_feature *feature = &smu->smu_feature; 1154 struct amdgpu_device *adev = smu->adev; 1155 uint32_t pcie_gen = 0, pcie_width = 0; 1156 uint64_t features_supported; 1157 int ret = 0; 1158 1159 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1160 dev_info(adev->dev, "dpm has been enabled\n"); 1161 /* this is needed specifically */ 1162 switch (adev->ip_versions[MP1_HWIP][0]) { 1163 case IP_VERSION(11, 0, 7): 1164 case IP_VERSION(11, 0, 11): 1165 case IP_VERSION(11, 5, 0): 1166 case IP_VERSION(11, 0, 12): 1167 ret = smu_system_features_control(smu, true); 1168 if (ret) 1169 dev_err(adev->dev, "Failed system features control!\n"); 1170 break; 1171 default: 1172 break; 1173 } 1174 return ret; 1175 } 1176 1177 ret = smu_init_display_count(smu, 0); 1178 if (ret) { 1179 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1180 return ret; 1181 } 1182 1183 ret = smu_set_driver_table_location(smu); 1184 if (ret) { 1185 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1186 return ret; 1187 } 1188 1189 /* 1190 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1191 */ 1192 ret = smu_set_tool_table_location(smu); 1193 if (ret) { 1194 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1195 return ret; 1196 } 1197 1198 /* 1199 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1200 * pool location. 1201 */ 1202 ret = smu_notify_memory_pool_location(smu); 1203 if (ret) { 1204 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1205 return ret; 1206 } 1207 1208 ret = smu_setup_pptable(smu); 1209 if (ret) { 1210 dev_err(adev->dev, "Failed to setup pptable!\n"); 1211 return ret; 1212 } 1213 1214 /* smu_dump_pptable(smu); */ 1215 1216 /* 1217 * With SCPM enabled, PSP is responsible for the PPTable transferring 1218 * (to SMU). Driver involvement is not needed and permitted. 1219 */ 1220 if (!adev->scpm_enabled) { 1221 /* 1222 * Copy pptable bo in the vram to smc with SMU MSGs such as 1223 * SetDriverDramAddr and TransferTableDram2Smu. 1224 */ 1225 ret = smu_write_pptable(smu); 1226 if (ret) { 1227 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1228 return ret; 1229 } 1230 } 1231 1232 /* issue Run*Btc msg */ 1233 ret = smu_run_btc(smu); 1234 if (ret) 1235 return ret; 1236 1237 /* 1238 * With SCPM enabled, these actions(and relevant messages) are 1239 * not needed and permitted. 1240 */ 1241 if (!adev->scpm_enabled) { 1242 ret = smu_feature_set_allowed_mask(smu); 1243 if (ret) { 1244 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1245 return ret; 1246 } 1247 } 1248 1249 ret = smu_system_features_control(smu, true); 1250 if (ret) { 1251 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1252 return ret; 1253 } 1254 1255 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1256 if (ret) { 1257 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1258 return ret; 1259 } 1260 bitmap_copy(feature->supported, 1261 (unsigned long *)&features_supported, 1262 feature->feature_num); 1263 1264 if (!smu_is_dpm_running(smu)) 1265 dev_info(adev->dev, "dpm has been disabled\n"); 1266 1267 /* 1268 * Set initialized values (get from vbios) to dpm tables context such as 1269 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1270 * type of clks. 1271 */ 1272 ret = smu_set_default_dpm_table(smu); 1273 if (ret) { 1274 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1275 return ret; 1276 } 1277 1278 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1279 pcie_gen = 3; 1280 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1281 pcie_gen = 2; 1282 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1283 pcie_gen = 1; 1284 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1285 pcie_gen = 0; 1286 1287 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1288 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1289 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1290 */ 1291 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1292 pcie_width = 6; 1293 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1294 pcie_width = 5; 1295 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1296 pcie_width = 4; 1297 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1298 pcie_width = 3; 1299 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1300 pcie_width = 2; 1301 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1302 pcie_width = 1; 1303 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1304 if (ret) { 1305 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1306 return ret; 1307 } 1308 1309 ret = smu_get_thermal_temperature_range(smu); 1310 if (ret) { 1311 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1312 return ret; 1313 } 1314 1315 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 10)) { 1316 ret = smu_enable_thermal_alert(smu); 1317 if (ret) { 1318 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1319 return ret; 1320 } 1321 } 1322 1323 ret = smu_notify_display_change(smu); 1324 if (ret) { 1325 dev_err(adev->dev, "Failed to notify display change!\n"); 1326 return ret; 1327 } 1328 1329 /* 1330 * Set min deep sleep dce fclk with bootup value from vbios via 1331 * SetMinDeepSleepDcefclk MSG. 1332 */ 1333 ret = smu_set_min_dcef_deep_sleep(smu, 1334 smu->smu_table.boot_values.dcefclk / 100); 1335 1336 return ret; 1337 } 1338 1339 static int smu_start_smc_engine(struct smu_context *smu) 1340 { 1341 struct amdgpu_device *adev = smu->adev; 1342 int ret = 0; 1343 1344 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1345 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1346 if (smu->ppt_funcs->load_microcode) { 1347 ret = smu->ppt_funcs->load_microcode(smu); 1348 if (ret) 1349 return ret; 1350 } 1351 } 1352 } 1353 1354 if (smu->ppt_funcs->check_fw_status) { 1355 ret = smu->ppt_funcs->check_fw_status(smu); 1356 if (ret) { 1357 dev_err(adev->dev, "SMC is not ready\n"); 1358 return ret; 1359 } 1360 } 1361 1362 /* 1363 * Send msg GetDriverIfVersion to check if the return value is equal 1364 * with DRIVER_IF_VERSION of smc header. 1365 */ 1366 ret = smu_check_fw_version(smu); 1367 if (ret) 1368 return ret; 1369 1370 return ret; 1371 } 1372 1373 static int smu_hw_init(void *handle) 1374 { 1375 int ret; 1376 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1377 struct smu_context *smu = adev->powerplay.pp_handle; 1378 1379 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1380 smu->pm_enabled = false; 1381 return 0; 1382 } 1383 1384 ret = smu_start_smc_engine(smu); 1385 if (ret) { 1386 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1387 return ret; 1388 } 1389 1390 if (smu->is_apu) { 1391 if ((smu->ppt_funcs->set_gfx_power_up_by_imu) && 1392 likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 1393 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 1394 if (ret) { 1395 dev_err(adev->dev, "Failed to Enable gfx imu!\n"); 1396 return ret; 1397 } 1398 } 1399 1400 smu_dpm_set_vcn_enable(smu, true); 1401 smu_dpm_set_jpeg_enable(smu, true); 1402 smu_set_gfx_cgpg(smu, true); 1403 } 1404 1405 if (!smu->pm_enabled) 1406 return 0; 1407 1408 ret = smu_get_driver_allowed_feature_mask(smu); 1409 if (ret) 1410 return ret; 1411 1412 ret = smu_smc_hw_setup(smu); 1413 if (ret) { 1414 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1415 return ret; 1416 } 1417 1418 /* 1419 * Move maximum sustainable clock retrieving here considering 1420 * 1. It is not needed on resume(from S3). 1421 * 2. DAL settings come between .hw_init and .late_init of SMU. 1422 * And DAL needs to know the maximum sustainable clocks. Thus 1423 * it cannot be put in .late_init(). 1424 */ 1425 ret = smu_init_max_sustainable_clocks(smu); 1426 if (ret) { 1427 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1428 return ret; 1429 } 1430 1431 adev->pm.dpm_enabled = true; 1432 1433 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1434 1435 return 0; 1436 } 1437 1438 static int smu_disable_dpms(struct smu_context *smu) 1439 { 1440 struct amdgpu_device *adev = smu->adev; 1441 int ret = 0; 1442 bool use_baco = !smu->is_apu && 1443 ((amdgpu_in_reset(adev) && 1444 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1445 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1446 1447 /* 1448 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1449 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1450 */ 1451 switch (adev->ip_versions[MP1_HWIP][0]) { 1452 case IP_VERSION(13, 0, 0): 1453 case IP_VERSION(13, 0, 7): 1454 return 0; 1455 default: 1456 break; 1457 } 1458 1459 /* 1460 * For custom pptable uploading, skip the DPM features 1461 * disable process on Navi1x ASICs. 1462 * - As the gfx related features are under control of 1463 * RLC on those ASICs. RLC reinitialization will be 1464 * needed to reenable them. That will cost much more 1465 * efforts. 1466 * 1467 * - SMU firmware can handle the DPM reenablement 1468 * properly. 1469 */ 1470 if (smu->uploading_custom_pp_table) { 1471 switch (adev->ip_versions[MP1_HWIP][0]) { 1472 case IP_VERSION(11, 0, 0): 1473 case IP_VERSION(11, 0, 5): 1474 case IP_VERSION(11, 0, 9): 1475 case IP_VERSION(11, 0, 7): 1476 case IP_VERSION(11, 0, 11): 1477 case IP_VERSION(11, 5, 0): 1478 case IP_VERSION(11, 0, 12): 1479 case IP_VERSION(11, 0, 13): 1480 return 0; 1481 default: 1482 break; 1483 } 1484 } 1485 1486 /* 1487 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1488 * on BACO in. Driver involvement is unnecessary. 1489 */ 1490 if (use_baco) { 1491 switch (adev->ip_versions[MP1_HWIP][0]) { 1492 case IP_VERSION(11, 0, 7): 1493 case IP_VERSION(11, 0, 0): 1494 case IP_VERSION(11, 0, 5): 1495 case IP_VERSION(11, 0, 9): 1496 case IP_VERSION(13, 0, 7): 1497 return 0; 1498 default: 1499 break; 1500 } 1501 } 1502 1503 /* 1504 * For gpu reset, runpm and hibernation through BACO, 1505 * BACO feature has to be kept enabled. 1506 */ 1507 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1508 ret = smu_disable_all_features_with_exception(smu, 1509 SMU_FEATURE_BACO_BIT); 1510 if (ret) 1511 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1512 } else { 1513 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1514 if (!adev->scpm_enabled) { 1515 ret = smu_system_features_control(smu, false); 1516 if (ret) 1517 dev_err(adev->dev, "Failed to disable smu features.\n"); 1518 } 1519 } 1520 1521 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1522 adev->gfx.rlc.funcs->stop) 1523 adev->gfx.rlc.funcs->stop(adev); 1524 1525 return ret; 1526 } 1527 1528 static int smu_smc_hw_cleanup(struct smu_context *smu) 1529 { 1530 struct amdgpu_device *adev = smu->adev; 1531 int ret = 0; 1532 1533 cancel_work_sync(&smu->throttling_logging_work); 1534 cancel_work_sync(&smu->interrupt_work); 1535 1536 ret = smu_disable_thermal_alert(smu); 1537 if (ret) { 1538 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1539 return ret; 1540 } 1541 1542 ret = smu_disable_dpms(smu); 1543 if (ret) { 1544 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1545 return ret; 1546 } 1547 1548 return 0; 1549 } 1550 1551 static int smu_hw_fini(void *handle) 1552 { 1553 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1554 struct smu_context *smu = adev->powerplay.pp_handle; 1555 1556 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1557 return 0; 1558 1559 smu_dpm_set_vcn_enable(smu, false); 1560 smu_dpm_set_jpeg_enable(smu, false); 1561 1562 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1563 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1564 1565 if (!smu->pm_enabled) 1566 return 0; 1567 1568 adev->pm.dpm_enabled = false; 1569 1570 return smu_smc_hw_cleanup(smu); 1571 } 1572 1573 static void smu_late_fini(void *handle) 1574 { 1575 struct amdgpu_device *adev = handle; 1576 struct smu_context *smu = adev->powerplay.pp_handle; 1577 1578 kfree(smu); 1579 } 1580 1581 static int smu_reset(struct smu_context *smu) 1582 { 1583 struct amdgpu_device *adev = smu->adev; 1584 int ret; 1585 1586 ret = smu_hw_fini(adev); 1587 if (ret) 1588 return ret; 1589 1590 ret = smu_hw_init(adev); 1591 if (ret) 1592 return ret; 1593 1594 ret = smu_late_init(adev); 1595 if (ret) 1596 return ret; 1597 1598 return 0; 1599 } 1600 1601 static int smu_suspend(void *handle) 1602 { 1603 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1604 struct smu_context *smu = adev->powerplay.pp_handle; 1605 int ret; 1606 uint64_t count; 1607 1608 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1609 return 0; 1610 1611 if (!smu->pm_enabled) 1612 return 0; 1613 1614 adev->pm.dpm_enabled = false; 1615 1616 ret = smu_smc_hw_cleanup(smu); 1617 if (ret) 1618 return ret; 1619 1620 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1621 1622 smu_set_gfx_cgpg(smu, false); 1623 1624 /* 1625 * pwfw resets entrycount when device is suspended, so we save the 1626 * last value to be used when we resume to keep it consistent 1627 */ 1628 ret = smu_get_entrycount_gfxoff(smu, &count); 1629 if (!ret) 1630 adev->gfx.gfx_off_entrycount = count; 1631 1632 return 0; 1633 } 1634 1635 static int smu_resume(void *handle) 1636 { 1637 int ret; 1638 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1639 struct smu_context *smu = adev->powerplay.pp_handle; 1640 1641 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1642 return 0; 1643 1644 if (!smu->pm_enabled) 1645 return 0; 1646 1647 dev_info(adev->dev, "SMU is resuming...\n"); 1648 1649 ret = smu_start_smc_engine(smu); 1650 if (ret) { 1651 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1652 return ret; 1653 } 1654 1655 ret = smu_smc_hw_setup(smu); 1656 if (ret) { 1657 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1658 return ret; 1659 } 1660 1661 smu_set_gfx_cgpg(smu, true); 1662 1663 smu->disable_uclk_switch = 0; 1664 1665 adev->pm.dpm_enabled = true; 1666 1667 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1668 1669 return 0; 1670 } 1671 1672 static int smu_display_configuration_change(void *handle, 1673 const struct amd_pp_display_configuration *display_config) 1674 { 1675 struct smu_context *smu = handle; 1676 int index = 0; 1677 int num_of_active_display = 0; 1678 1679 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1680 return -EOPNOTSUPP; 1681 1682 if (!display_config) 1683 return -EINVAL; 1684 1685 smu_set_min_dcef_deep_sleep(smu, 1686 display_config->min_dcef_deep_sleep_set_clk / 100); 1687 1688 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1689 if (display_config->displays[index].controller_id != 0) 1690 num_of_active_display++; 1691 } 1692 1693 return 0; 1694 } 1695 1696 static int smu_set_clockgating_state(void *handle, 1697 enum amd_clockgating_state state) 1698 { 1699 return 0; 1700 } 1701 1702 static int smu_set_powergating_state(void *handle, 1703 enum amd_powergating_state state) 1704 { 1705 return 0; 1706 } 1707 1708 static int smu_enable_umd_pstate(void *handle, 1709 enum amd_dpm_forced_level *level) 1710 { 1711 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1712 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1713 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1714 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1715 1716 struct smu_context *smu = (struct smu_context*)(handle); 1717 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1718 1719 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1720 return -EINVAL; 1721 1722 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1723 /* enter umd pstate, save current level, disable gfx cg*/ 1724 if (*level & profile_mode_mask) { 1725 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1726 smu_gpo_control(smu, false); 1727 smu_gfx_ulv_control(smu, false); 1728 smu_deep_sleep_control(smu, false); 1729 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1730 } 1731 } else { 1732 /* exit umd pstate, restore level, enable gfx cg*/ 1733 if (!(*level & profile_mode_mask)) { 1734 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1735 *level = smu_dpm_ctx->saved_dpm_level; 1736 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1737 smu_deep_sleep_control(smu, true); 1738 smu_gfx_ulv_control(smu, true); 1739 smu_gpo_control(smu, true); 1740 } 1741 } 1742 1743 return 0; 1744 } 1745 1746 static int smu_bump_power_profile_mode(struct smu_context *smu, 1747 long *param, 1748 uint32_t param_size) 1749 { 1750 int ret = 0; 1751 1752 if (smu->ppt_funcs->set_power_profile_mode) 1753 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1754 1755 return ret; 1756 } 1757 1758 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1759 enum amd_dpm_forced_level level, 1760 bool skip_display_settings) 1761 { 1762 int ret = 0; 1763 int index = 0; 1764 long workload; 1765 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1766 1767 if (!skip_display_settings) { 1768 ret = smu_display_config_changed(smu); 1769 if (ret) { 1770 dev_err(smu->adev->dev, "Failed to change display config!"); 1771 return ret; 1772 } 1773 } 1774 1775 ret = smu_apply_clocks_adjust_rules(smu); 1776 if (ret) { 1777 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1778 return ret; 1779 } 1780 1781 if (!skip_display_settings) { 1782 ret = smu_notify_smc_display_config(smu); 1783 if (ret) { 1784 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1785 return ret; 1786 } 1787 } 1788 1789 if (smu_dpm_ctx->dpm_level != level) { 1790 ret = smu_asic_set_performance_level(smu, level); 1791 if (ret) { 1792 dev_err(smu->adev->dev, "Failed to set performance level!"); 1793 return ret; 1794 } 1795 1796 /* update the saved copy */ 1797 smu_dpm_ctx->dpm_level = level; 1798 } 1799 1800 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1801 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1802 index = fls(smu->workload_mask); 1803 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1804 workload = smu->workload_setting[index]; 1805 1806 if (smu->power_profile_mode != workload) 1807 smu_bump_power_profile_mode(smu, &workload, 0); 1808 } 1809 1810 return ret; 1811 } 1812 1813 static int smu_handle_task(struct smu_context *smu, 1814 enum amd_dpm_forced_level level, 1815 enum amd_pp_task task_id) 1816 { 1817 int ret = 0; 1818 1819 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1820 return -EOPNOTSUPP; 1821 1822 switch (task_id) { 1823 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1824 ret = smu_pre_display_config_changed(smu); 1825 if (ret) 1826 return ret; 1827 ret = smu_adjust_power_state_dynamic(smu, level, false); 1828 break; 1829 case AMD_PP_TASK_COMPLETE_INIT: 1830 case AMD_PP_TASK_READJUST_POWER_STATE: 1831 ret = smu_adjust_power_state_dynamic(smu, level, true); 1832 break; 1833 default: 1834 break; 1835 } 1836 1837 return ret; 1838 } 1839 1840 static int smu_handle_dpm_task(void *handle, 1841 enum amd_pp_task task_id, 1842 enum amd_pm_state_type *user_state) 1843 { 1844 struct smu_context *smu = handle; 1845 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1846 1847 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 1848 1849 } 1850 1851 static int smu_switch_power_profile(void *handle, 1852 enum PP_SMC_POWER_PROFILE type, 1853 bool en) 1854 { 1855 struct smu_context *smu = handle; 1856 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1857 long workload; 1858 uint32_t index; 1859 1860 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1861 return -EOPNOTSUPP; 1862 1863 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1864 return -EINVAL; 1865 1866 if (!en) { 1867 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1868 index = fls(smu->workload_mask); 1869 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1870 workload = smu->workload_setting[index]; 1871 } else { 1872 smu->workload_mask |= (1 << smu->workload_prority[type]); 1873 index = fls(smu->workload_mask); 1874 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1875 workload = smu->workload_setting[index]; 1876 } 1877 1878 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1879 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1880 smu_bump_power_profile_mode(smu, &workload, 0); 1881 1882 return 0; 1883 } 1884 1885 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1886 { 1887 struct smu_context *smu = handle; 1888 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1889 1890 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1891 return -EOPNOTSUPP; 1892 1893 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1894 return -EINVAL; 1895 1896 return smu_dpm_ctx->dpm_level; 1897 } 1898 1899 static int smu_force_performance_level(void *handle, 1900 enum amd_dpm_forced_level level) 1901 { 1902 struct smu_context *smu = handle; 1903 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1904 int ret = 0; 1905 1906 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1907 return -EOPNOTSUPP; 1908 1909 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1910 return -EINVAL; 1911 1912 ret = smu_enable_umd_pstate(smu, &level); 1913 if (ret) 1914 return ret; 1915 1916 ret = smu_handle_task(smu, level, 1917 AMD_PP_TASK_READJUST_POWER_STATE); 1918 1919 /* reset user dpm clock state */ 1920 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1921 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1922 smu->user_dpm_profile.clk_dependency = 0; 1923 } 1924 1925 return ret; 1926 } 1927 1928 static int smu_set_display_count(void *handle, uint32_t count) 1929 { 1930 struct smu_context *smu = handle; 1931 1932 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1933 return -EOPNOTSUPP; 1934 1935 return smu_init_display_count(smu, count); 1936 } 1937 1938 static int smu_force_smuclk_levels(struct smu_context *smu, 1939 enum smu_clk_type clk_type, 1940 uint32_t mask) 1941 { 1942 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1943 int ret = 0; 1944 1945 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1946 return -EOPNOTSUPP; 1947 1948 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1949 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1950 return -EINVAL; 1951 } 1952 1953 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1954 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1955 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1956 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1957 smu_set_user_clk_dependencies(smu, clk_type); 1958 } 1959 } 1960 1961 return ret; 1962 } 1963 1964 static int smu_force_ppclk_levels(void *handle, 1965 enum pp_clock_type type, 1966 uint32_t mask) 1967 { 1968 struct smu_context *smu = handle; 1969 enum smu_clk_type clk_type; 1970 1971 switch (type) { 1972 case PP_SCLK: 1973 clk_type = SMU_SCLK; break; 1974 case PP_MCLK: 1975 clk_type = SMU_MCLK; break; 1976 case PP_PCIE: 1977 clk_type = SMU_PCIE; break; 1978 case PP_SOCCLK: 1979 clk_type = SMU_SOCCLK; break; 1980 case PP_FCLK: 1981 clk_type = SMU_FCLK; break; 1982 case PP_DCEFCLK: 1983 clk_type = SMU_DCEFCLK; break; 1984 case PP_VCLK: 1985 clk_type = SMU_VCLK; break; 1986 case PP_DCLK: 1987 clk_type = SMU_DCLK; break; 1988 case OD_SCLK: 1989 clk_type = SMU_OD_SCLK; break; 1990 case OD_MCLK: 1991 clk_type = SMU_OD_MCLK; break; 1992 case OD_VDDC_CURVE: 1993 clk_type = SMU_OD_VDDC_CURVE; break; 1994 case OD_RANGE: 1995 clk_type = SMU_OD_RANGE; break; 1996 default: 1997 return -EINVAL; 1998 } 1999 2000 return smu_force_smuclk_levels(smu, clk_type, mask); 2001 } 2002 2003 /* 2004 * On system suspending or resetting, the dpm_enabled 2005 * flag will be cleared. So that those SMU services which 2006 * are not supported will be gated. 2007 * However, the mp1 state setting should still be granted 2008 * even if the dpm_enabled cleared. 2009 */ 2010 static int smu_set_mp1_state(void *handle, 2011 enum pp_mp1_state mp1_state) 2012 { 2013 struct smu_context *smu = handle; 2014 int ret = 0; 2015 2016 if (!smu->pm_enabled) 2017 return -EOPNOTSUPP; 2018 2019 if (smu->ppt_funcs && 2020 smu->ppt_funcs->set_mp1_state) 2021 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2022 2023 return ret; 2024 } 2025 2026 static int smu_set_df_cstate(void *handle, 2027 enum pp_df_cstate state) 2028 { 2029 struct smu_context *smu = handle; 2030 int ret = 0; 2031 2032 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2033 return -EOPNOTSUPP; 2034 2035 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2036 return 0; 2037 2038 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2039 if (ret) 2040 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2041 2042 return ret; 2043 } 2044 2045 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 2046 { 2047 int ret = 0; 2048 2049 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2050 return -EOPNOTSUPP; 2051 2052 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2053 return 0; 2054 2055 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2056 if (ret) 2057 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2058 2059 return ret; 2060 } 2061 2062 int smu_write_watermarks_table(struct smu_context *smu) 2063 { 2064 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2065 return -EOPNOTSUPP; 2066 2067 return smu_set_watermarks_table(smu, NULL); 2068 } 2069 2070 static int smu_set_watermarks_for_clock_ranges(void *handle, 2071 struct pp_smu_wm_range_sets *clock_ranges) 2072 { 2073 struct smu_context *smu = handle; 2074 2075 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2076 return -EOPNOTSUPP; 2077 2078 if (smu->disable_watermark) 2079 return 0; 2080 2081 return smu_set_watermarks_table(smu, clock_ranges); 2082 } 2083 2084 int smu_set_ac_dc(struct smu_context *smu) 2085 { 2086 int ret = 0; 2087 2088 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2089 return -EOPNOTSUPP; 2090 2091 /* controlled by firmware */ 2092 if (smu->dc_controlled_by_gpio) 2093 return 0; 2094 2095 ret = smu_set_power_source(smu, 2096 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2097 SMU_POWER_SOURCE_DC); 2098 if (ret) 2099 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2100 smu->adev->pm.ac_power ? "AC" : "DC"); 2101 2102 return ret; 2103 } 2104 2105 const struct amd_ip_funcs smu_ip_funcs = { 2106 .name = "smu", 2107 .early_init = smu_early_init, 2108 .late_init = smu_late_init, 2109 .sw_init = smu_sw_init, 2110 .sw_fini = smu_sw_fini, 2111 .hw_init = smu_hw_init, 2112 .hw_fini = smu_hw_fini, 2113 .late_fini = smu_late_fini, 2114 .suspend = smu_suspend, 2115 .resume = smu_resume, 2116 .is_idle = NULL, 2117 .check_soft_reset = NULL, 2118 .wait_for_idle = NULL, 2119 .soft_reset = NULL, 2120 .set_clockgating_state = smu_set_clockgating_state, 2121 .set_powergating_state = smu_set_powergating_state, 2122 }; 2123 2124 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2125 { 2126 .type = AMD_IP_BLOCK_TYPE_SMC, 2127 .major = 11, 2128 .minor = 0, 2129 .rev = 0, 2130 .funcs = &smu_ip_funcs, 2131 }; 2132 2133 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2134 { 2135 .type = AMD_IP_BLOCK_TYPE_SMC, 2136 .major = 12, 2137 .minor = 0, 2138 .rev = 0, 2139 .funcs = &smu_ip_funcs, 2140 }; 2141 2142 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2143 { 2144 .type = AMD_IP_BLOCK_TYPE_SMC, 2145 .major = 13, 2146 .minor = 0, 2147 .rev = 0, 2148 .funcs = &smu_ip_funcs, 2149 }; 2150 2151 static int smu_load_microcode(void *handle) 2152 { 2153 struct smu_context *smu = handle; 2154 struct amdgpu_device *adev = smu->adev; 2155 int ret = 0; 2156 2157 if (!smu->pm_enabled) 2158 return -EOPNOTSUPP; 2159 2160 /* This should be used for non PSP loading */ 2161 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2162 return 0; 2163 2164 if (smu->ppt_funcs->load_microcode) { 2165 ret = smu->ppt_funcs->load_microcode(smu); 2166 if (ret) { 2167 dev_err(adev->dev, "Load microcode failed\n"); 2168 return ret; 2169 } 2170 } 2171 2172 if (smu->ppt_funcs->check_fw_status) { 2173 ret = smu->ppt_funcs->check_fw_status(smu); 2174 if (ret) { 2175 dev_err(adev->dev, "SMC is not ready\n"); 2176 return ret; 2177 } 2178 } 2179 2180 return ret; 2181 } 2182 2183 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2184 { 2185 int ret = 0; 2186 2187 if (smu->ppt_funcs->set_gfx_cgpg) 2188 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2189 2190 return ret; 2191 } 2192 2193 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2194 { 2195 struct smu_context *smu = handle; 2196 int ret = 0; 2197 2198 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2199 return -EOPNOTSUPP; 2200 2201 if (!smu->ppt_funcs->set_fan_speed_rpm) 2202 return -EOPNOTSUPP; 2203 2204 if (speed == U32_MAX) 2205 return -EINVAL; 2206 2207 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2208 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2209 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2210 smu->user_dpm_profile.fan_speed_rpm = speed; 2211 2212 /* Override custom PWM setting as they cannot co-exist */ 2213 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2214 smu->user_dpm_profile.fan_speed_pwm = 0; 2215 } 2216 2217 return ret; 2218 } 2219 2220 /** 2221 * smu_get_power_limit - Request one of the SMU Power Limits 2222 * 2223 * @handle: pointer to smu context 2224 * @limit: requested limit is written back to this variable 2225 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2226 * @pp_power_type: &pp_power_type type of power 2227 * Return: 0 on success, <0 on error 2228 * 2229 */ 2230 int smu_get_power_limit(void *handle, 2231 uint32_t *limit, 2232 enum pp_power_limit_level pp_limit_level, 2233 enum pp_power_type pp_power_type) 2234 { 2235 struct smu_context *smu = handle; 2236 struct amdgpu_device *adev = smu->adev; 2237 enum smu_ppt_limit_level limit_level; 2238 uint32_t limit_type; 2239 int ret = 0; 2240 2241 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2242 return -EOPNOTSUPP; 2243 2244 switch(pp_power_type) { 2245 case PP_PWR_TYPE_SUSTAINED: 2246 limit_type = SMU_DEFAULT_PPT_LIMIT; 2247 break; 2248 case PP_PWR_TYPE_FAST: 2249 limit_type = SMU_FAST_PPT_LIMIT; 2250 break; 2251 default: 2252 return -EOPNOTSUPP; 2253 break; 2254 } 2255 2256 switch(pp_limit_level){ 2257 case PP_PWR_LIMIT_CURRENT: 2258 limit_level = SMU_PPT_LIMIT_CURRENT; 2259 break; 2260 case PP_PWR_LIMIT_DEFAULT: 2261 limit_level = SMU_PPT_LIMIT_DEFAULT; 2262 break; 2263 case PP_PWR_LIMIT_MAX: 2264 limit_level = SMU_PPT_LIMIT_MAX; 2265 break; 2266 case PP_PWR_LIMIT_MIN: 2267 default: 2268 return -EOPNOTSUPP; 2269 break; 2270 } 2271 2272 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2273 if (smu->ppt_funcs->get_ppt_limit) 2274 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2275 } else { 2276 switch (limit_level) { 2277 case SMU_PPT_LIMIT_CURRENT: 2278 switch (adev->ip_versions[MP1_HWIP][0]) { 2279 case IP_VERSION(13, 0, 2): 2280 case IP_VERSION(11, 0, 7): 2281 case IP_VERSION(11, 0, 11): 2282 case IP_VERSION(11, 0, 12): 2283 case IP_VERSION(11, 0, 13): 2284 ret = smu_get_asic_power_limits(smu, 2285 &smu->current_power_limit, 2286 NULL, 2287 NULL); 2288 break; 2289 default: 2290 break; 2291 } 2292 *limit = smu->current_power_limit; 2293 break; 2294 case SMU_PPT_LIMIT_DEFAULT: 2295 *limit = smu->default_power_limit; 2296 break; 2297 case SMU_PPT_LIMIT_MAX: 2298 *limit = smu->max_power_limit; 2299 break; 2300 default: 2301 break; 2302 } 2303 } 2304 2305 return ret; 2306 } 2307 2308 static int smu_set_power_limit(void *handle, uint32_t limit) 2309 { 2310 struct smu_context *smu = handle; 2311 uint32_t limit_type = limit >> 24; 2312 int ret = 0; 2313 2314 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2315 return -EOPNOTSUPP; 2316 2317 limit &= (1<<24)-1; 2318 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2319 if (smu->ppt_funcs->set_power_limit) 2320 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2321 2322 if (limit > smu->max_power_limit) { 2323 dev_err(smu->adev->dev, 2324 "New power limit (%d) is over the max allowed %d\n", 2325 limit, smu->max_power_limit); 2326 return -EINVAL; 2327 } 2328 2329 if (!limit) 2330 limit = smu->current_power_limit; 2331 2332 if (smu->ppt_funcs->set_power_limit) { 2333 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2334 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2335 smu->user_dpm_profile.power_limit = limit; 2336 } 2337 2338 return ret; 2339 } 2340 2341 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2342 { 2343 int ret = 0; 2344 2345 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2346 return -EOPNOTSUPP; 2347 2348 if (smu->ppt_funcs->print_clk_levels) 2349 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2350 2351 return ret; 2352 } 2353 2354 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2355 { 2356 enum smu_clk_type clk_type; 2357 2358 switch (type) { 2359 case PP_SCLK: 2360 clk_type = SMU_SCLK; break; 2361 case PP_MCLK: 2362 clk_type = SMU_MCLK; break; 2363 case PP_PCIE: 2364 clk_type = SMU_PCIE; break; 2365 case PP_SOCCLK: 2366 clk_type = SMU_SOCCLK; break; 2367 case PP_FCLK: 2368 clk_type = SMU_FCLK; break; 2369 case PP_DCEFCLK: 2370 clk_type = SMU_DCEFCLK; break; 2371 case PP_VCLK: 2372 clk_type = SMU_VCLK; break; 2373 case PP_DCLK: 2374 clk_type = SMU_DCLK; break; 2375 case OD_SCLK: 2376 clk_type = SMU_OD_SCLK; break; 2377 case OD_MCLK: 2378 clk_type = SMU_OD_MCLK; break; 2379 case OD_VDDC_CURVE: 2380 clk_type = SMU_OD_VDDC_CURVE; break; 2381 case OD_RANGE: 2382 clk_type = SMU_OD_RANGE; break; 2383 case OD_VDDGFX_OFFSET: 2384 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2385 case OD_CCLK: 2386 clk_type = SMU_OD_CCLK; break; 2387 default: 2388 clk_type = SMU_CLK_COUNT; break; 2389 } 2390 2391 return clk_type; 2392 } 2393 2394 static int smu_print_ppclk_levels(void *handle, 2395 enum pp_clock_type type, 2396 char *buf) 2397 { 2398 struct smu_context *smu = handle; 2399 enum smu_clk_type clk_type; 2400 2401 clk_type = smu_convert_to_smuclk(type); 2402 if (clk_type == SMU_CLK_COUNT) 2403 return -EINVAL; 2404 2405 return smu_print_smuclk_levels(smu, clk_type, buf); 2406 } 2407 2408 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2409 { 2410 struct smu_context *smu = handle; 2411 enum smu_clk_type clk_type; 2412 2413 clk_type = smu_convert_to_smuclk(type); 2414 if (clk_type == SMU_CLK_COUNT) 2415 return -EINVAL; 2416 2417 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2418 return -EOPNOTSUPP; 2419 2420 if (!smu->ppt_funcs->emit_clk_levels) 2421 return -ENOENT; 2422 2423 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2424 2425 } 2426 2427 static int smu_od_edit_dpm_table(void *handle, 2428 enum PP_OD_DPM_TABLE_COMMAND type, 2429 long *input, uint32_t size) 2430 { 2431 struct smu_context *smu = handle; 2432 int ret = 0; 2433 2434 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2435 return -EOPNOTSUPP; 2436 2437 if (smu->ppt_funcs->od_edit_dpm_table) { 2438 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2439 } 2440 2441 return ret; 2442 } 2443 2444 static int smu_read_sensor(void *handle, 2445 int sensor, 2446 void *data, 2447 int *size_arg) 2448 { 2449 struct smu_context *smu = handle; 2450 struct smu_umd_pstate_table *pstate_table = 2451 &smu->pstate_table; 2452 int ret = 0; 2453 uint32_t *size, size_val; 2454 2455 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2456 return -EOPNOTSUPP; 2457 2458 if (!data || !size_arg) 2459 return -EINVAL; 2460 2461 size_val = *size_arg; 2462 size = &size_val; 2463 2464 if (smu->ppt_funcs->read_sensor) 2465 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2466 goto unlock; 2467 2468 switch (sensor) { 2469 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2470 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2471 *size = 4; 2472 break; 2473 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2474 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2475 *size = 4; 2476 break; 2477 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2478 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2479 *size = 8; 2480 break; 2481 case AMDGPU_PP_SENSOR_UVD_POWER: 2482 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2483 *size = 4; 2484 break; 2485 case AMDGPU_PP_SENSOR_VCE_POWER: 2486 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2487 *size = 4; 2488 break; 2489 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2490 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2491 *size = 4; 2492 break; 2493 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2494 *(uint32_t *)data = 0; 2495 *size = 4; 2496 break; 2497 default: 2498 *size = 0; 2499 ret = -EOPNOTSUPP; 2500 break; 2501 } 2502 2503 unlock: 2504 // assign uint32_t to int 2505 *size_arg = size_val; 2506 2507 return ret; 2508 } 2509 2510 static int smu_get_power_profile_mode(void *handle, char *buf) 2511 { 2512 struct smu_context *smu = handle; 2513 2514 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2515 !smu->ppt_funcs->get_power_profile_mode) 2516 return -EOPNOTSUPP; 2517 if (!buf) 2518 return -EINVAL; 2519 2520 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2521 } 2522 2523 static int smu_set_power_profile_mode(void *handle, 2524 long *param, 2525 uint32_t param_size) 2526 { 2527 struct smu_context *smu = handle; 2528 2529 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2530 !smu->ppt_funcs->set_power_profile_mode) 2531 return -EOPNOTSUPP; 2532 2533 return smu_bump_power_profile_mode(smu, param, param_size); 2534 } 2535 2536 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2537 { 2538 struct smu_context *smu = handle; 2539 2540 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2541 return -EOPNOTSUPP; 2542 2543 if (!smu->ppt_funcs->get_fan_control_mode) 2544 return -EOPNOTSUPP; 2545 2546 if (!fan_mode) 2547 return -EINVAL; 2548 2549 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 2550 2551 return 0; 2552 } 2553 2554 static int smu_set_fan_control_mode(void *handle, u32 value) 2555 { 2556 struct smu_context *smu = handle; 2557 int ret = 0; 2558 2559 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2560 return -EOPNOTSUPP; 2561 2562 if (!smu->ppt_funcs->set_fan_control_mode) 2563 return -EOPNOTSUPP; 2564 2565 if (value == U32_MAX) 2566 return -EINVAL; 2567 2568 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2569 if (ret) 2570 goto out; 2571 2572 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2573 smu->user_dpm_profile.fan_mode = value; 2574 2575 /* reset user dpm fan speed */ 2576 if (value != AMD_FAN_CTRL_MANUAL) { 2577 smu->user_dpm_profile.fan_speed_pwm = 0; 2578 smu->user_dpm_profile.fan_speed_rpm = 0; 2579 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2580 } 2581 } 2582 2583 out: 2584 return ret; 2585 } 2586 2587 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2588 { 2589 struct smu_context *smu = handle; 2590 int ret = 0; 2591 2592 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2593 return -EOPNOTSUPP; 2594 2595 if (!smu->ppt_funcs->get_fan_speed_pwm) 2596 return -EOPNOTSUPP; 2597 2598 if (!speed) 2599 return -EINVAL; 2600 2601 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2602 2603 return ret; 2604 } 2605 2606 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2607 { 2608 struct smu_context *smu = handle; 2609 int ret = 0; 2610 2611 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2612 return -EOPNOTSUPP; 2613 2614 if (!smu->ppt_funcs->set_fan_speed_pwm) 2615 return -EOPNOTSUPP; 2616 2617 if (speed == U32_MAX) 2618 return -EINVAL; 2619 2620 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2621 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2622 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2623 smu->user_dpm_profile.fan_speed_pwm = speed; 2624 2625 /* Override custom RPM setting as they cannot co-exist */ 2626 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2627 smu->user_dpm_profile.fan_speed_rpm = 0; 2628 } 2629 2630 return ret; 2631 } 2632 2633 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2634 { 2635 struct smu_context *smu = handle; 2636 int ret = 0; 2637 2638 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2639 return -EOPNOTSUPP; 2640 2641 if (!smu->ppt_funcs->get_fan_speed_rpm) 2642 return -EOPNOTSUPP; 2643 2644 if (!speed) 2645 return -EINVAL; 2646 2647 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2648 2649 return ret; 2650 } 2651 2652 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2653 { 2654 struct smu_context *smu = handle; 2655 2656 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2657 return -EOPNOTSUPP; 2658 2659 return smu_set_min_dcef_deep_sleep(smu, clk); 2660 } 2661 2662 static int smu_get_clock_by_type_with_latency(void *handle, 2663 enum amd_pp_clock_type type, 2664 struct pp_clock_levels_with_latency *clocks) 2665 { 2666 struct smu_context *smu = handle; 2667 enum smu_clk_type clk_type; 2668 int ret = 0; 2669 2670 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2671 return -EOPNOTSUPP; 2672 2673 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2674 switch (type) { 2675 case amd_pp_sys_clock: 2676 clk_type = SMU_GFXCLK; 2677 break; 2678 case amd_pp_mem_clock: 2679 clk_type = SMU_MCLK; 2680 break; 2681 case amd_pp_dcef_clock: 2682 clk_type = SMU_DCEFCLK; 2683 break; 2684 case amd_pp_disp_clock: 2685 clk_type = SMU_DISPCLK; 2686 break; 2687 default: 2688 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2689 return -EINVAL; 2690 } 2691 2692 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2693 } 2694 2695 return ret; 2696 } 2697 2698 static int smu_display_clock_voltage_request(void *handle, 2699 struct pp_display_clock_request *clock_req) 2700 { 2701 struct smu_context *smu = handle; 2702 int ret = 0; 2703 2704 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2705 return -EOPNOTSUPP; 2706 2707 if (smu->ppt_funcs->display_clock_voltage_request) 2708 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2709 2710 return ret; 2711 } 2712 2713 2714 static int smu_display_disable_memory_clock_switch(void *handle, 2715 bool disable_memory_clock_switch) 2716 { 2717 struct smu_context *smu = handle; 2718 int ret = -EINVAL; 2719 2720 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2721 return -EOPNOTSUPP; 2722 2723 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2724 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2725 2726 return ret; 2727 } 2728 2729 static int smu_set_xgmi_pstate(void *handle, 2730 uint32_t pstate) 2731 { 2732 struct smu_context *smu = handle; 2733 int ret = 0; 2734 2735 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2736 return -EOPNOTSUPP; 2737 2738 if (smu->ppt_funcs->set_xgmi_pstate) 2739 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2740 2741 if(ret) 2742 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2743 2744 return ret; 2745 } 2746 2747 static int smu_get_baco_capability(void *handle, bool *cap) 2748 { 2749 struct smu_context *smu = handle; 2750 2751 *cap = false; 2752 2753 if (!smu->pm_enabled) 2754 return 0; 2755 2756 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2757 *cap = smu->ppt_funcs->baco_is_support(smu); 2758 2759 return 0; 2760 } 2761 2762 static int smu_baco_set_state(void *handle, int state) 2763 { 2764 struct smu_context *smu = handle; 2765 int ret = 0; 2766 2767 if (!smu->pm_enabled) 2768 return -EOPNOTSUPP; 2769 2770 if (state == 0) { 2771 if (smu->ppt_funcs->baco_exit) 2772 ret = smu->ppt_funcs->baco_exit(smu); 2773 } else if (state == 1) { 2774 if (smu->ppt_funcs->baco_enter) 2775 ret = smu->ppt_funcs->baco_enter(smu); 2776 } else { 2777 return -EINVAL; 2778 } 2779 2780 if (ret) 2781 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2782 (state)?"enter":"exit"); 2783 2784 return ret; 2785 } 2786 2787 bool smu_mode1_reset_is_support(struct smu_context *smu) 2788 { 2789 bool ret = false; 2790 2791 if (!smu->pm_enabled) 2792 return false; 2793 2794 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2795 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2796 2797 return ret; 2798 } 2799 2800 bool smu_mode2_reset_is_support(struct smu_context *smu) 2801 { 2802 bool ret = false; 2803 2804 if (!smu->pm_enabled) 2805 return false; 2806 2807 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2808 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2809 2810 return ret; 2811 } 2812 2813 int smu_mode1_reset(struct smu_context *smu) 2814 { 2815 int ret = 0; 2816 2817 if (!smu->pm_enabled) 2818 return -EOPNOTSUPP; 2819 2820 if (smu->ppt_funcs->mode1_reset) 2821 ret = smu->ppt_funcs->mode1_reset(smu); 2822 2823 return ret; 2824 } 2825 2826 static int smu_mode2_reset(void *handle) 2827 { 2828 struct smu_context *smu = handle; 2829 int ret = 0; 2830 2831 if (!smu->pm_enabled) 2832 return -EOPNOTSUPP; 2833 2834 if (smu->ppt_funcs->mode2_reset) 2835 ret = smu->ppt_funcs->mode2_reset(smu); 2836 2837 if (ret) 2838 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2839 2840 return ret; 2841 } 2842 2843 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2844 struct pp_smu_nv_clock_table *max_clocks) 2845 { 2846 struct smu_context *smu = handle; 2847 int ret = 0; 2848 2849 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2850 return -EOPNOTSUPP; 2851 2852 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2853 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2854 2855 return ret; 2856 } 2857 2858 static int smu_get_uclk_dpm_states(void *handle, 2859 unsigned int *clock_values_in_khz, 2860 unsigned int *num_states) 2861 { 2862 struct smu_context *smu = handle; 2863 int ret = 0; 2864 2865 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2866 return -EOPNOTSUPP; 2867 2868 if (smu->ppt_funcs->get_uclk_dpm_states) 2869 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2870 2871 return ret; 2872 } 2873 2874 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2875 { 2876 struct smu_context *smu = handle; 2877 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2878 2879 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2880 return -EOPNOTSUPP; 2881 2882 if (smu->ppt_funcs->get_current_power_state) 2883 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2884 2885 return pm_state; 2886 } 2887 2888 static int smu_get_dpm_clock_table(void *handle, 2889 struct dpm_clocks *clock_table) 2890 { 2891 struct smu_context *smu = handle; 2892 int ret = 0; 2893 2894 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2895 return -EOPNOTSUPP; 2896 2897 if (smu->ppt_funcs->get_dpm_clock_table) 2898 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2899 2900 return ret; 2901 } 2902 2903 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2904 { 2905 struct smu_context *smu = handle; 2906 2907 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2908 return -EOPNOTSUPP; 2909 2910 if (!smu->ppt_funcs->get_gpu_metrics) 2911 return -EOPNOTSUPP; 2912 2913 return smu->ppt_funcs->get_gpu_metrics(smu, table); 2914 } 2915 2916 static int smu_enable_mgpu_fan_boost(void *handle) 2917 { 2918 struct smu_context *smu = handle; 2919 int ret = 0; 2920 2921 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2922 return -EOPNOTSUPP; 2923 2924 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2925 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2926 2927 return ret; 2928 } 2929 2930 static int smu_gfx_state_change_set(void *handle, 2931 uint32_t state) 2932 { 2933 struct smu_context *smu = handle; 2934 int ret = 0; 2935 2936 if (smu->ppt_funcs->gfx_state_change_set) 2937 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2938 2939 return ret; 2940 } 2941 2942 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 2943 { 2944 int ret = 0; 2945 2946 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 2947 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 2948 2949 return ret; 2950 } 2951 2952 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 2953 { 2954 int ret = -EOPNOTSUPP; 2955 2956 if (smu->ppt_funcs && 2957 smu->ppt_funcs->get_ecc_info) 2958 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 2959 2960 return ret; 2961 2962 } 2963 2964 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 2965 { 2966 struct smu_context *smu = handle; 2967 struct smu_table_context *smu_table = &smu->smu_table; 2968 struct smu_table *memory_pool = &smu_table->memory_pool; 2969 2970 if (!addr || !size) 2971 return -EINVAL; 2972 2973 *addr = NULL; 2974 *size = 0; 2975 if (memory_pool->bo) { 2976 *addr = memory_pool->cpu_addr; 2977 *size = memory_pool->size; 2978 } 2979 2980 return 0; 2981 } 2982 2983 static const struct amd_pm_funcs swsmu_pm_funcs = { 2984 /* export for sysfs */ 2985 .set_fan_control_mode = smu_set_fan_control_mode, 2986 .get_fan_control_mode = smu_get_fan_control_mode, 2987 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 2988 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 2989 .force_clock_level = smu_force_ppclk_levels, 2990 .print_clock_levels = smu_print_ppclk_levels, 2991 .emit_clock_levels = smu_emit_ppclk_levels, 2992 .force_performance_level = smu_force_performance_level, 2993 .read_sensor = smu_read_sensor, 2994 .get_performance_level = smu_get_performance_level, 2995 .get_current_power_state = smu_get_current_power_state, 2996 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 2997 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 2998 .get_pp_num_states = smu_get_power_num_states, 2999 .get_pp_table = smu_sys_get_pp_table, 3000 .set_pp_table = smu_sys_set_pp_table, 3001 .switch_power_profile = smu_switch_power_profile, 3002 /* export to amdgpu */ 3003 .dispatch_tasks = smu_handle_dpm_task, 3004 .load_firmware = smu_load_microcode, 3005 .set_powergating_by_smu = smu_dpm_set_power_gate, 3006 .set_power_limit = smu_set_power_limit, 3007 .get_power_limit = smu_get_power_limit, 3008 .get_power_profile_mode = smu_get_power_profile_mode, 3009 .set_power_profile_mode = smu_set_power_profile_mode, 3010 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3011 .set_mp1_state = smu_set_mp1_state, 3012 .gfx_state_change_set = smu_gfx_state_change_set, 3013 /* export to DC */ 3014 .get_sclk = smu_get_sclk, 3015 .get_mclk = smu_get_mclk, 3016 .display_configuration_change = smu_display_configuration_change, 3017 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3018 .display_clock_voltage_request = smu_display_clock_voltage_request, 3019 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3020 .set_active_display_count = smu_set_display_count, 3021 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3022 .get_asic_baco_capability = smu_get_baco_capability, 3023 .set_asic_baco_state = smu_baco_set_state, 3024 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3025 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3026 .asic_reset_mode_2 = smu_mode2_reset, 3027 .set_df_cstate = smu_set_df_cstate, 3028 .set_xgmi_pstate = smu_set_xgmi_pstate, 3029 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3030 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3031 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3032 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3033 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3034 .get_dpm_clock_table = smu_get_dpm_clock_table, 3035 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3036 }; 3037 3038 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3039 uint64_t event_arg) 3040 { 3041 int ret = -EINVAL; 3042 3043 if (smu->ppt_funcs->wait_for_event) 3044 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3045 3046 return ret; 3047 } 3048 3049 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3050 { 3051 3052 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3053 return -EOPNOTSUPP; 3054 3055 /* Confirm the buffer allocated is of correct size */ 3056 if (size != smu->stb_context.stb_buf_size) 3057 return -EINVAL; 3058 3059 /* 3060 * No need to lock smu mutex as we access STB directly through MMIO 3061 * and not going through SMU messaging route (for now at least). 3062 * For registers access rely on implementation internal locking. 3063 */ 3064 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3065 } 3066 3067 #if defined(CONFIG_DEBUG_FS) 3068 3069 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3070 { 3071 struct amdgpu_device *adev = filp->f_inode->i_private; 3072 struct smu_context *smu = adev->powerplay.pp_handle; 3073 unsigned char *buf; 3074 int r; 3075 3076 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3077 if (!buf) 3078 return -ENOMEM; 3079 3080 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3081 if (r) 3082 goto out; 3083 3084 filp->private_data = buf; 3085 3086 return 0; 3087 3088 out: 3089 kvfree(buf); 3090 return r; 3091 } 3092 3093 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3094 loff_t *pos) 3095 { 3096 struct amdgpu_device *adev = filp->f_inode->i_private; 3097 struct smu_context *smu = adev->powerplay.pp_handle; 3098 3099 3100 if (!filp->private_data) 3101 return -EINVAL; 3102 3103 return simple_read_from_buffer(buf, 3104 size, 3105 pos, filp->private_data, 3106 smu->stb_context.stb_buf_size); 3107 } 3108 3109 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3110 { 3111 kvfree(filp->private_data); 3112 filp->private_data = NULL; 3113 3114 return 0; 3115 } 3116 3117 /* 3118 * We have to define not only read method but also 3119 * open and release because .read takes up to PAGE_SIZE 3120 * data each time so and so is invoked multiple times. 3121 * We allocate the STB buffer in .open and release it 3122 * in .release 3123 */ 3124 static const struct file_operations smu_stb_debugfs_fops = { 3125 .owner = THIS_MODULE, 3126 .open = smu_stb_debugfs_open, 3127 .read = smu_stb_debugfs_read, 3128 .release = smu_stb_debugfs_release, 3129 .llseek = default_llseek, 3130 }; 3131 3132 #endif 3133 3134 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3135 { 3136 #if defined(CONFIG_DEBUG_FS) 3137 3138 struct smu_context *smu = adev->powerplay.pp_handle; 3139 3140 if (!smu || (!smu->stb_context.stb_buf_size)) 3141 return; 3142 3143 debugfs_create_file_size("amdgpu_smu_stb_dump", 3144 S_IRUSR, 3145 adev_to_drm(adev)->primary->debugfs_root, 3146 adev, 3147 &smu_stb_debugfs_fops, 3148 smu->stb_context.stb_buf_size); 3149 #endif 3150 } 3151 3152 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3153 { 3154 int ret = 0; 3155 3156 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3157 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3158 3159 return ret; 3160 } 3161 3162 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3163 { 3164 int ret = 0; 3165 3166 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3167 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3168 3169 return ret; 3170 } 3171