1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "smu_v13_0_0_ppt.h" 41 #include "smu_v13_0_4_ppt.h" 42 #include "smu_v13_0_5_ppt.h" 43 #include "smu_v13_0_6_ppt.h" 44 #include "smu_v13_0_7_ppt.h" 45 #include "amd_pcie.h" 46 47 /* 48 * DO NOT use these for err/warn/info/debug messages. 49 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 50 * They are more MGPU friendly. 51 */ 52 #undef pr_err 53 #undef pr_warn 54 #undef pr_info 55 #undef pr_debug 56 57 static const struct amd_pm_funcs swsmu_pm_funcs; 58 static int smu_force_smuclk_levels(struct smu_context *smu, 59 enum smu_clk_type clk_type, 60 uint32_t mask); 61 static int smu_handle_task(struct smu_context *smu, 62 enum amd_dpm_forced_level level, 63 enum amd_pp_task task_id); 64 static int smu_reset(struct smu_context *smu); 65 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 66 static int smu_set_fan_control_mode(void *handle, u32 value); 67 static int smu_set_power_limit(void *handle, uint32_t limit); 68 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 69 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 70 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 71 72 static int smu_sys_get_pp_feature_mask(void *handle, 73 char *buf) 74 { 75 struct smu_context *smu = handle; 76 77 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 78 return -EOPNOTSUPP; 79 80 return smu_get_pp_feature_mask(smu, buf); 81 } 82 83 static int smu_sys_set_pp_feature_mask(void *handle, 84 uint64_t new_mask) 85 { 86 struct smu_context *smu = handle; 87 88 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 89 return -EOPNOTSUPP; 90 91 return smu_set_pp_feature_mask(smu, new_mask); 92 } 93 94 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 95 { 96 if (!smu->ppt_funcs->set_gfx_off_residency) 97 return -EINVAL; 98 99 return smu_set_gfx_off_residency(smu, value); 100 } 101 102 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 103 { 104 if (!smu->ppt_funcs->get_gfx_off_residency) 105 return -EINVAL; 106 107 return smu_get_gfx_off_residency(smu, value); 108 } 109 110 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 111 { 112 if (!smu->ppt_funcs->get_gfx_off_entrycount) 113 return -EINVAL; 114 115 return smu_get_gfx_off_entrycount(smu, value); 116 } 117 118 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 119 { 120 if (!smu->ppt_funcs->get_gfx_off_status) 121 return -EINVAL; 122 123 *value = smu_get_gfx_off_status(smu); 124 125 return 0; 126 } 127 128 int smu_set_soft_freq_range(struct smu_context *smu, 129 enum smu_clk_type clk_type, 130 uint32_t min, 131 uint32_t max) 132 { 133 int ret = 0; 134 135 if (smu->ppt_funcs->set_soft_freq_limited_range) 136 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 137 clk_type, 138 min, 139 max); 140 141 return ret; 142 } 143 144 int smu_get_dpm_freq_range(struct smu_context *smu, 145 enum smu_clk_type clk_type, 146 uint32_t *min, 147 uint32_t *max) 148 { 149 int ret = -ENOTSUPP; 150 151 if (!min && !max) 152 return -EINVAL; 153 154 if (smu->ppt_funcs->get_dpm_ultimate_freq) 155 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 156 clk_type, 157 min, 158 max); 159 160 return ret; 161 } 162 163 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 164 { 165 int ret = 0; 166 struct amdgpu_device *adev = smu->adev; 167 168 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 169 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 170 if (ret) 171 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 172 } 173 return ret; 174 } 175 176 static u32 smu_get_mclk(void *handle, bool low) 177 { 178 struct smu_context *smu = handle; 179 uint32_t clk_freq; 180 int ret = 0; 181 182 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 183 low ? &clk_freq : NULL, 184 !low ? &clk_freq : NULL); 185 if (ret) 186 return 0; 187 return clk_freq * 100; 188 } 189 190 static u32 smu_get_sclk(void *handle, bool low) 191 { 192 struct smu_context *smu = handle; 193 uint32_t clk_freq; 194 int ret = 0; 195 196 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 197 low ? &clk_freq : NULL, 198 !low ? &clk_freq : NULL); 199 if (ret) 200 return 0; 201 return clk_freq * 100; 202 } 203 204 static int smu_set_gfx_imu_enable(struct smu_context *smu) 205 { 206 struct amdgpu_device *adev = smu->adev; 207 208 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 209 return 0; 210 211 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 212 return 0; 213 214 return smu_set_gfx_power_up_by_imu(smu); 215 } 216 217 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 218 bool enable) 219 { 220 struct smu_power_context *smu_power = &smu->smu_power; 221 struct smu_power_gate *power_gate = &smu_power->power_gate; 222 int ret = 0; 223 224 if (!smu->ppt_funcs->dpm_set_vcn_enable) 225 return 0; 226 227 if (atomic_read(&power_gate->vcn_gated) ^ enable) 228 return 0; 229 230 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 231 if (!ret) 232 atomic_set(&power_gate->vcn_gated, !enable); 233 234 return ret; 235 } 236 237 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 238 bool enable) 239 { 240 struct smu_power_context *smu_power = &smu->smu_power; 241 struct smu_power_gate *power_gate = &smu_power->power_gate; 242 int ret = 0; 243 244 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 245 return 0; 246 247 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 248 return 0; 249 250 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 251 if (!ret) 252 atomic_set(&power_gate->jpeg_gated, !enable); 253 254 return ret; 255 } 256 257 /** 258 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 259 * 260 * @handle: smu_context pointer 261 * @block_type: the IP block to power gate/ungate 262 * @gate: to power gate if true, ungate otherwise 263 * 264 * This API uses no smu->mutex lock protection due to: 265 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 266 * This is guarded to be race condition free by the caller. 267 * 2. Or get called on user setting request of power_dpm_force_performance_level. 268 * Under this case, the smu->mutex lock protection is already enforced on 269 * the parent API smu_force_performance_level of the call path. 270 */ 271 static int smu_dpm_set_power_gate(void *handle, 272 uint32_t block_type, 273 bool gate) 274 { 275 struct smu_context *smu = handle; 276 int ret = 0; 277 278 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 279 dev_WARN(smu->adev->dev, 280 "SMU uninitialized but power %s requested for %u!\n", 281 gate ? "gate" : "ungate", block_type); 282 return -EOPNOTSUPP; 283 } 284 285 switch (block_type) { 286 /* 287 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 288 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 289 */ 290 case AMD_IP_BLOCK_TYPE_UVD: 291 case AMD_IP_BLOCK_TYPE_VCN: 292 ret = smu_dpm_set_vcn_enable(smu, !gate); 293 if (ret) 294 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 295 gate ? "gate" : "ungate"); 296 break; 297 case AMD_IP_BLOCK_TYPE_GFX: 298 ret = smu_gfx_off_control(smu, gate); 299 if (ret) 300 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 301 gate ? "enable" : "disable"); 302 break; 303 case AMD_IP_BLOCK_TYPE_SDMA: 304 ret = smu_powergate_sdma(smu, gate); 305 if (ret) 306 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 307 gate ? "gate" : "ungate"); 308 break; 309 case AMD_IP_BLOCK_TYPE_JPEG: 310 ret = smu_dpm_set_jpeg_enable(smu, !gate); 311 if (ret) 312 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 313 gate ? "gate" : "ungate"); 314 break; 315 default: 316 dev_err(smu->adev->dev, "Unsupported block type!\n"); 317 return -EINVAL; 318 } 319 320 return ret; 321 } 322 323 /** 324 * smu_set_user_clk_dependencies - set user profile clock dependencies 325 * 326 * @smu: smu_context pointer 327 * @clk: enum smu_clk_type type 328 * 329 * Enable/Disable the clock dependency for the @clk type. 330 */ 331 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 332 { 333 if (smu->adev->in_suspend) 334 return; 335 336 if (clk == SMU_MCLK) { 337 smu->user_dpm_profile.clk_dependency = 0; 338 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 339 } else if (clk == SMU_FCLK) { 340 /* MCLK takes precedence over FCLK */ 341 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 342 return; 343 344 smu->user_dpm_profile.clk_dependency = 0; 345 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 346 } else if (clk == SMU_SOCCLK) { 347 /* MCLK takes precedence over SOCCLK */ 348 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 349 return; 350 351 smu->user_dpm_profile.clk_dependency = 0; 352 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 353 } else 354 /* Add clk dependencies here, if any */ 355 return; 356 } 357 358 /** 359 * smu_restore_dpm_user_profile - reinstate user dpm profile 360 * 361 * @smu: smu_context pointer 362 * 363 * Restore the saved user power configurations include power limit, 364 * clock frequencies, fan control mode and fan speed. 365 */ 366 static void smu_restore_dpm_user_profile(struct smu_context *smu) 367 { 368 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 369 int ret = 0; 370 371 if (!smu->adev->in_suspend) 372 return; 373 374 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 375 return; 376 377 /* Enable restore flag */ 378 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 379 380 /* set the user dpm power limit */ 381 if (smu->user_dpm_profile.power_limit) { 382 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 383 if (ret) 384 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 385 } 386 387 /* set the user dpm clock configurations */ 388 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 389 enum smu_clk_type clk_type; 390 391 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 392 /* 393 * Iterate over smu clk type and force the saved user clk 394 * configs, skip if clock dependency is enabled 395 */ 396 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 397 smu->user_dpm_profile.clk_mask[clk_type]) { 398 ret = smu_force_smuclk_levels(smu, clk_type, 399 smu->user_dpm_profile.clk_mask[clk_type]); 400 if (ret) 401 dev_err(smu->adev->dev, 402 "Failed to set clock type = %d\n", clk_type); 403 } 404 } 405 } 406 407 /* set the user dpm fan configurations */ 408 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 409 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 410 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 411 if (ret != -EOPNOTSUPP) { 412 smu->user_dpm_profile.fan_speed_pwm = 0; 413 smu->user_dpm_profile.fan_speed_rpm = 0; 414 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 415 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 416 } 417 418 if (smu->user_dpm_profile.fan_speed_pwm) { 419 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 420 if (ret != -EOPNOTSUPP) 421 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 422 } 423 424 if (smu->user_dpm_profile.fan_speed_rpm) { 425 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 426 if (ret != -EOPNOTSUPP) 427 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 428 } 429 } 430 431 /* Restore user customized OD settings */ 432 if (smu->user_dpm_profile.user_od) { 433 if (smu->ppt_funcs->restore_user_od_settings) { 434 ret = smu->ppt_funcs->restore_user_od_settings(smu); 435 if (ret) 436 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 437 } 438 } 439 440 /* Disable restore flag */ 441 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 442 } 443 444 static int smu_get_power_num_states(void *handle, 445 struct pp_states_info *state_info) 446 { 447 if (!state_info) 448 return -EINVAL; 449 450 /* not support power state */ 451 memset(state_info, 0, sizeof(struct pp_states_info)); 452 state_info->nums = 1; 453 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 454 455 return 0; 456 } 457 458 bool is_support_sw_smu(struct amdgpu_device *adev) 459 { 460 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 461 if (adev->asic_type == CHIP_VEGA20) 462 return false; 463 464 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 465 return true; 466 467 return false; 468 } 469 470 bool is_support_cclk_dpm(struct amdgpu_device *adev) 471 { 472 struct smu_context *smu = adev->powerplay.pp_handle; 473 474 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 475 return false; 476 477 return true; 478 } 479 480 481 static int smu_sys_get_pp_table(void *handle, 482 char **table) 483 { 484 struct smu_context *smu = handle; 485 struct smu_table_context *smu_table = &smu->smu_table; 486 487 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 488 return -EOPNOTSUPP; 489 490 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 491 return -EINVAL; 492 493 if (smu_table->hardcode_pptable) 494 *table = smu_table->hardcode_pptable; 495 else 496 *table = smu_table->power_play_table; 497 498 return smu_table->power_play_table_size; 499 } 500 501 static int smu_sys_set_pp_table(void *handle, 502 const char *buf, 503 size_t size) 504 { 505 struct smu_context *smu = handle; 506 struct smu_table_context *smu_table = &smu->smu_table; 507 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 508 int ret = 0; 509 510 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 511 return -EOPNOTSUPP; 512 513 if (header->usStructureSize != size) { 514 dev_err(smu->adev->dev, "pp table size not matched !\n"); 515 return -EIO; 516 } 517 518 if (!smu_table->hardcode_pptable) { 519 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 520 if (!smu_table->hardcode_pptable) 521 return -ENOMEM; 522 } 523 524 memcpy(smu_table->hardcode_pptable, buf, size); 525 smu_table->power_play_table = smu_table->hardcode_pptable; 526 smu_table->power_play_table_size = size; 527 528 /* 529 * Special hw_fini action(for Navi1x, the DPMs disablement will be 530 * skipped) may be needed for custom pptable uploading. 531 */ 532 smu->uploading_custom_pp_table = true; 533 534 ret = smu_reset(smu); 535 if (ret) 536 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 537 538 smu->uploading_custom_pp_table = false; 539 540 return ret; 541 } 542 543 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 544 { 545 struct smu_feature *feature = &smu->smu_feature; 546 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 547 int ret = 0; 548 549 /* 550 * With SCPM enabled, the allowed featuremasks setting(via 551 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 552 * That means there is no way to let PMFW knows the settings below. 553 * Thus, we just assume all the features are allowed under 554 * such scenario. 555 */ 556 if (smu->adev->scpm_enabled) { 557 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 558 return 0; 559 } 560 561 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 562 563 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 564 SMU_FEATURE_MAX/32); 565 if (ret) 566 return ret; 567 568 bitmap_or(feature->allowed, feature->allowed, 569 (unsigned long *)allowed_feature_mask, 570 feature->feature_num); 571 572 return ret; 573 } 574 575 static int smu_set_funcs(struct amdgpu_device *adev) 576 { 577 struct smu_context *smu = adev->powerplay.pp_handle; 578 579 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 580 smu->od_enabled = true; 581 582 switch (adev->ip_versions[MP1_HWIP][0]) { 583 case IP_VERSION(11, 0, 0): 584 case IP_VERSION(11, 0, 5): 585 case IP_VERSION(11, 0, 9): 586 navi10_set_ppt_funcs(smu); 587 break; 588 case IP_VERSION(11, 0, 7): 589 case IP_VERSION(11, 0, 11): 590 case IP_VERSION(11, 0, 12): 591 case IP_VERSION(11, 0, 13): 592 sienna_cichlid_set_ppt_funcs(smu); 593 break; 594 case IP_VERSION(12, 0, 0): 595 case IP_VERSION(12, 0, 1): 596 renoir_set_ppt_funcs(smu); 597 break; 598 case IP_VERSION(11, 5, 0): 599 vangogh_set_ppt_funcs(smu); 600 break; 601 case IP_VERSION(13, 0, 1): 602 case IP_VERSION(13, 0, 3): 603 case IP_VERSION(13, 0, 8): 604 yellow_carp_set_ppt_funcs(smu); 605 break; 606 case IP_VERSION(13, 0, 4): 607 case IP_VERSION(13, 0, 11): 608 smu_v13_0_4_set_ppt_funcs(smu); 609 break; 610 case IP_VERSION(13, 0, 5): 611 smu_v13_0_5_set_ppt_funcs(smu); 612 break; 613 case IP_VERSION(11, 0, 8): 614 cyan_skillfish_set_ppt_funcs(smu); 615 break; 616 case IP_VERSION(11, 0, 2): 617 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 618 arcturus_set_ppt_funcs(smu); 619 /* OD is not supported on Arcturus */ 620 smu->od_enabled =false; 621 break; 622 case IP_VERSION(13, 0, 2): 623 aldebaran_set_ppt_funcs(smu); 624 /* Enable pp_od_clk_voltage node */ 625 smu->od_enabled = true; 626 break; 627 case IP_VERSION(13, 0, 0): 628 case IP_VERSION(13, 0, 10): 629 smu_v13_0_0_set_ppt_funcs(smu); 630 break; 631 case IP_VERSION(13, 0, 6): 632 smu_v13_0_6_set_ppt_funcs(smu); 633 /* Enable pp_od_clk_voltage node */ 634 smu->od_enabled = true; 635 break; 636 case IP_VERSION(13, 0, 7): 637 smu_v13_0_7_set_ppt_funcs(smu); 638 break; 639 default: 640 return -EINVAL; 641 } 642 643 return 0; 644 } 645 646 static int smu_early_init(void *handle) 647 { 648 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 649 struct smu_context *smu; 650 int r; 651 652 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 653 if (!smu) 654 return -ENOMEM; 655 656 smu->adev = adev; 657 smu->pm_enabled = !!amdgpu_dpm; 658 smu->is_apu = false; 659 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 660 smu->smu_baco.platform_support = false; 661 smu->user_dpm_profile.fan_mode = -1; 662 663 mutex_init(&smu->message_lock); 664 665 adev->powerplay.pp_handle = smu; 666 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 667 668 r = smu_set_funcs(adev); 669 if (r) 670 return r; 671 return smu_init_microcode(smu); 672 } 673 674 static int smu_set_default_dpm_table(struct smu_context *smu) 675 { 676 struct smu_power_context *smu_power = &smu->smu_power; 677 struct smu_power_gate *power_gate = &smu_power->power_gate; 678 int vcn_gate, jpeg_gate; 679 int ret = 0; 680 681 if (!smu->ppt_funcs->set_default_dpm_table) 682 return 0; 683 684 vcn_gate = atomic_read(&power_gate->vcn_gated); 685 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 686 687 ret = smu_dpm_set_vcn_enable(smu, true); 688 if (ret) 689 return ret; 690 691 ret = smu_dpm_set_jpeg_enable(smu, true); 692 if (ret) 693 goto err_out; 694 695 ret = smu->ppt_funcs->set_default_dpm_table(smu); 696 if (ret) 697 dev_err(smu->adev->dev, 698 "Failed to setup default dpm clock tables!\n"); 699 700 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 701 err_out: 702 smu_dpm_set_vcn_enable(smu, !vcn_gate); 703 return ret; 704 } 705 706 static int smu_apply_default_config_table_settings(struct smu_context *smu) 707 { 708 struct amdgpu_device *adev = smu->adev; 709 int ret = 0; 710 711 ret = smu_get_default_config_table_settings(smu, 712 &adev->pm.config_table); 713 if (ret) 714 return ret; 715 716 return smu_set_config_table(smu, &adev->pm.config_table); 717 } 718 719 static int smu_late_init(void *handle) 720 { 721 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 722 struct smu_context *smu = adev->powerplay.pp_handle; 723 int ret = 0; 724 725 smu_set_fine_grain_gfx_freq_parameters(smu); 726 727 if (!smu->pm_enabled) 728 return 0; 729 730 ret = smu_post_init(smu); 731 if (ret) { 732 dev_err(adev->dev, "Failed to post smu init!\n"); 733 return ret; 734 } 735 736 /* 737 * Explicitly notify PMFW the power mode the system in. Since 738 * the PMFW may boot the ASIC with a different mode. 739 * For those supporting ACDC switch via gpio, PMFW will 740 * handle the switch automatically. Driver involvement 741 * is unnecessary. 742 */ 743 if (!smu->dc_controlled_by_gpio) { 744 ret = smu_set_power_source(smu, 745 adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 746 SMU_POWER_SOURCE_DC); 747 if (ret) { 748 dev_err(adev->dev, "Failed to switch to %s mode!\n", 749 adev->pm.ac_power ? "AC" : "DC"); 750 return ret; 751 } 752 } 753 754 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 755 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 756 return 0; 757 758 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 759 ret = smu_set_default_od_settings(smu); 760 if (ret) { 761 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 762 return ret; 763 } 764 } 765 766 ret = smu_populate_umd_state_clk(smu); 767 if (ret) { 768 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 769 return ret; 770 } 771 772 ret = smu_get_asic_power_limits(smu, 773 &smu->current_power_limit, 774 &smu->default_power_limit, 775 &smu->max_power_limit); 776 if (ret) { 777 dev_err(adev->dev, "Failed to get asic power limits!\n"); 778 return ret; 779 } 780 781 if (!amdgpu_sriov_vf(adev)) 782 smu_get_unique_id(smu); 783 784 smu_get_fan_parameters(smu); 785 786 smu_handle_task(smu, 787 smu->smu_dpm.dpm_level, 788 AMD_PP_TASK_COMPLETE_INIT); 789 790 ret = smu_apply_default_config_table_settings(smu); 791 if (ret && (ret != -EOPNOTSUPP)) { 792 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 793 return ret; 794 } 795 796 smu_restore_dpm_user_profile(smu); 797 798 return 0; 799 } 800 801 static int smu_init_fb_allocations(struct smu_context *smu) 802 { 803 struct amdgpu_device *adev = smu->adev; 804 struct smu_table_context *smu_table = &smu->smu_table; 805 struct smu_table *tables = smu_table->tables; 806 struct smu_table *driver_table = &(smu_table->driver_table); 807 uint32_t max_table_size = 0; 808 int ret, i; 809 810 /* VRAM allocation for tool table */ 811 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 812 ret = amdgpu_bo_create_kernel(adev, 813 tables[SMU_TABLE_PMSTATUSLOG].size, 814 tables[SMU_TABLE_PMSTATUSLOG].align, 815 tables[SMU_TABLE_PMSTATUSLOG].domain, 816 &tables[SMU_TABLE_PMSTATUSLOG].bo, 817 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 818 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 819 if (ret) { 820 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 821 return ret; 822 } 823 } 824 825 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 826 /* VRAM allocation for driver table */ 827 for (i = 0; i < SMU_TABLE_COUNT; i++) { 828 if (tables[i].size == 0) 829 continue; 830 831 /* If one of the tables has VRAM domain restriction, keep it in 832 * VRAM 833 */ 834 if ((tables[i].domain & 835 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 836 AMDGPU_GEM_DOMAIN_VRAM) 837 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 838 839 if (i == SMU_TABLE_PMSTATUSLOG) 840 continue; 841 842 if (max_table_size < tables[i].size) 843 max_table_size = tables[i].size; 844 } 845 846 driver_table->size = max_table_size; 847 driver_table->align = PAGE_SIZE; 848 849 ret = amdgpu_bo_create_kernel(adev, 850 driver_table->size, 851 driver_table->align, 852 driver_table->domain, 853 &driver_table->bo, 854 &driver_table->mc_address, 855 &driver_table->cpu_addr); 856 if (ret) { 857 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 858 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 859 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 860 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 861 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 862 } 863 864 return ret; 865 } 866 867 static int smu_fini_fb_allocations(struct smu_context *smu) 868 { 869 struct smu_table_context *smu_table = &smu->smu_table; 870 struct smu_table *tables = smu_table->tables; 871 struct smu_table *driver_table = &(smu_table->driver_table); 872 873 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 874 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 875 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 876 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 877 878 amdgpu_bo_free_kernel(&driver_table->bo, 879 &driver_table->mc_address, 880 &driver_table->cpu_addr); 881 882 return 0; 883 } 884 885 /** 886 * smu_alloc_memory_pool - allocate memory pool in the system memory 887 * 888 * @smu: amdgpu_device pointer 889 * 890 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 891 * and DramLogSetDramAddr can notify it changed. 892 * 893 * Returns 0 on success, error on failure. 894 */ 895 static int smu_alloc_memory_pool(struct smu_context *smu) 896 { 897 struct amdgpu_device *adev = smu->adev; 898 struct smu_table_context *smu_table = &smu->smu_table; 899 struct smu_table *memory_pool = &smu_table->memory_pool; 900 uint64_t pool_size = smu->pool_size; 901 int ret = 0; 902 903 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 904 return ret; 905 906 memory_pool->size = pool_size; 907 memory_pool->align = PAGE_SIZE; 908 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 909 910 switch (pool_size) { 911 case SMU_MEMORY_POOL_SIZE_256_MB: 912 case SMU_MEMORY_POOL_SIZE_512_MB: 913 case SMU_MEMORY_POOL_SIZE_1_GB: 914 case SMU_MEMORY_POOL_SIZE_2_GB: 915 ret = amdgpu_bo_create_kernel(adev, 916 memory_pool->size, 917 memory_pool->align, 918 memory_pool->domain, 919 &memory_pool->bo, 920 &memory_pool->mc_address, 921 &memory_pool->cpu_addr); 922 if (ret) 923 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 924 break; 925 default: 926 break; 927 } 928 929 return ret; 930 } 931 932 static int smu_free_memory_pool(struct smu_context *smu) 933 { 934 struct smu_table_context *smu_table = &smu->smu_table; 935 struct smu_table *memory_pool = &smu_table->memory_pool; 936 937 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 938 return 0; 939 940 amdgpu_bo_free_kernel(&memory_pool->bo, 941 &memory_pool->mc_address, 942 &memory_pool->cpu_addr); 943 944 memset(memory_pool, 0, sizeof(struct smu_table)); 945 946 return 0; 947 } 948 949 static int smu_alloc_dummy_read_table(struct smu_context *smu) 950 { 951 struct smu_table_context *smu_table = &smu->smu_table; 952 struct smu_table *dummy_read_1_table = 953 &smu_table->dummy_read_1_table; 954 struct amdgpu_device *adev = smu->adev; 955 int ret = 0; 956 957 if (!dummy_read_1_table->size) 958 return 0; 959 960 ret = amdgpu_bo_create_kernel(adev, 961 dummy_read_1_table->size, 962 dummy_read_1_table->align, 963 dummy_read_1_table->domain, 964 &dummy_read_1_table->bo, 965 &dummy_read_1_table->mc_address, 966 &dummy_read_1_table->cpu_addr); 967 if (ret) 968 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 969 970 return ret; 971 } 972 973 static void smu_free_dummy_read_table(struct smu_context *smu) 974 { 975 struct smu_table_context *smu_table = &smu->smu_table; 976 struct smu_table *dummy_read_1_table = 977 &smu_table->dummy_read_1_table; 978 979 980 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 981 &dummy_read_1_table->mc_address, 982 &dummy_read_1_table->cpu_addr); 983 984 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 985 } 986 987 static int smu_smc_table_sw_init(struct smu_context *smu) 988 { 989 int ret; 990 991 /** 992 * Create smu_table structure, and init smc tables such as 993 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 994 */ 995 ret = smu_init_smc_tables(smu); 996 if (ret) { 997 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 998 return ret; 999 } 1000 1001 /** 1002 * Create smu_power_context structure, and allocate smu_dpm_context and 1003 * context size to fill the smu_power_context data. 1004 */ 1005 ret = smu_init_power(smu); 1006 if (ret) { 1007 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1008 return ret; 1009 } 1010 1011 /* 1012 * allocate vram bos to store smc table contents. 1013 */ 1014 ret = smu_init_fb_allocations(smu); 1015 if (ret) 1016 return ret; 1017 1018 ret = smu_alloc_memory_pool(smu); 1019 if (ret) 1020 return ret; 1021 1022 ret = smu_alloc_dummy_read_table(smu); 1023 if (ret) 1024 return ret; 1025 1026 ret = smu_i2c_init(smu); 1027 if (ret) 1028 return ret; 1029 1030 return 0; 1031 } 1032 1033 static int smu_smc_table_sw_fini(struct smu_context *smu) 1034 { 1035 int ret; 1036 1037 smu_i2c_fini(smu); 1038 1039 smu_free_dummy_read_table(smu); 1040 1041 ret = smu_free_memory_pool(smu); 1042 if (ret) 1043 return ret; 1044 1045 ret = smu_fini_fb_allocations(smu); 1046 if (ret) 1047 return ret; 1048 1049 ret = smu_fini_power(smu); 1050 if (ret) { 1051 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1052 return ret; 1053 } 1054 1055 ret = smu_fini_smc_tables(smu); 1056 if (ret) { 1057 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1058 return ret; 1059 } 1060 1061 return 0; 1062 } 1063 1064 static void smu_throttling_logging_work_fn(struct work_struct *work) 1065 { 1066 struct smu_context *smu = container_of(work, struct smu_context, 1067 throttling_logging_work); 1068 1069 smu_log_thermal_throttling(smu); 1070 } 1071 1072 static void smu_interrupt_work_fn(struct work_struct *work) 1073 { 1074 struct smu_context *smu = container_of(work, struct smu_context, 1075 interrupt_work); 1076 1077 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1078 smu->ppt_funcs->interrupt_work(smu); 1079 } 1080 1081 static int smu_sw_init(void *handle) 1082 { 1083 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1084 struct smu_context *smu = adev->powerplay.pp_handle; 1085 int ret; 1086 1087 smu->pool_size = adev->pm.smu_prv_buffer_size; 1088 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1089 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1090 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1091 1092 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1093 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1094 atomic64_set(&smu->throttle_int_counter, 0); 1095 smu->watermarks_bitmap = 0; 1096 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1097 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1098 1099 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1100 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1101 1102 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1103 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1104 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1105 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1106 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1107 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1108 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1109 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1110 1111 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1112 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1113 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1114 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1115 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1116 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1117 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1118 smu->display_config = &adev->pm.pm_display_cfg; 1119 1120 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1121 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1122 1123 ret = smu_smc_table_sw_init(smu); 1124 if (ret) { 1125 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1126 return ret; 1127 } 1128 1129 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1130 ret = smu_get_vbios_bootup_values(smu); 1131 if (ret) { 1132 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1133 return ret; 1134 } 1135 1136 ret = smu_init_pptable_microcode(smu); 1137 if (ret) { 1138 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1139 return ret; 1140 } 1141 1142 ret = smu_register_irq_handler(smu); 1143 if (ret) { 1144 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1145 return ret; 1146 } 1147 1148 /* If there is no way to query fan control mode, fan control is not supported */ 1149 if (!smu->ppt_funcs->get_fan_control_mode) 1150 smu->adev->pm.no_fan = true; 1151 1152 return 0; 1153 } 1154 1155 static int smu_sw_fini(void *handle) 1156 { 1157 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1158 struct smu_context *smu = adev->powerplay.pp_handle; 1159 int ret; 1160 1161 ret = smu_smc_table_sw_fini(smu); 1162 if (ret) { 1163 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1164 return ret; 1165 } 1166 1167 smu_fini_microcode(smu); 1168 1169 return 0; 1170 } 1171 1172 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1173 { 1174 struct amdgpu_device *adev = smu->adev; 1175 struct smu_temperature_range *range = 1176 &smu->thermal_range; 1177 int ret = 0; 1178 1179 if (!smu->ppt_funcs->get_thermal_temperature_range) 1180 return 0; 1181 1182 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1183 if (ret) 1184 return ret; 1185 1186 adev->pm.dpm.thermal.min_temp = range->min; 1187 adev->pm.dpm.thermal.max_temp = range->max; 1188 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1189 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1190 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1191 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1192 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1193 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1194 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1195 1196 return ret; 1197 } 1198 1199 static int smu_smc_hw_setup(struct smu_context *smu) 1200 { 1201 struct smu_feature *feature = &smu->smu_feature; 1202 struct amdgpu_device *adev = smu->adev; 1203 uint32_t pcie_gen = 0, pcie_width = 0; 1204 uint64_t features_supported; 1205 int ret = 0; 1206 1207 switch (adev->ip_versions[MP1_HWIP][0]) { 1208 case IP_VERSION(11, 0, 7): 1209 case IP_VERSION(11, 0, 11): 1210 case IP_VERSION(11, 5, 0): 1211 case IP_VERSION(11, 0, 12): 1212 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1213 dev_info(adev->dev, "dpm has been enabled\n"); 1214 ret = smu_system_features_control(smu, true); 1215 if (ret) 1216 dev_err(adev->dev, "Failed system features control!\n"); 1217 return ret; 1218 } 1219 break; 1220 default: 1221 break; 1222 } 1223 1224 ret = smu_init_display_count(smu, 0); 1225 if (ret) { 1226 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1227 return ret; 1228 } 1229 1230 ret = smu_set_driver_table_location(smu); 1231 if (ret) { 1232 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1233 return ret; 1234 } 1235 1236 /* 1237 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1238 */ 1239 ret = smu_set_tool_table_location(smu); 1240 if (ret) { 1241 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1242 return ret; 1243 } 1244 1245 /* 1246 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1247 * pool location. 1248 */ 1249 ret = smu_notify_memory_pool_location(smu); 1250 if (ret) { 1251 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1252 return ret; 1253 } 1254 1255 /* 1256 * It is assumed the pptable used before runpm is same as 1257 * the one used afterwards. Thus, we can reuse the stored 1258 * copy and do not need to resetup the pptable again. 1259 */ 1260 if (!adev->in_runpm) { 1261 ret = smu_setup_pptable(smu); 1262 if (ret) { 1263 dev_err(adev->dev, "Failed to setup pptable!\n"); 1264 return ret; 1265 } 1266 } 1267 1268 /* smu_dump_pptable(smu); */ 1269 1270 /* 1271 * With SCPM enabled, PSP is responsible for the PPTable transferring 1272 * (to SMU). Driver involvement is not needed and permitted. 1273 */ 1274 if (!adev->scpm_enabled) { 1275 /* 1276 * Copy pptable bo in the vram to smc with SMU MSGs such as 1277 * SetDriverDramAddr and TransferTableDram2Smu. 1278 */ 1279 ret = smu_write_pptable(smu); 1280 if (ret) { 1281 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1282 return ret; 1283 } 1284 } 1285 1286 /* issue Run*Btc msg */ 1287 ret = smu_run_btc(smu); 1288 if (ret) 1289 return ret; 1290 1291 /* 1292 * With SCPM enabled, these actions(and relevant messages) are 1293 * not needed and permitted. 1294 */ 1295 if (!adev->scpm_enabled) { 1296 ret = smu_feature_set_allowed_mask(smu); 1297 if (ret) { 1298 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1299 return ret; 1300 } 1301 } 1302 1303 ret = smu_system_features_control(smu, true); 1304 if (ret) { 1305 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1306 return ret; 1307 } 1308 1309 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1310 if (ret) { 1311 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1312 return ret; 1313 } 1314 bitmap_copy(feature->supported, 1315 (unsigned long *)&features_supported, 1316 feature->feature_num); 1317 1318 if (!smu_is_dpm_running(smu)) 1319 dev_info(adev->dev, "dpm has been disabled\n"); 1320 1321 /* 1322 * Set initialized values (get from vbios) to dpm tables context such as 1323 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1324 * type of clks. 1325 */ 1326 ret = smu_set_default_dpm_table(smu); 1327 if (ret) { 1328 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1329 return ret; 1330 } 1331 1332 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1333 pcie_gen = 3; 1334 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1335 pcie_gen = 2; 1336 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1337 pcie_gen = 1; 1338 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1339 pcie_gen = 0; 1340 1341 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1342 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1343 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1344 */ 1345 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1346 pcie_width = 6; 1347 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1348 pcie_width = 5; 1349 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1350 pcie_width = 4; 1351 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1352 pcie_width = 3; 1353 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1354 pcie_width = 2; 1355 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1356 pcie_width = 1; 1357 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1358 if (ret) { 1359 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1360 return ret; 1361 } 1362 1363 ret = smu_get_thermal_temperature_range(smu); 1364 if (ret) { 1365 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1366 return ret; 1367 } 1368 1369 ret = smu_enable_thermal_alert(smu); 1370 if (ret) { 1371 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1372 return ret; 1373 } 1374 1375 ret = smu_notify_display_change(smu); 1376 if (ret) { 1377 dev_err(adev->dev, "Failed to notify display change!\n"); 1378 return ret; 1379 } 1380 1381 /* 1382 * Set min deep sleep dce fclk with bootup value from vbios via 1383 * SetMinDeepSleepDcefclk MSG. 1384 */ 1385 ret = smu_set_min_dcef_deep_sleep(smu, 1386 smu->smu_table.boot_values.dcefclk / 100); 1387 1388 return ret; 1389 } 1390 1391 static int smu_start_smc_engine(struct smu_context *smu) 1392 { 1393 struct amdgpu_device *adev = smu->adev; 1394 int ret = 0; 1395 1396 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1397 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1398 if (smu->ppt_funcs->load_microcode) { 1399 ret = smu->ppt_funcs->load_microcode(smu); 1400 if (ret) 1401 return ret; 1402 } 1403 } 1404 } 1405 1406 if (smu->ppt_funcs->check_fw_status) { 1407 ret = smu->ppt_funcs->check_fw_status(smu); 1408 if (ret) { 1409 dev_err(adev->dev, "SMC is not ready\n"); 1410 return ret; 1411 } 1412 } 1413 1414 /* 1415 * Send msg GetDriverIfVersion to check if the return value is equal 1416 * with DRIVER_IF_VERSION of smc header. 1417 */ 1418 ret = smu_check_fw_version(smu); 1419 if (ret) 1420 return ret; 1421 1422 return ret; 1423 } 1424 1425 static int smu_hw_init(void *handle) 1426 { 1427 int ret; 1428 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1429 struct smu_context *smu = adev->powerplay.pp_handle; 1430 1431 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1432 smu->pm_enabled = false; 1433 return 0; 1434 } 1435 1436 ret = smu_start_smc_engine(smu); 1437 if (ret) { 1438 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1439 return ret; 1440 } 1441 1442 if (smu->is_apu) { 1443 ret = smu_set_gfx_imu_enable(smu); 1444 if (ret) 1445 return ret; 1446 smu_dpm_set_vcn_enable(smu, true); 1447 smu_dpm_set_jpeg_enable(smu, true); 1448 smu_set_gfx_cgpg(smu, true); 1449 } 1450 1451 if (!smu->pm_enabled) 1452 return 0; 1453 1454 ret = smu_get_driver_allowed_feature_mask(smu); 1455 if (ret) 1456 return ret; 1457 1458 ret = smu_smc_hw_setup(smu); 1459 if (ret) { 1460 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1461 return ret; 1462 } 1463 1464 /* 1465 * Move maximum sustainable clock retrieving here considering 1466 * 1. It is not needed on resume(from S3). 1467 * 2. DAL settings come between .hw_init and .late_init of SMU. 1468 * And DAL needs to know the maximum sustainable clocks. Thus 1469 * it cannot be put in .late_init(). 1470 */ 1471 ret = smu_init_max_sustainable_clocks(smu); 1472 if (ret) { 1473 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1474 return ret; 1475 } 1476 1477 adev->pm.dpm_enabled = true; 1478 1479 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1480 1481 return 0; 1482 } 1483 1484 static int smu_disable_dpms(struct smu_context *smu) 1485 { 1486 struct amdgpu_device *adev = smu->adev; 1487 int ret = 0; 1488 bool use_baco = !smu->is_apu && 1489 ((amdgpu_in_reset(adev) && 1490 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1491 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1492 1493 /* 1494 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1495 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1496 */ 1497 switch (adev->ip_versions[MP1_HWIP][0]) { 1498 case IP_VERSION(13, 0, 0): 1499 case IP_VERSION(13, 0, 7): 1500 case IP_VERSION(13, 0, 10): 1501 return 0; 1502 default: 1503 break; 1504 } 1505 1506 /* 1507 * For custom pptable uploading, skip the DPM features 1508 * disable process on Navi1x ASICs. 1509 * - As the gfx related features are under control of 1510 * RLC on those ASICs. RLC reinitialization will be 1511 * needed to reenable them. That will cost much more 1512 * efforts. 1513 * 1514 * - SMU firmware can handle the DPM reenablement 1515 * properly. 1516 */ 1517 if (smu->uploading_custom_pp_table) { 1518 switch (adev->ip_versions[MP1_HWIP][0]) { 1519 case IP_VERSION(11, 0, 0): 1520 case IP_VERSION(11, 0, 5): 1521 case IP_VERSION(11, 0, 9): 1522 case IP_VERSION(11, 0, 7): 1523 case IP_VERSION(11, 0, 11): 1524 case IP_VERSION(11, 5, 0): 1525 case IP_VERSION(11, 0, 12): 1526 case IP_VERSION(11, 0, 13): 1527 return 0; 1528 default: 1529 break; 1530 } 1531 } 1532 1533 /* 1534 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1535 * on BACO in. Driver involvement is unnecessary. 1536 */ 1537 if (use_baco) { 1538 switch (adev->ip_versions[MP1_HWIP][0]) { 1539 case IP_VERSION(11, 0, 7): 1540 case IP_VERSION(11, 0, 0): 1541 case IP_VERSION(11, 0, 5): 1542 case IP_VERSION(11, 0, 9): 1543 case IP_VERSION(13, 0, 7): 1544 return 0; 1545 default: 1546 break; 1547 } 1548 } 1549 1550 /* 1551 * For SMU 13.0.4/11, PMFW will handle the features disablement properly 1552 * for gpu reset case. Driver involvement is unnecessary. 1553 */ 1554 if (amdgpu_in_reset(adev)) { 1555 switch (adev->ip_versions[MP1_HWIP][0]) { 1556 case IP_VERSION(13, 0, 4): 1557 case IP_VERSION(13, 0, 11): 1558 return 0; 1559 default: 1560 break; 1561 } 1562 } 1563 1564 /* 1565 * For gpu reset, runpm and hibernation through BACO, 1566 * BACO feature has to be kept enabled. 1567 */ 1568 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1569 ret = smu_disable_all_features_with_exception(smu, 1570 SMU_FEATURE_BACO_BIT); 1571 if (ret) 1572 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1573 } else { 1574 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1575 if (!adev->scpm_enabled) { 1576 ret = smu_system_features_control(smu, false); 1577 if (ret) 1578 dev_err(adev->dev, "Failed to disable smu features.\n"); 1579 } 1580 } 1581 1582 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1583 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1584 adev->gfx.rlc.funcs->stop(adev); 1585 1586 return ret; 1587 } 1588 1589 static int smu_smc_hw_cleanup(struct smu_context *smu) 1590 { 1591 struct amdgpu_device *adev = smu->adev; 1592 int ret = 0; 1593 1594 cancel_work_sync(&smu->throttling_logging_work); 1595 cancel_work_sync(&smu->interrupt_work); 1596 1597 ret = smu_disable_thermal_alert(smu); 1598 if (ret) { 1599 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1600 return ret; 1601 } 1602 1603 ret = smu_disable_dpms(smu); 1604 if (ret) { 1605 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1606 return ret; 1607 } 1608 1609 return 0; 1610 } 1611 1612 static int smu_hw_fini(void *handle) 1613 { 1614 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1615 struct smu_context *smu = adev->powerplay.pp_handle; 1616 1617 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1618 return 0; 1619 1620 smu_dpm_set_vcn_enable(smu, false); 1621 smu_dpm_set_jpeg_enable(smu, false); 1622 1623 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1624 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1625 1626 if (!smu->pm_enabled) 1627 return 0; 1628 1629 adev->pm.dpm_enabled = false; 1630 1631 return smu_smc_hw_cleanup(smu); 1632 } 1633 1634 static void smu_late_fini(void *handle) 1635 { 1636 struct amdgpu_device *adev = handle; 1637 struct smu_context *smu = adev->powerplay.pp_handle; 1638 1639 kfree(smu); 1640 } 1641 1642 static int smu_reset(struct smu_context *smu) 1643 { 1644 struct amdgpu_device *adev = smu->adev; 1645 int ret; 1646 1647 ret = smu_hw_fini(adev); 1648 if (ret) 1649 return ret; 1650 1651 ret = smu_hw_init(adev); 1652 if (ret) 1653 return ret; 1654 1655 ret = smu_late_init(adev); 1656 if (ret) 1657 return ret; 1658 1659 return 0; 1660 } 1661 1662 static int smu_suspend(void *handle) 1663 { 1664 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1665 struct smu_context *smu = adev->powerplay.pp_handle; 1666 int ret; 1667 uint64_t count; 1668 1669 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1670 return 0; 1671 1672 if (!smu->pm_enabled) 1673 return 0; 1674 1675 adev->pm.dpm_enabled = false; 1676 1677 ret = smu_smc_hw_cleanup(smu); 1678 if (ret) 1679 return ret; 1680 1681 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1682 1683 smu_set_gfx_cgpg(smu, false); 1684 1685 /* 1686 * pwfw resets entrycount when device is suspended, so we save the 1687 * last value to be used when we resume to keep it consistent 1688 */ 1689 ret = smu_get_entrycount_gfxoff(smu, &count); 1690 if (!ret) 1691 adev->gfx.gfx_off_entrycount = count; 1692 1693 return 0; 1694 } 1695 1696 static int smu_resume(void *handle) 1697 { 1698 int ret; 1699 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1700 struct smu_context *smu = adev->powerplay.pp_handle; 1701 1702 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1703 return 0; 1704 1705 if (!smu->pm_enabled) 1706 return 0; 1707 1708 dev_info(adev->dev, "SMU is resuming...\n"); 1709 1710 ret = smu_start_smc_engine(smu); 1711 if (ret) { 1712 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1713 return ret; 1714 } 1715 1716 ret = smu_smc_hw_setup(smu); 1717 if (ret) { 1718 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1719 return ret; 1720 } 1721 1722 ret = smu_set_gfx_imu_enable(smu); 1723 if (ret) 1724 return ret; 1725 1726 smu_set_gfx_cgpg(smu, true); 1727 1728 smu->disable_uclk_switch = 0; 1729 1730 adev->pm.dpm_enabled = true; 1731 1732 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1733 1734 return 0; 1735 } 1736 1737 static int smu_display_configuration_change(void *handle, 1738 const struct amd_pp_display_configuration *display_config) 1739 { 1740 struct smu_context *smu = handle; 1741 1742 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1743 return -EOPNOTSUPP; 1744 1745 if (!display_config) 1746 return -EINVAL; 1747 1748 smu_set_min_dcef_deep_sleep(smu, 1749 display_config->min_dcef_deep_sleep_set_clk / 100); 1750 1751 return 0; 1752 } 1753 1754 static int smu_set_clockgating_state(void *handle, 1755 enum amd_clockgating_state state) 1756 { 1757 return 0; 1758 } 1759 1760 static int smu_set_powergating_state(void *handle, 1761 enum amd_powergating_state state) 1762 { 1763 return 0; 1764 } 1765 1766 static int smu_enable_umd_pstate(void *handle, 1767 enum amd_dpm_forced_level *level) 1768 { 1769 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1770 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1771 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1772 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1773 1774 struct smu_context *smu = (struct smu_context*)(handle); 1775 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1776 1777 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1778 return -EINVAL; 1779 1780 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1781 /* enter umd pstate, save current level, disable gfx cg*/ 1782 if (*level & profile_mode_mask) { 1783 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1784 smu_gpo_control(smu, false); 1785 smu_gfx_ulv_control(smu, false); 1786 smu_deep_sleep_control(smu, false); 1787 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1788 } 1789 } else { 1790 /* exit umd pstate, restore level, enable gfx cg*/ 1791 if (!(*level & profile_mode_mask)) { 1792 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1793 *level = smu_dpm_ctx->saved_dpm_level; 1794 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1795 smu_deep_sleep_control(smu, true); 1796 smu_gfx_ulv_control(smu, true); 1797 smu_gpo_control(smu, true); 1798 } 1799 } 1800 1801 return 0; 1802 } 1803 1804 static int smu_bump_power_profile_mode(struct smu_context *smu, 1805 long *param, 1806 uint32_t param_size) 1807 { 1808 int ret = 0; 1809 1810 if (smu->ppt_funcs->set_power_profile_mode) 1811 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1812 1813 return ret; 1814 } 1815 1816 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1817 enum amd_dpm_forced_level level, 1818 bool skip_display_settings) 1819 { 1820 int ret = 0; 1821 int index = 0; 1822 long workload; 1823 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1824 1825 if (!skip_display_settings) { 1826 ret = smu_display_config_changed(smu); 1827 if (ret) { 1828 dev_err(smu->adev->dev, "Failed to change display config!"); 1829 return ret; 1830 } 1831 } 1832 1833 ret = smu_apply_clocks_adjust_rules(smu); 1834 if (ret) { 1835 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1836 return ret; 1837 } 1838 1839 if (!skip_display_settings) { 1840 ret = smu_notify_smc_display_config(smu); 1841 if (ret) { 1842 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1843 return ret; 1844 } 1845 } 1846 1847 if (smu_dpm_ctx->dpm_level != level) { 1848 ret = smu_asic_set_performance_level(smu, level); 1849 if (ret) { 1850 dev_err(smu->adev->dev, "Failed to set performance level!"); 1851 return ret; 1852 } 1853 1854 /* update the saved copy */ 1855 smu_dpm_ctx->dpm_level = level; 1856 } 1857 1858 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1859 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1860 index = fls(smu->workload_mask); 1861 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1862 workload = smu->workload_setting[index]; 1863 1864 if (smu->power_profile_mode != workload) 1865 smu_bump_power_profile_mode(smu, &workload, 0); 1866 } 1867 1868 return ret; 1869 } 1870 1871 static int smu_handle_task(struct smu_context *smu, 1872 enum amd_dpm_forced_level level, 1873 enum amd_pp_task task_id) 1874 { 1875 int ret = 0; 1876 1877 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1878 return -EOPNOTSUPP; 1879 1880 switch (task_id) { 1881 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1882 ret = smu_pre_display_config_changed(smu); 1883 if (ret) 1884 return ret; 1885 ret = smu_adjust_power_state_dynamic(smu, level, false); 1886 break; 1887 case AMD_PP_TASK_COMPLETE_INIT: 1888 case AMD_PP_TASK_READJUST_POWER_STATE: 1889 ret = smu_adjust_power_state_dynamic(smu, level, true); 1890 break; 1891 default: 1892 break; 1893 } 1894 1895 return ret; 1896 } 1897 1898 static int smu_handle_dpm_task(void *handle, 1899 enum amd_pp_task task_id, 1900 enum amd_pm_state_type *user_state) 1901 { 1902 struct smu_context *smu = handle; 1903 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1904 1905 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 1906 1907 } 1908 1909 static int smu_switch_power_profile(void *handle, 1910 enum PP_SMC_POWER_PROFILE type, 1911 bool en) 1912 { 1913 struct smu_context *smu = handle; 1914 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1915 long workload; 1916 uint32_t index; 1917 1918 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1919 return -EOPNOTSUPP; 1920 1921 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1922 return -EINVAL; 1923 1924 if (!en) { 1925 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1926 index = fls(smu->workload_mask); 1927 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1928 workload = smu->workload_setting[index]; 1929 } else { 1930 smu->workload_mask |= (1 << smu->workload_prority[type]); 1931 index = fls(smu->workload_mask); 1932 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1933 workload = smu->workload_setting[index]; 1934 } 1935 1936 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1937 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1938 smu_bump_power_profile_mode(smu, &workload, 0); 1939 1940 return 0; 1941 } 1942 1943 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1944 { 1945 struct smu_context *smu = handle; 1946 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1947 1948 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1949 return -EOPNOTSUPP; 1950 1951 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1952 return -EINVAL; 1953 1954 return smu_dpm_ctx->dpm_level; 1955 } 1956 1957 static int smu_force_performance_level(void *handle, 1958 enum amd_dpm_forced_level level) 1959 { 1960 struct smu_context *smu = handle; 1961 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1962 int ret = 0; 1963 1964 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1965 return -EOPNOTSUPP; 1966 1967 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1968 return -EINVAL; 1969 1970 ret = smu_enable_umd_pstate(smu, &level); 1971 if (ret) 1972 return ret; 1973 1974 ret = smu_handle_task(smu, level, 1975 AMD_PP_TASK_READJUST_POWER_STATE); 1976 1977 /* reset user dpm clock state */ 1978 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1979 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1980 smu->user_dpm_profile.clk_dependency = 0; 1981 } 1982 1983 return ret; 1984 } 1985 1986 static int smu_set_display_count(void *handle, uint32_t count) 1987 { 1988 struct smu_context *smu = handle; 1989 1990 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1991 return -EOPNOTSUPP; 1992 1993 return smu_init_display_count(smu, count); 1994 } 1995 1996 static int smu_force_smuclk_levels(struct smu_context *smu, 1997 enum smu_clk_type clk_type, 1998 uint32_t mask) 1999 { 2000 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2001 int ret = 0; 2002 2003 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2004 return -EOPNOTSUPP; 2005 2006 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2007 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2008 return -EINVAL; 2009 } 2010 2011 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2012 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2013 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2014 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2015 smu_set_user_clk_dependencies(smu, clk_type); 2016 } 2017 } 2018 2019 return ret; 2020 } 2021 2022 static int smu_force_ppclk_levels(void *handle, 2023 enum pp_clock_type type, 2024 uint32_t mask) 2025 { 2026 struct smu_context *smu = handle; 2027 enum smu_clk_type clk_type; 2028 2029 switch (type) { 2030 case PP_SCLK: 2031 clk_type = SMU_SCLK; break; 2032 case PP_MCLK: 2033 clk_type = SMU_MCLK; break; 2034 case PP_PCIE: 2035 clk_type = SMU_PCIE; break; 2036 case PP_SOCCLK: 2037 clk_type = SMU_SOCCLK; break; 2038 case PP_FCLK: 2039 clk_type = SMU_FCLK; break; 2040 case PP_DCEFCLK: 2041 clk_type = SMU_DCEFCLK; break; 2042 case PP_VCLK: 2043 clk_type = SMU_VCLK; break; 2044 case PP_VCLK1: 2045 clk_type = SMU_VCLK1; break; 2046 case PP_DCLK: 2047 clk_type = SMU_DCLK; break; 2048 case PP_DCLK1: 2049 clk_type = SMU_DCLK1; break; 2050 case OD_SCLK: 2051 clk_type = SMU_OD_SCLK; break; 2052 case OD_MCLK: 2053 clk_type = SMU_OD_MCLK; break; 2054 case OD_VDDC_CURVE: 2055 clk_type = SMU_OD_VDDC_CURVE; break; 2056 case OD_RANGE: 2057 clk_type = SMU_OD_RANGE; break; 2058 default: 2059 return -EINVAL; 2060 } 2061 2062 return smu_force_smuclk_levels(smu, clk_type, mask); 2063 } 2064 2065 /* 2066 * On system suspending or resetting, the dpm_enabled 2067 * flag will be cleared. So that those SMU services which 2068 * are not supported will be gated. 2069 * However, the mp1 state setting should still be granted 2070 * even if the dpm_enabled cleared. 2071 */ 2072 static int smu_set_mp1_state(void *handle, 2073 enum pp_mp1_state mp1_state) 2074 { 2075 struct smu_context *smu = handle; 2076 int ret = 0; 2077 2078 if (!smu->pm_enabled) 2079 return -EOPNOTSUPP; 2080 2081 if (smu->ppt_funcs && 2082 smu->ppt_funcs->set_mp1_state) 2083 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2084 2085 return ret; 2086 } 2087 2088 static int smu_set_df_cstate(void *handle, 2089 enum pp_df_cstate state) 2090 { 2091 struct smu_context *smu = handle; 2092 int ret = 0; 2093 2094 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2095 return -EOPNOTSUPP; 2096 2097 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2098 return 0; 2099 2100 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2101 if (ret) 2102 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2103 2104 return ret; 2105 } 2106 2107 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 2108 { 2109 int ret = 0; 2110 2111 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2112 return -EOPNOTSUPP; 2113 2114 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2115 return 0; 2116 2117 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2118 if (ret) 2119 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2120 2121 return ret; 2122 } 2123 2124 int smu_write_watermarks_table(struct smu_context *smu) 2125 { 2126 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2127 return -EOPNOTSUPP; 2128 2129 return smu_set_watermarks_table(smu, NULL); 2130 } 2131 2132 static int smu_set_watermarks_for_clock_ranges(void *handle, 2133 struct pp_smu_wm_range_sets *clock_ranges) 2134 { 2135 struct smu_context *smu = handle; 2136 2137 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2138 return -EOPNOTSUPP; 2139 2140 if (smu->disable_watermark) 2141 return 0; 2142 2143 return smu_set_watermarks_table(smu, clock_ranges); 2144 } 2145 2146 int smu_set_ac_dc(struct smu_context *smu) 2147 { 2148 int ret = 0; 2149 2150 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2151 return -EOPNOTSUPP; 2152 2153 /* controlled by firmware */ 2154 if (smu->dc_controlled_by_gpio) 2155 return 0; 2156 2157 ret = smu_set_power_source(smu, 2158 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2159 SMU_POWER_SOURCE_DC); 2160 if (ret) 2161 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2162 smu->adev->pm.ac_power ? "AC" : "DC"); 2163 2164 return ret; 2165 } 2166 2167 const struct amd_ip_funcs smu_ip_funcs = { 2168 .name = "smu", 2169 .early_init = smu_early_init, 2170 .late_init = smu_late_init, 2171 .sw_init = smu_sw_init, 2172 .sw_fini = smu_sw_fini, 2173 .hw_init = smu_hw_init, 2174 .hw_fini = smu_hw_fini, 2175 .late_fini = smu_late_fini, 2176 .suspend = smu_suspend, 2177 .resume = smu_resume, 2178 .is_idle = NULL, 2179 .check_soft_reset = NULL, 2180 .wait_for_idle = NULL, 2181 .soft_reset = NULL, 2182 .set_clockgating_state = smu_set_clockgating_state, 2183 .set_powergating_state = smu_set_powergating_state, 2184 }; 2185 2186 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2187 { 2188 .type = AMD_IP_BLOCK_TYPE_SMC, 2189 .major = 11, 2190 .minor = 0, 2191 .rev = 0, 2192 .funcs = &smu_ip_funcs, 2193 }; 2194 2195 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2196 { 2197 .type = AMD_IP_BLOCK_TYPE_SMC, 2198 .major = 12, 2199 .minor = 0, 2200 .rev = 0, 2201 .funcs = &smu_ip_funcs, 2202 }; 2203 2204 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2205 { 2206 .type = AMD_IP_BLOCK_TYPE_SMC, 2207 .major = 13, 2208 .minor = 0, 2209 .rev = 0, 2210 .funcs = &smu_ip_funcs, 2211 }; 2212 2213 static int smu_load_microcode(void *handle) 2214 { 2215 struct smu_context *smu = handle; 2216 struct amdgpu_device *adev = smu->adev; 2217 int ret = 0; 2218 2219 if (!smu->pm_enabled) 2220 return -EOPNOTSUPP; 2221 2222 /* This should be used for non PSP loading */ 2223 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2224 return 0; 2225 2226 if (smu->ppt_funcs->load_microcode) { 2227 ret = smu->ppt_funcs->load_microcode(smu); 2228 if (ret) { 2229 dev_err(adev->dev, "Load microcode failed\n"); 2230 return ret; 2231 } 2232 } 2233 2234 if (smu->ppt_funcs->check_fw_status) { 2235 ret = smu->ppt_funcs->check_fw_status(smu); 2236 if (ret) { 2237 dev_err(adev->dev, "SMC is not ready\n"); 2238 return ret; 2239 } 2240 } 2241 2242 return ret; 2243 } 2244 2245 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2246 { 2247 int ret = 0; 2248 2249 if (smu->ppt_funcs->set_gfx_cgpg) 2250 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2251 2252 return ret; 2253 } 2254 2255 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2256 { 2257 struct smu_context *smu = handle; 2258 int ret = 0; 2259 2260 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2261 return -EOPNOTSUPP; 2262 2263 if (!smu->ppt_funcs->set_fan_speed_rpm) 2264 return -EOPNOTSUPP; 2265 2266 if (speed == U32_MAX) 2267 return -EINVAL; 2268 2269 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2270 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2271 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2272 smu->user_dpm_profile.fan_speed_rpm = speed; 2273 2274 /* Override custom PWM setting as they cannot co-exist */ 2275 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2276 smu->user_dpm_profile.fan_speed_pwm = 0; 2277 } 2278 2279 return ret; 2280 } 2281 2282 /** 2283 * smu_get_power_limit - Request one of the SMU Power Limits 2284 * 2285 * @handle: pointer to smu context 2286 * @limit: requested limit is written back to this variable 2287 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2288 * @pp_power_type: &pp_power_type type of power 2289 * Return: 0 on success, <0 on error 2290 * 2291 */ 2292 int smu_get_power_limit(void *handle, 2293 uint32_t *limit, 2294 enum pp_power_limit_level pp_limit_level, 2295 enum pp_power_type pp_power_type) 2296 { 2297 struct smu_context *smu = handle; 2298 struct amdgpu_device *adev = smu->adev; 2299 enum smu_ppt_limit_level limit_level; 2300 uint32_t limit_type; 2301 int ret = 0; 2302 2303 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2304 return -EOPNOTSUPP; 2305 2306 switch(pp_power_type) { 2307 case PP_PWR_TYPE_SUSTAINED: 2308 limit_type = SMU_DEFAULT_PPT_LIMIT; 2309 break; 2310 case PP_PWR_TYPE_FAST: 2311 limit_type = SMU_FAST_PPT_LIMIT; 2312 break; 2313 default: 2314 return -EOPNOTSUPP; 2315 break; 2316 } 2317 2318 switch(pp_limit_level){ 2319 case PP_PWR_LIMIT_CURRENT: 2320 limit_level = SMU_PPT_LIMIT_CURRENT; 2321 break; 2322 case PP_PWR_LIMIT_DEFAULT: 2323 limit_level = SMU_PPT_LIMIT_DEFAULT; 2324 break; 2325 case PP_PWR_LIMIT_MAX: 2326 limit_level = SMU_PPT_LIMIT_MAX; 2327 break; 2328 case PP_PWR_LIMIT_MIN: 2329 default: 2330 return -EOPNOTSUPP; 2331 break; 2332 } 2333 2334 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2335 if (smu->ppt_funcs->get_ppt_limit) 2336 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2337 } else { 2338 switch (limit_level) { 2339 case SMU_PPT_LIMIT_CURRENT: 2340 switch (adev->ip_versions[MP1_HWIP][0]) { 2341 case IP_VERSION(13, 0, 2): 2342 case IP_VERSION(11, 0, 7): 2343 case IP_VERSION(11, 0, 11): 2344 case IP_VERSION(11, 0, 12): 2345 case IP_VERSION(11, 0, 13): 2346 ret = smu_get_asic_power_limits(smu, 2347 &smu->current_power_limit, 2348 NULL, 2349 NULL); 2350 break; 2351 default: 2352 break; 2353 } 2354 *limit = smu->current_power_limit; 2355 break; 2356 case SMU_PPT_LIMIT_DEFAULT: 2357 *limit = smu->default_power_limit; 2358 break; 2359 case SMU_PPT_LIMIT_MAX: 2360 *limit = smu->max_power_limit; 2361 break; 2362 default: 2363 break; 2364 } 2365 } 2366 2367 return ret; 2368 } 2369 2370 static int smu_set_power_limit(void *handle, uint32_t limit) 2371 { 2372 struct smu_context *smu = handle; 2373 uint32_t limit_type = limit >> 24; 2374 int ret = 0; 2375 2376 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2377 return -EOPNOTSUPP; 2378 2379 limit &= (1<<24)-1; 2380 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2381 if (smu->ppt_funcs->set_power_limit) 2382 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2383 2384 if (limit > smu->max_power_limit) { 2385 dev_err(smu->adev->dev, 2386 "New power limit (%d) is over the max allowed %d\n", 2387 limit, smu->max_power_limit); 2388 return -EINVAL; 2389 } 2390 2391 if (!limit) 2392 limit = smu->current_power_limit; 2393 2394 if (smu->ppt_funcs->set_power_limit) { 2395 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2396 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2397 smu->user_dpm_profile.power_limit = limit; 2398 } 2399 2400 return ret; 2401 } 2402 2403 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2404 { 2405 int ret = 0; 2406 2407 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2408 return -EOPNOTSUPP; 2409 2410 if (smu->ppt_funcs->print_clk_levels) 2411 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2412 2413 return ret; 2414 } 2415 2416 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2417 { 2418 enum smu_clk_type clk_type; 2419 2420 switch (type) { 2421 case PP_SCLK: 2422 clk_type = SMU_SCLK; break; 2423 case PP_MCLK: 2424 clk_type = SMU_MCLK; break; 2425 case PP_PCIE: 2426 clk_type = SMU_PCIE; break; 2427 case PP_SOCCLK: 2428 clk_type = SMU_SOCCLK; break; 2429 case PP_FCLK: 2430 clk_type = SMU_FCLK; break; 2431 case PP_DCEFCLK: 2432 clk_type = SMU_DCEFCLK; break; 2433 case PP_VCLK: 2434 clk_type = SMU_VCLK; break; 2435 case PP_VCLK1: 2436 clk_type = SMU_VCLK1; break; 2437 case PP_DCLK: 2438 clk_type = SMU_DCLK; break; 2439 case PP_DCLK1: 2440 clk_type = SMU_DCLK1; break; 2441 case OD_SCLK: 2442 clk_type = SMU_OD_SCLK; break; 2443 case OD_MCLK: 2444 clk_type = SMU_OD_MCLK; break; 2445 case OD_VDDC_CURVE: 2446 clk_type = SMU_OD_VDDC_CURVE; break; 2447 case OD_RANGE: 2448 clk_type = SMU_OD_RANGE; break; 2449 case OD_VDDGFX_OFFSET: 2450 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2451 case OD_CCLK: 2452 clk_type = SMU_OD_CCLK; break; 2453 default: 2454 clk_type = SMU_CLK_COUNT; break; 2455 } 2456 2457 return clk_type; 2458 } 2459 2460 static int smu_print_ppclk_levels(void *handle, 2461 enum pp_clock_type type, 2462 char *buf) 2463 { 2464 struct smu_context *smu = handle; 2465 enum smu_clk_type clk_type; 2466 2467 clk_type = smu_convert_to_smuclk(type); 2468 if (clk_type == SMU_CLK_COUNT) 2469 return -EINVAL; 2470 2471 return smu_print_smuclk_levels(smu, clk_type, buf); 2472 } 2473 2474 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2475 { 2476 struct smu_context *smu = handle; 2477 enum smu_clk_type clk_type; 2478 2479 clk_type = smu_convert_to_smuclk(type); 2480 if (clk_type == SMU_CLK_COUNT) 2481 return -EINVAL; 2482 2483 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2484 return -EOPNOTSUPP; 2485 2486 if (!smu->ppt_funcs->emit_clk_levels) 2487 return -ENOENT; 2488 2489 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2490 2491 } 2492 2493 static int smu_od_edit_dpm_table(void *handle, 2494 enum PP_OD_DPM_TABLE_COMMAND type, 2495 long *input, uint32_t size) 2496 { 2497 struct smu_context *smu = handle; 2498 int ret = 0; 2499 2500 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2501 return -EOPNOTSUPP; 2502 2503 if (smu->ppt_funcs->od_edit_dpm_table) { 2504 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2505 } 2506 2507 return ret; 2508 } 2509 2510 static int smu_read_sensor(void *handle, 2511 int sensor, 2512 void *data, 2513 int *size_arg) 2514 { 2515 struct smu_context *smu = handle; 2516 struct smu_umd_pstate_table *pstate_table = 2517 &smu->pstate_table; 2518 int ret = 0; 2519 uint32_t *size, size_val; 2520 2521 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2522 return -EOPNOTSUPP; 2523 2524 if (!data || !size_arg) 2525 return -EINVAL; 2526 2527 size_val = *size_arg; 2528 size = &size_val; 2529 2530 if (smu->ppt_funcs->read_sensor) 2531 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2532 goto unlock; 2533 2534 switch (sensor) { 2535 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2536 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2537 *size = 4; 2538 break; 2539 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2540 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2541 *size = 4; 2542 break; 2543 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2544 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2545 *size = 4; 2546 break; 2547 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2548 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2549 *size = 4; 2550 break; 2551 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2552 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2553 *size = 8; 2554 break; 2555 case AMDGPU_PP_SENSOR_UVD_POWER: 2556 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2557 *size = 4; 2558 break; 2559 case AMDGPU_PP_SENSOR_VCE_POWER: 2560 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2561 *size = 4; 2562 break; 2563 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2564 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2565 *size = 4; 2566 break; 2567 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2568 *(uint32_t *)data = 0; 2569 *size = 4; 2570 break; 2571 default: 2572 *size = 0; 2573 ret = -EOPNOTSUPP; 2574 break; 2575 } 2576 2577 unlock: 2578 // assign uint32_t to int 2579 *size_arg = size_val; 2580 2581 return ret; 2582 } 2583 2584 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 2585 { 2586 int ret = -EINVAL; 2587 struct smu_context *smu = handle; 2588 2589 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 2590 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 2591 2592 return ret; 2593 } 2594 2595 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 2596 { 2597 int ret = -EINVAL; 2598 struct smu_context *smu = handle; 2599 2600 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 2601 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 2602 2603 return ret; 2604 } 2605 2606 static int smu_get_power_profile_mode(void *handle, char *buf) 2607 { 2608 struct smu_context *smu = handle; 2609 2610 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2611 !smu->ppt_funcs->get_power_profile_mode) 2612 return -EOPNOTSUPP; 2613 if (!buf) 2614 return -EINVAL; 2615 2616 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2617 } 2618 2619 static int smu_set_power_profile_mode(void *handle, 2620 long *param, 2621 uint32_t param_size) 2622 { 2623 struct smu_context *smu = handle; 2624 2625 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2626 !smu->ppt_funcs->set_power_profile_mode) 2627 return -EOPNOTSUPP; 2628 2629 return smu_bump_power_profile_mode(smu, param, param_size); 2630 } 2631 2632 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2633 { 2634 struct smu_context *smu = handle; 2635 2636 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2637 return -EOPNOTSUPP; 2638 2639 if (!smu->ppt_funcs->get_fan_control_mode) 2640 return -EOPNOTSUPP; 2641 2642 if (!fan_mode) 2643 return -EINVAL; 2644 2645 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 2646 2647 return 0; 2648 } 2649 2650 static int smu_set_fan_control_mode(void *handle, u32 value) 2651 { 2652 struct smu_context *smu = handle; 2653 int ret = 0; 2654 2655 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2656 return -EOPNOTSUPP; 2657 2658 if (!smu->ppt_funcs->set_fan_control_mode) 2659 return -EOPNOTSUPP; 2660 2661 if (value == U32_MAX) 2662 return -EINVAL; 2663 2664 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2665 if (ret) 2666 goto out; 2667 2668 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2669 smu->user_dpm_profile.fan_mode = value; 2670 2671 /* reset user dpm fan speed */ 2672 if (value != AMD_FAN_CTRL_MANUAL) { 2673 smu->user_dpm_profile.fan_speed_pwm = 0; 2674 smu->user_dpm_profile.fan_speed_rpm = 0; 2675 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2676 } 2677 } 2678 2679 out: 2680 return ret; 2681 } 2682 2683 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2684 { 2685 struct smu_context *smu = handle; 2686 int ret = 0; 2687 2688 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2689 return -EOPNOTSUPP; 2690 2691 if (!smu->ppt_funcs->get_fan_speed_pwm) 2692 return -EOPNOTSUPP; 2693 2694 if (!speed) 2695 return -EINVAL; 2696 2697 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2698 2699 return ret; 2700 } 2701 2702 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2703 { 2704 struct smu_context *smu = handle; 2705 int ret = 0; 2706 2707 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2708 return -EOPNOTSUPP; 2709 2710 if (!smu->ppt_funcs->set_fan_speed_pwm) 2711 return -EOPNOTSUPP; 2712 2713 if (speed == U32_MAX) 2714 return -EINVAL; 2715 2716 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2717 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2718 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2719 smu->user_dpm_profile.fan_speed_pwm = speed; 2720 2721 /* Override custom RPM setting as they cannot co-exist */ 2722 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2723 smu->user_dpm_profile.fan_speed_rpm = 0; 2724 } 2725 2726 return ret; 2727 } 2728 2729 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2730 { 2731 struct smu_context *smu = handle; 2732 int ret = 0; 2733 2734 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2735 return -EOPNOTSUPP; 2736 2737 if (!smu->ppt_funcs->get_fan_speed_rpm) 2738 return -EOPNOTSUPP; 2739 2740 if (!speed) 2741 return -EINVAL; 2742 2743 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2744 2745 return ret; 2746 } 2747 2748 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2749 { 2750 struct smu_context *smu = handle; 2751 2752 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2753 return -EOPNOTSUPP; 2754 2755 return smu_set_min_dcef_deep_sleep(smu, clk); 2756 } 2757 2758 static int smu_get_clock_by_type_with_latency(void *handle, 2759 enum amd_pp_clock_type type, 2760 struct pp_clock_levels_with_latency *clocks) 2761 { 2762 struct smu_context *smu = handle; 2763 enum smu_clk_type clk_type; 2764 int ret = 0; 2765 2766 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2767 return -EOPNOTSUPP; 2768 2769 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2770 switch (type) { 2771 case amd_pp_sys_clock: 2772 clk_type = SMU_GFXCLK; 2773 break; 2774 case amd_pp_mem_clock: 2775 clk_type = SMU_MCLK; 2776 break; 2777 case amd_pp_dcef_clock: 2778 clk_type = SMU_DCEFCLK; 2779 break; 2780 case amd_pp_disp_clock: 2781 clk_type = SMU_DISPCLK; 2782 break; 2783 default: 2784 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2785 return -EINVAL; 2786 } 2787 2788 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2789 } 2790 2791 return ret; 2792 } 2793 2794 static int smu_display_clock_voltage_request(void *handle, 2795 struct pp_display_clock_request *clock_req) 2796 { 2797 struct smu_context *smu = handle; 2798 int ret = 0; 2799 2800 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2801 return -EOPNOTSUPP; 2802 2803 if (smu->ppt_funcs->display_clock_voltage_request) 2804 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2805 2806 return ret; 2807 } 2808 2809 2810 static int smu_display_disable_memory_clock_switch(void *handle, 2811 bool disable_memory_clock_switch) 2812 { 2813 struct smu_context *smu = handle; 2814 int ret = -EINVAL; 2815 2816 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2817 return -EOPNOTSUPP; 2818 2819 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2820 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2821 2822 return ret; 2823 } 2824 2825 static int smu_set_xgmi_pstate(void *handle, 2826 uint32_t pstate) 2827 { 2828 struct smu_context *smu = handle; 2829 int ret = 0; 2830 2831 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2832 return -EOPNOTSUPP; 2833 2834 if (smu->ppt_funcs->set_xgmi_pstate) 2835 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2836 2837 if(ret) 2838 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2839 2840 return ret; 2841 } 2842 2843 static int smu_get_baco_capability(void *handle, bool *cap) 2844 { 2845 struct smu_context *smu = handle; 2846 2847 *cap = false; 2848 2849 if (!smu->pm_enabled) 2850 return 0; 2851 2852 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2853 *cap = smu->ppt_funcs->baco_is_support(smu); 2854 2855 return 0; 2856 } 2857 2858 static int smu_baco_set_state(void *handle, int state) 2859 { 2860 struct smu_context *smu = handle; 2861 int ret = 0; 2862 2863 if (!smu->pm_enabled) 2864 return -EOPNOTSUPP; 2865 2866 if (state == 0) { 2867 if (smu->ppt_funcs->baco_exit) 2868 ret = smu->ppt_funcs->baco_exit(smu); 2869 } else if (state == 1) { 2870 if (smu->ppt_funcs->baco_enter) 2871 ret = smu->ppt_funcs->baco_enter(smu); 2872 } else { 2873 return -EINVAL; 2874 } 2875 2876 if (ret) 2877 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2878 (state)?"enter":"exit"); 2879 2880 return ret; 2881 } 2882 2883 bool smu_mode1_reset_is_support(struct smu_context *smu) 2884 { 2885 bool ret = false; 2886 2887 if (!smu->pm_enabled) 2888 return false; 2889 2890 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2891 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2892 2893 return ret; 2894 } 2895 2896 bool smu_mode2_reset_is_support(struct smu_context *smu) 2897 { 2898 bool ret = false; 2899 2900 if (!smu->pm_enabled) 2901 return false; 2902 2903 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2904 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2905 2906 return ret; 2907 } 2908 2909 int smu_mode1_reset(struct smu_context *smu) 2910 { 2911 int ret = 0; 2912 2913 if (!smu->pm_enabled) 2914 return -EOPNOTSUPP; 2915 2916 if (smu->ppt_funcs->mode1_reset) 2917 ret = smu->ppt_funcs->mode1_reset(smu); 2918 2919 return ret; 2920 } 2921 2922 static int smu_mode2_reset(void *handle) 2923 { 2924 struct smu_context *smu = handle; 2925 int ret = 0; 2926 2927 if (!smu->pm_enabled) 2928 return -EOPNOTSUPP; 2929 2930 if (smu->ppt_funcs->mode2_reset) 2931 ret = smu->ppt_funcs->mode2_reset(smu); 2932 2933 if (ret) 2934 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2935 2936 return ret; 2937 } 2938 2939 static int smu_enable_gfx_features(void *handle) 2940 { 2941 struct smu_context *smu = handle; 2942 int ret = 0; 2943 2944 if (!smu->pm_enabled) 2945 return -EOPNOTSUPP; 2946 2947 if (smu->ppt_funcs->enable_gfx_features) 2948 ret = smu->ppt_funcs->enable_gfx_features(smu); 2949 2950 if (ret) 2951 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 2952 2953 return ret; 2954 } 2955 2956 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2957 struct pp_smu_nv_clock_table *max_clocks) 2958 { 2959 struct smu_context *smu = handle; 2960 int ret = 0; 2961 2962 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2963 return -EOPNOTSUPP; 2964 2965 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2966 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2967 2968 return ret; 2969 } 2970 2971 static int smu_get_uclk_dpm_states(void *handle, 2972 unsigned int *clock_values_in_khz, 2973 unsigned int *num_states) 2974 { 2975 struct smu_context *smu = handle; 2976 int ret = 0; 2977 2978 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2979 return -EOPNOTSUPP; 2980 2981 if (smu->ppt_funcs->get_uclk_dpm_states) 2982 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2983 2984 return ret; 2985 } 2986 2987 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2988 { 2989 struct smu_context *smu = handle; 2990 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2991 2992 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2993 return -EOPNOTSUPP; 2994 2995 if (smu->ppt_funcs->get_current_power_state) 2996 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2997 2998 return pm_state; 2999 } 3000 3001 static int smu_get_dpm_clock_table(void *handle, 3002 struct dpm_clocks *clock_table) 3003 { 3004 struct smu_context *smu = handle; 3005 int ret = 0; 3006 3007 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3008 return -EOPNOTSUPP; 3009 3010 if (smu->ppt_funcs->get_dpm_clock_table) 3011 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3012 3013 return ret; 3014 } 3015 3016 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3017 { 3018 struct smu_context *smu = handle; 3019 3020 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3021 return -EOPNOTSUPP; 3022 3023 if (!smu->ppt_funcs->get_gpu_metrics) 3024 return -EOPNOTSUPP; 3025 3026 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3027 } 3028 3029 static int smu_enable_mgpu_fan_boost(void *handle) 3030 { 3031 struct smu_context *smu = handle; 3032 int ret = 0; 3033 3034 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3035 return -EOPNOTSUPP; 3036 3037 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3038 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3039 3040 return ret; 3041 } 3042 3043 static int smu_gfx_state_change_set(void *handle, 3044 uint32_t state) 3045 { 3046 struct smu_context *smu = handle; 3047 int ret = 0; 3048 3049 if (smu->ppt_funcs->gfx_state_change_set) 3050 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3051 3052 return ret; 3053 } 3054 3055 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3056 { 3057 int ret = 0; 3058 3059 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3060 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3061 3062 return ret; 3063 } 3064 3065 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3066 { 3067 int ret = -EOPNOTSUPP; 3068 3069 if (smu->ppt_funcs && 3070 smu->ppt_funcs->get_ecc_info) 3071 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3072 3073 return ret; 3074 3075 } 3076 3077 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3078 { 3079 struct smu_context *smu = handle; 3080 struct smu_table_context *smu_table = &smu->smu_table; 3081 struct smu_table *memory_pool = &smu_table->memory_pool; 3082 3083 if (!addr || !size) 3084 return -EINVAL; 3085 3086 *addr = NULL; 3087 *size = 0; 3088 if (memory_pool->bo) { 3089 *addr = memory_pool->cpu_addr; 3090 *size = memory_pool->size; 3091 } 3092 3093 return 0; 3094 } 3095 3096 static const struct amd_pm_funcs swsmu_pm_funcs = { 3097 /* export for sysfs */ 3098 .set_fan_control_mode = smu_set_fan_control_mode, 3099 .get_fan_control_mode = smu_get_fan_control_mode, 3100 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3101 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3102 .force_clock_level = smu_force_ppclk_levels, 3103 .print_clock_levels = smu_print_ppclk_levels, 3104 .emit_clock_levels = smu_emit_ppclk_levels, 3105 .force_performance_level = smu_force_performance_level, 3106 .read_sensor = smu_read_sensor, 3107 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3108 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3109 .get_performance_level = smu_get_performance_level, 3110 .get_current_power_state = smu_get_current_power_state, 3111 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3112 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3113 .get_pp_num_states = smu_get_power_num_states, 3114 .get_pp_table = smu_sys_get_pp_table, 3115 .set_pp_table = smu_sys_set_pp_table, 3116 .switch_power_profile = smu_switch_power_profile, 3117 /* export to amdgpu */ 3118 .dispatch_tasks = smu_handle_dpm_task, 3119 .load_firmware = smu_load_microcode, 3120 .set_powergating_by_smu = smu_dpm_set_power_gate, 3121 .set_power_limit = smu_set_power_limit, 3122 .get_power_limit = smu_get_power_limit, 3123 .get_power_profile_mode = smu_get_power_profile_mode, 3124 .set_power_profile_mode = smu_set_power_profile_mode, 3125 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3126 .set_mp1_state = smu_set_mp1_state, 3127 .gfx_state_change_set = smu_gfx_state_change_set, 3128 /* export to DC */ 3129 .get_sclk = smu_get_sclk, 3130 .get_mclk = smu_get_mclk, 3131 .display_configuration_change = smu_display_configuration_change, 3132 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3133 .display_clock_voltage_request = smu_display_clock_voltage_request, 3134 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3135 .set_active_display_count = smu_set_display_count, 3136 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3137 .get_asic_baco_capability = smu_get_baco_capability, 3138 .set_asic_baco_state = smu_baco_set_state, 3139 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3140 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3141 .asic_reset_mode_2 = smu_mode2_reset, 3142 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3143 .set_df_cstate = smu_set_df_cstate, 3144 .set_xgmi_pstate = smu_set_xgmi_pstate, 3145 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3146 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3147 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3148 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3149 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3150 .get_dpm_clock_table = smu_get_dpm_clock_table, 3151 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3152 }; 3153 3154 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3155 uint64_t event_arg) 3156 { 3157 int ret = -EINVAL; 3158 3159 if (smu->ppt_funcs->wait_for_event) 3160 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3161 3162 return ret; 3163 } 3164 3165 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3166 { 3167 3168 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3169 return -EOPNOTSUPP; 3170 3171 /* Confirm the buffer allocated is of correct size */ 3172 if (size != smu->stb_context.stb_buf_size) 3173 return -EINVAL; 3174 3175 /* 3176 * No need to lock smu mutex as we access STB directly through MMIO 3177 * and not going through SMU messaging route (for now at least). 3178 * For registers access rely on implementation internal locking. 3179 */ 3180 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3181 } 3182 3183 #if defined(CONFIG_DEBUG_FS) 3184 3185 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3186 { 3187 struct amdgpu_device *adev = filp->f_inode->i_private; 3188 struct smu_context *smu = adev->powerplay.pp_handle; 3189 unsigned char *buf; 3190 int r; 3191 3192 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3193 if (!buf) 3194 return -ENOMEM; 3195 3196 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3197 if (r) 3198 goto out; 3199 3200 filp->private_data = buf; 3201 3202 return 0; 3203 3204 out: 3205 kvfree(buf); 3206 return r; 3207 } 3208 3209 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3210 loff_t *pos) 3211 { 3212 struct amdgpu_device *adev = filp->f_inode->i_private; 3213 struct smu_context *smu = adev->powerplay.pp_handle; 3214 3215 3216 if (!filp->private_data) 3217 return -EINVAL; 3218 3219 return simple_read_from_buffer(buf, 3220 size, 3221 pos, filp->private_data, 3222 smu->stb_context.stb_buf_size); 3223 } 3224 3225 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3226 { 3227 kvfree(filp->private_data); 3228 filp->private_data = NULL; 3229 3230 return 0; 3231 } 3232 3233 /* 3234 * We have to define not only read method but also 3235 * open and release because .read takes up to PAGE_SIZE 3236 * data each time so and so is invoked multiple times. 3237 * We allocate the STB buffer in .open and release it 3238 * in .release 3239 */ 3240 static const struct file_operations smu_stb_debugfs_fops = { 3241 .owner = THIS_MODULE, 3242 .open = smu_stb_debugfs_open, 3243 .read = smu_stb_debugfs_read, 3244 .release = smu_stb_debugfs_release, 3245 .llseek = default_llseek, 3246 }; 3247 3248 #endif 3249 3250 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3251 { 3252 #if defined(CONFIG_DEBUG_FS) 3253 3254 struct smu_context *smu = adev->powerplay.pp_handle; 3255 3256 if (!smu || (!smu->stb_context.stb_buf_size)) 3257 return; 3258 3259 debugfs_create_file_size("amdgpu_smu_stb_dump", 3260 S_IRUSR, 3261 adev_to_drm(adev)->primary->debugfs_root, 3262 adev, 3263 &smu_stb_debugfs_fops, 3264 smu->stb_context.stb_buf_size); 3265 #endif 3266 } 3267 3268 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3269 { 3270 int ret = 0; 3271 3272 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3273 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3274 3275 return ret; 3276 } 3277 3278 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3279 { 3280 int ret = 0; 3281 3282 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3283 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3284 3285 return ret; 3286 } 3287