1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 76 static int smu_sys_get_pp_feature_mask(void *handle, 77 char *buf) 78 { 79 struct smu_context *smu = handle; 80 81 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 82 return -EOPNOTSUPP; 83 84 return smu_get_pp_feature_mask(smu, buf); 85 } 86 87 static int smu_sys_set_pp_feature_mask(void *handle, 88 uint64_t new_mask) 89 { 90 struct smu_context *smu = handle; 91 92 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 93 return -EOPNOTSUPP; 94 95 return smu_set_pp_feature_mask(smu, new_mask); 96 } 97 98 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 99 { 100 if (!smu->ppt_funcs->set_gfx_off_residency) 101 return -EINVAL; 102 103 return smu_set_gfx_off_residency(smu, value); 104 } 105 106 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 107 { 108 if (!smu->ppt_funcs->get_gfx_off_residency) 109 return -EINVAL; 110 111 return smu_get_gfx_off_residency(smu, value); 112 } 113 114 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 115 { 116 if (!smu->ppt_funcs->get_gfx_off_entrycount) 117 return -EINVAL; 118 119 return smu_get_gfx_off_entrycount(smu, value); 120 } 121 122 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 123 { 124 if (!smu->ppt_funcs->get_gfx_off_status) 125 return -EINVAL; 126 127 *value = smu_get_gfx_off_status(smu); 128 129 return 0; 130 } 131 132 int smu_set_soft_freq_range(struct smu_context *smu, 133 enum smu_clk_type clk_type, 134 uint32_t min, 135 uint32_t max) 136 { 137 int ret = 0; 138 139 if (smu->ppt_funcs->set_soft_freq_limited_range) 140 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 141 clk_type, 142 min, 143 max); 144 145 return ret; 146 } 147 148 int smu_get_dpm_freq_range(struct smu_context *smu, 149 enum smu_clk_type clk_type, 150 uint32_t *min, 151 uint32_t *max) 152 { 153 int ret = -ENOTSUPP; 154 155 if (!min && !max) 156 return -EINVAL; 157 158 if (smu->ppt_funcs->get_dpm_ultimate_freq) 159 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 160 clk_type, 161 min, 162 max); 163 164 return ret; 165 } 166 167 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 168 { 169 int ret = 0; 170 struct amdgpu_device *adev = smu->adev; 171 172 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 173 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 174 if (ret) 175 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 176 } 177 return ret; 178 } 179 180 static u32 smu_get_mclk(void *handle, bool low) 181 { 182 struct smu_context *smu = handle; 183 uint32_t clk_freq; 184 int ret = 0; 185 186 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 187 low ? &clk_freq : NULL, 188 !low ? &clk_freq : NULL); 189 if (ret) 190 return 0; 191 return clk_freq * 100; 192 } 193 194 static u32 smu_get_sclk(void *handle, bool low) 195 { 196 struct smu_context *smu = handle; 197 uint32_t clk_freq; 198 int ret = 0; 199 200 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 201 low ? &clk_freq : NULL, 202 !low ? &clk_freq : NULL); 203 if (ret) 204 return 0; 205 return clk_freq * 100; 206 } 207 208 static int smu_set_gfx_imu_enable(struct smu_context *smu) 209 { 210 struct amdgpu_device *adev = smu->adev; 211 212 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 213 return 0; 214 215 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 216 return 0; 217 218 return smu_set_gfx_power_up_by_imu(smu); 219 } 220 221 static bool is_vcn_enabled(struct amdgpu_device *adev) 222 { 223 int i; 224 225 for (i = 0; i < adev->num_ip_blocks; i++) { 226 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 227 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 228 !adev->ip_blocks[i].status.valid) 229 return false; 230 } 231 232 return true; 233 } 234 235 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 236 bool enable) 237 { 238 struct smu_power_context *smu_power = &smu->smu_power; 239 struct smu_power_gate *power_gate = &smu_power->power_gate; 240 int ret = 0; 241 242 /* 243 * don't poweron vcn/jpeg when they are skipped. 244 */ 245 if (!is_vcn_enabled(smu->adev)) 246 return 0; 247 248 if (!smu->ppt_funcs->dpm_set_vcn_enable) 249 return 0; 250 251 if (atomic_read(&power_gate->vcn_gated) ^ enable) 252 return 0; 253 254 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 255 if (!ret) 256 atomic_set(&power_gate->vcn_gated, !enable); 257 258 return ret; 259 } 260 261 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 262 bool enable) 263 { 264 struct smu_power_context *smu_power = &smu->smu_power; 265 struct smu_power_gate *power_gate = &smu_power->power_gate; 266 int ret = 0; 267 268 if (!is_vcn_enabled(smu->adev)) 269 return 0; 270 271 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 272 return 0; 273 274 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 275 return 0; 276 277 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 278 if (!ret) 279 atomic_set(&power_gate->jpeg_gated, !enable); 280 281 return ret; 282 } 283 284 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 285 bool enable) 286 { 287 struct smu_power_context *smu_power = &smu->smu_power; 288 struct smu_power_gate *power_gate = &smu_power->power_gate; 289 int ret = 0; 290 291 if (!smu->ppt_funcs->dpm_set_vpe_enable) 292 return 0; 293 294 if (atomic_read(&power_gate->vpe_gated) ^ enable) 295 return 0; 296 297 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 298 if (!ret) 299 atomic_set(&power_gate->vpe_gated, !enable); 300 301 return ret; 302 } 303 304 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 305 bool enable) 306 { 307 struct smu_power_context *smu_power = &smu->smu_power; 308 struct smu_power_gate *power_gate = &smu_power->power_gate; 309 int ret = 0; 310 311 if (!smu->adev->enable_umsch_mm) 312 return 0; 313 314 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 315 return 0; 316 317 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 318 return 0; 319 320 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 321 if (!ret) 322 atomic_set(&power_gate->umsch_mm_gated, !enable); 323 324 return ret; 325 } 326 327 static int smu_set_mall_enable(struct smu_context *smu) 328 { 329 int ret = 0; 330 331 if (!smu->ppt_funcs->set_mall_enable) 332 return 0; 333 334 ret = smu->ppt_funcs->set_mall_enable(smu); 335 336 return ret; 337 } 338 339 /** 340 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 341 * 342 * @handle: smu_context pointer 343 * @block_type: the IP block to power gate/ungate 344 * @gate: to power gate if true, ungate otherwise 345 * 346 * This API uses no smu->mutex lock protection due to: 347 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 348 * This is guarded to be race condition free by the caller. 349 * 2. Or get called on user setting request of power_dpm_force_performance_level. 350 * Under this case, the smu->mutex lock protection is already enforced on 351 * the parent API smu_force_performance_level of the call path. 352 */ 353 static int smu_dpm_set_power_gate(void *handle, 354 uint32_t block_type, 355 bool gate) 356 { 357 struct smu_context *smu = handle; 358 int ret = 0; 359 360 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 361 dev_WARN(smu->adev->dev, 362 "SMU uninitialized but power %s requested for %u!\n", 363 gate ? "gate" : "ungate", block_type); 364 return -EOPNOTSUPP; 365 } 366 367 switch (block_type) { 368 /* 369 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 370 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 371 */ 372 case AMD_IP_BLOCK_TYPE_UVD: 373 case AMD_IP_BLOCK_TYPE_VCN: 374 ret = smu_dpm_set_vcn_enable(smu, !gate); 375 if (ret) 376 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 377 gate ? "gate" : "ungate"); 378 break; 379 case AMD_IP_BLOCK_TYPE_GFX: 380 ret = smu_gfx_off_control(smu, gate); 381 if (ret) 382 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 383 gate ? "enable" : "disable"); 384 break; 385 case AMD_IP_BLOCK_TYPE_SDMA: 386 ret = smu_powergate_sdma(smu, gate); 387 if (ret) 388 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 389 gate ? "gate" : "ungate"); 390 break; 391 case AMD_IP_BLOCK_TYPE_JPEG: 392 ret = smu_dpm_set_jpeg_enable(smu, !gate); 393 if (ret) 394 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 395 gate ? "gate" : "ungate"); 396 break; 397 case AMD_IP_BLOCK_TYPE_VPE: 398 ret = smu_dpm_set_vpe_enable(smu, !gate); 399 if (ret) 400 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 401 gate ? "gate" : "ungate"); 402 break; 403 default: 404 dev_err(smu->adev->dev, "Unsupported block type!\n"); 405 return -EINVAL; 406 } 407 408 return ret; 409 } 410 411 /** 412 * smu_set_user_clk_dependencies - set user profile clock dependencies 413 * 414 * @smu: smu_context pointer 415 * @clk: enum smu_clk_type type 416 * 417 * Enable/Disable the clock dependency for the @clk type. 418 */ 419 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 420 { 421 if (smu->adev->in_suspend) 422 return; 423 424 if (clk == SMU_MCLK) { 425 smu->user_dpm_profile.clk_dependency = 0; 426 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 427 } else if (clk == SMU_FCLK) { 428 /* MCLK takes precedence over FCLK */ 429 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 430 return; 431 432 smu->user_dpm_profile.clk_dependency = 0; 433 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 434 } else if (clk == SMU_SOCCLK) { 435 /* MCLK takes precedence over SOCCLK */ 436 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 437 return; 438 439 smu->user_dpm_profile.clk_dependency = 0; 440 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 441 } else 442 /* Add clk dependencies here, if any */ 443 return; 444 } 445 446 /** 447 * smu_restore_dpm_user_profile - reinstate user dpm profile 448 * 449 * @smu: smu_context pointer 450 * 451 * Restore the saved user power configurations include power limit, 452 * clock frequencies, fan control mode and fan speed. 453 */ 454 static void smu_restore_dpm_user_profile(struct smu_context *smu) 455 { 456 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 457 int ret = 0; 458 459 if (!smu->adev->in_suspend) 460 return; 461 462 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 463 return; 464 465 /* Enable restore flag */ 466 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 467 468 /* set the user dpm power limit */ 469 if (smu->user_dpm_profile.power_limit) { 470 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 471 if (ret) 472 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 473 } 474 475 /* set the user dpm clock configurations */ 476 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 477 enum smu_clk_type clk_type; 478 479 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 480 /* 481 * Iterate over smu clk type and force the saved user clk 482 * configs, skip if clock dependency is enabled 483 */ 484 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 485 smu->user_dpm_profile.clk_mask[clk_type]) { 486 ret = smu_force_smuclk_levels(smu, clk_type, 487 smu->user_dpm_profile.clk_mask[clk_type]); 488 if (ret) 489 dev_err(smu->adev->dev, 490 "Failed to set clock type = %d\n", clk_type); 491 } 492 } 493 } 494 495 /* set the user dpm fan configurations */ 496 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 497 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 498 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 499 if (ret != -EOPNOTSUPP) { 500 smu->user_dpm_profile.fan_speed_pwm = 0; 501 smu->user_dpm_profile.fan_speed_rpm = 0; 502 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 503 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 504 } 505 506 if (smu->user_dpm_profile.fan_speed_pwm) { 507 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 508 if (ret != -EOPNOTSUPP) 509 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 510 } 511 512 if (smu->user_dpm_profile.fan_speed_rpm) { 513 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 514 if (ret != -EOPNOTSUPP) 515 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 516 } 517 } 518 519 /* Restore user customized OD settings */ 520 if (smu->user_dpm_profile.user_od) { 521 if (smu->ppt_funcs->restore_user_od_settings) { 522 ret = smu->ppt_funcs->restore_user_od_settings(smu); 523 if (ret) 524 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 525 } 526 } 527 528 /* Disable restore flag */ 529 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 530 } 531 532 static int smu_get_power_num_states(void *handle, 533 struct pp_states_info *state_info) 534 { 535 if (!state_info) 536 return -EINVAL; 537 538 /* not support power state */ 539 memset(state_info, 0, sizeof(struct pp_states_info)); 540 state_info->nums = 1; 541 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 542 543 return 0; 544 } 545 546 bool is_support_sw_smu(struct amdgpu_device *adev) 547 { 548 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 549 if (adev->asic_type == CHIP_VEGA20) 550 return false; 551 552 if (amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) 553 return true; 554 555 return false; 556 } 557 558 bool is_support_cclk_dpm(struct amdgpu_device *adev) 559 { 560 struct smu_context *smu = adev->powerplay.pp_handle; 561 562 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 563 return false; 564 565 return true; 566 } 567 568 569 static int smu_sys_get_pp_table(void *handle, 570 char **table) 571 { 572 struct smu_context *smu = handle; 573 struct smu_table_context *smu_table = &smu->smu_table; 574 575 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 576 return -EOPNOTSUPP; 577 578 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 579 return -EINVAL; 580 581 if (smu_table->hardcode_pptable) 582 *table = smu_table->hardcode_pptable; 583 else 584 *table = smu_table->power_play_table; 585 586 return smu_table->power_play_table_size; 587 } 588 589 static int smu_sys_set_pp_table(void *handle, 590 const char *buf, 591 size_t size) 592 { 593 struct smu_context *smu = handle; 594 struct smu_table_context *smu_table = &smu->smu_table; 595 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 596 int ret = 0; 597 598 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 599 return -EOPNOTSUPP; 600 601 if (header->usStructureSize != size) { 602 dev_err(smu->adev->dev, "pp table size not matched !\n"); 603 return -EIO; 604 } 605 606 if (!smu_table->hardcode_pptable) { 607 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 608 if (!smu_table->hardcode_pptable) 609 return -ENOMEM; 610 } 611 612 memcpy(smu_table->hardcode_pptable, buf, size); 613 smu_table->power_play_table = smu_table->hardcode_pptable; 614 smu_table->power_play_table_size = size; 615 616 /* 617 * Special hw_fini action(for Navi1x, the DPMs disablement will be 618 * skipped) may be needed for custom pptable uploading. 619 */ 620 smu->uploading_custom_pp_table = true; 621 622 ret = smu_reset(smu); 623 if (ret) 624 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 625 626 smu->uploading_custom_pp_table = false; 627 628 return ret; 629 } 630 631 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 632 { 633 struct smu_feature *feature = &smu->smu_feature; 634 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 635 int ret = 0; 636 637 /* 638 * With SCPM enabled, the allowed featuremasks setting(via 639 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 640 * That means there is no way to let PMFW knows the settings below. 641 * Thus, we just assume all the features are allowed under 642 * such scenario. 643 */ 644 if (smu->adev->scpm_enabled) { 645 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 646 return 0; 647 } 648 649 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 650 651 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 652 SMU_FEATURE_MAX/32); 653 if (ret) 654 return ret; 655 656 bitmap_or(feature->allowed, feature->allowed, 657 (unsigned long *)allowed_feature_mask, 658 feature->feature_num); 659 660 return ret; 661 } 662 663 static int smu_set_funcs(struct amdgpu_device *adev) 664 { 665 struct smu_context *smu = adev->powerplay.pp_handle; 666 667 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 668 smu->od_enabled = true; 669 670 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 671 case IP_VERSION(11, 0, 0): 672 case IP_VERSION(11, 0, 5): 673 case IP_VERSION(11, 0, 9): 674 navi10_set_ppt_funcs(smu); 675 break; 676 case IP_VERSION(11, 0, 7): 677 case IP_VERSION(11, 0, 11): 678 case IP_VERSION(11, 0, 12): 679 case IP_VERSION(11, 0, 13): 680 sienna_cichlid_set_ppt_funcs(smu); 681 break; 682 case IP_VERSION(12, 0, 0): 683 case IP_VERSION(12, 0, 1): 684 renoir_set_ppt_funcs(smu); 685 break; 686 case IP_VERSION(11, 5, 0): 687 vangogh_set_ppt_funcs(smu); 688 break; 689 case IP_VERSION(13, 0, 1): 690 case IP_VERSION(13, 0, 3): 691 case IP_VERSION(13, 0, 8): 692 yellow_carp_set_ppt_funcs(smu); 693 break; 694 case IP_VERSION(13, 0, 4): 695 case IP_VERSION(13, 0, 11): 696 smu_v13_0_4_set_ppt_funcs(smu); 697 break; 698 case IP_VERSION(13, 0, 5): 699 smu_v13_0_5_set_ppt_funcs(smu); 700 break; 701 case IP_VERSION(11, 0, 8): 702 cyan_skillfish_set_ppt_funcs(smu); 703 break; 704 case IP_VERSION(11, 0, 2): 705 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 706 arcturus_set_ppt_funcs(smu); 707 /* OD is not supported on Arcturus */ 708 smu->od_enabled = false; 709 break; 710 case IP_VERSION(13, 0, 2): 711 aldebaran_set_ppt_funcs(smu); 712 /* Enable pp_od_clk_voltage node */ 713 smu->od_enabled = true; 714 break; 715 case IP_VERSION(13, 0, 0): 716 case IP_VERSION(13, 0, 10): 717 smu_v13_0_0_set_ppt_funcs(smu); 718 break; 719 case IP_VERSION(13, 0, 6): 720 case IP_VERSION(13, 0, 14): 721 smu_v13_0_6_set_ppt_funcs(smu); 722 /* Enable pp_od_clk_voltage node */ 723 smu->od_enabled = true; 724 break; 725 case IP_VERSION(13, 0, 7): 726 smu_v13_0_7_set_ppt_funcs(smu); 727 break; 728 case IP_VERSION(14, 0, 0): 729 case IP_VERSION(14, 0, 1): 730 case IP_VERSION(14, 0, 4): 731 smu_v14_0_0_set_ppt_funcs(smu); 732 break; 733 case IP_VERSION(14, 0, 2): 734 case IP_VERSION(14, 0, 3): 735 smu_v14_0_2_set_ppt_funcs(smu); 736 break; 737 default: 738 return -EINVAL; 739 } 740 741 return 0; 742 } 743 744 static int smu_early_init(void *handle) 745 { 746 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 747 struct smu_context *smu; 748 int r; 749 750 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 751 if (!smu) 752 return -ENOMEM; 753 754 smu->adev = adev; 755 smu->pm_enabled = !!amdgpu_dpm; 756 smu->is_apu = false; 757 smu->smu_baco.state = SMU_BACO_STATE_NONE; 758 smu->smu_baco.platform_support = false; 759 smu->smu_baco.maco_support = false; 760 smu->user_dpm_profile.fan_mode = -1; 761 762 mutex_init(&smu->message_lock); 763 764 adev->powerplay.pp_handle = smu; 765 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 766 767 r = smu_set_funcs(adev); 768 if (r) 769 return r; 770 return smu_init_microcode(smu); 771 } 772 773 static int smu_set_default_dpm_table(struct smu_context *smu) 774 { 775 struct amdgpu_device *adev = smu->adev; 776 struct smu_power_context *smu_power = &smu->smu_power; 777 struct smu_power_gate *power_gate = &smu_power->power_gate; 778 int vcn_gate, jpeg_gate; 779 int ret = 0; 780 781 if (!smu->ppt_funcs->set_default_dpm_table) 782 return 0; 783 784 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 785 vcn_gate = atomic_read(&power_gate->vcn_gated); 786 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 787 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 788 789 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 790 ret = smu_dpm_set_vcn_enable(smu, true); 791 if (ret) 792 return ret; 793 } 794 795 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 796 ret = smu_dpm_set_jpeg_enable(smu, true); 797 if (ret) 798 goto err_out; 799 } 800 801 ret = smu->ppt_funcs->set_default_dpm_table(smu); 802 if (ret) 803 dev_err(smu->adev->dev, 804 "Failed to setup default dpm clock tables!\n"); 805 806 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 807 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 808 err_out: 809 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 810 smu_dpm_set_vcn_enable(smu, !vcn_gate); 811 812 return ret; 813 } 814 815 static int smu_apply_default_config_table_settings(struct smu_context *smu) 816 { 817 struct amdgpu_device *adev = smu->adev; 818 int ret = 0; 819 820 ret = smu_get_default_config_table_settings(smu, 821 &adev->pm.config_table); 822 if (ret) 823 return ret; 824 825 return smu_set_config_table(smu, &adev->pm.config_table); 826 } 827 828 static int smu_late_init(void *handle) 829 { 830 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 831 struct smu_context *smu = adev->powerplay.pp_handle; 832 int ret = 0; 833 834 smu_set_fine_grain_gfx_freq_parameters(smu); 835 836 if (!smu->pm_enabled) 837 return 0; 838 839 ret = smu_post_init(smu); 840 if (ret) { 841 dev_err(adev->dev, "Failed to post smu init!\n"); 842 return ret; 843 } 844 845 /* 846 * Explicitly notify PMFW the power mode the system in. Since 847 * the PMFW may boot the ASIC with a different mode. 848 * For those supporting ACDC switch via gpio, PMFW will 849 * handle the switch automatically. Driver involvement 850 * is unnecessary. 851 */ 852 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 853 smu_set_ac_dc(smu); 854 855 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 856 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 857 return 0; 858 859 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 860 ret = smu_set_default_od_settings(smu); 861 if (ret) { 862 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 863 return ret; 864 } 865 } 866 867 ret = smu_populate_umd_state_clk(smu); 868 if (ret) { 869 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 870 return ret; 871 } 872 873 ret = smu_get_asic_power_limits(smu, 874 &smu->current_power_limit, 875 &smu->default_power_limit, 876 &smu->max_power_limit, 877 &smu->min_power_limit); 878 if (ret) { 879 dev_err(adev->dev, "Failed to get asic power limits!\n"); 880 return ret; 881 } 882 883 if (!amdgpu_sriov_vf(adev)) 884 smu_get_unique_id(smu); 885 886 smu_get_fan_parameters(smu); 887 888 smu_handle_task(smu, 889 smu->smu_dpm.dpm_level, 890 AMD_PP_TASK_COMPLETE_INIT); 891 892 ret = smu_apply_default_config_table_settings(smu); 893 if (ret && (ret != -EOPNOTSUPP)) { 894 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 895 return ret; 896 } 897 898 smu_restore_dpm_user_profile(smu); 899 900 return 0; 901 } 902 903 static int smu_init_fb_allocations(struct smu_context *smu) 904 { 905 struct amdgpu_device *adev = smu->adev; 906 struct smu_table_context *smu_table = &smu->smu_table; 907 struct smu_table *tables = smu_table->tables; 908 struct smu_table *driver_table = &(smu_table->driver_table); 909 uint32_t max_table_size = 0; 910 int ret, i; 911 912 /* VRAM allocation for tool table */ 913 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 914 ret = amdgpu_bo_create_kernel(adev, 915 tables[SMU_TABLE_PMSTATUSLOG].size, 916 tables[SMU_TABLE_PMSTATUSLOG].align, 917 tables[SMU_TABLE_PMSTATUSLOG].domain, 918 &tables[SMU_TABLE_PMSTATUSLOG].bo, 919 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 920 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 921 if (ret) { 922 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 923 return ret; 924 } 925 } 926 927 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 928 /* VRAM allocation for driver table */ 929 for (i = 0; i < SMU_TABLE_COUNT; i++) { 930 if (tables[i].size == 0) 931 continue; 932 933 /* If one of the tables has VRAM domain restriction, keep it in 934 * VRAM 935 */ 936 if ((tables[i].domain & 937 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 938 AMDGPU_GEM_DOMAIN_VRAM) 939 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 940 941 if (i == SMU_TABLE_PMSTATUSLOG) 942 continue; 943 944 if (max_table_size < tables[i].size) 945 max_table_size = tables[i].size; 946 } 947 948 driver_table->size = max_table_size; 949 driver_table->align = PAGE_SIZE; 950 951 ret = amdgpu_bo_create_kernel(adev, 952 driver_table->size, 953 driver_table->align, 954 driver_table->domain, 955 &driver_table->bo, 956 &driver_table->mc_address, 957 &driver_table->cpu_addr); 958 if (ret) { 959 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 960 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 961 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 962 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 963 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 964 } 965 966 return ret; 967 } 968 969 static int smu_fini_fb_allocations(struct smu_context *smu) 970 { 971 struct smu_table_context *smu_table = &smu->smu_table; 972 struct smu_table *tables = smu_table->tables; 973 struct smu_table *driver_table = &(smu_table->driver_table); 974 975 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 976 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 977 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 978 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 979 980 amdgpu_bo_free_kernel(&driver_table->bo, 981 &driver_table->mc_address, 982 &driver_table->cpu_addr); 983 984 return 0; 985 } 986 987 /** 988 * smu_alloc_memory_pool - allocate memory pool in the system memory 989 * 990 * @smu: amdgpu_device pointer 991 * 992 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 993 * and DramLogSetDramAddr can notify it changed. 994 * 995 * Returns 0 on success, error on failure. 996 */ 997 static int smu_alloc_memory_pool(struct smu_context *smu) 998 { 999 struct amdgpu_device *adev = smu->adev; 1000 struct smu_table_context *smu_table = &smu->smu_table; 1001 struct smu_table *memory_pool = &smu_table->memory_pool; 1002 uint64_t pool_size = smu->pool_size; 1003 int ret = 0; 1004 1005 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1006 return ret; 1007 1008 memory_pool->size = pool_size; 1009 memory_pool->align = PAGE_SIZE; 1010 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 1011 1012 switch (pool_size) { 1013 case SMU_MEMORY_POOL_SIZE_256_MB: 1014 case SMU_MEMORY_POOL_SIZE_512_MB: 1015 case SMU_MEMORY_POOL_SIZE_1_GB: 1016 case SMU_MEMORY_POOL_SIZE_2_GB: 1017 ret = amdgpu_bo_create_kernel(adev, 1018 memory_pool->size, 1019 memory_pool->align, 1020 memory_pool->domain, 1021 &memory_pool->bo, 1022 &memory_pool->mc_address, 1023 &memory_pool->cpu_addr); 1024 if (ret) 1025 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1026 break; 1027 default: 1028 break; 1029 } 1030 1031 return ret; 1032 } 1033 1034 static int smu_free_memory_pool(struct smu_context *smu) 1035 { 1036 struct smu_table_context *smu_table = &smu->smu_table; 1037 struct smu_table *memory_pool = &smu_table->memory_pool; 1038 1039 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1040 return 0; 1041 1042 amdgpu_bo_free_kernel(&memory_pool->bo, 1043 &memory_pool->mc_address, 1044 &memory_pool->cpu_addr); 1045 1046 memset(memory_pool, 0, sizeof(struct smu_table)); 1047 1048 return 0; 1049 } 1050 1051 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1052 { 1053 struct smu_table_context *smu_table = &smu->smu_table; 1054 struct smu_table *dummy_read_1_table = 1055 &smu_table->dummy_read_1_table; 1056 struct amdgpu_device *adev = smu->adev; 1057 int ret = 0; 1058 1059 if (!dummy_read_1_table->size) 1060 return 0; 1061 1062 ret = amdgpu_bo_create_kernel(adev, 1063 dummy_read_1_table->size, 1064 dummy_read_1_table->align, 1065 dummy_read_1_table->domain, 1066 &dummy_read_1_table->bo, 1067 &dummy_read_1_table->mc_address, 1068 &dummy_read_1_table->cpu_addr); 1069 if (ret) 1070 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1071 1072 return ret; 1073 } 1074 1075 static void smu_free_dummy_read_table(struct smu_context *smu) 1076 { 1077 struct smu_table_context *smu_table = &smu->smu_table; 1078 struct smu_table *dummy_read_1_table = 1079 &smu_table->dummy_read_1_table; 1080 1081 1082 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1083 &dummy_read_1_table->mc_address, 1084 &dummy_read_1_table->cpu_addr); 1085 1086 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1087 } 1088 1089 static int smu_smc_table_sw_init(struct smu_context *smu) 1090 { 1091 int ret; 1092 1093 /** 1094 * Create smu_table structure, and init smc tables such as 1095 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1096 */ 1097 ret = smu_init_smc_tables(smu); 1098 if (ret) { 1099 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1100 return ret; 1101 } 1102 1103 /** 1104 * Create smu_power_context structure, and allocate smu_dpm_context and 1105 * context size to fill the smu_power_context data. 1106 */ 1107 ret = smu_init_power(smu); 1108 if (ret) { 1109 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1110 return ret; 1111 } 1112 1113 /* 1114 * allocate vram bos to store smc table contents. 1115 */ 1116 ret = smu_init_fb_allocations(smu); 1117 if (ret) 1118 return ret; 1119 1120 ret = smu_alloc_memory_pool(smu); 1121 if (ret) 1122 return ret; 1123 1124 ret = smu_alloc_dummy_read_table(smu); 1125 if (ret) 1126 return ret; 1127 1128 ret = smu_i2c_init(smu); 1129 if (ret) 1130 return ret; 1131 1132 return 0; 1133 } 1134 1135 static int smu_smc_table_sw_fini(struct smu_context *smu) 1136 { 1137 int ret; 1138 1139 smu_i2c_fini(smu); 1140 1141 smu_free_dummy_read_table(smu); 1142 1143 ret = smu_free_memory_pool(smu); 1144 if (ret) 1145 return ret; 1146 1147 ret = smu_fini_fb_allocations(smu); 1148 if (ret) 1149 return ret; 1150 1151 ret = smu_fini_power(smu); 1152 if (ret) { 1153 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1154 return ret; 1155 } 1156 1157 ret = smu_fini_smc_tables(smu); 1158 if (ret) { 1159 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1160 return ret; 1161 } 1162 1163 return 0; 1164 } 1165 1166 static void smu_throttling_logging_work_fn(struct work_struct *work) 1167 { 1168 struct smu_context *smu = container_of(work, struct smu_context, 1169 throttling_logging_work); 1170 1171 smu_log_thermal_throttling(smu); 1172 } 1173 1174 static void smu_interrupt_work_fn(struct work_struct *work) 1175 { 1176 struct smu_context *smu = container_of(work, struct smu_context, 1177 interrupt_work); 1178 1179 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1180 smu->ppt_funcs->interrupt_work(smu); 1181 } 1182 1183 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1184 { 1185 struct smu_context *smu = 1186 container_of(work, struct smu_context, swctf_delayed_work.work); 1187 struct smu_temperature_range *range = 1188 &smu->thermal_range; 1189 struct amdgpu_device *adev = smu->adev; 1190 uint32_t hotspot_tmp, size; 1191 1192 /* 1193 * If the hotspot temperature is confirmed as below SW CTF setting point 1194 * after the delay enforced, nothing will be done. 1195 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1196 */ 1197 if (range->software_shutdown_temp && 1198 smu->ppt_funcs->read_sensor && 1199 !smu->ppt_funcs->read_sensor(smu, 1200 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1201 &hotspot_tmp, 1202 &size) && 1203 hotspot_tmp / 1000 < range->software_shutdown_temp) 1204 return; 1205 1206 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1207 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1208 orderly_poweroff(true); 1209 } 1210 1211 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1212 { 1213 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1214 struct smu_dpm_policy_ctxt *policy_ctxt; 1215 struct smu_dpm_policy *policy; 1216 1217 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1218 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1219 if (policy) 1220 policy->current_level = XGMI_PLPD_DEFAULT; 1221 return; 1222 } 1223 1224 /* PMFW put PLPD into default policy after enabling the feature */ 1225 if (smu_feature_is_enabled(smu, 1226 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1227 if (policy) 1228 policy->current_level = XGMI_PLPD_DEFAULT; 1229 } else { 1230 policy_ctxt = dpm_ctxt->dpm_policies; 1231 if (policy_ctxt) 1232 policy_ctxt->policy_mask &= 1233 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1234 } 1235 } 1236 1237 static int smu_sw_init(void *handle) 1238 { 1239 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1240 struct smu_context *smu = adev->powerplay.pp_handle; 1241 int ret; 1242 1243 smu->pool_size = adev->pm.smu_prv_buffer_size; 1244 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1245 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1246 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1247 1248 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1249 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1250 atomic64_set(&smu->throttle_int_counter, 0); 1251 smu->watermarks_bitmap = 0; 1252 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1253 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1254 1255 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1256 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1257 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1258 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1259 1260 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1261 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1262 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1263 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1264 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1265 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1266 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1267 1268 if (smu->is_apu) 1269 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1270 else 1271 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D]; 1272 1273 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1274 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1275 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1276 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1277 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1278 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1279 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1280 smu->display_config = &adev->pm.pm_display_cfg; 1281 1282 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1283 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1284 1285 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1286 smu_swctf_delayed_work_handler); 1287 1288 ret = smu_smc_table_sw_init(smu); 1289 if (ret) { 1290 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1291 return ret; 1292 } 1293 1294 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1295 ret = smu_get_vbios_bootup_values(smu); 1296 if (ret) { 1297 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1298 return ret; 1299 } 1300 1301 ret = smu_init_pptable_microcode(smu); 1302 if (ret) { 1303 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1304 return ret; 1305 } 1306 1307 ret = smu_register_irq_handler(smu); 1308 if (ret) { 1309 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1310 return ret; 1311 } 1312 1313 /* If there is no way to query fan control mode, fan control is not supported */ 1314 if (!smu->ppt_funcs->get_fan_control_mode) 1315 smu->adev->pm.no_fan = true; 1316 1317 return 0; 1318 } 1319 1320 static int smu_sw_fini(void *handle) 1321 { 1322 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1323 struct smu_context *smu = adev->powerplay.pp_handle; 1324 int ret; 1325 1326 ret = smu_smc_table_sw_fini(smu); 1327 if (ret) { 1328 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1329 return ret; 1330 } 1331 1332 smu_fini_microcode(smu); 1333 1334 return 0; 1335 } 1336 1337 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1338 { 1339 struct amdgpu_device *adev = smu->adev; 1340 struct smu_temperature_range *range = 1341 &smu->thermal_range; 1342 int ret = 0; 1343 1344 if (!smu->ppt_funcs->get_thermal_temperature_range) 1345 return 0; 1346 1347 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1348 if (ret) 1349 return ret; 1350 1351 adev->pm.dpm.thermal.min_temp = range->min; 1352 adev->pm.dpm.thermal.max_temp = range->max; 1353 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1354 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1355 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1356 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1357 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1358 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1359 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1360 1361 return ret; 1362 } 1363 1364 /** 1365 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1366 * 1367 * @smu: smu_context pointer 1368 * 1369 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1370 * Returns 0 on success, error on failure. 1371 */ 1372 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1373 { 1374 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1375 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1376 struct amdgpu_device *adev = smu->adev; 1377 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1378 uint64_t start, end; 1379 int ret, i, j; 1380 1381 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1382 if (ret) { 1383 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1384 return ret; 1385 } 1386 1387 /* 1388 * The exclusion ranges array we got might be filled with holes and duplicate 1389 * entries. For example: 1390 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1391 * We need to do some sortups to eliminate those holes and duplicate entries. 1392 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1393 */ 1394 for (i = 0; i < num_of_wbrf_ranges; i++) { 1395 start = wifi_bands[i].start; 1396 end = wifi_bands[i].end; 1397 1398 /* get the last valid entry to fill the intermediate hole */ 1399 if (!start && !end) { 1400 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1401 if (wifi_bands[j].start && wifi_bands[j].end) 1402 break; 1403 1404 /* no valid entry left */ 1405 if (j <= i) 1406 break; 1407 1408 start = wifi_bands[i].start = wifi_bands[j].start; 1409 end = wifi_bands[i].end = wifi_bands[j].end; 1410 wifi_bands[j].start = 0; 1411 wifi_bands[j].end = 0; 1412 num_of_wbrf_ranges = j; 1413 } 1414 1415 /* eliminate duplicate entries */ 1416 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1417 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1418 wifi_bands[j].start = 0; 1419 wifi_bands[j].end = 0; 1420 } 1421 } 1422 } 1423 1424 /* Send the sorted wifi_bands to PMFW */ 1425 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1426 /* Try to set the wifi_bands again */ 1427 if (unlikely(ret == -EBUSY)) { 1428 mdelay(5); 1429 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1430 } 1431 1432 return ret; 1433 } 1434 1435 /** 1436 * smu_wbrf_event_handler - handle notify events 1437 * 1438 * @nb: notifier block 1439 * @action: event type 1440 * @_arg: event data 1441 * 1442 * Calls relevant amdgpu function in response to wbrf event 1443 * notification from kernel. 1444 */ 1445 static int smu_wbrf_event_handler(struct notifier_block *nb, 1446 unsigned long action, void *_arg) 1447 { 1448 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1449 1450 switch (action) { 1451 case WBRF_CHANGED: 1452 schedule_delayed_work(&smu->wbrf_delayed_work, 1453 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1454 break; 1455 default: 1456 return NOTIFY_DONE; 1457 } 1458 1459 return NOTIFY_OK; 1460 } 1461 1462 /** 1463 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1464 * 1465 * @work: struct work_struct pointer 1466 * 1467 * Flood is over and driver will consume the latest exclusion ranges. 1468 */ 1469 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1470 { 1471 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1472 1473 smu_wbrf_handle_exclusion_ranges(smu); 1474 } 1475 1476 /** 1477 * smu_wbrf_support_check - check wbrf support 1478 * 1479 * @smu: smu_context pointer 1480 * 1481 * Verifies the ACPI interface whether wbrf is supported. 1482 */ 1483 static void smu_wbrf_support_check(struct smu_context *smu) 1484 { 1485 struct amdgpu_device *adev = smu->adev; 1486 1487 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1488 acpi_amd_wbrf_supported_consumer(adev->dev); 1489 1490 if (smu->wbrf_supported) 1491 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1492 } 1493 1494 /** 1495 * smu_wbrf_init - init driver wbrf support 1496 * 1497 * @smu: smu_context pointer 1498 * 1499 * Verifies the AMD ACPI interfaces and registers with the wbrf 1500 * notifier chain if wbrf feature is supported. 1501 * Returns 0 on success, error on failure. 1502 */ 1503 static int smu_wbrf_init(struct smu_context *smu) 1504 { 1505 int ret; 1506 1507 if (!smu->wbrf_supported) 1508 return 0; 1509 1510 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1511 1512 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1513 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1514 if (ret) 1515 return ret; 1516 1517 /* 1518 * Some wifiband exclusion ranges may be already there 1519 * before our driver loaded. To make sure our driver 1520 * is awared of those exclusion ranges. 1521 */ 1522 schedule_delayed_work(&smu->wbrf_delayed_work, 1523 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1524 1525 return 0; 1526 } 1527 1528 /** 1529 * smu_wbrf_fini - tear down driver wbrf support 1530 * 1531 * @smu: smu_context pointer 1532 * 1533 * Unregisters with the wbrf notifier chain. 1534 */ 1535 static void smu_wbrf_fini(struct smu_context *smu) 1536 { 1537 if (!smu->wbrf_supported) 1538 return; 1539 1540 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1541 1542 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1543 } 1544 1545 static int smu_smc_hw_setup(struct smu_context *smu) 1546 { 1547 struct smu_feature *feature = &smu->smu_feature; 1548 struct amdgpu_device *adev = smu->adev; 1549 uint8_t pcie_gen = 0, pcie_width = 0; 1550 uint64_t features_supported; 1551 int ret = 0; 1552 1553 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1554 case IP_VERSION(11, 0, 7): 1555 case IP_VERSION(11, 0, 11): 1556 case IP_VERSION(11, 5, 0): 1557 case IP_VERSION(11, 0, 12): 1558 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1559 dev_info(adev->dev, "dpm has been enabled\n"); 1560 ret = smu_system_features_control(smu, true); 1561 if (ret) 1562 dev_err(adev->dev, "Failed system features control!\n"); 1563 return ret; 1564 } 1565 break; 1566 default: 1567 break; 1568 } 1569 1570 ret = smu_init_display_count(smu, 0); 1571 if (ret) { 1572 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1573 return ret; 1574 } 1575 1576 ret = smu_set_driver_table_location(smu); 1577 if (ret) { 1578 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1579 return ret; 1580 } 1581 1582 /* 1583 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1584 */ 1585 ret = smu_set_tool_table_location(smu); 1586 if (ret) { 1587 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1588 return ret; 1589 } 1590 1591 /* 1592 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1593 * pool location. 1594 */ 1595 ret = smu_notify_memory_pool_location(smu); 1596 if (ret) { 1597 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1598 return ret; 1599 } 1600 1601 /* 1602 * It is assumed the pptable used before runpm is same as 1603 * the one used afterwards. Thus, we can reuse the stored 1604 * copy and do not need to resetup the pptable again. 1605 */ 1606 if (!adev->in_runpm) { 1607 ret = smu_setup_pptable(smu); 1608 if (ret) { 1609 dev_err(adev->dev, "Failed to setup pptable!\n"); 1610 return ret; 1611 } 1612 } 1613 1614 /* smu_dump_pptable(smu); */ 1615 1616 /* 1617 * With SCPM enabled, PSP is responsible for the PPTable transferring 1618 * (to SMU). Driver involvement is not needed and permitted. 1619 */ 1620 if (!adev->scpm_enabled) { 1621 /* 1622 * Copy pptable bo in the vram to smc with SMU MSGs such as 1623 * SetDriverDramAddr and TransferTableDram2Smu. 1624 */ 1625 ret = smu_write_pptable(smu); 1626 if (ret) { 1627 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1628 return ret; 1629 } 1630 } 1631 1632 /* issue Run*Btc msg */ 1633 ret = smu_run_btc(smu); 1634 if (ret) 1635 return ret; 1636 1637 /* Enable UclkShadow on wbrf supported */ 1638 if (smu->wbrf_supported) { 1639 ret = smu_enable_uclk_shadow(smu, true); 1640 if (ret) { 1641 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1642 return ret; 1643 } 1644 } 1645 1646 /* 1647 * With SCPM enabled, these actions(and relevant messages) are 1648 * not needed and permitted. 1649 */ 1650 if (!adev->scpm_enabled) { 1651 ret = smu_feature_set_allowed_mask(smu); 1652 if (ret) { 1653 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1654 return ret; 1655 } 1656 } 1657 1658 ret = smu_system_features_control(smu, true); 1659 if (ret) { 1660 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1661 return ret; 1662 } 1663 1664 smu_init_xgmi_plpd_mode(smu); 1665 1666 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1667 if (ret) { 1668 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1669 return ret; 1670 } 1671 bitmap_copy(feature->supported, 1672 (unsigned long *)&features_supported, 1673 feature->feature_num); 1674 1675 if (!smu_is_dpm_running(smu)) 1676 dev_info(adev->dev, "dpm has been disabled\n"); 1677 1678 /* 1679 * Set initialized values (get from vbios) to dpm tables context such as 1680 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1681 * type of clks. 1682 */ 1683 ret = smu_set_default_dpm_table(smu); 1684 if (ret) { 1685 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1686 return ret; 1687 } 1688 1689 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1690 pcie_gen = 3; 1691 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1692 pcie_gen = 2; 1693 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1694 pcie_gen = 1; 1695 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1696 pcie_gen = 0; 1697 1698 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1699 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1700 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1701 */ 1702 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1703 pcie_width = 6; 1704 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1705 pcie_width = 5; 1706 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1707 pcie_width = 4; 1708 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1709 pcie_width = 3; 1710 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1711 pcie_width = 2; 1712 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1713 pcie_width = 1; 1714 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1715 if (ret) { 1716 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1717 return ret; 1718 } 1719 1720 ret = smu_get_thermal_temperature_range(smu); 1721 if (ret) { 1722 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1723 return ret; 1724 } 1725 1726 ret = smu_enable_thermal_alert(smu); 1727 if (ret) { 1728 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1729 return ret; 1730 } 1731 1732 ret = smu_notify_display_change(smu); 1733 if (ret) { 1734 dev_err(adev->dev, "Failed to notify display change!\n"); 1735 return ret; 1736 } 1737 1738 /* 1739 * Set min deep sleep dce fclk with bootup value from vbios via 1740 * SetMinDeepSleepDcefclk MSG. 1741 */ 1742 ret = smu_set_min_dcef_deep_sleep(smu, 1743 smu->smu_table.boot_values.dcefclk / 100); 1744 if (ret) { 1745 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1746 return ret; 1747 } 1748 1749 /* Init wbrf support. Properly setup the notifier */ 1750 ret = smu_wbrf_init(smu); 1751 if (ret) 1752 dev_err(adev->dev, "Error during wbrf init call\n"); 1753 1754 return ret; 1755 } 1756 1757 static int smu_start_smc_engine(struct smu_context *smu) 1758 { 1759 struct amdgpu_device *adev = smu->adev; 1760 int ret = 0; 1761 1762 smu->smc_fw_state = SMU_FW_INIT; 1763 1764 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1765 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1766 if (smu->ppt_funcs->load_microcode) { 1767 ret = smu->ppt_funcs->load_microcode(smu); 1768 if (ret) 1769 return ret; 1770 } 1771 } 1772 } 1773 1774 if (smu->ppt_funcs->check_fw_status) { 1775 ret = smu->ppt_funcs->check_fw_status(smu); 1776 if (ret) { 1777 dev_err(adev->dev, "SMC is not ready\n"); 1778 return ret; 1779 } 1780 } 1781 1782 /* 1783 * Send msg GetDriverIfVersion to check if the return value is equal 1784 * with DRIVER_IF_VERSION of smc header. 1785 */ 1786 ret = smu_check_fw_version(smu); 1787 if (ret) 1788 return ret; 1789 1790 return ret; 1791 } 1792 1793 static int smu_hw_init(void *handle) 1794 { 1795 int ret; 1796 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1797 struct smu_context *smu = adev->powerplay.pp_handle; 1798 1799 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1800 smu->pm_enabled = false; 1801 return 0; 1802 } 1803 1804 ret = smu_start_smc_engine(smu); 1805 if (ret) { 1806 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1807 return ret; 1808 } 1809 1810 /* 1811 * Check whether wbrf is supported. This needs to be done 1812 * before SMU setup starts since part of SMU configuration 1813 * relies on this. 1814 */ 1815 smu_wbrf_support_check(smu); 1816 1817 if (smu->is_apu) { 1818 ret = smu_set_gfx_imu_enable(smu); 1819 if (ret) 1820 return ret; 1821 smu_dpm_set_vcn_enable(smu, true); 1822 smu_dpm_set_jpeg_enable(smu, true); 1823 smu_dpm_set_vpe_enable(smu, true); 1824 smu_dpm_set_umsch_mm_enable(smu, true); 1825 smu_set_mall_enable(smu); 1826 smu_set_gfx_cgpg(smu, true); 1827 } 1828 1829 if (!smu->pm_enabled) 1830 return 0; 1831 1832 ret = smu_get_driver_allowed_feature_mask(smu); 1833 if (ret) 1834 return ret; 1835 1836 ret = smu_smc_hw_setup(smu); 1837 if (ret) { 1838 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1839 return ret; 1840 } 1841 1842 /* 1843 * Move maximum sustainable clock retrieving here considering 1844 * 1. It is not needed on resume(from S3). 1845 * 2. DAL settings come between .hw_init and .late_init of SMU. 1846 * And DAL needs to know the maximum sustainable clocks. Thus 1847 * it cannot be put in .late_init(). 1848 */ 1849 ret = smu_init_max_sustainable_clocks(smu); 1850 if (ret) { 1851 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1852 return ret; 1853 } 1854 1855 adev->pm.dpm_enabled = true; 1856 1857 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1858 1859 return 0; 1860 } 1861 1862 static int smu_disable_dpms(struct smu_context *smu) 1863 { 1864 struct amdgpu_device *adev = smu->adev; 1865 int ret = 0; 1866 bool use_baco = !smu->is_apu && 1867 ((amdgpu_in_reset(adev) && 1868 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1869 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1870 1871 /* 1872 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1873 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1874 */ 1875 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1876 case IP_VERSION(13, 0, 0): 1877 case IP_VERSION(13, 0, 7): 1878 case IP_VERSION(13, 0, 10): 1879 case IP_VERSION(14, 0, 2): 1880 case IP_VERSION(14, 0, 3): 1881 return 0; 1882 default: 1883 break; 1884 } 1885 1886 /* 1887 * For custom pptable uploading, skip the DPM features 1888 * disable process on Navi1x ASICs. 1889 * - As the gfx related features are under control of 1890 * RLC on those ASICs. RLC reinitialization will be 1891 * needed to reenable them. That will cost much more 1892 * efforts. 1893 * 1894 * - SMU firmware can handle the DPM reenablement 1895 * properly. 1896 */ 1897 if (smu->uploading_custom_pp_table) { 1898 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1899 case IP_VERSION(11, 0, 0): 1900 case IP_VERSION(11, 0, 5): 1901 case IP_VERSION(11, 0, 9): 1902 case IP_VERSION(11, 0, 7): 1903 case IP_VERSION(11, 0, 11): 1904 case IP_VERSION(11, 5, 0): 1905 case IP_VERSION(11, 0, 12): 1906 case IP_VERSION(11, 0, 13): 1907 return 0; 1908 default: 1909 break; 1910 } 1911 } 1912 1913 /* 1914 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1915 * on BACO in. Driver involvement is unnecessary. 1916 */ 1917 if (use_baco) { 1918 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1919 case IP_VERSION(11, 0, 7): 1920 case IP_VERSION(11, 0, 0): 1921 case IP_VERSION(11, 0, 5): 1922 case IP_VERSION(11, 0, 9): 1923 case IP_VERSION(13, 0, 7): 1924 return 0; 1925 default: 1926 break; 1927 } 1928 } 1929 1930 /* 1931 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 1932 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1933 */ 1934 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 1935 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 1936 return 0; 1937 1938 /* 1939 * For gpu reset, runpm and hibernation through BACO, 1940 * BACO feature has to be kept enabled. 1941 */ 1942 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1943 ret = smu_disable_all_features_with_exception(smu, 1944 SMU_FEATURE_BACO_BIT); 1945 if (ret) 1946 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1947 } else { 1948 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1949 if (!adev->scpm_enabled) { 1950 ret = smu_system_features_control(smu, false); 1951 if (ret) 1952 dev_err(adev->dev, "Failed to disable smu features.\n"); 1953 } 1954 } 1955 1956 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1957 * otherwise SMU will hang while interacting with RLC if RLC is halted 1958 * this is a WA for Vangogh asic which fix the SMU hang issue. 1959 */ 1960 ret = smu_notify_rlc_state(smu, false); 1961 if (ret) { 1962 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1963 return ret; 1964 } 1965 1966 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1967 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1968 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1969 adev->gfx.rlc.funcs->stop(adev); 1970 1971 return ret; 1972 } 1973 1974 static int smu_smc_hw_cleanup(struct smu_context *smu) 1975 { 1976 struct amdgpu_device *adev = smu->adev; 1977 int ret = 0; 1978 1979 smu_wbrf_fini(smu); 1980 1981 cancel_work_sync(&smu->throttling_logging_work); 1982 cancel_work_sync(&smu->interrupt_work); 1983 1984 ret = smu_disable_thermal_alert(smu); 1985 if (ret) { 1986 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1987 return ret; 1988 } 1989 1990 cancel_delayed_work_sync(&smu->swctf_delayed_work); 1991 1992 ret = smu_disable_dpms(smu); 1993 if (ret) { 1994 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1995 return ret; 1996 } 1997 1998 return 0; 1999 } 2000 2001 static int smu_reset_mp1_state(struct smu_context *smu) 2002 { 2003 struct amdgpu_device *adev = smu->adev; 2004 int ret = 0; 2005 2006 if ((!adev->in_runpm) && (!adev->in_suspend) && 2007 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 2008 IP_VERSION(13, 0, 10) && 2009 !amdgpu_device_has_display_hardware(adev)) 2010 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2011 2012 return ret; 2013 } 2014 2015 static int smu_hw_fini(void *handle) 2016 { 2017 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2018 struct smu_context *smu = adev->powerplay.pp_handle; 2019 int ret; 2020 2021 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2022 return 0; 2023 2024 smu_dpm_set_vcn_enable(smu, false); 2025 smu_dpm_set_jpeg_enable(smu, false); 2026 smu_dpm_set_vpe_enable(smu, false); 2027 smu_dpm_set_umsch_mm_enable(smu, false); 2028 2029 adev->vcn.cur_state = AMD_PG_STATE_GATE; 2030 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2031 2032 if (!smu->pm_enabled) 2033 return 0; 2034 2035 adev->pm.dpm_enabled = false; 2036 2037 ret = smu_smc_hw_cleanup(smu); 2038 if (ret) 2039 return ret; 2040 2041 ret = smu_reset_mp1_state(smu); 2042 if (ret) 2043 return ret; 2044 2045 return 0; 2046 } 2047 2048 static void smu_late_fini(void *handle) 2049 { 2050 struct amdgpu_device *adev = handle; 2051 struct smu_context *smu = adev->powerplay.pp_handle; 2052 2053 kfree(smu); 2054 } 2055 2056 static int smu_reset(struct smu_context *smu) 2057 { 2058 struct amdgpu_device *adev = smu->adev; 2059 int ret; 2060 2061 ret = smu_hw_fini(adev); 2062 if (ret) 2063 return ret; 2064 2065 ret = smu_hw_init(adev); 2066 if (ret) 2067 return ret; 2068 2069 ret = smu_late_init(adev); 2070 if (ret) 2071 return ret; 2072 2073 return 0; 2074 } 2075 2076 static int smu_suspend(void *handle) 2077 { 2078 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2079 struct smu_context *smu = adev->powerplay.pp_handle; 2080 int ret; 2081 uint64_t count; 2082 2083 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2084 return 0; 2085 2086 if (!smu->pm_enabled) 2087 return 0; 2088 2089 adev->pm.dpm_enabled = false; 2090 2091 ret = smu_smc_hw_cleanup(smu); 2092 if (ret) 2093 return ret; 2094 2095 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2096 2097 smu_set_gfx_cgpg(smu, false); 2098 2099 /* 2100 * pwfw resets entrycount when device is suspended, so we save the 2101 * last value to be used when we resume to keep it consistent 2102 */ 2103 ret = smu_get_entrycount_gfxoff(smu, &count); 2104 if (!ret) 2105 adev->gfx.gfx_off_entrycount = count; 2106 2107 return 0; 2108 } 2109 2110 static int smu_resume(void *handle) 2111 { 2112 int ret; 2113 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2114 struct smu_context *smu = adev->powerplay.pp_handle; 2115 2116 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2117 return 0; 2118 2119 if (!smu->pm_enabled) 2120 return 0; 2121 2122 dev_info(adev->dev, "SMU is resuming...\n"); 2123 2124 ret = smu_start_smc_engine(smu); 2125 if (ret) { 2126 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2127 return ret; 2128 } 2129 2130 ret = smu_smc_hw_setup(smu); 2131 if (ret) { 2132 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2133 return ret; 2134 } 2135 2136 ret = smu_set_gfx_imu_enable(smu); 2137 if (ret) 2138 return ret; 2139 2140 smu_set_gfx_cgpg(smu, true); 2141 2142 smu->disable_uclk_switch = 0; 2143 2144 adev->pm.dpm_enabled = true; 2145 2146 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2147 2148 return 0; 2149 } 2150 2151 static int smu_display_configuration_change(void *handle, 2152 const struct amd_pp_display_configuration *display_config) 2153 { 2154 struct smu_context *smu = handle; 2155 2156 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2157 return -EOPNOTSUPP; 2158 2159 if (!display_config) 2160 return -EINVAL; 2161 2162 smu_set_min_dcef_deep_sleep(smu, 2163 display_config->min_dcef_deep_sleep_set_clk / 100); 2164 2165 return 0; 2166 } 2167 2168 static int smu_set_clockgating_state(void *handle, 2169 enum amd_clockgating_state state) 2170 { 2171 return 0; 2172 } 2173 2174 static int smu_set_powergating_state(void *handle, 2175 enum amd_powergating_state state) 2176 { 2177 return 0; 2178 } 2179 2180 static int smu_enable_umd_pstate(void *handle, 2181 enum amd_dpm_forced_level *level) 2182 { 2183 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2184 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2185 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2186 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2187 2188 struct smu_context *smu = (struct smu_context*)(handle); 2189 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2190 2191 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2192 return -EINVAL; 2193 2194 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2195 /* enter umd pstate, save current level, disable gfx cg*/ 2196 if (*level & profile_mode_mask) { 2197 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2198 smu_gpo_control(smu, false); 2199 smu_gfx_ulv_control(smu, false); 2200 smu_deep_sleep_control(smu, false); 2201 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2202 } 2203 } else { 2204 /* exit umd pstate, restore level, enable gfx cg*/ 2205 if (!(*level & profile_mode_mask)) { 2206 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2207 *level = smu_dpm_ctx->saved_dpm_level; 2208 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2209 smu_deep_sleep_control(smu, true); 2210 smu_gfx_ulv_control(smu, true); 2211 smu_gpo_control(smu, true); 2212 } 2213 } 2214 2215 return 0; 2216 } 2217 2218 static int smu_bump_power_profile_mode(struct smu_context *smu, 2219 long *param, 2220 uint32_t param_size) 2221 { 2222 int ret = 0; 2223 2224 if (smu->ppt_funcs->set_power_profile_mode) 2225 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2226 2227 return ret; 2228 } 2229 2230 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2231 enum amd_dpm_forced_level level, 2232 bool skip_display_settings, 2233 bool init) 2234 { 2235 int ret = 0; 2236 int index = 0; 2237 long workload[1]; 2238 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2239 2240 if (!skip_display_settings) { 2241 ret = smu_display_config_changed(smu); 2242 if (ret) { 2243 dev_err(smu->adev->dev, "Failed to change display config!"); 2244 return ret; 2245 } 2246 } 2247 2248 ret = smu_apply_clocks_adjust_rules(smu); 2249 if (ret) { 2250 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2251 return ret; 2252 } 2253 2254 if (!skip_display_settings) { 2255 ret = smu_notify_smc_display_config(smu); 2256 if (ret) { 2257 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2258 return ret; 2259 } 2260 } 2261 2262 if (smu_dpm_ctx->dpm_level != level) { 2263 ret = smu_asic_set_performance_level(smu, level); 2264 if (ret) { 2265 dev_err(smu->adev->dev, "Failed to set performance level!"); 2266 return ret; 2267 } 2268 2269 /* update the saved copy */ 2270 smu_dpm_ctx->dpm_level = level; 2271 } 2272 2273 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2274 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2275 index = fls(smu->workload_mask); 2276 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2277 workload[0] = smu->workload_setting[index]; 2278 2279 if (init || smu->power_profile_mode != workload[0]) 2280 smu_bump_power_profile_mode(smu, workload, 0); 2281 } 2282 2283 return ret; 2284 } 2285 2286 static int smu_handle_task(struct smu_context *smu, 2287 enum amd_dpm_forced_level level, 2288 enum amd_pp_task task_id) 2289 { 2290 int ret = 0; 2291 2292 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2293 return -EOPNOTSUPP; 2294 2295 switch (task_id) { 2296 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2297 ret = smu_pre_display_config_changed(smu); 2298 if (ret) 2299 return ret; 2300 ret = smu_adjust_power_state_dynamic(smu, level, false, false); 2301 break; 2302 case AMD_PP_TASK_COMPLETE_INIT: 2303 ret = smu_adjust_power_state_dynamic(smu, level, true, true); 2304 break; 2305 case AMD_PP_TASK_READJUST_POWER_STATE: 2306 ret = smu_adjust_power_state_dynamic(smu, level, true, false); 2307 break; 2308 default: 2309 break; 2310 } 2311 2312 return ret; 2313 } 2314 2315 static int smu_handle_dpm_task(void *handle, 2316 enum amd_pp_task task_id, 2317 enum amd_pm_state_type *user_state) 2318 { 2319 struct smu_context *smu = handle; 2320 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2321 2322 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2323 2324 } 2325 2326 static int smu_switch_power_profile(void *handle, 2327 enum PP_SMC_POWER_PROFILE type, 2328 bool en) 2329 { 2330 struct smu_context *smu = handle; 2331 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2332 long workload[1]; 2333 uint32_t index; 2334 2335 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2336 return -EOPNOTSUPP; 2337 2338 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2339 return -EINVAL; 2340 2341 if (!en) { 2342 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 2343 index = fls(smu->workload_mask); 2344 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2345 workload[0] = smu->workload_setting[index]; 2346 } else { 2347 smu->workload_mask |= (1 << smu->workload_prority[type]); 2348 index = fls(smu->workload_mask); 2349 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2350 workload[0] = smu->workload_setting[index]; 2351 } 2352 2353 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2354 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2355 smu_bump_power_profile_mode(smu, workload, 0); 2356 2357 return 0; 2358 } 2359 2360 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2361 { 2362 struct smu_context *smu = handle; 2363 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2364 2365 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2366 return -EOPNOTSUPP; 2367 2368 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2369 return -EINVAL; 2370 2371 return smu_dpm_ctx->dpm_level; 2372 } 2373 2374 static int smu_force_performance_level(void *handle, 2375 enum amd_dpm_forced_level level) 2376 { 2377 struct smu_context *smu = handle; 2378 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2379 int ret = 0; 2380 2381 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2382 return -EOPNOTSUPP; 2383 2384 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2385 return -EINVAL; 2386 2387 ret = smu_enable_umd_pstate(smu, &level); 2388 if (ret) 2389 return ret; 2390 2391 ret = smu_handle_task(smu, level, 2392 AMD_PP_TASK_READJUST_POWER_STATE); 2393 2394 /* reset user dpm clock state */ 2395 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2396 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2397 smu->user_dpm_profile.clk_dependency = 0; 2398 } 2399 2400 return ret; 2401 } 2402 2403 static int smu_set_display_count(void *handle, uint32_t count) 2404 { 2405 struct smu_context *smu = handle; 2406 2407 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2408 return -EOPNOTSUPP; 2409 2410 return smu_init_display_count(smu, count); 2411 } 2412 2413 static int smu_force_smuclk_levels(struct smu_context *smu, 2414 enum smu_clk_type clk_type, 2415 uint32_t mask) 2416 { 2417 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2418 int ret = 0; 2419 2420 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2421 return -EOPNOTSUPP; 2422 2423 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2424 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2425 return -EINVAL; 2426 } 2427 2428 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2429 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2430 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2431 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2432 smu_set_user_clk_dependencies(smu, clk_type); 2433 } 2434 } 2435 2436 return ret; 2437 } 2438 2439 static int smu_force_ppclk_levels(void *handle, 2440 enum pp_clock_type type, 2441 uint32_t mask) 2442 { 2443 struct smu_context *smu = handle; 2444 enum smu_clk_type clk_type; 2445 2446 switch (type) { 2447 case PP_SCLK: 2448 clk_type = SMU_SCLK; break; 2449 case PP_MCLK: 2450 clk_type = SMU_MCLK; break; 2451 case PP_PCIE: 2452 clk_type = SMU_PCIE; break; 2453 case PP_SOCCLK: 2454 clk_type = SMU_SOCCLK; break; 2455 case PP_FCLK: 2456 clk_type = SMU_FCLK; break; 2457 case PP_DCEFCLK: 2458 clk_type = SMU_DCEFCLK; break; 2459 case PP_VCLK: 2460 clk_type = SMU_VCLK; break; 2461 case PP_VCLK1: 2462 clk_type = SMU_VCLK1; break; 2463 case PP_DCLK: 2464 clk_type = SMU_DCLK; break; 2465 case PP_DCLK1: 2466 clk_type = SMU_DCLK1; break; 2467 case OD_SCLK: 2468 clk_type = SMU_OD_SCLK; break; 2469 case OD_MCLK: 2470 clk_type = SMU_OD_MCLK; break; 2471 case OD_VDDC_CURVE: 2472 clk_type = SMU_OD_VDDC_CURVE; break; 2473 case OD_RANGE: 2474 clk_type = SMU_OD_RANGE; break; 2475 default: 2476 return -EINVAL; 2477 } 2478 2479 return smu_force_smuclk_levels(smu, clk_type, mask); 2480 } 2481 2482 /* 2483 * On system suspending or resetting, the dpm_enabled 2484 * flag will be cleared. So that those SMU services which 2485 * are not supported will be gated. 2486 * However, the mp1 state setting should still be granted 2487 * even if the dpm_enabled cleared. 2488 */ 2489 static int smu_set_mp1_state(void *handle, 2490 enum pp_mp1_state mp1_state) 2491 { 2492 struct smu_context *smu = handle; 2493 int ret = 0; 2494 2495 if (!smu->pm_enabled) 2496 return -EOPNOTSUPP; 2497 2498 if (smu->ppt_funcs && 2499 smu->ppt_funcs->set_mp1_state) 2500 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2501 2502 return ret; 2503 } 2504 2505 static int smu_set_df_cstate(void *handle, 2506 enum pp_df_cstate state) 2507 { 2508 struct smu_context *smu = handle; 2509 int ret = 0; 2510 2511 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2512 return -EOPNOTSUPP; 2513 2514 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2515 return 0; 2516 2517 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2518 if (ret) 2519 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2520 2521 return ret; 2522 } 2523 2524 int smu_write_watermarks_table(struct smu_context *smu) 2525 { 2526 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2527 return -EOPNOTSUPP; 2528 2529 return smu_set_watermarks_table(smu, NULL); 2530 } 2531 2532 static int smu_set_watermarks_for_clock_ranges(void *handle, 2533 struct pp_smu_wm_range_sets *clock_ranges) 2534 { 2535 struct smu_context *smu = handle; 2536 2537 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2538 return -EOPNOTSUPP; 2539 2540 if (smu->disable_watermark) 2541 return 0; 2542 2543 return smu_set_watermarks_table(smu, clock_ranges); 2544 } 2545 2546 int smu_set_ac_dc(struct smu_context *smu) 2547 { 2548 int ret = 0; 2549 2550 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2551 return -EOPNOTSUPP; 2552 2553 /* controlled by firmware */ 2554 if (smu->dc_controlled_by_gpio) 2555 return 0; 2556 2557 ret = smu_set_power_source(smu, 2558 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2559 SMU_POWER_SOURCE_DC); 2560 if (ret) 2561 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2562 smu->adev->pm.ac_power ? "AC" : "DC"); 2563 2564 return ret; 2565 } 2566 2567 const struct amd_ip_funcs smu_ip_funcs = { 2568 .name = "smu", 2569 .early_init = smu_early_init, 2570 .late_init = smu_late_init, 2571 .sw_init = smu_sw_init, 2572 .sw_fini = smu_sw_fini, 2573 .hw_init = smu_hw_init, 2574 .hw_fini = smu_hw_fini, 2575 .late_fini = smu_late_fini, 2576 .suspend = smu_suspend, 2577 .resume = smu_resume, 2578 .is_idle = NULL, 2579 .check_soft_reset = NULL, 2580 .wait_for_idle = NULL, 2581 .soft_reset = NULL, 2582 .set_clockgating_state = smu_set_clockgating_state, 2583 .set_powergating_state = smu_set_powergating_state, 2584 }; 2585 2586 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2587 .type = AMD_IP_BLOCK_TYPE_SMC, 2588 .major = 11, 2589 .minor = 0, 2590 .rev = 0, 2591 .funcs = &smu_ip_funcs, 2592 }; 2593 2594 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2595 .type = AMD_IP_BLOCK_TYPE_SMC, 2596 .major = 12, 2597 .minor = 0, 2598 .rev = 0, 2599 .funcs = &smu_ip_funcs, 2600 }; 2601 2602 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2603 .type = AMD_IP_BLOCK_TYPE_SMC, 2604 .major = 13, 2605 .minor = 0, 2606 .rev = 0, 2607 .funcs = &smu_ip_funcs, 2608 }; 2609 2610 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2611 .type = AMD_IP_BLOCK_TYPE_SMC, 2612 .major = 14, 2613 .minor = 0, 2614 .rev = 0, 2615 .funcs = &smu_ip_funcs, 2616 }; 2617 2618 static int smu_load_microcode(void *handle) 2619 { 2620 struct smu_context *smu = handle; 2621 struct amdgpu_device *adev = smu->adev; 2622 int ret = 0; 2623 2624 if (!smu->pm_enabled) 2625 return -EOPNOTSUPP; 2626 2627 /* This should be used for non PSP loading */ 2628 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2629 return 0; 2630 2631 if (smu->ppt_funcs->load_microcode) { 2632 ret = smu->ppt_funcs->load_microcode(smu); 2633 if (ret) { 2634 dev_err(adev->dev, "Load microcode failed\n"); 2635 return ret; 2636 } 2637 } 2638 2639 if (smu->ppt_funcs->check_fw_status) { 2640 ret = smu->ppt_funcs->check_fw_status(smu); 2641 if (ret) { 2642 dev_err(adev->dev, "SMC is not ready\n"); 2643 return ret; 2644 } 2645 } 2646 2647 return ret; 2648 } 2649 2650 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2651 { 2652 int ret = 0; 2653 2654 if (smu->ppt_funcs->set_gfx_cgpg) 2655 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2656 2657 return ret; 2658 } 2659 2660 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2661 { 2662 struct smu_context *smu = handle; 2663 int ret = 0; 2664 2665 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2666 return -EOPNOTSUPP; 2667 2668 if (!smu->ppt_funcs->set_fan_speed_rpm) 2669 return -EOPNOTSUPP; 2670 2671 if (speed == U32_MAX) 2672 return -EINVAL; 2673 2674 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2675 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2676 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2677 smu->user_dpm_profile.fan_speed_rpm = speed; 2678 2679 /* Override custom PWM setting as they cannot co-exist */ 2680 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2681 smu->user_dpm_profile.fan_speed_pwm = 0; 2682 } 2683 2684 return ret; 2685 } 2686 2687 /** 2688 * smu_get_power_limit - Request one of the SMU Power Limits 2689 * 2690 * @handle: pointer to smu context 2691 * @limit: requested limit is written back to this variable 2692 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2693 * @pp_power_type: &pp_power_type type of power 2694 * Return: 0 on success, <0 on error 2695 * 2696 */ 2697 int smu_get_power_limit(void *handle, 2698 uint32_t *limit, 2699 enum pp_power_limit_level pp_limit_level, 2700 enum pp_power_type pp_power_type) 2701 { 2702 struct smu_context *smu = handle; 2703 struct amdgpu_device *adev = smu->adev; 2704 enum smu_ppt_limit_level limit_level; 2705 uint32_t limit_type; 2706 int ret = 0; 2707 2708 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2709 return -EOPNOTSUPP; 2710 2711 switch (pp_power_type) { 2712 case PP_PWR_TYPE_SUSTAINED: 2713 limit_type = SMU_DEFAULT_PPT_LIMIT; 2714 break; 2715 case PP_PWR_TYPE_FAST: 2716 limit_type = SMU_FAST_PPT_LIMIT; 2717 break; 2718 default: 2719 return -EOPNOTSUPP; 2720 } 2721 2722 switch (pp_limit_level) { 2723 case PP_PWR_LIMIT_CURRENT: 2724 limit_level = SMU_PPT_LIMIT_CURRENT; 2725 break; 2726 case PP_PWR_LIMIT_DEFAULT: 2727 limit_level = SMU_PPT_LIMIT_DEFAULT; 2728 break; 2729 case PP_PWR_LIMIT_MAX: 2730 limit_level = SMU_PPT_LIMIT_MAX; 2731 break; 2732 case PP_PWR_LIMIT_MIN: 2733 limit_level = SMU_PPT_LIMIT_MIN; 2734 break; 2735 default: 2736 return -EOPNOTSUPP; 2737 } 2738 2739 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2740 if (smu->ppt_funcs->get_ppt_limit) 2741 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2742 } else { 2743 switch (limit_level) { 2744 case SMU_PPT_LIMIT_CURRENT: 2745 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2746 case IP_VERSION(13, 0, 2): 2747 case IP_VERSION(13, 0, 6): 2748 case IP_VERSION(13, 0, 14): 2749 case IP_VERSION(11, 0, 7): 2750 case IP_VERSION(11, 0, 11): 2751 case IP_VERSION(11, 0, 12): 2752 case IP_VERSION(11, 0, 13): 2753 ret = smu_get_asic_power_limits(smu, 2754 &smu->current_power_limit, 2755 NULL, NULL, NULL); 2756 break; 2757 default: 2758 break; 2759 } 2760 *limit = smu->current_power_limit; 2761 break; 2762 case SMU_PPT_LIMIT_DEFAULT: 2763 *limit = smu->default_power_limit; 2764 break; 2765 case SMU_PPT_LIMIT_MAX: 2766 *limit = smu->max_power_limit; 2767 break; 2768 case SMU_PPT_LIMIT_MIN: 2769 *limit = smu->min_power_limit; 2770 break; 2771 default: 2772 return -EINVAL; 2773 } 2774 } 2775 2776 return ret; 2777 } 2778 2779 static int smu_set_power_limit(void *handle, uint32_t limit) 2780 { 2781 struct smu_context *smu = handle; 2782 uint32_t limit_type = limit >> 24; 2783 int ret = 0; 2784 2785 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2786 return -EOPNOTSUPP; 2787 2788 limit &= (1<<24)-1; 2789 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2790 if (smu->ppt_funcs->set_power_limit) 2791 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2792 2793 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2794 dev_err(smu->adev->dev, 2795 "New power limit (%d) is out of range [%d,%d]\n", 2796 limit, smu->min_power_limit, smu->max_power_limit); 2797 return -EINVAL; 2798 } 2799 2800 if (!limit) 2801 limit = smu->current_power_limit; 2802 2803 if (smu->ppt_funcs->set_power_limit) { 2804 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2805 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2806 smu->user_dpm_profile.power_limit = limit; 2807 } 2808 2809 return ret; 2810 } 2811 2812 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2813 { 2814 int ret = 0; 2815 2816 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2817 return -EOPNOTSUPP; 2818 2819 if (smu->ppt_funcs->print_clk_levels) 2820 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2821 2822 return ret; 2823 } 2824 2825 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2826 { 2827 enum smu_clk_type clk_type; 2828 2829 switch (type) { 2830 case PP_SCLK: 2831 clk_type = SMU_SCLK; break; 2832 case PP_MCLK: 2833 clk_type = SMU_MCLK; break; 2834 case PP_PCIE: 2835 clk_type = SMU_PCIE; break; 2836 case PP_SOCCLK: 2837 clk_type = SMU_SOCCLK; break; 2838 case PP_FCLK: 2839 clk_type = SMU_FCLK; break; 2840 case PP_DCEFCLK: 2841 clk_type = SMU_DCEFCLK; break; 2842 case PP_VCLK: 2843 clk_type = SMU_VCLK; break; 2844 case PP_VCLK1: 2845 clk_type = SMU_VCLK1; break; 2846 case PP_DCLK: 2847 clk_type = SMU_DCLK; break; 2848 case PP_DCLK1: 2849 clk_type = SMU_DCLK1; break; 2850 case OD_SCLK: 2851 clk_type = SMU_OD_SCLK; break; 2852 case OD_MCLK: 2853 clk_type = SMU_OD_MCLK; break; 2854 case OD_VDDC_CURVE: 2855 clk_type = SMU_OD_VDDC_CURVE; break; 2856 case OD_RANGE: 2857 clk_type = SMU_OD_RANGE; break; 2858 case OD_VDDGFX_OFFSET: 2859 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2860 case OD_CCLK: 2861 clk_type = SMU_OD_CCLK; break; 2862 case OD_FAN_CURVE: 2863 clk_type = SMU_OD_FAN_CURVE; break; 2864 case OD_ACOUSTIC_LIMIT: 2865 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2866 case OD_ACOUSTIC_TARGET: 2867 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2868 case OD_FAN_TARGET_TEMPERATURE: 2869 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2870 case OD_FAN_MINIMUM_PWM: 2871 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2872 default: 2873 clk_type = SMU_CLK_COUNT; break; 2874 } 2875 2876 return clk_type; 2877 } 2878 2879 static int smu_print_ppclk_levels(void *handle, 2880 enum pp_clock_type type, 2881 char *buf) 2882 { 2883 struct smu_context *smu = handle; 2884 enum smu_clk_type clk_type; 2885 2886 clk_type = smu_convert_to_smuclk(type); 2887 if (clk_type == SMU_CLK_COUNT) 2888 return -EINVAL; 2889 2890 return smu_print_smuclk_levels(smu, clk_type, buf); 2891 } 2892 2893 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2894 { 2895 struct smu_context *smu = handle; 2896 enum smu_clk_type clk_type; 2897 2898 clk_type = smu_convert_to_smuclk(type); 2899 if (clk_type == SMU_CLK_COUNT) 2900 return -EINVAL; 2901 2902 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2903 return -EOPNOTSUPP; 2904 2905 if (!smu->ppt_funcs->emit_clk_levels) 2906 return -ENOENT; 2907 2908 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2909 2910 } 2911 2912 static int smu_od_edit_dpm_table(void *handle, 2913 enum PP_OD_DPM_TABLE_COMMAND type, 2914 long *input, uint32_t size) 2915 { 2916 struct smu_context *smu = handle; 2917 int ret = 0; 2918 2919 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2920 return -EOPNOTSUPP; 2921 2922 if (smu->ppt_funcs->od_edit_dpm_table) { 2923 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2924 } 2925 2926 return ret; 2927 } 2928 2929 static int smu_read_sensor(void *handle, 2930 int sensor, 2931 void *data, 2932 int *size_arg) 2933 { 2934 struct smu_context *smu = handle; 2935 struct smu_umd_pstate_table *pstate_table = 2936 &smu->pstate_table; 2937 int ret = 0; 2938 uint32_t *size, size_val; 2939 2940 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2941 return -EOPNOTSUPP; 2942 2943 if (!data || !size_arg) 2944 return -EINVAL; 2945 2946 size_val = *size_arg; 2947 size = &size_val; 2948 2949 if (smu->ppt_funcs->read_sensor) 2950 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2951 goto unlock; 2952 2953 switch (sensor) { 2954 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2955 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2956 *size = 4; 2957 break; 2958 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2959 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2960 *size = 4; 2961 break; 2962 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2963 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2964 *size = 4; 2965 break; 2966 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2967 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2968 *size = 4; 2969 break; 2970 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2971 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2972 *size = 8; 2973 break; 2974 case AMDGPU_PP_SENSOR_UVD_POWER: 2975 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2976 *size = 4; 2977 break; 2978 case AMDGPU_PP_SENSOR_VCE_POWER: 2979 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2980 *size = 4; 2981 break; 2982 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2983 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 2984 *size = 4; 2985 break; 2986 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2987 *(uint32_t *)data = 0; 2988 *size = 4; 2989 break; 2990 default: 2991 *size = 0; 2992 ret = -EOPNOTSUPP; 2993 break; 2994 } 2995 2996 unlock: 2997 // assign uint32_t to int 2998 *size_arg = size_val; 2999 3000 return ret; 3001 } 3002 3003 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3004 { 3005 int ret = -EOPNOTSUPP; 3006 struct smu_context *smu = handle; 3007 3008 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3009 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3010 3011 return ret; 3012 } 3013 3014 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3015 { 3016 int ret = -EOPNOTSUPP; 3017 struct smu_context *smu = handle; 3018 3019 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3020 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3021 3022 return ret; 3023 } 3024 3025 static int smu_get_power_profile_mode(void *handle, char *buf) 3026 { 3027 struct smu_context *smu = handle; 3028 3029 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3030 !smu->ppt_funcs->get_power_profile_mode) 3031 return -EOPNOTSUPP; 3032 if (!buf) 3033 return -EINVAL; 3034 3035 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3036 } 3037 3038 static int smu_set_power_profile_mode(void *handle, 3039 long *param, 3040 uint32_t param_size) 3041 { 3042 struct smu_context *smu = handle; 3043 3044 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3045 !smu->ppt_funcs->set_power_profile_mode) 3046 return -EOPNOTSUPP; 3047 3048 return smu_bump_power_profile_mode(smu, param, param_size); 3049 } 3050 3051 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3052 { 3053 struct smu_context *smu = handle; 3054 3055 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3056 return -EOPNOTSUPP; 3057 3058 if (!smu->ppt_funcs->get_fan_control_mode) 3059 return -EOPNOTSUPP; 3060 3061 if (!fan_mode) 3062 return -EINVAL; 3063 3064 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3065 3066 return 0; 3067 } 3068 3069 static int smu_set_fan_control_mode(void *handle, u32 value) 3070 { 3071 struct smu_context *smu = handle; 3072 int ret = 0; 3073 3074 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3075 return -EOPNOTSUPP; 3076 3077 if (!smu->ppt_funcs->set_fan_control_mode) 3078 return -EOPNOTSUPP; 3079 3080 if (value == U32_MAX) 3081 return -EINVAL; 3082 3083 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3084 if (ret) 3085 goto out; 3086 3087 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3088 smu->user_dpm_profile.fan_mode = value; 3089 3090 /* reset user dpm fan speed */ 3091 if (value != AMD_FAN_CTRL_MANUAL) { 3092 smu->user_dpm_profile.fan_speed_pwm = 0; 3093 smu->user_dpm_profile.fan_speed_rpm = 0; 3094 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3095 } 3096 } 3097 3098 out: 3099 return ret; 3100 } 3101 3102 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3103 { 3104 struct smu_context *smu = handle; 3105 int ret = 0; 3106 3107 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3108 return -EOPNOTSUPP; 3109 3110 if (!smu->ppt_funcs->get_fan_speed_pwm) 3111 return -EOPNOTSUPP; 3112 3113 if (!speed) 3114 return -EINVAL; 3115 3116 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3117 3118 return ret; 3119 } 3120 3121 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3122 { 3123 struct smu_context *smu = handle; 3124 int ret = 0; 3125 3126 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3127 return -EOPNOTSUPP; 3128 3129 if (!smu->ppt_funcs->set_fan_speed_pwm) 3130 return -EOPNOTSUPP; 3131 3132 if (speed == U32_MAX) 3133 return -EINVAL; 3134 3135 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3136 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3137 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3138 smu->user_dpm_profile.fan_speed_pwm = speed; 3139 3140 /* Override custom RPM setting as they cannot co-exist */ 3141 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3142 smu->user_dpm_profile.fan_speed_rpm = 0; 3143 } 3144 3145 return ret; 3146 } 3147 3148 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3149 { 3150 struct smu_context *smu = handle; 3151 int ret = 0; 3152 3153 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3154 return -EOPNOTSUPP; 3155 3156 if (!smu->ppt_funcs->get_fan_speed_rpm) 3157 return -EOPNOTSUPP; 3158 3159 if (!speed) 3160 return -EINVAL; 3161 3162 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3163 3164 return ret; 3165 } 3166 3167 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3168 { 3169 struct smu_context *smu = handle; 3170 3171 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3172 return -EOPNOTSUPP; 3173 3174 return smu_set_min_dcef_deep_sleep(smu, clk); 3175 } 3176 3177 static int smu_get_clock_by_type_with_latency(void *handle, 3178 enum amd_pp_clock_type type, 3179 struct pp_clock_levels_with_latency *clocks) 3180 { 3181 struct smu_context *smu = handle; 3182 enum smu_clk_type clk_type; 3183 int ret = 0; 3184 3185 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3186 return -EOPNOTSUPP; 3187 3188 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3189 switch (type) { 3190 case amd_pp_sys_clock: 3191 clk_type = SMU_GFXCLK; 3192 break; 3193 case amd_pp_mem_clock: 3194 clk_type = SMU_MCLK; 3195 break; 3196 case amd_pp_dcef_clock: 3197 clk_type = SMU_DCEFCLK; 3198 break; 3199 case amd_pp_disp_clock: 3200 clk_type = SMU_DISPCLK; 3201 break; 3202 default: 3203 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3204 return -EINVAL; 3205 } 3206 3207 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3208 } 3209 3210 return ret; 3211 } 3212 3213 static int smu_display_clock_voltage_request(void *handle, 3214 struct pp_display_clock_request *clock_req) 3215 { 3216 struct smu_context *smu = handle; 3217 int ret = 0; 3218 3219 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3220 return -EOPNOTSUPP; 3221 3222 if (smu->ppt_funcs->display_clock_voltage_request) 3223 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3224 3225 return ret; 3226 } 3227 3228 3229 static int smu_display_disable_memory_clock_switch(void *handle, 3230 bool disable_memory_clock_switch) 3231 { 3232 struct smu_context *smu = handle; 3233 int ret = -EINVAL; 3234 3235 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3236 return -EOPNOTSUPP; 3237 3238 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3239 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3240 3241 return ret; 3242 } 3243 3244 static int smu_set_xgmi_pstate(void *handle, 3245 uint32_t pstate) 3246 { 3247 struct smu_context *smu = handle; 3248 int ret = 0; 3249 3250 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3251 return -EOPNOTSUPP; 3252 3253 if (smu->ppt_funcs->set_xgmi_pstate) 3254 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3255 3256 if (ret) 3257 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3258 3259 return ret; 3260 } 3261 3262 static int smu_get_baco_capability(void *handle) 3263 { 3264 struct smu_context *smu = handle; 3265 3266 if (!smu->pm_enabled) 3267 return false; 3268 3269 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3270 return false; 3271 3272 return smu->ppt_funcs->get_bamaco_support(smu); 3273 } 3274 3275 static int smu_baco_set_state(void *handle, int state) 3276 { 3277 struct smu_context *smu = handle; 3278 int ret = 0; 3279 3280 if (!smu->pm_enabled) 3281 return -EOPNOTSUPP; 3282 3283 if (state == 0) { 3284 if (smu->ppt_funcs->baco_exit) 3285 ret = smu->ppt_funcs->baco_exit(smu); 3286 } else if (state == 1) { 3287 if (smu->ppt_funcs->baco_enter) 3288 ret = smu->ppt_funcs->baco_enter(smu); 3289 } else { 3290 return -EINVAL; 3291 } 3292 3293 if (ret) 3294 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3295 (state)?"enter":"exit"); 3296 3297 return ret; 3298 } 3299 3300 bool smu_mode1_reset_is_support(struct smu_context *smu) 3301 { 3302 bool ret = false; 3303 3304 if (!smu->pm_enabled) 3305 return false; 3306 3307 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3308 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3309 3310 return ret; 3311 } 3312 3313 bool smu_mode2_reset_is_support(struct smu_context *smu) 3314 { 3315 bool ret = false; 3316 3317 if (!smu->pm_enabled) 3318 return false; 3319 3320 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3321 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3322 3323 return ret; 3324 } 3325 3326 int smu_mode1_reset(struct smu_context *smu) 3327 { 3328 int ret = 0; 3329 3330 if (!smu->pm_enabled) 3331 return -EOPNOTSUPP; 3332 3333 if (smu->ppt_funcs->mode1_reset) 3334 ret = smu->ppt_funcs->mode1_reset(smu); 3335 3336 return ret; 3337 } 3338 3339 static int smu_mode2_reset(void *handle) 3340 { 3341 struct smu_context *smu = handle; 3342 int ret = 0; 3343 3344 if (!smu->pm_enabled) 3345 return -EOPNOTSUPP; 3346 3347 if (smu->ppt_funcs->mode2_reset) 3348 ret = smu->ppt_funcs->mode2_reset(smu); 3349 3350 if (ret) 3351 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3352 3353 return ret; 3354 } 3355 3356 static int smu_enable_gfx_features(void *handle) 3357 { 3358 struct smu_context *smu = handle; 3359 int ret = 0; 3360 3361 if (!smu->pm_enabled) 3362 return -EOPNOTSUPP; 3363 3364 if (smu->ppt_funcs->enable_gfx_features) 3365 ret = smu->ppt_funcs->enable_gfx_features(smu); 3366 3367 if (ret) 3368 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3369 3370 return ret; 3371 } 3372 3373 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3374 struct pp_smu_nv_clock_table *max_clocks) 3375 { 3376 struct smu_context *smu = handle; 3377 int ret = 0; 3378 3379 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3380 return -EOPNOTSUPP; 3381 3382 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3383 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3384 3385 return ret; 3386 } 3387 3388 static int smu_get_uclk_dpm_states(void *handle, 3389 unsigned int *clock_values_in_khz, 3390 unsigned int *num_states) 3391 { 3392 struct smu_context *smu = handle; 3393 int ret = 0; 3394 3395 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3396 return -EOPNOTSUPP; 3397 3398 if (smu->ppt_funcs->get_uclk_dpm_states) 3399 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3400 3401 return ret; 3402 } 3403 3404 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3405 { 3406 struct smu_context *smu = handle; 3407 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3408 3409 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3410 return -EOPNOTSUPP; 3411 3412 if (smu->ppt_funcs->get_current_power_state) 3413 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3414 3415 return pm_state; 3416 } 3417 3418 static int smu_get_dpm_clock_table(void *handle, 3419 struct dpm_clocks *clock_table) 3420 { 3421 struct smu_context *smu = handle; 3422 int ret = 0; 3423 3424 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3425 return -EOPNOTSUPP; 3426 3427 if (smu->ppt_funcs->get_dpm_clock_table) 3428 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3429 3430 return ret; 3431 } 3432 3433 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3434 { 3435 struct smu_context *smu = handle; 3436 3437 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3438 return -EOPNOTSUPP; 3439 3440 if (!smu->ppt_funcs->get_gpu_metrics) 3441 return -EOPNOTSUPP; 3442 3443 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3444 } 3445 3446 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3447 size_t size) 3448 { 3449 struct smu_context *smu = handle; 3450 3451 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3452 return -EOPNOTSUPP; 3453 3454 if (!smu->ppt_funcs->get_pm_metrics) 3455 return -EOPNOTSUPP; 3456 3457 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3458 } 3459 3460 static int smu_enable_mgpu_fan_boost(void *handle) 3461 { 3462 struct smu_context *smu = handle; 3463 int ret = 0; 3464 3465 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3466 return -EOPNOTSUPP; 3467 3468 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3469 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3470 3471 return ret; 3472 } 3473 3474 static int smu_gfx_state_change_set(void *handle, 3475 uint32_t state) 3476 { 3477 struct smu_context *smu = handle; 3478 int ret = 0; 3479 3480 if (smu->ppt_funcs->gfx_state_change_set) 3481 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3482 3483 return ret; 3484 } 3485 3486 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3487 { 3488 int ret = 0; 3489 3490 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3491 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3492 3493 return ret; 3494 } 3495 3496 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3497 { 3498 int ret = -EOPNOTSUPP; 3499 3500 if (smu->ppt_funcs && 3501 smu->ppt_funcs->get_ecc_info) 3502 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3503 3504 return ret; 3505 3506 } 3507 3508 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3509 { 3510 struct smu_context *smu = handle; 3511 struct smu_table_context *smu_table = &smu->smu_table; 3512 struct smu_table *memory_pool = &smu_table->memory_pool; 3513 3514 if (!addr || !size) 3515 return -EINVAL; 3516 3517 *addr = NULL; 3518 *size = 0; 3519 if (memory_pool->bo) { 3520 *addr = memory_pool->cpu_addr; 3521 *size = memory_pool->size; 3522 } 3523 3524 return 0; 3525 } 3526 3527 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3528 size_t *size) 3529 { 3530 size_t offset = *size; 3531 int level; 3532 3533 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3534 if (level == policy->current_level) 3535 offset += sysfs_emit_at(sysbuf, offset, 3536 "%d : %s*\n", level, 3537 policy->desc->get_desc(policy, level)); 3538 else 3539 offset += sysfs_emit_at(sysbuf, offset, 3540 "%d : %s\n", level, 3541 policy->desc->get_desc(policy, level)); 3542 } 3543 3544 *size = offset; 3545 } 3546 3547 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3548 enum pp_pm_policy p_type, char *sysbuf) 3549 { 3550 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3551 struct smu_dpm_policy_ctxt *policy_ctxt; 3552 struct smu_dpm_policy *dpm_policy; 3553 size_t offset = 0; 3554 3555 policy_ctxt = dpm_ctxt->dpm_policies; 3556 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3557 !policy_ctxt->policy_mask) 3558 return -EOPNOTSUPP; 3559 3560 if (p_type == PP_PM_POLICY_NONE) 3561 return -EINVAL; 3562 3563 dpm_policy = smu_get_pm_policy(smu, p_type); 3564 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3565 return -ENOENT; 3566 3567 if (!sysbuf) 3568 return -EINVAL; 3569 3570 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3571 3572 return offset; 3573 } 3574 3575 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3576 enum pp_pm_policy p_type) 3577 { 3578 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3579 struct smu_dpm_policy_ctxt *policy_ctxt; 3580 int i; 3581 3582 policy_ctxt = dpm_ctxt->dpm_policies; 3583 if (!policy_ctxt) 3584 return NULL; 3585 3586 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3587 if (policy_ctxt->policies[i].policy_type == p_type) 3588 return &policy_ctxt->policies[i]; 3589 } 3590 3591 return NULL; 3592 } 3593 3594 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3595 int level) 3596 { 3597 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3598 struct smu_dpm_policy *dpm_policy = NULL; 3599 struct smu_dpm_policy_ctxt *policy_ctxt; 3600 int ret = -EOPNOTSUPP; 3601 3602 policy_ctxt = dpm_ctxt->dpm_policies; 3603 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3604 !policy_ctxt->policy_mask) 3605 return ret; 3606 3607 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3608 return -EINVAL; 3609 3610 dpm_policy = smu_get_pm_policy(smu, p_type); 3611 3612 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3613 return ret; 3614 3615 if (dpm_policy->current_level == level) 3616 return 0; 3617 3618 ret = dpm_policy->set_policy(smu, level); 3619 3620 if (!ret) 3621 dpm_policy->current_level = level; 3622 3623 return ret; 3624 } 3625 3626 static const struct amd_pm_funcs swsmu_pm_funcs = { 3627 /* export for sysfs */ 3628 .set_fan_control_mode = smu_set_fan_control_mode, 3629 .get_fan_control_mode = smu_get_fan_control_mode, 3630 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3631 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3632 .force_clock_level = smu_force_ppclk_levels, 3633 .print_clock_levels = smu_print_ppclk_levels, 3634 .emit_clock_levels = smu_emit_ppclk_levels, 3635 .force_performance_level = smu_force_performance_level, 3636 .read_sensor = smu_read_sensor, 3637 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3638 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3639 .get_performance_level = smu_get_performance_level, 3640 .get_current_power_state = smu_get_current_power_state, 3641 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3642 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3643 .get_pp_num_states = smu_get_power_num_states, 3644 .get_pp_table = smu_sys_get_pp_table, 3645 .set_pp_table = smu_sys_set_pp_table, 3646 .switch_power_profile = smu_switch_power_profile, 3647 /* export to amdgpu */ 3648 .dispatch_tasks = smu_handle_dpm_task, 3649 .load_firmware = smu_load_microcode, 3650 .set_powergating_by_smu = smu_dpm_set_power_gate, 3651 .set_power_limit = smu_set_power_limit, 3652 .get_power_limit = smu_get_power_limit, 3653 .get_power_profile_mode = smu_get_power_profile_mode, 3654 .set_power_profile_mode = smu_set_power_profile_mode, 3655 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3656 .set_mp1_state = smu_set_mp1_state, 3657 .gfx_state_change_set = smu_gfx_state_change_set, 3658 /* export to DC */ 3659 .get_sclk = smu_get_sclk, 3660 .get_mclk = smu_get_mclk, 3661 .display_configuration_change = smu_display_configuration_change, 3662 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3663 .display_clock_voltage_request = smu_display_clock_voltage_request, 3664 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3665 .set_active_display_count = smu_set_display_count, 3666 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3667 .get_asic_baco_capability = smu_get_baco_capability, 3668 .set_asic_baco_state = smu_baco_set_state, 3669 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3670 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3671 .asic_reset_mode_2 = smu_mode2_reset, 3672 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3673 .set_df_cstate = smu_set_df_cstate, 3674 .set_xgmi_pstate = smu_set_xgmi_pstate, 3675 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3676 .get_pm_metrics = smu_sys_get_pm_metrics, 3677 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3678 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3679 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3680 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3681 .get_dpm_clock_table = smu_get_dpm_clock_table, 3682 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3683 }; 3684 3685 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3686 uint64_t event_arg) 3687 { 3688 int ret = -EINVAL; 3689 3690 if (smu->ppt_funcs->wait_for_event) 3691 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3692 3693 return ret; 3694 } 3695 3696 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3697 { 3698 3699 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3700 return -EOPNOTSUPP; 3701 3702 /* Confirm the buffer allocated is of correct size */ 3703 if (size != smu->stb_context.stb_buf_size) 3704 return -EINVAL; 3705 3706 /* 3707 * No need to lock smu mutex as we access STB directly through MMIO 3708 * and not going through SMU messaging route (for now at least). 3709 * For registers access rely on implementation internal locking. 3710 */ 3711 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3712 } 3713 3714 #if defined(CONFIG_DEBUG_FS) 3715 3716 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3717 { 3718 struct amdgpu_device *adev = filp->f_inode->i_private; 3719 struct smu_context *smu = adev->powerplay.pp_handle; 3720 unsigned char *buf; 3721 int r; 3722 3723 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3724 if (!buf) 3725 return -ENOMEM; 3726 3727 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3728 if (r) 3729 goto out; 3730 3731 filp->private_data = buf; 3732 3733 return 0; 3734 3735 out: 3736 kvfree(buf); 3737 return r; 3738 } 3739 3740 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3741 loff_t *pos) 3742 { 3743 struct amdgpu_device *adev = filp->f_inode->i_private; 3744 struct smu_context *smu = adev->powerplay.pp_handle; 3745 3746 3747 if (!filp->private_data) 3748 return -EINVAL; 3749 3750 return simple_read_from_buffer(buf, 3751 size, 3752 pos, filp->private_data, 3753 smu->stb_context.stb_buf_size); 3754 } 3755 3756 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3757 { 3758 kvfree(filp->private_data); 3759 filp->private_data = NULL; 3760 3761 return 0; 3762 } 3763 3764 /* 3765 * We have to define not only read method but also 3766 * open and release because .read takes up to PAGE_SIZE 3767 * data each time so and so is invoked multiple times. 3768 * We allocate the STB buffer in .open and release it 3769 * in .release 3770 */ 3771 static const struct file_operations smu_stb_debugfs_fops = { 3772 .owner = THIS_MODULE, 3773 .open = smu_stb_debugfs_open, 3774 .read = smu_stb_debugfs_read, 3775 .release = smu_stb_debugfs_release, 3776 .llseek = default_llseek, 3777 }; 3778 3779 #endif 3780 3781 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3782 { 3783 #if defined(CONFIG_DEBUG_FS) 3784 3785 struct smu_context *smu = adev->powerplay.pp_handle; 3786 3787 if (!smu || (!smu->stb_context.stb_buf_size)) 3788 return; 3789 3790 debugfs_create_file_size("amdgpu_smu_stb_dump", 3791 S_IRUSR, 3792 adev_to_drm(adev)->primary->debugfs_root, 3793 adev, 3794 &smu_stb_debugfs_fops, 3795 smu->stb_context.stb_buf_size); 3796 #endif 3797 } 3798 3799 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3800 { 3801 int ret = 0; 3802 3803 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3804 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3805 3806 return ret; 3807 } 3808 3809 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3810 { 3811 int ret = 0; 3812 3813 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3814 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3815 3816 return ret; 3817 } 3818 3819 int smu_send_rma_reason(struct smu_context *smu) 3820 { 3821 int ret = 0; 3822 3823 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3824 ret = smu->ppt_funcs->send_rma_reason(smu); 3825 3826 return ret; 3827 } 3828