1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 static void smu_power_profile_mode_get(struct smu_context *smu, 76 enum PP_SMC_POWER_PROFILE profile_mode); 77 static void smu_power_profile_mode_put(struct smu_context *smu, 78 enum PP_SMC_POWER_PROFILE profile_mode); 79 80 static int smu_sys_get_pp_feature_mask(void *handle, 81 char *buf) 82 { 83 struct smu_context *smu = handle; 84 85 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 86 return -EOPNOTSUPP; 87 88 return smu_get_pp_feature_mask(smu, buf); 89 } 90 91 static int smu_sys_set_pp_feature_mask(void *handle, 92 uint64_t new_mask) 93 { 94 struct smu_context *smu = handle; 95 96 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 97 return -EOPNOTSUPP; 98 99 return smu_set_pp_feature_mask(smu, new_mask); 100 } 101 102 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 103 { 104 if (!smu->ppt_funcs->set_gfx_off_residency) 105 return -EINVAL; 106 107 return smu_set_gfx_off_residency(smu, value); 108 } 109 110 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 111 { 112 if (!smu->ppt_funcs->get_gfx_off_residency) 113 return -EINVAL; 114 115 return smu_get_gfx_off_residency(smu, value); 116 } 117 118 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 119 { 120 if (!smu->ppt_funcs->get_gfx_off_entrycount) 121 return -EINVAL; 122 123 return smu_get_gfx_off_entrycount(smu, value); 124 } 125 126 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 127 { 128 if (!smu->ppt_funcs->get_gfx_off_status) 129 return -EINVAL; 130 131 *value = smu_get_gfx_off_status(smu); 132 133 return 0; 134 } 135 136 int smu_set_soft_freq_range(struct smu_context *smu, 137 enum smu_clk_type clk_type, 138 uint32_t min, 139 uint32_t max) 140 { 141 int ret = 0; 142 143 if (smu->ppt_funcs->set_soft_freq_limited_range) 144 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 145 clk_type, 146 min, 147 max, 148 false); 149 150 return ret; 151 } 152 153 int smu_get_dpm_freq_range(struct smu_context *smu, 154 enum smu_clk_type clk_type, 155 uint32_t *min, 156 uint32_t *max) 157 { 158 int ret = -ENOTSUPP; 159 160 if (!min && !max) 161 return -EINVAL; 162 163 if (smu->ppt_funcs->get_dpm_ultimate_freq) 164 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 165 clk_type, 166 min, 167 max); 168 169 return ret; 170 } 171 172 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 173 { 174 int ret = 0; 175 struct amdgpu_device *adev = smu->adev; 176 177 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 178 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 179 if (ret) 180 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 181 } 182 return ret; 183 } 184 185 static u32 smu_get_mclk(void *handle, bool low) 186 { 187 struct smu_context *smu = handle; 188 uint32_t clk_freq; 189 int ret = 0; 190 191 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 192 low ? &clk_freq : NULL, 193 !low ? &clk_freq : NULL); 194 if (ret) 195 return 0; 196 return clk_freq * 100; 197 } 198 199 static u32 smu_get_sclk(void *handle, bool low) 200 { 201 struct smu_context *smu = handle; 202 uint32_t clk_freq; 203 int ret = 0; 204 205 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 206 low ? &clk_freq : NULL, 207 !low ? &clk_freq : NULL); 208 if (ret) 209 return 0; 210 return clk_freq * 100; 211 } 212 213 static int smu_set_gfx_imu_enable(struct smu_context *smu) 214 { 215 struct amdgpu_device *adev = smu->adev; 216 217 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 218 return 0; 219 220 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 221 return 0; 222 223 return smu_set_gfx_power_up_by_imu(smu); 224 } 225 226 static bool is_vcn_enabled(struct amdgpu_device *adev) 227 { 228 int i; 229 230 for (i = 0; i < adev->num_ip_blocks; i++) { 231 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 232 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 233 !adev->ip_blocks[i].status.valid) 234 return false; 235 } 236 237 return true; 238 } 239 240 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 241 bool enable, 242 int inst) 243 { 244 struct smu_power_context *smu_power = &smu->smu_power; 245 struct smu_power_gate *power_gate = &smu_power->power_gate; 246 int ret = 0; 247 248 /* 249 * don't poweron vcn/jpeg when they are skipped. 250 */ 251 if (!is_vcn_enabled(smu->adev)) 252 return 0; 253 254 if (!smu->ppt_funcs->dpm_set_vcn_enable) 255 return 0; 256 257 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable) 258 return 0; 259 260 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst); 261 if (!ret) 262 atomic_set(&power_gate->vcn_gated[inst], !enable); 263 264 return ret; 265 } 266 267 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 268 bool enable) 269 { 270 struct smu_power_context *smu_power = &smu->smu_power; 271 struct smu_power_gate *power_gate = &smu_power->power_gate; 272 int ret = 0; 273 274 if (!is_vcn_enabled(smu->adev)) 275 return 0; 276 277 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 278 return 0; 279 280 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 281 return 0; 282 283 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 284 if (!ret) 285 atomic_set(&power_gate->jpeg_gated, !enable); 286 287 return ret; 288 } 289 290 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 291 bool enable) 292 { 293 struct smu_power_context *smu_power = &smu->smu_power; 294 struct smu_power_gate *power_gate = &smu_power->power_gate; 295 int ret = 0; 296 297 if (!smu->ppt_funcs->dpm_set_vpe_enable) 298 return 0; 299 300 if (atomic_read(&power_gate->vpe_gated) ^ enable) 301 return 0; 302 303 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 304 if (!ret) 305 atomic_set(&power_gate->vpe_gated, !enable); 306 307 return ret; 308 } 309 310 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 311 bool enable) 312 { 313 struct smu_power_context *smu_power = &smu->smu_power; 314 struct smu_power_gate *power_gate = &smu_power->power_gate; 315 int ret = 0; 316 317 if (!smu->adev->enable_umsch_mm) 318 return 0; 319 320 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 321 return 0; 322 323 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 324 return 0; 325 326 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 327 if (!ret) 328 atomic_set(&power_gate->umsch_mm_gated, !enable); 329 330 return ret; 331 } 332 333 static int smu_set_mall_enable(struct smu_context *smu) 334 { 335 int ret = 0; 336 337 if (!smu->ppt_funcs->set_mall_enable) 338 return 0; 339 340 ret = smu->ppt_funcs->set_mall_enable(smu); 341 342 return ret; 343 } 344 345 /** 346 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 347 * 348 * @handle: smu_context pointer 349 * @block_type: the IP block to power gate/ungate 350 * @gate: to power gate if true, ungate otherwise 351 * @inst: the instance of the IP block to power gate/ungate 352 * 353 * This API uses no smu->mutex lock protection due to: 354 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 355 * This is guarded to be race condition free by the caller. 356 * 2. Or get called on user setting request of power_dpm_force_performance_level. 357 * Under this case, the smu->mutex lock protection is already enforced on 358 * the parent API smu_force_performance_level of the call path. 359 */ 360 static int smu_dpm_set_power_gate(void *handle, 361 uint32_t block_type, 362 bool gate, 363 int inst) 364 { 365 struct smu_context *smu = handle; 366 int ret = 0; 367 368 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 369 dev_WARN(smu->adev->dev, 370 "SMU uninitialized but power %s requested for %u!\n", 371 gate ? "gate" : "ungate", block_type); 372 return -EOPNOTSUPP; 373 } 374 375 switch (block_type) { 376 /* 377 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 378 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 379 */ 380 case AMD_IP_BLOCK_TYPE_UVD: 381 case AMD_IP_BLOCK_TYPE_VCN: 382 ret = smu_dpm_set_vcn_enable(smu, !gate, inst); 383 if (ret) 384 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n", 385 gate ? "gate" : "ungate", inst); 386 break; 387 case AMD_IP_BLOCK_TYPE_GFX: 388 ret = smu_gfx_off_control(smu, gate); 389 if (ret) 390 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 391 gate ? "enable" : "disable"); 392 break; 393 case AMD_IP_BLOCK_TYPE_SDMA: 394 ret = smu_powergate_sdma(smu, gate); 395 if (ret) 396 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 397 gate ? "gate" : "ungate"); 398 break; 399 case AMD_IP_BLOCK_TYPE_JPEG: 400 ret = smu_dpm_set_jpeg_enable(smu, !gate); 401 if (ret) 402 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 403 gate ? "gate" : "ungate"); 404 break; 405 case AMD_IP_BLOCK_TYPE_VPE: 406 ret = smu_dpm_set_vpe_enable(smu, !gate); 407 if (ret) 408 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 409 gate ? "gate" : "ungate"); 410 break; 411 default: 412 dev_err(smu->adev->dev, "Unsupported block type!\n"); 413 return -EINVAL; 414 } 415 416 return ret; 417 } 418 419 /** 420 * smu_set_user_clk_dependencies - set user profile clock dependencies 421 * 422 * @smu: smu_context pointer 423 * @clk: enum smu_clk_type type 424 * 425 * Enable/Disable the clock dependency for the @clk type. 426 */ 427 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 428 { 429 if (smu->adev->in_suspend) 430 return; 431 432 if (clk == SMU_MCLK) { 433 smu->user_dpm_profile.clk_dependency = 0; 434 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 435 } else if (clk == SMU_FCLK) { 436 /* MCLK takes precedence over FCLK */ 437 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 438 return; 439 440 smu->user_dpm_profile.clk_dependency = 0; 441 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 442 } else if (clk == SMU_SOCCLK) { 443 /* MCLK takes precedence over SOCCLK */ 444 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 445 return; 446 447 smu->user_dpm_profile.clk_dependency = 0; 448 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 449 } else 450 /* Add clk dependencies here, if any */ 451 return; 452 } 453 454 /** 455 * smu_restore_dpm_user_profile - reinstate user dpm profile 456 * 457 * @smu: smu_context pointer 458 * 459 * Restore the saved user power configurations include power limit, 460 * clock frequencies, fan control mode and fan speed. 461 */ 462 static void smu_restore_dpm_user_profile(struct smu_context *smu) 463 { 464 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 465 int ret = 0; 466 467 if (!smu->adev->in_suspend) 468 return; 469 470 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 471 return; 472 473 /* Enable restore flag */ 474 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 475 476 /* set the user dpm power limit */ 477 if (smu->user_dpm_profile.power_limit) { 478 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 479 if (ret) 480 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 481 } 482 483 /* set the user dpm clock configurations */ 484 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 485 enum smu_clk_type clk_type; 486 487 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 488 /* 489 * Iterate over smu clk type and force the saved user clk 490 * configs, skip if clock dependency is enabled 491 */ 492 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 493 smu->user_dpm_profile.clk_mask[clk_type]) { 494 ret = smu_force_smuclk_levels(smu, clk_type, 495 smu->user_dpm_profile.clk_mask[clk_type]); 496 if (ret) 497 dev_err(smu->adev->dev, 498 "Failed to set clock type = %d\n", clk_type); 499 } 500 } 501 } 502 503 /* set the user dpm fan configurations */ 504 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 505 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 506 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 507 if (ret != -EOPNOTSUPP) { 508 smu->user_dpm_profile.fan_speed_pwm = 0; 509 smu->user_dpm_profile.fan_speed_rpm = 0; 510 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 511 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 512 } 513 514 if (smu->user_dpm_profile.fan_speed_pwm) { 515 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 516 if (ret != -EOPNOTSUPP) 517 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 518 } 519 520 if (smu->user_dpm_profile.fan_speed_rpm) { 521 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 522 if (ret != -EOPNOTSUPP) 523 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 524 } 525 } 526 527 /* Restore user customized OD settings */ 528 if (smu->user_dpm_profile.user_od) { 529 if (smu->ppt_funcs->restore_user_od_settings) { 530 ret = smu->ppt_funcs->restore_user_od_settings(smu); 531 if (ret) 532 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 533 } 534 } 535 536 /* Disable restore flag */ 537 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 538 } 539 540 static int smu_get_power_num_states(void *handle, 541 struct pp_states_info *state_info) 542 { 543 if (!state_info) 544 return -EINVAL; 545 546 /* not support power state */ 547 memset(state_info, 0, sizeof(struct pp_states_info)); 548 state_info->nums = 1; 549 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 550 551 return 0; 552 } 553 554 bool is_support_sw_smu(struct amdgpu_device *adev) 555 { 556 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 557 if (adev->asic_type == CHIP_VEGA20) 558 return false; 559 560 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && 561 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) 562 return true; 563 564 return false; 565 } 566 567 bool is_support_cclk_dpm(struct amdgpu_device *adev) 568 { 569 struct smu_context *smu = adev->powerplay.pp_handle; 570 571 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 572 return false; 573 574 return true; 575 } 576 577 578 static int smu_sys_get_pp_table(void *handle, 579 char **table) 580 { 581 struct smu_context *smu = handle; 582 struct smu_table_context *smu_table = &smu->smu_table; 583 584 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 585 return -EOPNOTSUPP; 586 587 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 588 return -EINVAL; 589 590 if (smu_table->hardcode_pptable) 591 *table = smu_table->hardcode_pptable; 592 else 593 *table = smu_table->power_play_table; 594 595 return smu_table->power_play_table_size; 596 } 597 598 static int smu_sys_set_pp_table(void *handle, 599 const char *buf, 600 size_t size) 601 { 602 struct smu_context *smu = handle; 603 struct smu_table_context *smu_table = &smu->smu_table; 604 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 605 int ret = 0; 606 607 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 608 return -EOPNOTSUPP; 609 610 if (header->usStructureSize != size) { 611 dev_err(smu->adev->dev, "pp table size not matched !\n"); 612 return -EIO; 613 } 614 615 if (!smu_table->hardcode_pptable || smu_table->power_play_table_size < size) { 616 kfree(smu_table->hardcode_pptable); 617 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 618 if (!smu_table->hardcode_pptable) 619 return -ENOMEM; 620 } 621 622 memcpy(smu_table->hardcode_pptable, buf, size); 623 smu_table->power_play_table = smu_table->hardcode_pptable; 624 smu_table->power_play_table_size = size; 625 626 /* 627 * Special hw_fini action(for Navi1x, the DPMs disablement will be 628 * skipped) may be needed for custom pptable uploading. 629 */ 630 smu->uploading_custom_pp_table = true; 631 632 ret = smu_reset(smu); 633 if (ret) 634 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 635 636 smu->uploading_custom_pp_table = false; 637 638 return ret; 639 } 640 641 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 642 { 643 struct smu_feature *feature = &smu->smu_feature; 644 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 645 int ret = 0; 646 647 /* 648 * With SCPM enabled, the allowed featuremasks setting(via 649 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 650 * That means there is no way to let PMFW knows the settings below. 651 * Thus, we just assume all the features are allowed under 652 * such scenario. 653 */ 654 if (smu->adev->scpm_enabled) { 655 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 656 return 0; 657 } 658 659 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 660 661 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 662 SMU_FEATURE_MAX/32); 663 if (ret) 664 return ret; 665 666 bitmap_or(feature->allowed, feature->allowed, 667 (unsigned long *)allowed_feature_mask, 668 feature->feature_num); 669 670 return ret; 671 } 672 673 static int smu_set_funcs(struct amdgpu_device *adev) 674 { 675 struct smu_context *smu = adev->powerplay.pp_handle; 676 677 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 678 smu->od_enabled = true; 679 680 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 681 case IP_VERSION(11, 0, 0): 682 case IP_VERSION(11, 0, 5): 683 case IP_VERSION(11, 0, 9): 684 navi10_set_ppt_funcs(smu); 685 break; 686 case IP_VERSION(11, 0, 7): 687 case IP_VERSION(11, 0, 11): 688 case IP_VERSION(11, 0, 12): 689 case IP_VERSION(11, 0, 13): 690 sienna_cichlid_set_ppt_funcs(smu); 691 break; 692 case IP_VERSION(12, 0, 0): 693 case IP_VERSION(12, 0, 1): 694 renoir_set_ppt_funcs(smu); 695 break; 696 case IP_VERSION(11, 5, 0): 697 case IP_VERSION(11, 5, 2): 698 vangogh_set_ppt_funcs(smu); 699 break; 700 case IP_VERSION(13, 0, 1): 701 case IP_VERSION(13, 0, 3): 702 case IP_VERSION(13, 0, 8): 703 yellow_carp_set_ppt_funcs(smu); 704 break; 705 case IP_VERSION(13, 0, 4): 706 case IP_VERSION(13, 0, 11): 707 smu_v13_0_4_set_ppt_funcs(smu); 708 break; 709 case IP_VERSION(13, 0, 5): 710 smu_v13_0_5_set_ppt_funcs(smu); 711 break; 712 case IP_VERSION(11, 0, 8): 713 cyan_skillfish_set_ppt_funcs(smu); 714 break; 715 case IP_VERSION(11, 0, 2): 716 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 717 arcturus_set_ppt_funcs(smu); 718 /* OD is not supported on Arcturus */ 719 smu->od_enabled = false; 720 break; 721 case IP_VERSION(13, 0, 2): 722 aldebaran_set_ppt_funcs(smu); 723 /* Enable pp_od_clk_voltage node */ 724 smu->od_enabled = true; 725 break; 726 case IP_VERSION(13, 0, 0): 727 case IP_VERSION(13, 0, 10): 728 smu_v13_0_0_set_ppt_funcs(smu); 729 break; 730 case IP_VERSION(13, 0, 6): 731 case IP_VERSION(13, 0, 14): 732 case IP_VERSION(13, 0, 12): 733 smu_v13_0_6_set_ppt_funcs(smu); 734 /* Enable pp_od_clk_voltage node */ 735 smu->od_enabled = true; 736 break; 737 case IP_VERSION(13, 0, 7): 738 smu_v13_0_7_set_ppt_funcs(smu); 739 break; 740 case IP_VERSION(14, 0, 0): 741 case IP_VERSION(14, 0, 1): 742 case IP_VERSION(14, 0, 4): 743 case IP_VERSION(14, 0, 5): 744 smu_v14_0_0_set_ppt_funcs(smu); 745 break; 746 case IP_VERSION(14, 0, 2): 747 case IP_VERSION(14, 0, 3): 748 smu_v14_0_2_set_ppt_funcs(smu); 749 break; 750 default: 751 return -EINVAL; 752 } 753 754 return 0; 755 } 756 757 static int smu_early_init(struct amdgpu_ip_block *ip_block) 758 { 759 struct amdgpu_device *adev = ip_block->adev; 760 struct smu_context *smu; 761 int r; 762 763 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 764 if (!smu) 765 return -ENOMEM; 766 767 smu->adev = adev; 768 smu->pm_enabled = !!amdgpu_dpm; 769 smu->is_apu = false; 770 smu->smu_baco.state = SMU_BACO_STATE_NONE; 771 smu->smu_baco.platform_support = false; 772 smu->smu_baco.maco_support = false; 773 smu->user_dpm_profile.fan_mode = -1; 774 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN; 775 776 mutex_init(&smu->message_lock); 777 778 adev->powerplay.pp_handle = smu; 779 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 780 781 r = smu_set_funcs(adev); 782 if (r) 783 return r; 784 return smu_init_microcode(smu); 785 } 786 787 static int smu_set_default_dpm_table(struct smu_context *smu) 788 { 789 struct amdgpu_device *adev = smu->adev; 790 struct smu_power_context *smu_power = &smu->smu_power; 791 struct smu_power_gate *power_gate = &smu_power->power_gate; 792 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i; 793 int ret = 0; 794 795 if (!smu->ppt_funcs->set_default_dpm_table) 796 return 0; 797 798 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 799 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 800 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]); 801 } 802 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 803 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 804 805 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 806 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 807 ret = smu_dpm_set_vcn_enable(smu, true, i); 808 if (ret) 809 return ret; 810 } 811 } 812 813 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 814 ret = smu_dpm_set_jpeg_enable(smu, true); 815 if (ret) 816 goto err_out; 817 } 818 819 ret = smu->ppt_funcs->set_default_dpm_table(smu); 820 if (ret) 821 dev_err(smu->adev->dev, 822 "Failed to setup default dpm clock tables!\n"); 823 824 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 825 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 826 err_out: 827 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 828 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 829 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i); 830 } 831 832 return ret; 833 } 834 835 static int smu_apply_default_config_table_settings(struct smu_context *smu) 836 { 837 struct amdgpu_device *adev = smu->adev; 838 int ret = 0; 839 840 ret = smu_get_default_config_table_settings(smu, 841 &adev->pm.config_table); 842 if (ret) 843 return ret; 844 845 return smu_set_config_table(smu, &adev->pm.config_table); 846 } 847 848 static int smu_late_init(struct amdgpu_ip_block *ip_block) 849 { 850 struct amdgpu_device *adev = ip_block->adev; 851 struct smu_context *smu = adev->powerplay.pp_handle; 852 int ret = 0; 853 854 smu_set_fine_grain_gfx_freq_parameters(smu); 855 856 if (!smu->pm_enabled) 857 return 0; 858 859 ret = smu_post_init(smu); 860 if (ret) { 861 dev_err(adev->dev, "Failed to post smu init!\n"); 862 return ret; 863 } 864 865 /* 866 * Explicitly notify PMFW the power mode the system in. Since 867 * the PMFW may boot the ASIC with a different mode. 868 * For those supporting ACDC switch via gpio, PMFW will 869 * handle the switch automatically. Driver involvement 870 * is unnecessary. 871 */ 872 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 873 smu_set_ac_dc(smu); 874 875 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 876 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 877 return 0; 878 879 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 880 ret = smu_set_default_od_settings(smu); 881 if (ret) { 882 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 883 return ret; 884 } 885 } 886 887 ret = smu_populate_umd_state_clk(smu); 888 if (ret) { 889 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 890 return ret; 891 } 892 893 ret = smu_get_asic_power_limits(smu, 894 &smu->current_power_limit, 895 &smu->default_power_limit, 896 &smu->max_power_limit, 897 &smu->min_power_limit); 898 if (ret) { 899 dev_err(adev->dev, "Failed to get asic power limits!\n"); 900 return ret; 901 } 902 903 if (!amdgpu_sriov_vf(adev)) 904 smu_get_unique_id(smu); 905 906 smu_get_fan_parameters(smu); 907 908 smu_handle_task(smu, 909 smu->smu_dpm.dpm_level, 910 AMD_PP_TASK_COMPLETE_INIT); 911 912 ret = smu_apply_default_config_table_settings(smu); 913 if (ret && (ret != -EOPNOTSUPP)) { 914 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 915 return ret; 916 } 917 918 smu_restore_dpm_user_profile(smu); 919 920 return 0; 921 } 922 923 static int smu_init_fb_allocations(struct smu_context *smu) 924 { 925 struct amdgpu_device *adev = smu->adev; 926 struct smu_table_context *smu_table = &smu->smu_table; 927 struct smu_table *tables = smu_table->tables; 928 struct smu_table *driver_table = &(smu_table->driver_table); 929 uint32_t max_table_size = 0; 930 int ret, i; 931 932 /* VRAM allocation for tool table */ 933 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 934 ret = amdgpu_bo_create_kernel(adev, 935 tables[SMU_TABLE_PMSTATUSLOG].size, 936 tables[SMU_TABLE_PMSTATUSLOG].align, 937 tables[SMU_TABLE_PMSTATUSLOG].domain, 938 &tables[SMU_TABLE_PMSTATUSLOG].bo, 939 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 940 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 941 if (ret) { 942 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 943 return ret; 944 } 945 } 946 947 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 948 /* VRAM allocation for driver table */ 949 for (i = 0; i < SMU_TABLE_COUNT; i++) { 950 if (tables[i].size == 0) 951 continue; 952 953 /* If one of the tables has VRAM domain restriction, keep it in 954 * VRAM 955 */ 956 if ((tables[i].domain & 957 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 958 AMDGPU_GEM_DOMAIN_VRAM) 959 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 960 961 if (i == SMU_TABLE_PMSTATUSLOG) 962 continue; 963 964 if (max_table_size < tables[i].size) 965 max_table_size = tables[i].size; 966 } 967 968 driver_table->size = max_table_size; 969 driver_table->align = PAGE_SIZE; 970 971 ret = amdgpu_bo_create_kernel(adev, 972 driver_table->size, 973 driver_table->align, 974 driver_table->domain, 975 &driver_table->bo, 976 &driver_table->mc_address, 977 &driver_table->cpu_addr); 978 if (ret) { 979 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 980 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 981 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 982 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 983 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 984 } 985 986 return ret; 987 } 988 989 static int smu_fini_fb_allocations(struct smu_context *smu) 990 { 991 struct smu_table_context *smu_table = &smu->smu_table; 992 struct smu_table *tables = smu_table->tables; 993 struct smu_table *driver_table = &(smu_table->driver_table); 994 995 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 996 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 997 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 998 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 999 1000 amdgpu_bo_free_kernel(&driver_table->bo, 1001 &driver_table->mc_address, 1002 &driver_table->cpu_addr); 1003 1004 return 0; 1005 } 1006 1007 static void smu_update_gpu_addresses(struct smu_context *smu) 1008 { 1009 struct smu_table_context *smu_table = &smu->smu_table; 1010 struct smu_table *pm_status_table = smu_table->tables + SMU_TABLE_PMSTATUSLOG; 1011 struct smu_table *driver_table = &(smu_table->driver_table); 1012 struct smu_table *dummy_read_1_table = &smu_table->dummy_read_1_table; 1013 1014 if (pm_status_table->bo) 1015 pm_status_table->mc_address = amdgpu_bo_fb_aper_addr(pm_status_table->bo); 1016 if (driver_table->bo) 1017 driver_table->mc_address = amdgpu_bo_fb_aper_addr(driver_table->bo); 1018 if (dummy_read_1_table->bo) 1019 dummy_read_1_table->mc_address = amdgpu_bo_fb_aper_addr(dummy_read_1_table->bo); 1020 } 1021 1022 /** 1023 * smu_alloc_memory_pool - allocate memory pool in the system memory 1024 * 1025 * @smu: amdgpu_device pointer 1026 * 1027 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 1028 * and DramLogSetDramAddr can notify it changed. 1029 * 1030 * Returns 0 on success, error on failure. 1031 */ 1032 static int smu_alloc_memory_pool(struct smu_context *smu) 1033 { 1034 struct amdgpu_device *adev = smu->adev; 1035 struct smu_table_context *smu_table = &smu->smu_table; 1036 struct smu_table *memory_pool = &smu_table->memory_pool; 1037 uint64_t pool_size = smu->pool_size; 1038 int ret = 0; 1039 1040 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1041 return ret; 1042 1043 memory_pool->size = pool_size; 1044 memory_pool->align = PAGE_SIZE; 1045 memory_pool->domain = 1046 (adev->pm.smu_debug_mask & SMU_DEBUG_POOL_USE_VRAM) ? 1047 AMDGPU_GEM_DOMAIN_VRAM : 1048 AMDGPU_GEM_DOMAIN_GTT; 1049 1050 switch (pool_size) { 1051 case SMU_MEMORY_POOL_SIZE_256_MB: 1052 case SMU_MEMORY_POOL_SIZE_512_MB: 1053 case SMU_MEMORY_POOL_SIZE_1_GB: 1054 case SMU_MEMORY_POOL_SIZE_2_GB: 1055 ret = amdgpu_bo_create_kernel(adev, 1056 memory_pool->size, 1057 memory_pool->align, 1058 memory_pool->domain, 1059 &memory_pool->bo, 1060 &memory_pool->mc_address, 1061 &memory_pool->cpu_addr); 1062 if (ret) 1063 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1064 break; 1065 default: 1066 break; 1067 } 1068 1069 return ret; 1070 } 1071 1072 static int smu_free_memory_pool(struct smu_context *smu) 1073 { 1074 struct smu_table_context *smu_table = &smu->smu_table; 1075 struct smu_table *memory_pool = &smu_table->memory_pool; 1076 1077 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1078 return 0; 1079 1080 amdgpu_bo_free_kernel(&memory_pool->bo, 1081 &memory_pool->mc_address, 1082 &memory_pool->cpu_addr); 1083 1084 memset(memory_pool, 0, sizeof(struct smu_table)); 1085 1086 return 0; 1087 } 1088 1089 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1090 { 1091 struct smu_table_context *smu_table = &smu->smu_table; 1092 struct smu_table *dummy_read_1_table = 1093 &smu_table->dummy_read_1_table; 1094 struct amdgpu_device *adev = smu->adev; 1095 int ret = 0; 1096 1097 if (!dummy_read_1_table->size) 1098 return 0; 1099 1100 ret = amdgpu_bo_create_kernel(adev, 1101 dummy_read_1_table->size, 1102 dummy_read_1_table->align, 1103 dummy_read_1_table->domain, 1104 &dummy_read_1_table->bo, 1105 &dummy_read_1_table->mc_address, 1106 &dummy_read_1_table->cpu_addr); 1107 if (ret) 1108 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1109 1110 return ret; 1111 } 1112 1113 static void smu_free_dummy_read_table(struct smu_context *smu) 1114 { 1115 struct smu_table_context *smu_table = &smu->smu_table; 1116 struct smu_table *dummy_read_1_table = 1117 &smu_table->dummy_read_1_table; 1118 1119 1120 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1121 &dummy_read_1_table->mc_address, 1122 &dummy_read_1_table->cpu_addr); 1123 1124 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1125 } 1126 1127 static int smu_smc_table_sw_init(struct smu_context *smu) 1128 { 1129 int ret; 1130 1131 /** 1132 * Create smu_table structure, and init smc tables such as 1133 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1134 */ 1135 ret = smu_init_smc_tables(smu); 1136 if (ret) { 1137 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1138 return ret; 1139 } 1140 1141 /** 1142 * Create smu_power_context structure, and allocate smu_dpm_context and 1143 * context size to fill the smu_power_context data. 1144 */ 1145 ret = smu_init_power(smu); 1146 if (ret) { 1147 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1148 return ret; 1149 } 1150 1151 /* 1152 * allocate vram bos to store smc table contents. 1153 */ 1154 ret = smu_init_fb_allocations(smu); 1155 if (ret) 1156 return ret; 1157 1158 ret = smu_alloc_memory_pool(smu); 1159 if (ret) 1160 return ret; 1161 1162 ret = smu_alloc_dummy_read_table(smu); 1163 if (ret) 1164 return ret; 1165 1166 ret = smu_i2c_init(smu); 1167 if (ret) 1168 return ret; 1169 1170 return 0; 1171 } 1172 1173 static int smu_smc_table_sw_fini(struct smu_context *smu) 1174 { 1175 int ret; 1176 1177 smu_i2c_fini(smu); 1178 1179 smu_free_dummy_read_table(smu); 1180 1181 ret = smu_free_memory_pool(smu); 1182 if (ret) 1183 return ret; 1184 1185 ret = smu_fini_fb_allocations(smu); 1186 if (ret) 1187 return ret; 1188 1189 ret = smu_fini_power(smu); 1190 if (ret) { 1191 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1192 return ret; 1193 } 1194 1195 ret = smu_fini_smc_tables(smu); 1196 if (ret) { 1197 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1198 return ret; 1199 } 1200 1201 return 0; 1202 } 1203 1204 static void smu_throttling_logging_work_fn(struct work_struct *work) 1205 { 1206 struct smu_context *smu = container_of(work, struct smu_context, 1207 throttling_logging_work); 1208 1209 smu_log_thermal_throttling(smu); 1210 } 1211 1212 static void smu_interrupt_work_fn(struct work_struct *work) 1213 { 1214 struct smu_context *smu = container_of(work, struct smu_context, 1215 interrupt_work); 1216 1217 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1218 smu->ppt_funcs->interrupt_work(smu); 1219 } 1220 1221 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1222 { 1223 struct smu_context *smu = 1224 container_of(work, struct smu_context, swctf_delayed_work.work); 1225 struct smu_temperature_range *range = 1226 &smu->thermal_range; 1227 struct amdgpu_device *adev = smu->adev; 1228 uint32_t hotspot_tmp, size; 1229 1230 /* 1231 * If the hotspot temperature is confirmed as below SW CTF setting point 1232 * after the delay enforced, nothing will be done. 1233 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1234 */ 1235 if (range->software_shutdown_temp && 1236 smu->ppt_funcs->read_sensor && 1237 !smu->ppt_funcs->read_sensor(smu, 1238 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1239 &hotspot_tmp, 1240 &size) && 1241 hotspot_tmp / 1000 < range->software_shutdown_temp) 1242 return; 1243 1244 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1245 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1246 orderly_poweroff(true); 1247 } 1248 1249 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1250 { 1251 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1252 struct smu_dpm_policy_ctxt *policy_ctxt; 1253 struct smu_dpm_policy *policy; 1254 1255 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1256 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1257 if (policy) 1258 policy->current_level = XGMI_PLPD_DEFAULT; 1259 return; 1260 } 1261 1262 /* PMFW put PLPD into default policy after enabling the feature */ 1263 if (smu_feature_is_enabled(smu, 1264 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1265 if (policy) 1266 policy->current_level = XGMI_PLPD_DEFAULT; 1267 } else { 1268 policy_ctxt = dpm_ctxt->dpm_policies; 1269 if (policy_ctxt) 1270 policy_ctxt->policy_mask &= 1271 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1272 } 1273 } 1274 1275 static void smu_init_power_profile(struct smu_context *smu) 1276 { 1277 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) 1278 smu->power_profile_mode = 1279 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1280 smu_power_profile_mode_get(smu, smu->power_profile_mode); 1281 } 1282 1283 static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1284 { 1285 struct amdgpu_device *adev = ip_block->adev; 1286 struct smu_context *smu = adev->powerplay.pp_handle; 1287 int i, ret; 1288 1289 smu->pool_size = adev->pm.smu_prv_buffer_size; 1290 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1291 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1292 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1293 1294 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1295 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1296 atomic64_set(&smu->throttle_int_counter, 0); 1297 smu->watermarks_bitmap = 0; 1298 1299 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1300 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1); 1301 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1302 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1303 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1304 1305 smu_init_power_profile(smu); 1306 smu->display_config = &adev->pm.pm_display_cfg; 1307 1308 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1309 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1310 1311 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1312 smu_swctf_delayed_work_handler); 1313 1314 ret = smu_smc_table_sw_init(smu); 1315 if (ret) { 1316 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1317 return ret; 1318 } 1319 1320 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1321 ret = smu_get_vbios_bootup_values(smu); 1322 if (ret) { 1323 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1324 return ret; 1325 } 1326 1327 ret = smu_init_pptable_microcode(smu); 1328 if (ret) { 1329 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1330 return ret; 1331 } 1332 1333 ret = smu_register_irq_handler(smu); 1334 if (ret) { 1335 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1336 return ret; 1337 } 1338 1339 /* If there is no way to query fan control mode, fan control is not supported */ 1340 if (!smu->ppt_funcs->get_fan_control_mode) 1341 smu->adev->pm.no_fan = true; 1342 1343 return 0; 1344 } 1345 1346 static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1347 { 1348 struct amdgpu_device *adev = ip_block->adev; 1349 struct smu_context *smu = adev->powerplay.pp_handle; 1350 int ret; 1351 1352 ret = smu_smc_table_sw_fini(smu); 1353 if (ret) { 1354 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1355 return ret; 1356 } 1357 1358 if (smu->custom_profile_params) { 1359 kfree(smu->custom_profile_params); 1360 smu->custom_profile_params = NULL; 1361 } 1362 1363 smu_fini_microcode(smu); 1364 1365 return 0; 1366 } 1367 1368 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1369 { 1370 struct amdgpu_device *adev = smu->adev; 1371 struct smu_temperature_range *range = 1372 &smu->thermal_range; 1373 int ret = 0; 1374 1375 if (!smu->ppt_funcs->get_thermal_temperature_range) 1376 return 0; 1377 1378 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1379 if (ret) 1380 return ret; 1381 1382 adev->pm.dpm.thermal.min_temp = range->min; 1383 adev->pm.dpm.thermal.max_temp = range->max; 1384 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1385 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1386 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1387 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1388 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1389 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1390 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1391 1392 return ret; 1393 } 1394 1395 /** 1396 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1397 * 1398 * @smu: smu_context pointer 1399 * 1400 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1401 * Returns 0 on success, error on failure. 1402 */ 1403 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1404 { 1405 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1406 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1407 struct amdgpu_device *adev = smu->adev; 1408 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1409 uint64_t start, end; 1410 int ret, i, j; 1411 1412 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1413 if (ret) { 1414 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1415 return ret; 1416 } 1417 1418 /* 1419 * The exclusion ranges array we got might be filled with holes and duplicate 1420 * entries. For example: 1421 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1422 * We need to do some sortups to eliminate those holes and duplicate entries. 1423 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1424 */ 1425 for (i = 0; i < num_of_wbrf_ranges; i++) { 1426 start = wifi_bands[i].start; 1427 end = wifi_bands[i].end; 1428 1429 /* get the last valid entry to fill the intermediate hole */ 1430 if (!start && !end) { 1431 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1432 if (wifi_bands[j].start && wifi_bands[j].end) 1433 break; 1434 1435 /* no valid entry left */ 1436 if (j <= i) 1437 break; 1438 1439 start = wifi_bands[i].start = wifi_bands[j].start; 1440 end = wifi_bands[i].end = wifi_bands[j].end; 1441 wifi_bands[j].start = 0; 1442 wifi_bands[j].end = 0; 1443 num_of_wbrf_ranges = j; 1444 } 1445 1446 /* eliminate duplicate entries */ 1447 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1448 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1449 wifi_bands[j].start = 0; 1450 wifi_bands[j].end = 0; 1451 } 1452 } 1453 } 1454 1455 /* Send the sorted wifi_bands to PMFW */ 1456 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1457 /* Try to set the wifi_bands again */ 1458 if (unlikely(ret == -EBUSY)) { 1459 mdelay(5); 1460 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1461 } 1462 1463 return ret; 1464 } 1465 1466 /** 1467 * smu_wbrf_event_handler - handle notify events 1468 * 1469 * @nb: notifier block 1470 * @action: event type 1471 * @_arg: event data 1472 * 1473 * Calls relevant amdgpu function in response to wbrf event 1474 * notification from kernel. 1475 */ 1476 static int smu_wbrf_event_handler(struct notifier_block *nb, 1477 unsigned long action, void *_arg) 1478 { 1479 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1480 1481 switch (action) { 1482 case WBRF_CHANGED: 1483 schedule_delayed_work(&smu->wbrf_delayed_work, 1484 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1485 break; 1486 default: 1487 return NOTIFY_DONE; 1488 } 1489 1490 return NOTIFY_OK; 1491 } 1492 1493 /** 1494 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1495 * 1496 * @work: struct work_struct pointer 1497 * 1498 * Flood is over and driver will consume the latest exclusion ranges. 1499 */ 1500 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1501 { 1502 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1503 1504 smu_wbrf_handle_exclusion_ranges(smu); 1505 } 1506 1507 /** 1508 * smu_wbrf_support_check - check wbrf support 1509 * 1510 * @smu: smu_context pointer 1511 * 1512 * Verifies the ACPI interface whether wbrf is supported. 1513 */ 1514 static void smu_wbrf_support_check(struct smu_context *smu) 1515 { 1516 struct amdgpu_device *adev = smu->adev; 1517 1518 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1519 acpi_amd_wbrf_supported_consumer(adev->dev); 1520 1521 if (smu->wbrf_supported) 1522 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1523 } 1524 1525 /** 1526 * smu_wbrf_init - init driver wbrf support 1527 * 1528 * @smu: smu_context pointer 1529 * 1530 * Verifies the AMD ACPI interfaces and registers with the wbrf 1531 * notifier chain if wbrf feature is supported. 1532 * Returns 0 on success, error on failure. 1533 */ 1534 static int smu_wbrf_init(struct smu_context *smu) 1535 { 1536 int ret; 1537 1538 if (!smu->wbrf_supported) 1539 return 0; 1540 1541 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1542 1543 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1544 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1545 if (ret) 1546 return ret; 1547 1548 /* 1549 * Some wifiband exclusion ranges may be already there 1550 * before our driver loaded. To make sure our driver 1551 * is awared of those exclusion ranges. 1552 */ 1553 schedule_delayed_work(&smu->wbrf_delayed_work, 1554 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1555 1556 return 0; 1557 } 1558 1559 /** 1560 * smu_wbrf_fini - tear down driver wbrf support 1561 * 1562 * @smu: smu_context pointer 1563 * 1564 * Unregisters with the wbrf notifier chain. 1565 */ 1566 static void smu_wbrf_fini(struct smu_context *smu) 1567 { 1568 if (!smu->wbrf_supported) 1569 return; 1570 1571 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1572 1573 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1574 } 1575 1576 static int smu_smc_hw_setup(struct smu_context *smu) 1577 { 1578 struct smu_feature *feature = &smu->smu_feature; 1579 struct amdgpu_device *adev = smu->adev; 1580 uint8_t pcie_gen = 0, pcie_width = 0; 1581 uint64_t features_supported; 1582 int ret = 0; 1583 1584 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1585 case IP_VERSION(11, 0, 7): 1586 case IP_VERSION(11, 0, 11): 1587 case IP_VERSION(11, 5, 0): 1588 case IP_VERSION(11, 5, 2): 1589 case IP_VERSION(11, 0, 12): 1590 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1591 dev_info(adev->dev, "dpm has been enabled\n"); 1592 ret = smu_system_features_control(smu, true); 1593 if (ret) 1594 dev_err(adev->dev, "Failed system features control!\n"); 1595 return ret; 1596 } 1597 break; 1598 default: 1599 break; 1600 } 1601 1602 ret = smu_init_display_count(smu, 0); 1603 if (ret) { 1604 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1605 return ret; 1606 } 1607 1608 ret = smu_set_driver_table_location(smu); 1609 if (ret) { 1610 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1611 return ret; 1612 } 1613 1614 /* 1615 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1616 */ 1617 ret = smu_set_tool_table_location(smu); 1618 if (ret) { 1619 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1620 return ret; 1621 } 1622 1623 /* 1624 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1625 * pool location. 1626 */ 1627 ret = smu_notify_memory_pool_location(smu); 1628 if (ret) { 1629 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1630 return ret; 1631 } 1632 1633 /* 1634 * It is assumed the pptable used before runpm is same as 1635 * the one used afterwards. Thus, we can reuse the stored 1636 * copy and do not need to resetup the pptable again. 1637 */ 1638 if (!adev->in_runpm) { 1639 ret = smu_setup_pptable(smu); 1640 if (ret) { 1641 dev_err(adev->dev, "Failed to setup pptable!\n"); 1642 return ret; 1643 } 1644 } 1645 1646 /* smu_dump_pptable(smu); */ 1647 1648 /* 1649 * With SCPM enabled, PSP is responsible for the PPTable transferring 1650 * (to SMU). Driver involvement is not needed and permitted. 1651 */ 1652 if (!adev->scpm_enabled) { 1653 /* 1654 * Copy pptable bo in the vram to smc with SMU MSGs such as 1655 * SetDriverDramAddr and TransferTableDram2Smu. 1656 */ 1657 ret = smu_write_pptable(smu); 1658 if (ret) { 1659 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1660 return ret; 1661 } 1662 } 1663 1664 /* issue Run*Btc msg */ 1665 ret = smu_run_btc(smu); 1666 if (ret) 1667 return ret; 1668 1669 /* Enable UclkShadow on wbrf supported */ 1670 if (smu->wbrf_supported) { 1671 ret = smu_enable_uclk_shadow(smu, true); 1672 if (ret) { 1673 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1674 return ret; 1675 } 1676 } 1677 1678 /* 1679 * With SCPM enabled, these actions(and relevant messages) are 1680 * not needed and permitted. 1681 */ 1682 if (!adev->scpm_enabled) { 1683 ret = smu_feature_set_allowed_mask(smu); 1684 if (ret) { 1685 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1686 return ret; 1687 } 1688 } 1689 1690 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) 1691 pcie_gen = 4; 1692 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1693 pcie_gen = 3; 1694 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1695 pcie_gen = 2; 1696 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1697 pcie_gen = 1; 1698 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1699 pcie_gen = 0; 1700 1701 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1702 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1703 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1704 */ 1705 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) 1706 pcie_width = 7; 1707 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1708 pcie_width = 6; 1709 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1710 pcie_width = 5; 1711 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1712 pcie_width = 4; 1713 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1714 pcie_width = 3; 1715 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1716 pcie_width = 2; 1717 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1718 pcie_width = 1; 1719 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1720 if (ret) { 1721 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1722 return ret; 1723 } 1724 1725 ret = smu_system_features_control(smu, true); 1726 if (ret) { 1727 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1728 return ret; 1729 } 1730 1731 smu_init_xgmi_plpd_mode(smu); 1732 1733 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1734 if (ret) { 1735 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1736 return ret; 1737 } 1738 bitmap_copy(feature->supported, 1739 (unsigned long *)&features_supported, 1740 feature->feature_num); 1741 1742 if (!smu_is_dpm_running(smu)) 1743 dev_info(adev->dev, "dpm has been disabled\n"); 1744 1745 /* 1746 * Set initialized values (get from vbios) to dpm tables context such as 1747 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1748 * type of clks. 1749 */ 1750 ret = smu_set_default_dpm_table(smu); 1751 if (ret) { 1752 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1753 return ret; 1754 } 1755 1756 ret = smu_get_thermal_temperature_range(smu); 1757 if (ret) { 1758 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1759 return ret; 1760 } 1761 1762 ret = smu_enable_thermal_alert(smu); 1763 if (ret) { 1764 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1765 return ret; 1766 } 1767 1768 ret = smu_notify_display_change(smu); 1769 if (ret) { 1770 dev_err(adev->dev, "Failed to notify display change!\n"); 1771 return ret; 1772 } 1773 1774 /* 1775 * Set min deep sleep dce fclk with bootup value from vbios via 1776 * SetMinDeepSleepDcefclk MSG. 1777 */ 1778 ret = smu_set_min_dcef_deep_sleep(smu, 1779 smu->smu_table.boot_values.dcefclk / 100); 1780 if (ret) { 1781 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1782 return ret; 1783 } 1784 1785 /* Init wbrf support. Properly setup the notifier */ 1786 ret = smu_wbrf_init(smu); 1787 if (ret) 1788 dev_err(adev->dev, "Error during wbrf init call\n"); 1789 1790 return ret; 1791 } 1792 1793 static int smu_start_smc_engine(struct smu_context *smu) 1794 { 1795 struct amdgpu_device *adev = smu->adev; 1796 int ret = 0; 1797 1798 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 1799 smu_update_gpu_addresses(smu); 1800 1801 smu->smc_fw_state = SMU_FW_INIT; 1802 1803 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1804 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1805 if (smu->ppt_funcs->load_microcode) { 1806 ret = smu->ppt_funcs->load_microcode(smu); 1807 if (ret) 1808 return ret; 1809 } 1810 } 1811 } 1812 1813 if (smu->ppt_funcs->check_fw_status) { 1814 ret = smu->ppt_funcs->check_fw_status(smu); 1815 if (ret) { 1816 dev_err(adev->dev, "SMC is not ready\n"); 1817 return ret; 1818 } 1819 } 1820 1821 /* 1822 * Send msg GetDriverIfVersion to check if the return value is equal 1823 * with DRIVER_IF_VERSION of smc header. 1824 */ 1825 ret = smu_check_fw_version(smu); 1826 if (ret) 1827 return ret; 1828 1829 return ret; 1830 } 1831 1832 static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1833 { 1834 int i, ret; 1835 struct amdgpu_device *adev = ip_block->adev; 1836 struct smu_context *smu = adev->powerplay.pp_handle; 1837 1838 if (amdgpu_sriov_multi_vf_mode(adev)) { 1839 smu->pm_enabled = false; 1840 return 0; 1841 } 1842 1843 ret = smu_start_smc_engine(smu); 1844 if (ret) { 1845 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1846 return ret; 1847 } 1848 1849 /* 1850 * Check whether wbrf is supported. This needs to be done 1851 * before SMU setup starts since part of SMU configuration 1852 * relies on this. 1853 */ 1854 smu_wbrf_support_check(smu); 1855 1856 if (smu->is_apu) { 1857 ret = smu_set_gfx_imu_enable(smu); 1858 if (ret) 1859 return ret; 1860 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1861 smu_dpm_set_vcn_enable(smu, true, i); 1862 smu_dpm_set_jpeg_enable(smu, true); 1863 smu_dpm_set_vpe_enable(smu, true); 1864 smu_dpm_set_umsch_mm_enable(smu, true); 1865 smu_set_mall_enable(smu); 1866 smu_set_gfx_cgpg(smu, true); 1867 } 1868 1869 if (!smu->pm_enabled) 1870 return 0; 1871 1872 ret = smu_get_driver_allowed_feature_mask(smu); 1873 if (ret) 1874 return ret; 1875 1876 ret = smu_smc_hw_setup(smu); 1877 if (ret) { 1878 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1879 return ret; 1880 } 1881 1882 /* 1883 * Move maximum sustainable clock retrieving here considering 1884 * 1. It is not needed on resume(from S3). 1885 * 2. DAL settings come between .hw_init and .late_init of SMU. 1886 * And DAL needs to know the maximum sustainable clocks. Thus 1887 * it cannot be put in .late_init(). 1888 */ 1889 ret = smu_init_max_sustainable_clocks(smu); 1890 if (ret) { 1891 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1892 return ret; 1893 } 1894 1895 adev->pm.dpm_enabled = true; 1896 1897 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1898 1899 return 0; 1900 } 1901 1902 static int smu_disable_dpms(struct smu_context *smu) 1903 { 1904 struct amdgpu_device *adev = smu->adev; 1905 int ret = 0; 1906 bool use_baco = !smu->is_apu && 1907 ((amdgpu_in_reset(adev) && 1908 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1909 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1910 1911 /* 1912 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1913 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1914 */ 1915 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1916 case IP_VERSION(13, 0, 0): 1917 case IP_VERSION(13, 0, 7): 1918 case IP_VERSION(13, 0, 10): 1919 case IP_VERSION(14, 0, 2): 1920 case IP_VERSION(14, 0, 3): 1921 return 0; 1922 default: 1923 break; 1924 } 1925 1926 /* 1927 * For custom pptable uploading, skip the DPM features 1928 * disable process on Navi1x ASICs. 1929 * - As the gfx related features are under control of 1930 * RLC on those ASICs. RLC reinitialization will be 1931 * needed to reenable them. That will cost much more 1932 * efforts. 1933 * 1934 * - SMU firmware can handle the DPM reenablement 1935 * properly. 1936 */ 1937 if (smu->uploading_custom_pp_table) { 1938 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1939 case IP_VERSION(11, 0, 0): 1940 case IP_VERSION(11, 0, 5): 1941 case IP_VERSION(11, 0, 9): 1942 case IP_VERSION(11, 0, 7): 1943 case IP_VERSION(11, 0, 11): 1944 case IP_VERSION(11, 5, 0): 1945 case IP_VERSION(11, 5, 2): 1946 case IP_VERSION(11, 0, 12): 1947 case IP_VERSION(11, 0, 13): 1948 return 0; 1949 default: 1950 break; 1951 } 1952 } 1953 1954 /* 1955 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1956 * on BACO in. Driver involvement is unnecessary. 1957 */ 1958 if (use_baco) { 1959 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1960 case IP_VERSION(11, 0, 7): 1961 case IP_VERSION(11, 0, 0): 1962 case IP_VERSION(11, 0, 5): 1963 case IP_VERSION(11, 0, 9): 1964 case IP_VERSION(13, 0, 7): 1965 return 0; 1966 default: 1967 break; 1968 } 1969 } 1970 1971 /* 1972 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 1973 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1974 */ 1975 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 1976 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 1977 return 0; 1978 1979 /* 1980 * For gpu reset, runpm and hibernation through BACO, 1981 * BACO feature has to be kept enabled. 1982 */ 1983 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1984 ret = smu_disable_all_features_with_exception(smu, 1985 SMU_FEATURE_BACO_BIT); 1986 if (ret) 1987 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1988 } else { 1989 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1990 if (!adev->scpm_enabled) { 1991 ret = smu_system_features_control(smu, false); 1992 if (ret) 1993 dev_err(adev->dev, "Failed to disable smu features.\n"); 1994 } 1995 } 1996 1997 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1998 * otherwise SMU will hang while interacting with RLC if RLC is halted 1999 * this is a WA for Vangogh asic which fix the SMU hang issue. 2000 */ 2001 ret = smu_notify_rlc_state(smu, false); 2002 if (ret) { 2003 dev_err(adev->dev, "Fail to notify rlc status!\n"); 2004 return ret; 2005 } 2006 2007 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 2008 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 2009 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 2010 adev->gfx.rlc.funcs->stop(adev); 2011 2012 return ret; 2013 } 2014 2015 static int smu_smc_hw_cleanup(struct smu_context *smu) 2016 { 2017 struct amdgpu_device *adev = smu->adev; 2018 int ret = 0; 2019 2020 smu_wbrf_fini(smu); 2021 2022 cancel_work_sync(&smu->throttling_logging_work); 2023 cancel_work_sync(&smu->interrupt_work); 2024 2025 ret = smu_disable_thermal_alert(smu); 2026 if (ret) { 2027 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 2028 return ret; 2029 } 2030 2031 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2032 2033 ret = smu_disable_dpms(smu); 2034 if (ret) { 2035 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2036 return ret; 2037 } 2038 2039 return 0; 2040 } 2041 2042 static int smu_reset_mp1_state(struct smu_context *smu) 2043 { 2044 struct amdgpu_device *adev = smu->adev; 2045 int ret = 0; 2046 2047 if ((!adev->in_runpm) && (!adev->in_suspend) && 2048 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 2049 IP_VERSION(13, 0, 10) && 2050 !amdgpu_device_has_display_hardware(adev)) 2051 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2052 2053 return ret; 2054 } 2055 2056 static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2057 { 2058 struct amdgpu_device *adev = ip_block->adev; 2059 struct smu_context *smu = adev->powerplay.pp_handle; 2060 int i, ret; 2061 2062 if (amdgpu_sriov_multi_vf_mode(adev)) 2063 return 0; 2064 2065 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2066 smu_dpm_set_vcn_enable(smu, false, i); 2067 adev->vcn.inst[i].cur_state = AMD_PG_STATE_GATE; 2068 } 2069 smu_dpm_set_jpeg_enable(smu, false); 2070 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2071 smu_dpm_set_vpe_enable(smu, false); 2072 smu_dpm_set_umsch_mm_enable(smu, false); 2073 2074 if (!smu->pm_enabled) 2075 return 0; 2076 2077 adev->pm.dpm_enabled = false; 2078 2079 ret = smu_smc_hw_cleanup(smu); 2080 if (ret) 2081 return ret; 2082 2083 ret = smu_reset_mp1_state(smu); 2084 if (ret) 2085 return ret; 2086 2087 return 0; 2088 } 2089 2090 static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2091 { 2092 struct amdgpu_device *adev = ip_block->adev; 2093 struct smu_context *smu = adev->powerplay.pp_handle; 2094 2095 kfree(smu); 2096 } 2097 2098 static int smu_reset(struct smu_context *smu) 2099 { 2100 struct amdgpu_device *adev = smu->adev; 2101 struct amdgpu_ip_block *ip_block; 2102 int ret; 2103 2104 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2105 if (!ip_block) 2106 return -EINVAL; 2107 2108 ret = smu_hw_fini(ip_block); 2109 if (ret) 2110 return ret; 2111 2112 ret = smu_hw_init(ip_block); 2113 if (ret) 2114 return ret; 2115 2116 ret = smu_late_init(ip_block); 2117 if (ret) 2118 return ret; 2119 2120 return 0; 2121 } 2122 2123 static int smu_suspend(struct amdgpu_ip_block *ip_block) 2124 { 2125 struct amdgpu_device *adev = ip_block->adev; 2126 struct smu_context *smu = adev->powerplay.pp_handle; 2127 int ret; 2128 uint64_t count; 2129 2130 if (amdgpu_sriov_multi_vf_mode(adev)) 2131 return 0; 2132 2133 if (!smu->pm_enabled) 2134 return 0; 2135 2136 adev->pm.dpm_enabled = false; 2137 2138 ret = smu_smc_hw_cleanup(smu); 2139 if (ret) 2140 return ret; 2141 2142 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2143 2144 smu_set_gfx_cgpg(smu, false); 2145 2146 /* 2147 * pwfw resets entrycount when device is suspended, so we save the 2148 * last value to be used when we resume to keep it consistent 2149 */ 2150 ret = smu_get_entrycount_gfxoff(smu, &count); 2151 if (!ret) 2152 adev->gfx.gfx_off_entrycount = count; 2153 2154 /* clear this on suspend so it will get reprogrammed on resume */ 2155 smu->workload_mask = 0; 2156 2157 return 0; 2158 } 2159 2160 static int smu_resume(struct amdgpu_ip_block *ip_block) 2161 { 2162 int ret; 2163 struct amdgpu_device *adev = ip_block->adev; 2164 struct smu_context *smu = adev->powerplay.pp_handle; 2165 2166 if (amdgpu_sriov_multi_vf_mode(adev)) 2167 return 0; 2168 2169 if (!smu->pm_enabled) 2170 return 0; 2171 2172 dev_info(adev->dev, "SMU is resuming...\n"); 2173 2174 ret = smu_start_smc_engine(smu); 2175 if (ret) { 2176 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2177 return ret; 2178 } 2179 2180 ret = smu_smc_hw_setup(smu); 2181 if (ret) { 2182 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2183 return ret; 2184 } 2185 2186 ret = smu_set_gfx_imu_enable(smu); 2187 if (ret) 2188 return ret; 2189 2190 smu_set_gfx_cgpg(smu, true); 2191 2192 smu->disable_uclk_switch = 0; 2193 2194 adev->pm.dpm_enabled = true; 2195 2196 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2197 2198 return 0; 2199 } 2200 2201 static int smu_display_configuration_change(void *handle, 2202 const struct amd_pp_display_configuration *display_config) 2203 { 2204 struct smu_context *smu = handle; 2205 2206 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2207 return -EOPNOTSUPP; 2208 2209 if (!display_config) 2210 return -EINVAL; 2211 2212 smu_set_min_dcef_deep_sleep(smu, 2213 display_config->min_dcef_deep_sleep_set_clk / 100); 2214 2215 return 0; 2216 } 2217 2218 static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2219 enum amd_clockgating_state state) 2220 { 2221 return 0; 2222 } 2223 2224 static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block, 2225 enum amd_powergating_state state) 2226 { 2227 return 0; 2228 } 2229 2230 static int smu_enable_umd_pstate(void *handle, 2231 enum amd_dpm_forced_level *level) 2232 { 2233 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2234 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2235 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2236 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2237 2238 struct smu_context *smu = (struct smu_context*)(handle); 2239 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2240 2241 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2242 return -EINVAL; 2243 2244 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2245 /* enter umd pstate, save current level, disable gfx cg*/ 2246 if (*level & profile_mode_mask) { 2247 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2248 smu_gpo_control(smu, false); 2249 smu_gfx_ulv_control(smu, false); 2250 smu_deep_sleep_control(smu, false); 2251 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2252 } 2253 } else { 2254 /* exit umd pstate, restore level, enable gfx cg*/ 2255 if (!(*level & profile_mode_mask)) { 2256 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2257 *level = smu_dpm_ctx->saved_dpm_level; 2258 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2259 smu_deep_sleep_control(smu, true); 2260 smu_gfx_ulv_control(smu, true); 2261 smu_gpo_control(smu, true); 2262 } 2263 } 2264 2265 return 0; 2266 } 2267 2268 static int smu_bump_power_profile_mode(struct smu_context *smu, 2269 long *custom_params, 2270 u32 custom_params_max_idx) 2271 { 2272 u32 workload_mask = 0; 2273 int i, ret = 0; 2274 2275 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2276 if (smu->workload_refcount[i]) 2277 workload_mask |= 1 << i; 2278 } 2279 2280 if (smu->workload_mask == workload_mask) 2281 return 0; 2282 2283 if (smu->ppt_funcs->set_power_profile_mode) 2284 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask, 2285 custom_params, 2286 custom_params_max_idx); 2287 2288 if (!ret) 2289 smu->workload_mask = workload_mask; 2290 2291 return ret; 2292 } 2293 2294 static void smu_power_profile_mode_get(struct smu_context *smu, 2295 enum PP_SMC_POWER_PROFILE profile_mode) 2296 { 2297 smu->workload_refcount[profile_mode]++; 2298 } 2299 2300 static void smu_power_profile_mode_put(struct smu_context *smu, 2301 enum PP_SMC_POWER_PROFILE profile_mode) 2302 { 2303 if (smu->workload_refcount[profile_mode]) 2304 smu->workload_refcount[profile_mode]--; 2305 } 2306 2307 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2308 enum amd_dpm_forced_level level, 2309 bool skip_display_settings) 2310 { 2311 int ret = 0; 2312 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2313 2314 if (!skip_display_settings) { 2315 ret = smu_display_config_changed(smu); 2316 if (ret) { 2317 dev_err(smu->adev->dev, "Failed to change display config!"); 2318 return ret; 2319 } 2320 } 2321 2322 ret = smu_apply_clocks_adjust_rules(smu); 2323 if (ret) { 2324 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2325 return ret; 2326 } 2327 2328 if (!skip_display_settings) { 2329 ret = smu_notify_smc_display_config(smu); 2330 if (ret) { 2331 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2332 return ret; 2333 } 2334 } 2335 2336 if (smu_dpm_ctx->dpm_level != level) { 2337 ret = smu_asic_set_performance_level(smu, level); 2338 if (ret) { 2339 if (ret == -EOPNOTSUPP) 2340 dev_info(smu->adev->dev, "set performance level %d not supported", 2341 level); 2342 else 2343 dev_err(smu->adev->dev, "Failed to set performance level %d", 2344 level); 2345 return ret; 2346 } 2347 2348 /* update the saved copy */ 2349 smu_dpm_ctx->dpm_level = level; 2350 } 2351 2352 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2353 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2354 smu_bump_power_profile_mode(smu, NULL, 0); 2355 2356 return ret; 2357 } 2358 2359 static int smu_handle_task(struct smu_context *smu, 2360 enum amd_dpm_forced_level level, 2361 enum amd_pp_task task_id) 2362 { 2363 int ret = 0; 2364 2365 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2366 return -EOPNOTSUPP; 2367 2368 switch (task_id) { 2369 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2370 ret = smu_pre_display_config_changed(smu); 2371 if (ret) 2372 return ret; 2373 ret = smu_adjust_power_state_dynamic(smu, level, false); 2374 break; 2375 case AMD_PP_TASK_COMPLETE_INIT: 2376 ret = smu_adjust_power_state_dynamic(smu, level, true); 2377 break; 2378 case AMD_PP_TASK_READJUST_POWER_STATE: 2379 ret = smu_adjust_power_state_dynamic(smu, level, true); 2380 break; 2381 default: 2382 break; 2383 } 2384 2385 return ret; 2386 } 2387 2388 static int smu_handle_dpm_task(void *handle, 2389 enum amd_pp_task task_id, 2390 enum amd_pm_state_type *user_state) 2391 { 2392 struct smu_context *smu = handle; 2393 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2394 2395 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2396 2397 } 2398 2399 static int smu_switch_power_profile(void *handle, 2400 enum PP_SMC_POWER_PROFILE type, 2401 bool enable) 2402 { 2403 struct smu_context *smu = handle; 2404 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2405 int ret; 2406 2407 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2408 return -EOPNOTSUPP; 2409 2410 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2411 return -EINVAL; 2412 2413 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2414 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2415 if (enable) 2416 smu_power_profile_mode_get(smu, type); 2417 else 2418 smu_power_profile_mode_put(smu, type); 2419 /* don't switch the active workload when paused */ 2420 if (smu->pause_workload) 2421 ret = 0; 2422 else 2423 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2424 if (ret) { 2425 if (enable) 2426 smu_power_profile_mode_put(smu, type); 2427 else 2428 smu_power_profile_mode_get(smu, type); 2429 return ret; 2430 } 2431 } 2432 2433 return 0; 2434 } 2435 2436 static int smu_pause_power_profile(void *handle, 2437 bool pause) 2438 { 2439 struct smu_context *smu = handle; 2440 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2441 u32 workload_mask = 1 << PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 2442 int ret; 2443 2444 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2445 return -EOPNOTSUPP; 2446 2447 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2448 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2449 smu->pause_workload = pause; 2450 2451 /* force to bootup default profile */ 2452 if (smu->pause_workload && smu->ppt_funcs->set_power_profile_mode) 2453 ret = smu->ppt_funcs->set_power_profile_mode(smu, 2454 workload_mask, 2455 NULL, 2456 0); 2457 else 2458 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2459 return ret; 2460 } 2461 2462 return 0; 2463 } 2464 2465 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2466 { 2467 struct smu_context *smu = handle; 2468 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2469 2470 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2471 return -EOPNOTSUPP; 2472 2473 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2474 return -EINVAL; 2475 2476 return smu_dpm_ctx->dpm_level; 2477 } 2478 2479 static int smu_force_performance_level(void *handle, 2480 enum amd_dpm_forced_level level) 2481 { 2482 struct smu_context *smu = handle; 2483 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2484 int ret = 0; 2485 2486 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2487 return -EOPNOTSUPP; 2488 2489 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2490 return -EINVAL; 2491 2492 ret = smu_enable_umd_pstate(smu, &level); 2493 if (ret) 2494 return ret; 2495 2496 ret = smu_handle_task(smu, level, 2497 AMD_PP_TASK_READJUST_POWER_STATE); 2498 2499 /* reset user dpm clock state */ 2500 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2501 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2502 smu->user_dpm_profile.clk_dependency = 0; 2503 } 2504 2505 return ret; 2506 } 2507 2508 static int smu_set_display_count(void *handle, uint32_t count) 2509 { 2510 struct smu_context *smu = handle; 2511 2512 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2513 return -EOPNOTSUPP; 2514 2515 return smu_init_display_count(smu, count); 2516 } 2517 2518 static int smu_force_smuclk_levels(struct smu_context *smu, 2519 enum smu_clk_type clk_type, 2520 uint32_t mask) 2521 { 2522 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2523 int ret = 0; 2524 2525 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2526 return -EOPNOTSUPP; 2527 2528 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2529 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2530 return -EINVAL; 2531 } 2532 2533 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2534 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2535 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2536 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2537 smu_set_user_clk_dependencies(smu, clk_type); 2538 } 2539 } 2540 2541 return ret; 2542 } 2543 2544 static int smu_force_ppclk_levels(void *handle, 2545 enum pp_clock_type type, 2546 uint32_t mask) 2547 { 2548 struct smu_context *smu = handle; 2549 enum smu_clk_type clk_type; 2550 2551 switch (type) { 2552 case PP_SCLK: 2553 clk_type = SMU_SCLK; break; 2554 case PP_MCLK: 2555 clk_type = SMU_MCLK; break; 2556 case PP_PCIE: 2557 clk_type = SMU_PCIE; break; 2558 case PP_SOCCLK: 2559 clk_type = SMU_SOCCLK; break; 2560 case PP_FCLK: 2561 clk_type = SMU_FCLK; break; 2562 case PP_DCEFCLK: 2563 clk_type = SMU_DCEFCLK; break; 2564 case PP_VCLK: 2565 clk_type = SMU_VCLK; break; 2566 case PP_VCLK1: 2567 clk_type = SMU_VCLK1; break; 2568 case PP_DCLK: 2569 clk_type = SMU_DCLK; break; 2570 case PP_DCLK1: 2571 clk_type = SMU_DCLK1; break; 2572 case OD_SCLK: 2573 clk_type = SMU_OD_SCLK; break; 2574 case OD_MCLK: 2575 clk_type = SMU_OD_MCLK; break; 2576 case OD_VDDC_CURVE: 2577 clk_type = SMU_OD_VDDC_CURVE; break; 2578 case OD_RANGE: 2579 clk_type = SMU_OD_RANGE; break; 2580 default: 2581 return -EINVAL; 2582 } 2583 2584 return smu_force_smuclk_levels(smu, clk_type, mask); 2585 } 2586 2587 /* 2588 * On system suspending or resetting, the dpm_enabled 2589 * flag will be cleared. So that those SMU services which 2590 * are not supported will be gated. 2591 * However, the mp1 state setting should still be granted 2592 * even if the dpm_enabled cleared. 2593 */ 2594 static int smu_set_mp1_state(void *handle, 2595 enum pp_mp1_state mp1_state) 2596 { 2597 struct smu_context *smu = handle; 2598 int ret = 0; 2599 2600 if (!smu->pm_enabled) 2601 return -EOPNOTSUPP; 2602 2603 if (smu->ppt_funcs && 2604 smu->ppt_funcs->set_mp1_state) 2605 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2606 2607 return ret; 2608 } 2609 2610 static int smu_set_df_cstate(void *handle, 2611 enum pp_df_cstate state) 2612 { 2613 struct smu_context *smu = handle; 2614 int ret = 0; 2615 2616 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2617 return -EOPNOTSUPP; 2618 2619 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2620 return 0; 2621 2622 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2623 if (ret) 2624 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2625 2626 return ret; 2627 } 2628 2629 int smu_write_watermarks_table(struct smu_context *smu) 2630 { 2631 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2632 return -EOPNOTSUPP; 2633 2634 return smu_set_watermarks_table(smu, NULL); 2635 } 2636 2637 static int smu_set_watermarks_for_clock_ranges(void *handle, 2638 struct pp_smu_wm_range_sets *clock_ranges) 2639 { 2640 struct smu_context *smu = handle; 2641 2642 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2643 return -EOPNOTSUPP; 2644 2645 if (smu->disable_watermark) 2646 return 0; 2647 2648 return smu_set_watermarks_table(smu, clock_ranges); 2649 } 2650 2651 int smu_set_ac_dc(struct smu_context *smu) 2652 { 2653 int ret = 0; 2654 2655 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2656 return -EOPNOTSUPP; 2657 2658 /* controlled by firmware */ 2659 if (smu->dc_controlled_by_gpio) 2660 return 0; 2661 2662 ret = smu_set_power_source(smu, 2663 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2664 SMU_POWER_SOURCE_DC); 2665 if (ret) 2666 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2667 smu->adev->pm.ac_power ? "AC" : "DC"); 2668 2669 return ret; 2670 } 2671 2672 const struct amd_ip_funcs smu_ip_funcs = { 2673 .name = "smu", 2674 .early_init = smu_early_init, 2675 .late_init = smu_late_init, 2676 .sw_init = smu_sw_init, 2677 .sw_fini = smu_sw_fini, 2678 .hw_init = smu_hw_init, 2679 .hw_fini = smu_hw_fini, 2680 .late_fini = smu_late_fini, 2681 .suspend = smu_suspend, 2682 .resume = smu_resume, 2683 .is_idle = NULL, 2684 .check_soft_reset = NULL, 2685 .wait_for_idle = NULL, 2686 .soft_reset = NULL, 2687 .set_clockgating_state = smu_set_clockgating_state, 2688 .set_powergating_state = smu_set_powergating_state, 2689 }; 2690 2691 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2692 .type = AMD_IP_BLOCK_TYPE_SMC, 2693 .major = 11, 2694 .minor = 0, 2695 .rev = 0, 2696 .funcs = &smu_ip_funcs, 2697 }; 2698 2699 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2700 .type = AMD_IP_BLOCK_TYPE_SMC, 2701 .major = 12, 2702 .minor = 0, 2703 .rev = 0, 2704 .funcs = &smu_ip_funcs, 2705 }; 2706 2707 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2708 .type = AMD_IP_BLOCK_TYPE_SMC, 2709 .major = 13, 2710 .minor = 0, 2711 .rev = 0, 2712 .funcs = &smu_ip_funcs, 2713 }; 2714 2715 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2716 .type = AMD_IP_BLOCK_TYPE_SMC, 2717 .major = 14, 2718 .minor = 0, 2719 .rev = 0, 2720 .funcs = &smu_ip_funcs, 2721 }; 2722 2723 static int smu_load_microcode(void *handle) 2724 { 2725 struct smu_context *smu = handle; 2726 struct amdgpu_device *adev = smu->adev; 2727 int ret = 0; 2728 2729 if (!smu->pm_enabled) 2730 return -EOPNOTSUPP; 2731 2732 /* This should be used for non PSP loading */ 2733 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2734 return 0; 2735 2736 if (smu->ppt_funcs->load_microcode) { 2737 ret = smu->ppt_funcs->load_microcode(smu); 2738 if (ret) { 2739 dev_err(adev->dev, "Load microcode failed\n"); 2740 return ret; 2741 } 2742 } 2743 2744 if (smu->ppt_funcs->check_fw_status) { 2745 ret = smu->ppt_funcs->check_fw_status(smu); 2746 if (ret) { 2747 dev_err(adev->dev, "SMC is not ready\n"); 2748 return ret; 2749 } 2750 } 2751 2752 return ret; 2753 } 2754 2755 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2756 { 2757 int ret = 0; 2758 2759 if (smu->ppt_funcs->set_gfx_cgpg) 2760 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2761 2762 return ret; 2763 } 2764 2765 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2766 { 2767 struct smu_context *smu = handle; 2768 int ret = 0; 2769 2770 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2771 return -EOPNOTSUPP; 2772 2773 if (!smu->ppt_funcs->set_fan_speed_rpm) 2774 return -EOPNOTSUPP; 2775 2776 if (speed == U32_MAX) 2777 return -EINVAL; 2778 2779 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2780 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2781 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2782 smu->user_dpm_profile.fan_speed_rpm = speed; 2783 2784 /* Override custom PWM setting as they cannot co-exist */ 2785 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2786 smu->user_dpm_profile.fan_speed_pwm = 0; 2787 } 2788 2789 return ret; 2790 } 2791 2792 /** 2793 * smu_get_power_limit - Request one of the SMU Power Limits 2794 * 2795 * @handle: pointer to smu context 2796 * @limit: requested limit is written back to this variable 2797 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2798 * @pp_power_type: &pp_power_type type of power 2799 * Return: 0 on success, <0 on error 2800 * 2801 */ 2802 int smu_get_power_limit(void *handle, 2803 uint32_t *limit, 2804 enum pp_power_limit_level pp_limit_level, 2805 enum pp_power_type pp_power_type) 2806 { 2807 struct smu_context *smu = handle; 2808 struct amdgpu_device *adev = smu->adev; 2809 enum smu_ppt_limit_level limit_level; 2810 uint32_t limit_type; 2811 int ret = 0; 2812 2813 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2814 return -EOPNOTSUPP; 2815 2816 switch (pp_power_type) { 2817 case PP_PWR_TYPE_SUSTAINED: 2818 limit_type = SMU_DEFAULT_PPT_LIMIT; 2819 break; 2820 case PP_PWR_TYPE_FAST: 2821 limit_type = SMU_FAST_PPT_LIMIT; 2822 break; 2823 default: 2824 return -EOPNOTSUPP; 2825 } 2826 2827 switch (pp_limit_level) { 2828 case PP_PWR_LIMIT_CURRENT: 2829 limit_level = SMU_PPT_LIMIT_CURRENT; 2830 break; 2831 case PP_PWR_LIMIT_DEFAULT: 2832 limit_level = SMU_PPT_LIMIT_DEFAULT; 2833 break; 2834 case PP_PWR_LIMIT_MAX: 2835 limit_level = SMU_PPT_LIMIT_MAX; 2836 break; 2837 case PP_PWR_LIMIT_MIN: 2838 limit_level = SMU_PPT_LIMIT_MIN; 2839 break; 2840 default: 2841 return -EOPNOTSUPP; 2842 } 2843 2844 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2845 if (smu->ppt_funcs->get_ppt_limit) 2846 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2847 } else { 2848 switch (limit_level) { 2849 case SMU_PPT_LIMIT_CURRENT: 2850 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2851 case IP_VERSION(13, 0, 2): 2852 case IP_VERSION(13, 0, 6): 2853 case IP_VERSION(13, 0, 12): 2854 case IP_VERSION(13, 0, 14): 2855 case IP_VERSION(11, 0, 7): 2856 case IP_VERSION(11, 0, 11): 2857 case IP_VERSION(11, 0, 12): 2858 case IP_VERSION(11, 0, 13): 2859 ret = smu_get_asic_power_limits(smu, 2860 &smu->current_power_limit, 2861 NULL, NULL, NULL); 2862 break; 2863 default: 2864 break; 2865 } 2866 *limit = smu->current_power_limit; 2867 break; 2868 case SMU_PPT_LIMIT_DEFAULT: 2869 *limit = smu->default_power_limit; 2870 break; 2871 case SMU_PPT_LIMIT_MAX: 2872 *limit = smu->max_power_limit; 2873 break; 2874 case SMU_PPT_LIMIT_MIN: 2875 *limit = smu->min_power_limit; 2876 break; 2877 default: 2878 return -EINVAL; 2879 } 2880 } 2881 2882 return ret; 2883 } 2884 2885 static int smu_set_power_limit(void *handle, uint32_t limit) 2886 { 2887 struct smu_context *smu = handle; 2888 uint32_t limit_type = limit >> 24; 2889 int ret = 0; 2890 2891 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2892 return -EOPNOTSUPP; 2893 2894 limit &= (1<<24)-1; 2895 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2896 if (smu->ppt_funcs->set_power_limit) 2897 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2898 2899 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2900 dev_err(smu->adev->dev, 2901 "New power limit (%d) is out of range [%d,%d]\n", 2902 limit, smu->min_power_limit, smu->max_power_limit); 2903 return -EINVAL; 2904 } 2905 2906 if (!limit) 2907 limit = smu->current_power_limit; 2908 2909 if (smu->ppt_funcs->set_power_limit) { 2910 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2911 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2912 smu->user_dpm_profile.power_limit = limit; 2913 } 2914 2915 return ret; 2916 } 2917 2918 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2919 { 2920 int ret = 0; 2921 2922 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2923 return -EOPNOTSUPP; 2924 2925 if (smu->ppt_funcs->print_clk_levels) 2926 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2927 2928 return ret; 2929 } 2930 2931 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2932 { 2933 enum smu_clk_type clk_type; 2934 2935 switch (type) { 2936 case PP_SCLK: 2937 clk_type = SMU_SCLK; break; 2938 case PP_MCLK: 2939 clk_type = SMU_MCLK; break; 2940 case PP_PCIE: 2941 clk_type = SMU_PCIE; break; 2942 case PP_SOCCLK: 2943 clk_type = SMU_SOCCLK; break; 2944 case PP_FCLK: 2945 clk_type = SMU_FCLK; break; 2946 case PP_DCEFCLK: 2947 clk_type = SMU_DCEFCLK; break; 2948 case PP_VCLK: 2949 clk_type = SMU_VCLK; break; 2950 case PP_VCLK1: 2951 clk_type = SMU_VCLK1; break; 2952 case PP_DCLK: 2953 clk_type = SMU_DCLK; break; 2954 case PP_DCLK1: 2955 clk_type = SMU_DCLK1; break; 2956 case OD_SCLK: 2957 clk_type = SMU_OD_SCLK; break; 2958 case OD_MCLK: 2959 clk_type = SMU_OD_MCLK; break; 2960 case OD_VDDC_CURVE: 2961 clk_type = SMU_OD_VDDC_CURVE; break; 2962 case OD_RANGE: 2963 clk_type = SMU_OD_RANGE; break; 2964 case OD_VDDGFX_OFFSET: 2965 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2966 case OD_CCLK: 2967 clk_type = SMU_OD_CCLK; break; 2968 case OD_FAN_CURVE: 2969 clk_type = SMU_OD_FAN_CURVE; break; 2970 case OD_ACOUSTIC_LIMIT: 2971 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2972 case OD_ACOUSTIC_TARGET: 2973 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2974 case OD_FAN_TARGET_TEMPERATURE: 2975 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2976 case OD_FAN_MINIMUM_PWM: 2977 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2978 case OD_FAN_ZERO_RPM_ENABLE: 2979 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 2980 case OD_FAN_ZERO_RPM_STOP_TEMP: 2981 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 2982 default: 2983 clk_type = SMU_CLK_COUNT; break; 2984 } 2985 2986 return clk_type; 2987 } 2988 2989 static int smu_print_ppclk_levels(void *handle, 2990 enum pp_clock_type type, 2991 char *buf) 2992 { 2993 struct smu_context *smu = handle; 2994 enum smu_clk_type clk_type; 2995 2996 clk_type = smu_convert_to_smuclk(type); 2997 if (clk_type == SMU_CLK_COUNT) 2998 return -EINVAL; 2999 3000 return smu_print_smuclk_levels(smu, clk_type, buf); 3001 } 3002 3003 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 3004 { 3005 struct smu_context *smu = handle; 3006 enum smu_clk_type clk_type; 3007 3008 clk_type = smu_convert_to_smuclk(type); 3009 if (clk_type == SMU_CLK_COUNT) 3010 return -EINVAL; 3011 3012 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3013 return -EOPNOTSUPP; 3014 3015 if (!smu->ppt_funcs->emit_clk_levels) 3016 return -ENOENT; 3017 3018 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 3019 3020 } 3021 3022 static int smu_od_edit_dpm_table(void *handle, 3023 enum PP_OD_DPM_TABLE_COMMAND type, 3024 long *input, uint32_t size) 3025 { 3026 struct smu_context *smu = handle; 3027 int ret = 0; 3028 3029 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3030 return -EOPNOTSUPP; 3031 3032 if (smu->ppt_funcs->od_edit_dpm_table) { 3033 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 3034 } 3035 3036 return ret; 3037 } 3038 3039 static int smu_read_sensor(void *handle, 3040 int sensor, 3041 void *data, 3042 int *size_arg) 3043 { 3044 struct smu_context *smu = handle; 3045 struct amdgpu_device *adev = smu->adev; 3046 struct smu_umd_pstate_table *pstate_table = 3047 &smu->pstate_table; 3048 int i, ret = 0; 3049 uint32_t *size, size_val; 3050 3051 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3052 return -EOPNOTSUPP; 3053 3054 if (!data || !size_arg) 3055 return -EINVAL; 3056 3057 size_val = *size_arg; 3058 size = &size_val; 3059 3060 if (smu->ppt_funcs->read_sensor) 3061 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 3062 goto unlock; 3063 3064 switch (sensor) { 3065 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 3066 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 3067 *size = 4; 3068 break; 3069 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 3070 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 3071 *size = 4; 3072 break; 3073 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 3074 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 3075 *size = 4; 3076 break; 3077 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 3078 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3079 *size = 4; 3080 break; 3081 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 3082 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 3083 *size = 8; 3084 break; 3085 case AMDGPU_PP_SENSOR_UVD_POWER: 3086 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3087 *size = 4; 3088 break; 3089 case AMDGPU_PP_SENSOR_VCE_POWER: 3090 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 3091 *size = 4; 3092 break; 3093 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3094 *(uint32_t *)data = 0; 3095 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 3096 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) { 3097 *(uint32_t *)data = 1; 3098 break; 3099 } 3100 } 3101 *size = 4; 3102 break; 3103 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3104 *(uint32_t *)data = 0; 3105 *size = 4; 3106 break; 3107 default: 3108 *size = 0; 3109 ret = -EOPNOTSUPP; 3110 break; 3111 } 3112 3113 unlock: 3114 // assign uint32_t to int 3115 *size_arg = size_val; 3116 3117 return ret; 3118 } 3119 3120 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3121 { 3122 int ret = -EOPNOTSUPP; 3123 struct smu_context *smu = handle; 3124 3125 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3126 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3127 3128 return ret; 3129 } 3130 3131 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3132 { 3133 int ret = -EOPNOTSUPP; 3134 struct smu_context *smu = handle; 3135 3136 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3137 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3138 3139 return ret; 3140 } 3141 3142 static int smu_get_power_profile_mode(void *handle, char *buf) 3143 { 3144 struct smu_context *smu = handle; 3145 3146 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3147 !smu->ppt_funcs->get_power_profile_mode) 3148 return -EOPNOTSUPP; 3149 if (!buf) 3150 return -EINVAL; 3151 3152 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3153 } 3154 3155 static int smu_set_power_profile_mode(void *handle, 3156 long *param, 3157 uint32_t param_size) 3158 { 3159 struct smu_context *smu = handle; 3160 bool custom = false; 3161 int ret = 0; 3162 3163 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3164 !smu->ppt_funcs->set_power_profile_mode) 3165 return -EOPNOTSUPP; 3166 3167 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) { 3168 custom = true; 3169 /* clear frontend mask so custom changes propogate */ 3170 smu->workload_mask = 0; 3171 } 3172 3173 if ((param[param_size] != smu->power_profile_mode) || custom) { 3174 /* clear the old user preference */ 3175 smu_power_profile_mode_put(smu, smu->power_profile_mode); 3176 /* set the new user preference */ 3177 smu_power_profile_mode_get(smu, param[param_size]); 3178 ret = smu_bump_power_profile_mode(smu, 3179 custom ? param : NULL, 3180 custom ? param_size : 0); 3181 if (ret) 3182 smu_power_profile_mode_put(smu, param[param_size]); 3183 else 3184 /* store the user's preference */ 3185 smu->power_profile_mode = param[param_size]; 3186 } 3187 3188 return ret; 3189 } 3190 3191 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3192 { 3193 struct smu_context *smu = handle; 3194 3195 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3196 return -EOPNOTSUPP; 3197 3198 if (!smu->ppt_funcs->get_fan_control_mode) 3199 return -EOPNOTSUPP; 3200 3201 if (!fan_mode) 3202 return -EINVAL; 3203 3204 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3205 3206 return 0; 3207 } 3208 3209 static int smu_set_fan_control_mode(void *handle, u32 value) 3210 { 3211 struct smu_context *smu = handle; 3212 int ret = 0; 3213 3214 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3215 return -EOPNOTSUPP; 3216 3217 if (!smu->ppt_funcs->set_fan_control_mode) 3218 return -EOPNOTSUPP; 3219 3220 if (value == U32_MAX) 3221 return -EINVAL; 3222 3223 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3224 if (ret) 3225 goto out; 3226 3227 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3228 smu->user_dpm_profile.fan_mode = value; 3229 3230 /* reset user dpm fan speed */ 3231 if (value != AMD_FAN_CTRL_MANUAL) { 3232 smu->user_dpm_profile.fan_speed_pwm = 0; 3233 smu->user_dpm_profile.fan_speed_rpm = 0; 3234 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3235 } 3236 } 3237 3238 out: 3239 return ret; 3240 } 3241 3242 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3243 { 3244 struct smu_context *smu = handle; 3245 int ret = 0; 3246 3247 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3248 return -EOPNOTSUPP; 3249 3250 if (!smu->ppt_funcs->get_fan_speed_pwm) 3251 return -EOPNOTSUPP; 3252 3253 if (!speed) 3254 return -EINVAL; 3255 3256 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3257 3258 return ret; 3259 } 3260 3261 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3262 { 3263 struct smu_context *smu = handle; 3264 int ret = 0; 3265 3266 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3267 return -EOPNOTSUPP; 3268 3269 if (!smu->ppt_funcs->set_fan_speed_pwm) 3270 return -EOPNOTSUPP; 3271 3272 if (speed == U32_MAX) 3273 return -EINVAL; 3274 3275 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3276 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3277 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3278 smu->user_dpm_profile.fan_speed_pwm = speed; 3279 3280 /* Override custom RPM setting as they cannot co-exist */ 3281 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3282 smu->user_dpm_profile.fan_speed_rpm = 0; 3283 } 3284 3285 return ret; 3286 } 3287 3288 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3289 { 3290 struct smu_context *smu = handle; 3291 int ret = 0; 3292 3293 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3294 return -EOPNOTSUPP; 3295 3296 if (!smu->ppt_funcs->get_fan_speed_rpm) 3297 return -EOPNOTSUPP; 3298 3299 if (!speed) 3300 return -EINVAL; 3301 3302 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3303 3304 return ret; 3305 } 3306 3307 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3308 { 3309 struct smu_context *smu = handle; 3310 3311 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3312 return -EOPNOTSUPP; 3313 3314 return smu_set_min_dcef_deep_sleep(smu, clk); 3315 } 3316 3317 static int smu_get_clock_by_type_with_latency(void *handle, 3318 enum amd_pp_clock_type type, 3319 struct pp_clock_levels_with_latency *clocks) 3320 { 3321 struct smu_context *smu = handle; 3322 enum smu_clk_type clk_type; 3323 int ret = 0; 3324 3325 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3326 return -EOPNOTSUPP; 3327 3328 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3329 switch (type) { 3330 case amd_pp_sys_clock: 3331 clk_type = SMU_GFXCLK; 3332 break; 3333 case amd_pp_mem_clock: 3334 clk_type = SMU_MCLK; 3335 break; 3336 case amd_pp_dcef_clock: 3337 clk_type = SMU_DCEFCLK; 3338 break; 3339 case amd_pp_disp_clock: 3340 clk_type = SMU_DISPCLK; 3341 break; 3342 default: 3343 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3344 return -EINVAL; 3345 } 3346 3347 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3348 } 3349 3350 return ret; 3351 } 3352 3353 static int smu_display_clock_voltage_request(void *handle, 3354 struct pp_display_clock_request *clock_req) 3355 { 3356 struct smu_context *smu = handle; 3357 int ret = 0; 3358 3359 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3360 return -EOPNOTSUPP; 3361 3362 if (smu->ppt_funcs->display_clock_voltage_request) 3363 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3364 3365 return ret; 3366 } 3367 3368 3369 static int smu_display_disable_memory_clock_switch(void *handle, 3370 bool disable_memory_clock_switch) 3371 { 3372 struct smu_context *smu = handle; 3373 int ret = -EINVAL; 3374 3375 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3376 return -EOPNOTSUPP; 3377 3378 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3379 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3380 3381 return ret; 3382 } 3383 3384 static int smu_set_xgmi_pstate(void *handle, 3385 uint32_t pstate) 3386 { 3387 struct smu_context *smu = handle; 3388 int ret = 0; 3389 3390 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3391 return -EOPNOTSUPP; 3392 3393 if (smu->ppt_funcs->set_xgmi_pstate) 3394 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3395 3396 if (ret) 3397 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3398 3399 return ret; 3400 } 3401 3402 static int smu_get_baco_capability(void *handle) 3403 { 3404 struct smu_context *smu = handle; 3405 3406 if (!smu->pm_enabled) 3407 return false; 3408 3409 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3410 return false; 3411 3412 return smu->ppt_funcs->get_bamaco_support(smu); 3413 } 3414 3415 static int smu_baco_set_state(void *handle, int state) 3416 { 3417 struct smu_context *smu = handle; 3418 int ret = 0; 3419 3420 if (!smu->pm_enabled) 3421 return -EOPNOTSUPP; 3422 3423 if (state == 0) { 3424 if (smu->ppt_funcs->baco_exit) 3425 ret = smu->ppt_funcs->baco_exit(smu); 3426 } else if (state == 1) { 3427 if (smu->ppt_funcs->baco_enter) 3428 ret = smu->ppt_funcs->baco_enter(smu); 3429 } else { 3430 return -EINVAL; 3431 } 3432 3433 if (ret) 3434 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3435 (state)?"enter":"exit"); 3436 3437 return ret; 3438 } 3439 3440 bool smu_mode1_reset_is_support(struct smu_context *smu) 3441 { 3442 bool ret = false; 3443 3444 if (!smu->pm_enabled) 3445 return false; 3446 3447 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3448 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3449 3450 return ret; 3451 } 3452 3453 bool smu_link_reset_is_support(struct smu_context *smu) 3454 { 3455 bool ret = false; 3456 3457 if (!smu->pm_enabled) 3458 return false; 3459 3460 if (smu->ppt_funcs && smu->ppt_funcs->link_reset_is_support) 3461 ret = smu->ppt_funcs->link_reset_is_support(smu); 3462 3463 return ret; 3464 } 3465 3466 int smu_mode1_reset(struct smu_context *smu) 3467 { 3468 int ret = 0; 3469 3470 if (!smu->pm_enabled) 3471 return -EOPNOTSUPP; 3472 3473 if (smu->ppt_funcs->mode1_reset) 3474 ret = smu->ppt_funcs->mode1_reset(smu); 3475 3476 return ret; 3477 } 3478 3479 static int smu_mode2_reset(void *handle) 3480 { 3481 struct smu_context *smu = handle; 3482 int ret = 0; 3483 3484 if (!smu->pm_enabled) 3485 return -EOPNOTSUPP; 3486 3487 if (smu->ppt_funcs->mode2_reset) 3488 ret = smu->ppt_funcs->mode2_reset(smu); 3489 3490 if (ret) 3491 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3492 3493 return ret; 3494 } 3495 3496 int smu_link_reset(struct smu_context *smu) 3497 { 3498 int ret = 0; 3499 3500 if (!smu->pm_enabled) 3501 return -EOPNOTSUPP; 3502 3503 if (smu->ppt_funcs->link_reset) 3504 ret = smu->ppt_funcs->link_reset(smu); 3505 3506 return ret; 3507 } 3508 3509 static int smu_enable_gfx_features(void *handle) 3510 { 3511 struct smu_context *smu = handle; 3512 int ret = 0; 3513 3514 if (!smu->pm_enabled) 3515 return -EOPNOTSUPP; 3516 3517 if (smu->ppt_funcs->enable_gfx_features) 3518 ret = smu->ppt_funcs->enable_gfx_features(smu); 3519 3520 if (ret) 3521 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3522 3523 return ret; 3524 } 3525 3526 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3527 struct pp_smu_nv_clock_table *max_clocks) 3528 { 3529 struct smu_context *smu = handle; 3530 int ret = 0; 3531 3532 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3533 return -EOPNOTSUPP; 3534 3535 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3536 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3537 3538 return ret; 3539 } 3540 3541 static int smu_get_uclk_dpm_states(void *handle, 3542 unsigned int *clock_values_in_khz, 3543 unsigned int *num_states) 3544 { 3545 struct smu_context *smu = handle; 3546 int ret = 0; 3547 3548 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3549 return -EOPNOTSUPP; 3550 3551 if (smu->ppt_funcs->get_uclk_dpm_states) 3552 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3553 3554 return ret; 3555 } 3556 3557 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3558 { 3559 struct smu_context *smu = handle; 3560 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3561 3562 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3563 return -EOPNOTSUPP; 3564 3565 if (smu->ppt_funcs->get_current_power_state) 3566 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3567 3568 return pm_state; 3569 } 3570 3571 static int smu_get_dpm_clock_table(void *handle, 3572 struct dpm_clocks *clock_table) 3573 { 3574 struct smu_context *smu = handle; 3575 int ret = 0; 3576 3577 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3578 return -EOPNOTSUPP; 3579 3580 if (smu->ppt_funcs->get_dpm_clock_table) 3581 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3582 3583 return ret; 3584 } 3585 3586 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3587 { 3588 struct smu_context *smu = handle; 3589 3590 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3591 return -EOPNOTSUPP; 3592 3593 if (!smu->ppt_funcs->get_gpu_metrics) 3594 return -EOPNOTSUPP; 3595 3596 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3597 } 3598 3599 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3600 size_t size) 3601 { 3602 struct smu_context *smu = handle; 3603 3604 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3605 return -EOPNOTSUPP; 3606 3607 if (!smu->ppt_funcs->get_pm_metrics) 3608 return -EOPNOTSUPP; 3609 3610 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3611 } 3612 3613 static int smu_enable_mgpu_fan_boost(void *handle) 3614 { 3615 struct smu_context *smu = handle; 3616 int ret = 0; 3617 3618 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3619 return -EOPNOTSUPP; 3620 3621 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3622 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3623 3624 return ret; 3625 } 3626 3627 static int smu_gfx_state_change_set(void *handle, 3628 uint32_t state) 3629 { 3630 struct smu_context *smu = handle; 3631 int ret = 0; 3632 3633 if (smu->ppt_funcs->gfx_state_change_set) 3634 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3635 3636 return ret; 3637 } 3638 3639 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3640 { 3641 int ret = 0; 3642 3643 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3644 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3645 3646 return ret; 3647 } 3648 3649 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3650 { 3651 int ret = -EOPNOTSUPP; 3652 3653 if (smu->ppt_funcs && 3654 smu->ppt_funcs->get_ecc_info) 3655 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3656 3657 return ret; 3658 3659 } 3660 3661 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3662 { 3663 struct smu_context *smu = handle; 3664 struct smu_table_context *smu_table = &smu->smu_table; 3665 struct smu_table *memory_pool = &smu_table->memory_pool; 3666 3667 if (!addr || !size) 3668 return -EINVAL; 3669 3670 *addr = NULL; 3671 *size = 0; 3672 if (memory_pool->bo) { 3673 *addr = memory_pool->cpu_addr; 3674 *size = memory_pool->size; 3675 } 3676 3677 return 0; 3678 } 3679 3680 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3681 size_t *size) 3682 { 3683 size_t offset = *size; 3684 int level; 3685 3686 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3687 if (level == policy->current_level) 3688 offset += sysfs_emit_at(sysbuf, offset, 3689 "%d : %s*\n", level, 3690 policy->desc->get_desc(policy, level)); 3691 else 3692 offset += sysfs_emit_at(sysbuf, offset, 3693 "%d : %s\n", level, 3694 policy->desc->get_desc(policy, level)); 3695 } 3696 3697 *size = offset; 3698 } 3699 3700 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3701 enum pp_pm_policy p_type, char *sysbuf) 3702 { 3703 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3704 struct smu_dpm_policy_ctxt *policy_ctxt; 3705 struct smu_dpm_policy *dpm_policy; 3706 size_t offset = 0; 3707 3708 policy_ctxt = dpm_ctxt->dpm_policies; 3709 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3710 !policy_ctxt->policy_mask) 3711 return -EOPNOTSUPP; 3712 3713 if (p_type == PP_PM_POLICY_NONE) 3714 return -EINVAL; 3715 3716 dpm_policy = smu_get_pm_policy(smu, p_type); 3717 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3718 return -ENOENT; 3719 3720 if (!sysbuf) 3721 return -EINVAL; 3722 3723 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3724 3725 return offset; 3726 } 3727 3728 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3729 enum pp_pm_policy p_type) 3730 { 3731 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3732 struct smu_dpm_policy_ctxt *policy_ctxt; 3733 int i; 3734 3735 policy_ctxt = dpm_ctxt->dpm_policies; 3736 if (!policy_ctxt) 3737 return NULL; 3738 3739 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3740 if (policy_ctxt->policies[i].policy_type == p_type) 3741 return &policy_ctxt->policies[i]; 3742 } 3743 3744 return NULL; 3745 } 3746 3747 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3748 int level) 3749 { 3750 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3751 struct smu_dpm_policy *dpm_policy = NULL; 3752 struct smu_dpm_policy_ctxt *policy_ctxt; 3753 int ret = -EOPNOTSUPP; 3754 3755 policy_ctxt = dpm_ctxt->dpm_policies; 3756 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3757 !policy_ctxt->policy_mask) 3758 return ret; 3759 3760 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3761 return -EINVAL; 3762 3763 dpm_policy = smu_get_pm_policy(smu, p_type); 3764 3765 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3766 return ret; 3767 3768 if (dpm_policy->current_level == level) 3769 return 0; 3770 3771 ret = dpm_policy->set_policy(smu, level); 3772 3773 if (!ret) 3774 dpm_policy->current_level = level; 3775 3776 return ret; 3777 } 3778 3779 static ssize_t smu_sys_get_xcp_metrics(void *handle, int xcp_id, void *table) 3780 { 3781 struct smu_context *smu = handle; 3782 3783 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3784 return -EOPNOTSUPP; 3785 3786 if (!smu->adev->xcp_mgr || !smu->ppt_funcs->get_xcp_metrics) 3787 return -EOPNOTSUPP; 3788 3789 return smu->ppt_funcs->get_xcp_metrics(smu, xcp_id, table); 3790 } 3791 3792 static const struct amd_pm_funcs swsmu_pm_funcs = { 3793 /* export for sysfs */ 3794 .set_fan_control_mode = smu_set_fan_control_mode, 3795 .get_fan_control_mode = smu_get_fan_control_mode, 3796 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3797 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3798 .force_clock_level = smu_force_ppclk_levels, 3799 .print_clock_levels = smu_print_ppclk_levels, 3800 .emit_clock_levels = smu_emit_ppclk_levels, 3801 .force_performance_level = smu_force_performance_level, 3802 .read_sensor = smu_read_sensor, 3803 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3804 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3805 .get_performance_level = smu_get_performance_level, 3806 .get_current_power_state = smu_get_current_power_state, 3807 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3808 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3809 .get_pp_num_states = smu_get_power_num_states, 3810 .get_pp_table = smu_sys_get_pp_table, 3811 .set_pp_table = smu_sys_set_pp_table, 3812 .switch_power_profile = smu_switch_power_profile, 3813 .pause_power_profile = smu_pause_power_profile, 3814 /* export to amdgpu */ 3815 .dispatch_tasks = smu_handle_dpm_task, 3816 .load_firmware = smu_load_microcode, 3817 .set_powergating_by_smu = smu_dpm_set_power_gate, 3818 .set_power_limit = smu_set_power_limit, 3819 .get_power_limit = smu_get_power_limit, 3820 .get_power_profile_mode = smu_get_power_profile_mode, 3821 .set_power_profile_mode = smu_set_power_profile_mode, 3822 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3823 .set_mp1_state = smu_set_mp1_state, 3824 .gfx_state_change_set = smu_gfx_state_change_set, 3825 /* export to DC */ 3826 .get_sclk = smu_get_sclk, 3827 .get_mclk = smu_get_mclk, 3828 .display_configuration_change = smu_display_configuration_change, 3829 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3830 .display_clock_voltage_request = smu_display_clock_voltage_request, 3831 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3832 .set_active_display_count = smu_set_display_count, 3833 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3834 .get_asic_baco_capability = smu_get_baco_capability, 3835 .set_asic_baco_state = smu_baco_set_state, 3836 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3837 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3838 .asic_reset_mode_2 = smu_mode2_reset, 3839 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3840 .set_df_cstate = smu_set_df_cstate, 3841 .set_xgmi_pstate = smu_set_xgmi_pstate, 3842 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3843 .get_pm_metrics = smu_sys_get_pm_metrics, 3844 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3845 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3846 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3847 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3848 .get_dpm_clock_table = smu_get_dpm_clock_table, 3849 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3850 .get_xcp_metrics = smu_sys_get_xcp_metrics, 3851 }; 3852 3853 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3854 uint64_t event_arg) 3855 { 3856 int ret = -EINVAL; 3857 3858 if (smu->ppt_funcs->wait_for_event) 3859 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3860 3861 return ret; 3862 } 3863 3864 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3865 { 3866 3867 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3868 return -EOPNOTSUPP; 3869 3870 /* Confirm the buffer allocated is of correct size */ 3871 if (size != smu->stb_context.stb_buf_size) 3872 return -EINVAL; 3873 3874 /* 3875 * No need to lock smu mutex as we access STB directly through MMIO 3876 * and not going through SMU messaging route (for now at least). 3877 * For registers access rely on implementation internal locking. 3878 */ 3879 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3880 } 3881 3882 #if defined(CONFIG_DEBUG_FS) 3883 3884 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3885 { 3886 struct amdgpu_device *adev = filp->f_inode->i_private; 3887 struct smu_context *smu = adev->powerplay.pp_handle; 3888 unsigned char *buf; 3889 int r; 3890 3891 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3892 if (!buf) 3893 return -ENOMEM; 3894 3895 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3896 if (r) 3897 goto out; 3898 3899 filp->private_data = buf; 3900 3901 return 0; 3902 3903 out: 3904 kvfree(buf); 3905 return r; 3906 } 3907 3908 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3909 loff_t *pos) 3910 { 3911 struct amdgpu_device *adev = filp->f_inode->i_private; 3912 struct smu_context *smu = adev->powerplay.pp_handle; 3913 3914 3915 if (!filp->private_data) 3916 return -EINVAL; 3917 3918 return simple_read_from_buffer(buf, 3919 size, 3920 pos, filp->private_data, 3921 smu->stb_context.stb_buf_size); 3922 } 3923 3924 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3925 { 3926 kvfree(filp->private_data); 3927 filp->private_data = NULL; 3928 3929 return 0; 3930 } 3931 3932 /* 3933 * We have to define not only read method but also 3934 * open and release because .read takes up to PAGE_SIZE 3935 * data each time so and so is invoked multiple times. 3936 * We allocate the STB buffer in .open and release it 3937 * in .release 3938 */ 3939 static const struct file_operations smu_stb_debugfs_fops = { 3940 .owner = THIS_MODULE, 3941 .open = smu_stb_debugfs_open, 3942 .read = smu_stb_debugfs_read, 3943 .release = smu_stb_debugfs_release, 3944 .llseek = default_llseek, 3945 }; 3946 3947 #endif 3948 3949 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3950 { 3951 #if defined(CONFIG_DEBUG_FS) 3952 3953 struct smu_context *smu = adev->powerplay.pp_handle; 3954 3955 if (!smu || (!smu->stb_context.stb_buf_size)) 3956 return; 3957 3958 debugfs_create_file_size("amdgpu_smu_stb_dump", 3959 S_IRUSR, 3960 adev_to_drm(adev)->primary->debugfs_root, 3961 adev, 3962 &smu_stb_debugfs_fops, 3963 smu->stb_context.stb_buf_size); 3964 #endif 3965 } 3966 3967 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3968 { 3969 int ret = 0; 3970 3971 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3972 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3973 3974 return ret; 3975 } 3976 3977 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3978 { 3979 int ret = 0; 3980 3981 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3982 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3983 3984 return ret; 3985 } 3986 3987 int smu_send_rma_reason(struct smu_context *smu) 3988 { 3989 int ret = 0; 3990 3991 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3992 ret = smu->ppt_funcs->send_rma_reason(smu); 3993 3994 return ret; 3995 } 3996 3997 /** 3998 * smu_reset_sdma_is_supported - Check if SDMA reset is supported by SMU 3999 * @smu: smu_context pointer 4000 * 4001 * This function checks if the SMU supports resetting the SDMA engine. 4002 * It returns true if supported, false otherwise. 4003 */ 4004 bool smu_reset_sdma_is_supported(struct smu_context *smu) 4005 { 4006 bool ret = false; 4007 4008 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma_is_supported) 4009 ret = smu->ppt_funcs->reset_sdma_is_supported(smu); 4010 4011 return ret; 4012 } 4013 4014 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask) 4015 { 4016 int ret = 0; 4017 4018 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma) 4019 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask); 4020 4021 return ret; 4022 } 4023 4024 int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask) 4025 { 4026 if (smu->ppt_funcs && smu->ppt_funcs->dpm_reset_vcn) 4027 smu->ppt_funcs->dpm_reset_vcn(smu, inst_mask); 4028 4029 return 0; 4030 } 4031