1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/reboot.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_smu.h" 31 #include "smu_internal.h" 32 #include "atom.h" 33 #include "arcturus_ppt.h" 34 #include "navi10_ppt.h" 35 #include "sienna_cichlid_ppt.h" 36 #include "renoir_ppt.h" 37 #include "vangogh_ppt.h" 38 #include "aldebaran_ppt.h" 39 #include "yellow_carp_ppt.h" 40 #include "cyan_skillfish_ppt.h" 41 #include "smu_v13_0_0_ppt.h" 42 #include "smu_v13_0_4_ppt.h" 43 #include "smu_v13_0_5_ppt.h" 44 #include "smu_v13_0_6_ppt.h" 45 #include "smu_v13_0_7_ppt.h" 46 #include "smu_v14_0_0_ppt.h" 47 #include "amd_pcie.h" 48 49 /* 50 * DO NOT use these for err/warn/info/debug messages. 51 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 52 * They are more MGPU friendly. 53 */ 54 #undef pr_err 55 #undef pr_warn 56 #undef pr_info 57 #undef pr_debug 58 59 static const struct amd_pm_funcs swsmu_pm_funcs; 60 static int smu_force_smuclk_levels(struct smu_context *smu, 61 enum smu_clk_type clk_type, 62 uint32_t mask); 63 static int smu_handle_task(struct smu_context *smu, 64 enum amd_dpm_forced_level level, 65 enum amd_pp_task task_id); 66 static int smu_reset(struct smu_context *smu); 67 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 68 static int smu_set_fan_control_mode(void *handle, u32 value); 69 static int smu_set_power_limit(void *handle, uint32_t limit); 70 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 71 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 72 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 73 74 static int smu_sys_get_pp_feature_mask(void *handle, 75 char *buf) 76 { 77 struct smu_context *smu = handle; 78 79 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 80 return -EOPNOTSUPP; 81 82 return smu_get_pp_feature_mask(smu, buf); 83 } 84 85 static int smu_sys_set_pp_feature_mask(void *handle, 86 uint64_t new_mask) 87 { 88 struct smu_context *smu = handle; 89 90 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 91 return -EOPNOTSUPP; 92 93 return smu_set_pp_feature_mask(smu, new_mask); 94 } 95 96 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 97 { 98 if (!smu->ppt_funcs->set_gfx_off_residency) 99 return -EINVAL; 100 101 return smu_set_gfx_off_residency(smu, value); 102 } 103 104 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 105 { 106 if (!smu->ppt_funcs->get_gfx_off_residency) 107 return -EINVAL; 108 109 return smu_get_gfx_off_residency(smu, value); 110 } 111 112 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 113 { 114 if (!smu->ppt_funcs->get_gfx_off_entrycount) 115 return -EINVAL; 116 117 return smu_get_gfx_off_entrycount(smu, value); 118 } 119 120 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 121 { 122 if (!smu->ppt_funcs->get_gfx_off_status) 123 return -EINVAL; 124 125 *value = smu_get_gfx_off_status(smu); 126 127 return 0; 128 } 129 130 int smu_set_soft_freq_range(struct smu_context *smu, 131 enum smu_clk_type clk_type, 132 uint32_t min, 133 uint32_t max) 134 { 135 int ret = 0; 136 137 if (smu->ppt_funcs->set_soft_freq_limited_range) 138 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 139 clk_type, 140 min, 141 max); 142 143 return ret; 144 } 145 146 int smu_get_dpm_freq_range(struct smu_context *smu, 147 enum smu_clk_type clk_type, 148 uint32_t *min, 149 uint32_t *max) 150 { 151 int ret = -ENOTSUPP; 152 153 if (!min && !max) 154 return -EINVAL; 155 156 if (smu->ppt_funcs->get_dpm_ultimate_freq) 157 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 158 clk_type, 159 min, 160 max); 161 162 return ret; 163 } 164 165 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 166 { 167 int ret = 0; 168 struct amdgpu_device *adev = smu->adev; 169 170 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 171 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 172 if (ret) 173 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 174 } 175 return ret; 176 } 177 178 static u32 smu_get_mclk(void *handle, bool low) 179 { 180 struct smu_context *smu = handle; 181 uint32_t clk_freq; 182 int ret = 0; 183 184 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 185 low ? &clk_freq : NULL, 186 !low ? &clk_freq : NULL); 187 if (ret) 188 return 0; 189 return clk_freq * 100; 190 } 191 192 static u32 smu_get_sclk(void *handle, bool low) 193 { 194 struct smu_context *smu = handle; 195 uint32_t clk_freq; 196 int ret = 0; 197 198 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 199 low ? &clk_freq : NULL, 200 !low ? &clk_freq : NULL); 201 if (ret) 202 return 0; 203 return clk_freq * 100; 204 } 205 206 static int smu_set_gfx_imu_enable(struct smu_context *smu) 207 { 208 struct amdgpu_device *adev = smu->adev; 209 210 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 211 return 0; 212 213 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 214 return 0; 215 216 return smu_set_gfx_power_up_by_imu(smu); 217 } 218 219 static bool is_vcn_enabled(struct amdgpu_device *adev) 220 { 221 int i; 222 223 for (i = 0; i < adev->num_ip_blocks; i++) { 224 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 225 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 226 !adev->ip_blocks[i].status.valid) 227 return false; 228 } 229 230 return true; 231 } 232 233 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 234 bool enable) 235 { 236 struct smu_power_context *smu_power = &smu->smu_power; 237 struct smu_power_gate *power_gate = &smu_power->power_gate; 238 int ret = 0; 239 240 /* 241 * don't poweron vcn/jpeg when they are skipped. 242 */ 243 if (!is_vcn_enabled(smu->adev)) 244 return 0; 245 246 if (!smu->ppt_funcs->dpm_set_vcn_enable) 247 return 0; 248 249 if (atomic_read(&power_gate->vcn_gated) ^ enable) 250 return 0; 251 252 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 253 if (!ret) 254 atomic_set(&power_gate->vcn_gated, !enable); 255 256 return ret; 257 } 258 259 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 260 bool enable) 261 { 262 struct smu_power_context *smu_power = &smu->smu_power; 263 struct smu_power_gate *power_gate = &smu_power->power_gate; 264 int ret = 0; 265 266 if (!is_vcn_enabled(smu->adev)) 267 return 0; 268 269 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 270 return 0; 271 272 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 273 return 0; 274 275 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 276 if (!ret) 277 atomic_set(&power_gate->jpeg_gated, !enable); 278 279 return ret; 280 } 281 282 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 283 bool enable) 284 { 285 struct smu_power_context *smu_power = &smu->smu_power; 286 struct smu_power_gate *power_gate = &smu_power->power_gate; 287 int ret = 0; 288 289 if (!smu->ppt_funcs->dpm_set_vpe_enable) 290 return 0; 291 292 if (atomic_read(&power_gate->vpe_gated) ^ enable) 293 return 0; 294 295 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 296 if (!ret) 297 atomic_set(&power_gate->vpe_gated, !enable); 298 299 return ret; 300 } 301 302 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 303 bool enable) 304 { 305 struct smu_power_context *smu_power = &smu->smu_power; 306 struct smu_power_gate *power_gate = &smu_power->power_gate; 307 int ret = 0; 308 309 if (!smu->adev->enable_umsch_mm) 310 return 0; 311 312 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 313 return 0; 314 315 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 316 return 0; 317 318 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 319 if (!ret) 320 atomic_set(&power_gate->umsch_mm_gated, !enable); 321 322 return ret; 323 } 324 325 /** 326 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 327 * 328 * @handle: smu_context pointer 329 * @block_type: the IP block to power gate/ungate 330 * @gate: to power gate if true, ungate otherwise 331 * 332 * This API uses no smu->mutex lock protection due to: 333 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 334 * This is guarded to be race condition free by the caller. 335 * 2. Or get called on user setting request of power_dpm_force_performance_level. 336 * Under this case, the smu->mutex lock protection is already enforced on 337 * the parent API smu_force_performance_level of the call path. 338 */ 339 static int smu_dpm_set_power_gate(void *handle, 340 uint32_t block_type, 341 bool gate) 342 { 343 struct smu_context *smu = handle; 344 int ret = 0; 345 346 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 347 dev_WARN(smu->adev->dev, 348 "SMU uninitialized but power %s requested for %u!\n", 349 gate ? "gate" : "ungate", block_type); 350 return -EOPNOTSUPP; 351 } 352 353 switch (block_type) { 354 /* 355 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 356 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 357 */ 358 case AMD_IP_BLOCK_TYPE_UVD: 359 case AMD_IP_BLOCK_TYPE_VCN: 360 ret = smu_dpm_set_vcn_enable(smu, !gate); 361 if (ret) 362 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 363 gate ? "gate" : "ungate"); 364 break; 365 case AMD_IP_BLOCK_TYPE_GFX: 366 ret = smu_gfx_off_control(smu, gate); 367 if (ret) 368 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 369 gate ? "enable" : "disable"); 370 break; 371 case AMD_IP_BLOCK_TYPE_SDMA: 372 ret = smu_powergate_sdma(smu, gate); 373 if (ret) 374 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 375 gate ? "gate" : "ungate"); 376 break; 377 case AMD_IP_BLOCK_TYPE_JPEG: 378 ret = smu_dpm_set_jpeg_enable(smu, !gate); 379 if (ret) 380 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 381 gate ? "gate" : "ungate"); 382 break; 383 case AMD_IP_BLOCK_TYPE_VPE: 384 ret = smu_dpm_set_vpe_enable(smu, !gate); 385 if (ret) 386 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 387 gate ? "gate" : "ungate"); 388 break; 389 default: 390 dev_err(smu->adev->dev, "Unsupported block type!\n"); 391 return -EINVAL; 392 } 393 394 return ret; 395 } 396 397 /** 398 * smu_set_user_clk_dependencies - set user profile clock dependencies 399 * 400 * @smu: smu_context pointer 401 * @clk: enum smu_clk_type type 402 * 403 * Enable/Disable the clock dependency for the @clk type. 404 */ 405 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 406 { 407 if (smu->adev->in_suspend) 408 return; 409 410 if (clk == SMU_MCLK) { 411 smu->user_dpm_profile.clk_dependency = 0; 412 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 413 } else if (clk == SMU_FCLK) { 414 /* MCLK takes precedence over FCLK */ 415 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 416 return; 417 418 smu->user_dpm_profile.clk_dependency = 0; 419 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 420 } else if (clk == SMU_SOCCLK) { 421 /* MCLK takes precedence over SOCCLK */ 422 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 423 return; 424 425 smu->user_dpm_profile.clk_dependency = 0; 426 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 427 } else 428 /* Add clk dependencies here, if any */ 429 return; 430 } 431 432 /** 433 * smu_restore_dpm_user_profile - reinstate user dpm profile 434 * 435 * @smu: smu_context pointer 436 * 437 * Restore the saved user power configurations include power limit, 438 * clock frequencies, fan control mode and fan speed. 439 */ 440 static void smu_restore_dpm_user_profile(struct smu_context *smu) 441 { 442 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 443 int ret = 0; 444 445 if (!smu->adev->in_suspend) 446 return; 447 448 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 449 return; 450 451 /* Enable restore flag */ 452 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 453 454 /* set the user dpm power limit */ 455 if (smu->user_dpm_profile.power_limit) { 456 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 457 if (ret) 458 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 459 } 460 461 /* set the user dpm clock configurations */ 462 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 463 enum smu_clk_type clk_type; 464 465 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 466 /* 467 * Iterate over smu clk type and force the saved user clk 468 * configs, skip if clock dependency is enabled 469 */ 470 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 471 smu->user_dpm_profile.clk_mask[clk_type]) { 472 ret = smu_force_smuclk_levels(smu, clk_type, 473 smu->user_dpm_profile.clk_mask[clk_type]); 474 if (ret) 475 dev_err(smu->adev->dev, 476 "Failed to set clock type = %d\n", clk_type); 477 } 478 } 479 } 480 481 /* set the user dpm fan configurations */ 482 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 483 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 484 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 485 if (ret != -EOPNOTSUPP) { 486 smu->user_dpm_profile.fan_speed_pwm = 0; 487 smu->user_dpm_profile.fan_speed_rpm = 0; 488 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 489 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 490 } 491 492 if (smu->user_dpm_profile.fan_speed_pwm) { 493 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 494 if (ret != -EOPNOTSUPP) 495 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 496 } 497 498 if (smu->user_dpm_profile.fan_speed_rpm) { 499 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 500 if (ret != -EOPNOTSUPP) 501 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 502 } 503 } 504 505 /* Restore user customized OD settings */ 506 if (smu->user_dpm_profile.user_od) { 507 if (smu->ppt_funcs->restore_user_od_settings) { 508 ret = smu->ppt_funcs->restore_user_od_settings(smu); 509 if (ret) 510 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 511 } 512 } 513 514 /* Disable restore flag */ 515 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 516 } 517 518 static int smu_get_power_num_states(void *handle, 519 struct pp_states_info *state_info) 520 { 521 if (!state_info) 522 return -EINVAL; 523 524 /* not support power state */ 525 memset(state_info, 0, sizeof(struct pp_states_info)); 526 state_info->nums = 1; 527 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 528 529 return 0; 530 } 531 532 bool is_support_sw_smu(struct amdgpu_device *adev) 533 { 534 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 535 if (adev->asic_type == CHIP_VEGA20) 536 return false; 537 538 if (amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) 539 return true; 540 541 return false; 542 } 543 544 bool is_support_cclk_dpm(struct amdgpu_device *adev) 545 { 546 struct smu_context *smu = adev->powerplay.pp_handle; 547 548 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 549 return false; 550 551 return true; 552 } 553 554 555 static int smu_sys_get_pp_table(void *handle, 556 char **table) 557 { 558 struct smu_context *smu = handle; 559 struct smu_table_context *smu_table = &smu->smu_table; 560 561 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 562 return -EOPNOTSUPP; 563 564 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 565 return -EINVAL; 566 567 if (smu_table->hardcode_pptable) 568 *table = smu_table->hardcode_pptable; 569 else 570 *table = smu_table->power_play_table; 571 572 return smu_table->power_play_table_size; 573 } 574 575 static int smu_sys_set_pp_table(void *handle, 576 const char *buf, 577 size_t size) 578 { 579 struct smu_context *smu = handle; 580 struct smu_table_context *smu_table = &smu->smu_table; 581 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 582 int ret = 0; 583 584 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 585 return -EOPNOTSUPP; 586 587 if (header->usStructureSize != size) { 588 dev_err(smu->adev->dev, "pp table size not matched !\n"); 589 return -EIO; 590 } 591 592 if (!smu_table->hardcode_pptable) { 593 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 594 if (!smu_table->hardcode_pptable) 595 return -ENOMEM; 596 } 597 598 memcpy(smu_table->hardcode_pptable, buf, size); 599 smu_table->power_play_table = smu_table->hardcode_pptable; 600 smu_table->power_play_table_size = size; 601 602 /* 603 * Special hw_fini action(for Navi1x, the DPMs disablement will be 604 * skipped) may be needed for custom pptable uploading. 605 */ 606 smu->uploading_custom_pp_table = true; 607 608 ret = smu_reset(smu); 609 if (ret) 610 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 611 612 smu->uploading_custom_pp_table = false; 613 614 return ret; 615 } 616 617 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 618 { 619 struct smu_feature *feature = &smu->smu_feature; 620 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 621 int ret = 0; 622 623 /* 624 * With SCPM enabled, the allowed featuremasks setting(via 625 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 626 * That means there is no way to let PMFW knows the settings below. 627 * Thus, we just assume all the features are allowed under 628 * such scenario. 629 */ 630 if (smu->adev->scpm_enabled) { 631 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 632 return 0; 633 } 634 635 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 636 637 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 638 SMU_FEATURE_MAX/32); 639 if (ret) 640 return ret; 641 642 bitmap_or(feature->allowed, feature->allowed, 643 (unsigned long *)allowed_feature_mask, 644 feature->feature_num); 645 646 return ret; 647 } 648 649 static int smu_set_funcs(struct amdgpu_device *adev) 650 { 651 struct smu_context *smu = adev->powerplay.pp_handle; 652 653 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 654 smu->od_enabled = true; 655 656 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 657 case IP_VERSION(11, 0, 0): 658 case IP_VERSION(11, 0, 5): 659 case IP_VERSION(11, 0, 9): 660 navi10_set_ppt_funcs(smu); 661 break; 662 case IP_VERSION(11, 0, 7): 663 case IP_VERSION(11, 0, 11): 664 case IP_VERSION(11, 0, 12): 665 case IP_VERSION(11, 0, 13): 666 sienna_cichlid_set_ppt_funcs(smu); 667 break; 668 case IP_VERSION(12, 0, 0): 669 case IP_VERSION(12, 0, 1): 670 renoir_set_ppt_funcs(smu); 671 break; 672 case IP_VERSION(11, 5, 0): 673 vangogh_set_ppt_funcs(smu); 674 break; 675 case IP_VERSION(13, 0, 1): 676 case IP_VERSION(13, 0, 3): 677 case IP_VERSION(13, 0, 8): 678 yellow_carp_set_ppt_funcs(smu); 679 break; 680 case IP_VERSION(13, 0, 4): 681 case IP_VERSION(13, 0, 11): 682 smu_v13_0_4_set_ppt_funcs(smu); 683 break; 684 case IP_VERSION(13, 0, 5): 685 smu_v13_0_5_set_ppt_funcs(smu); 686 break; 687 case IP_VERSION(11, 0, 8): 688 cyan_skillfish_set_ppt_funcs(smu); 689 break; 690 case IP_VERSION(11, 0, 2): 691 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 692 arcturus_set_ppt_funcs(smu); 693 /* OD is not supported on Arcturus */ 694 smu->od_enabled = false; 695 break; 696 case IP_VERSION(13, 0, 2): 697 aldebaran_set_ppt_funcs(smu); 698 /* Enable pp_od_clk_voltage node */ 699 smu->od_enabled = true; 700 break; 701 case IP_VERSION(13, 0, 0): 702 case IP_VERSION(13, 0, 10): 703 smu_v13_0_0_set_ppt_funcs(smu); 704 break; 705 case IP_VERSION(13, 0, 6): 706 smu_v13_0_6_set_ppt_funcs(smu); 707 /* Enable pp_od_clk_voltage node */ 708 smu->od_enabled = true; 709 break; 710 case IP_VERSION(13, 0, 7): 711 smu_v13_0_7_set_ppt_funcs(smu); 712 break; 713 case IP_VERSION(14, 0, 0): 714 smu_v14_0_0_set_ppt_funcs(smu); 715 break; 716 default: 717 return -EINVAL; 718 } 719 720 return 0; 721 } 722 723 static int smu_early_init(void *handle) 724 { 725 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 726 struct smu_context *smu; 727 int r; 728 729 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 730 if (!smu) 731 return -ENOMEM; 732 733 smu->adev = adev; 734 smu->pm_enabled = !!amdgpu_dpm; 735 smu->is_apu = false; 736 smu->smu_baco.state = SMU_BACO_STATE_NONE; 737 smu->smu_baco.platform_support = false; 738 smu->user_dpm_profile.fan_mode = -1; 739 740 mutex_init(&smu->message_lock); 741 742 adev->powerplay.pp_handle = smu; 743 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 744 745 r = smu_set_funcs(adev); 746 if (r) 747 return r; 748 return smu_init_microcode(smu); 749 } 750 751 static int smu_set_default_dpm_table(struct smu_context *smu) 752 { 753 struct smu_power_context *smu_power = &smu->smu_power; 754 struct smu_power_gate *power_gate = &smu_power->power_gate; 755 int vcn_gate, jpeg_gate; 756 int ret = 0; 757 758 if (!smu->ppt_funcs->set_default_dpm_table) 759 return 0; 760 761 vcn_gate = atomic_read(&power_gate->vcn_gated); 762 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 763 764 ret = smu_dpm_set_vcn_enable(smu, true); 765 if (ret) 766 return ret; 767 768 ret = smu_dpm_set_jpeg_enable(smu, true); 769 if (ret) 770 goto err_out; 771 772 ret = smu->ppt_funcs->set_default_dpm_table(smu); 773 if (ret) 774 dev_err(smu->adev->dev, 775 "Failed to setup default dpm clock tables!\n"); 776 777 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 778 err_out: 779 smu_dpm_set_vcn_enable(smu, !vcn_gate); 780 return ret; 781 } 782 783 static int smu_apply_default_config_table_settings(struct smu_context *smu) 784 { 785 struct amdgpu_device *adev = smu->adev; 786 int ret = 0; 787 788 ret = smu_get_default_config_table_settings(smu, 789 &adev->pm.config_table); 790 if (ret) 791 return ret; 792 793 return smu_set_config_table(smu, &adev->pm.config_table); 794 } 795 796 static int smu_late_init(void *handle) 797 { 798 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 799 struct smu_context *smu = adev->powerplay.pp_handle; 800 int ret = 0; 801 802 smu_set_fine_grain_gfx_freq_parameters(smu); 803 804 if (!smu->pm_enabled) 805 return 0; 806 807 ret = smu_post_init(smu); 808 if (ret) { 809 dev_err(adev->dev, "Failed to post smu init!\n"); 810 return ret; 811 } 812 813 /* 814 * Explicitly notify PMFW the power mode the system in. Since 815 * the PMFW may boot the ASIC with a different mode. 816 * For those supporting ACDC switch via gpio, PMFW will 817 * handle the switch automatically. Driver involvement 818 * is unnecessary. 819 */ 820 if (!smu->dc_controlled_by_gpio) { 821 ret = smu_set_power_source(smu, 822 adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 823 SMU_POWER_SOURCE_DC); 824 if (ret) { 825 dev_err(adev->dev, "Failed to switch to %s mode!\n", 826 adev->pm.ac_power ? "AC" : "DC"); 827 return ret; 828 } 829 } 830 831 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 832 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 833 return 0; 834 835 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 836 ret = smu_set_default_od_settings(smu); 837 if (ret) { 838 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 839 return ret; 840 } 841 } 842 843 ret = smu_populate_umd_state_clk(smu); 844 if (ret) { 845 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 846 return ret; 847 } 848 849 ret = smu_get_asic_power_limits(smu, 850 &smu->current_power_limit, 851 &smu->default_power_limit, 852 &smu->max_power_limit, 853 &smu->min_power_limit); 854 if (ret) { 855 dev_err(adev->dev, "Failed to get asic power limits!\n"); 856 return ret; 857 } 858 859 if (!amdgpu_sriov_vf(adev)) 860 smu_get_unique_id(smu); 861 862 smu_get_fan_parameters(smu); 863 864 smu_handle_task(smu, 865 smu->smu_dpm.dpm_level, 866 AMD_PP_TASK_COMPLETE_INIT); 867 868 ret = smu_apply_default_config_table_settings(smu); 869 if (ret && (ret != -EOPNOTSUPP)) { 870 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 871 return ret; 872 } 873 874 smu_restore_dpm_user_profile(smu); 875 876 return 0; 877 } 878 879 static int smu_init_fb_allocations(struct smu_context *smu) 880 { 881 struct amdgpu_device *adev = smu->adev; 882 struct smu_table_context *smu_table = &smu->smu_table; 883 struct smu_table *tables = smu_table->tables; 884 struct smu_table *driver_table = &(smu_table->driver_table); 885 uint32_t max_table_size = 0; 886 int ret, i; 887 888 /* VRAM allocation for tool table */ 889 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 890 ret = amdgpu_bo_create_kernel(adev, 891 tables[SMU_TABLE_PMSTATUSLOG].size, 892 tables[SMU_TABLE_PMSTATUSLOG].align, 893 tables[SMU_TABLE_PMSTATUSLOG].domain, 894 &tables[SMU_TABLE_PMSTATUSLOG].bo, 895 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 896 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 897 if (ret) { 898 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 899 return ret; 900 } 901 } 902 903 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 904 /* VRAM allocation for driver table */ 905 for (i = 0; i < SMU_TABLE_COUNT; i++) { 906 if (tables[i].size == 0) 907 continue; 908 909 /* If one of the tables has VRAM domain restriction, keep it in 910 * VRAM 911 */ 912 if ((tables[i].domain & 913 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 914 AMDGPU_GEM_DOMAIN_VRAM) 915 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 916 917 if (i == SMU_TABLE_PMSTATUSLOG) 918 continue; 919 920 if (max_table_size < tables[i].size) 921 max_table_size = tables[i].size; 922 } 923 924 driver_table->size = max_table_size; 925 driver_table->align = PAGE_SIZE; 926 927 ret = amdgpu_bo_create_kernel(adev, 928 driver_table->size, 929 driver_table->align, 930 driver_table->domain, 931 &driver_table->bo, 932 &driver_table->mc_address, 933 &driver_table->cpu_addr); 934 if (ret) { 935 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 936 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 937 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 938 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 939 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 940 } 941 942 return ret; 943 } 944 945 static int smu_fini_fb_allocations(struct smu_context *smu) 946 { 947 struct smu_table_context *smu_table = &smu->smu_table; 948 struct smu_table *tables = smu_table->tables; 949 struct smu_table *driver_table = &(smu_table->driver_table); 950 951 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 952 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 953 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 954 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 955 956 amdgpu_bo_free_kernel(&driver_table->bo, 957 &driver_table->mc_address, 958 &driver_table->cpu_addr); 959 960 return 0; 961 } 962 963 /** 964 * smu_alloc_memory_pool - allocate memory pool in the system memory 965 * 966 * @smu: amdgpu_device pointer 967 * 968 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 969 * and DramLogSetDramAddr can notify it changed. 970 * 971 * Returns 0 on success, error on failure. 972 */ 973 static int smu_alloc_memory_pool(struct smu_context *smu) 974 { 975 struct amdgpu_device *adev = smu->adev; 976 struct smu_table_context *smu_table = &smu->smu_table; 977 struct smu_table *memory_pool = &smu_table->memory_pool; 978 uint64_t pool_size = smu->pool_size; 979 int ret = 0; 980 981 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 982 return ret; 983 984 memory_pool->size = pool_size; 985 memory_pool->align = PAGE_SIZE; 986 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 987 988 switch (pool_size) { 989 case SMU_MEMORY_POOL_SIZE_256_MB: 990 case SMU_MEMORY_POOL_SIZE_512_MB: 991 case SMU_MEMORY_POOL_SIZE_1_GB: 992 case SMU_MEMORY_POOL_SIZE_2_GB: 993 ret = amdgpu_bo_create_kernel(adev, 994 memory_pool->size, 995 memory_pool->align, 996 memory_pool->domain, 997 &memory_pool->bo, 998 &memory_pool->mc_address, 999 &memory_pool->cpu_addr); 1000 if (ret) 1001 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1002 break; 1003 default: 1004 break; 1005 } 1006 1007 return ret; 1008 } 1009 1010 static int smu_free_memory_pool(struct smu_context *smu) 1011 { 1012 struct smu_table_context *smu_table = &smu->smu_table; 1013 struct smu_table *memory_pool = &smu_table->memory_pool; 1014 1015 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1016 return 0; 1017 1018 amdgpu_bo_free_kernel(&memory_pool->bo, 1019 &memory_pool->mc_address, 1020 &memory_pool->cpu_addr); 1021 1022 memset(memory_pool, 0, sizeof(struct smu_table)); 1023 1024 return 0; 1025 } 1026 1027 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1028 { 1029 struct smu_table_context *smu_table = &smu->smu_table; 1030 struct smu_table *dummy_read_1_table = 1031 &smu_table->dummy_read_1_table; 1032 struct amdgpu_device *adev = smu->adev; 1033 int ret = 0; 1034 1035 if (!dummy_read_1_table->size) 1036 return 0; 1037 1038 ret = amdgpu_bo_create_kernel(adev, 1039 dummy_read_1_table->size, 1040 dummy_read_1_table->align, 1041 dummy_read_1_table->domain, 1042 &dummy_read_1_table->bo, 1043 &dummy_read_1_table->mc_address, 1044 &dummy_read_1_table->cpu_addr); 1045 if (ret) 1046 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1047 1048 return ret; 1049 } 1050 1051 static void smu_free_dummy_read_table(struct smu_context *smu) 1052 { 1053 struct smu_table_context *smu_table = &smu->smu_table; 1054 struct smu_table *dummy_read_1_table = 1055 &smu_table->dummy_read_1_table; 1056 1057 1058 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1059 &dummy_read_1_table->mc_address, 1060 &dummy_read_1_table->cpu_addr); 1061 1062 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1063 } 1064 1065 static int smu_smc_table_sw_init(struct smu_context *smu) 1066 { 1067 int ret; 1068 1069 /** 1070 * Create smu_table structure, and init smc tables such as 1071 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1072 */ 1073 ret = smu_init_smc_tables(smu); 1074 if (ret) { 1075 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1076 return ret; 1077 } 1078 1079 /** 1080 * Create smu_power_context structure, and allocate smu_dpm_context and 1081 * context size to fill the smu_power_context data. 1082 */ 1083 ret = smu_init_power(smu); 1084 if (ret) { 1085 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1086 return ret; 1087 } 1088 1089 /* 1090 * allocate vram bos to store smc table contents. 1091 */ 1092 ret = smu_init_fb_allocations(smu); 1093 if (ret) 1094 return ret; 1095 1096 ret = smu_alloc_memory_pool(smu); 1097 if (ret) 1098 return ret; 1099 1100 ret = smu_alloc_dummy_read_table(smu); 1101 if (ret) 1102 return ret; 1103 1104 ret = smu_i2c_init(smu); 1105 if (ret) 1106 return ret; 1107 1108 return 0; 1109 } 1110 1111 static int smu_smc_table_sw_fini(struct smu_context *smu) 1112 { 1113 int ret; 1114 1115 smu_i2c_fini(smu); 1116 1117 smu_free_dummy_read_table(smu); 1118 1119 ret = smu_free_memory_pool(smu); 1120 if (ret) 1121 return ret; 1122 1123 ret = smu_fini_fb_allocations(smu); 1124 if (ret) 1125 return ret; 1126 1127 ret = smu_fini_power(smu); 1128 if (ret) { 1129 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1130 return ret; 1131 } 1132 1133 ret = smu_fini_smc_tables(smu); 1134 if (ret) { 1135 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1136 return ret; 1137 } 1138 1139 return 0; 1140 } 1141 1142 static void smu_throttling_logging_work_fn(struct work_struct *work) 1143 { 1144 struct smu_context *smu = container_of(work, struct smu_context, 1145 throttling_logging_work); 1146 1147 smu_log_thermal_throttling(smu); 1148 } 1149 1150 static void smu_interrupt_work_fn(struct work_struct *work) 1151 { 1152 struct smu_context *smu = container_of(work, struct smu_context, 1153 interrupt_work); 1154 1155 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1156 smu->ppt_funcs->interrupt_work(smu); 1157 } 1158 1159 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1160 { 1161 struct smu_context *smu = 1162 container_of(work, struct smu_context, swctf_delayed_work.work); 1163 struct smu_temperature_range *range = 1164 &smu->thermal_range; 1165 struct amdgpu_device *adev = smu->adev; 1166 uint32_t hotspot_tmp, size; 1167 1168 /* 1169 * If the hotspot temperature is confirmed as below SW CTF setting point 1170 * after the delay enforced, nothing will be done. 1171 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1172 */ 1173 if (range->software_shutdown_temp && 1174 smu->ppt_funcs->read_sensor && 1175 !smu->ppt_funcs->read_sensor(smu, 1176 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1177 &hotspot_tmp, 1178 &size) && 1179 hotspot_tmp / 1000 < range->software_shutdown_temp) 1180 return; 1181 1182 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1183 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1184 orderly_poweroff(true); 1185 } 1186 1187 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1188 { 1189 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1190 smu->plpd_mode = XGMI_PLPD_DEFAULT; 1191 return; 1192 } 1193 1194 /* PMFW put PLPD into default policy after enabling the feature */ 1195 if (smu_feature_is_enabled(smu, 1196 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) 1197 smu->plpd_mode = XGMI_PLPD_DEFAULT; 1198 else 1199 smu->plpd_mode = XGMI_PLPD_NONE; 1200 } 1201 1202 static int smu_sw_init(void *handle) 1203 { 1204 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1205 struct smu_context *smu = adev->powerplay.pp_handle; 1206 int ret; 1207 1208 smu->pool_size = adev->pm.smu_prv_buffer_size; 1209 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1210 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1211 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1212 1213 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1214 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1215 atomic64_set(&smu->throttle_int_counter, 0); 1216 smu->watermarks_bitmap = 0; 1217 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1218 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1219 1220 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1221 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1222 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1223 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1224 1225 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1226 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1227 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1228 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1229 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1230 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1231 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1232 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1233 1234 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1235 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1236 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1237 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1238 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1239 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1240 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1241 smu->display_config = &adev->pm.pm_display_cfg; 1242 1243 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1244 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1245 1246 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1247 smu_swctf_delayed_work_handler); 1248 1249 ret = smu_smc_table_sw_init(smu); 1250 if (ret) { 1251 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1252 return ret; 1253 } 1254 1255 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1256 ret = smu_get_vbios_bootup_values(smu); 1257 if (ret) { 1258 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1259 return ret; 1260 } 1261 1262 ret = smu_init_pptable_microcode(smu); 1263 if (ret) { 1264 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1265 return ret; 1266 } 1267 1268 ret = smu_register_irq_handler(smu); 1269 if (ret) { 1270 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1271 return ret; 1272 } 1273 1274 /* If there is no way to query fan control mode, fan control is not supported */ 1275 if (!smu->ppt_funcs->get_fan_control_mode) 1276 smu->adev->pm.no_fan = true; 1277 1278 return 0; 1279 } 1280 1281 static int smu_sw_fini(void *handle) 1282 { 1283 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1284 struct smu_context *smu = adev->powerplay.pp_handle; 1285 int ret; 1286 1287 ret = smu_smc_table_sw_fini(smu); 1288 if (ret) { 1289 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1290 return ret; 1291 } 1292 1293 smu_fini_microcode(smu); 1294 1295 return 0; 1296 } 1297 1298 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1299 { 1300 struct amdgpu_device *adev = smu->adev; 1301 struct smu_temperature_range *range = 1302 &smu->thermal_range; 1303 int ret = 0; 1304 1305 if (!smu->ppt_funcs->get_thermal_temperature_range) 1306 return 0; 1307 1308 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1309 if (ret) 1310 return ret; 1311 1312 adev->pm.dpm.thermal.min_temp = range->min; 1313 adev->pm.dpm.thermal.max_temp = range->max; 1314 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1315 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1316 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1317 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1318 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1319 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1320 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1321 1322 return ret; 1323 } 1324 1325 /** 1326 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1327 * 1328 * @smu: smu_context pointer 1329 * 1330 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1331 * Returns 0 on success, error on failure. 1332 */ 1333 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1334 { 1335 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1336 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1337 struct amdgpu_device *adev = smu->adev; 1338 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1339 uint64_t start, end; 1340 int ret, i, j; 1341 1342 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1343 if (ret) { 1344 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1345 return ret; 1346 } 1347 1348 /* 1349 * The exclusion ranges array we got might be filled with holes and duplicate 1350 * entries. For example: 1351 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1352 * We need to do some sortups to eliminate those holes and duplicate entries. 1353 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1354 */ 1355 for (i = 0; i < num_of_wbrf_ranges; i++) { 1356 start = wifi_bands[i].start; 1357 end = wifi_bands[i].end; 1358 1359 /* get the last valid entry to fill the intermediate hole */ 1360 if (!start && !end) { 1361 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1362 if (wifi_bands[j].start && wifi_bands[j].end) 1363 break; 1364 1365 /* no valid entry left */ 1366 if (j <= i) 1367 break; 1368 1369 start = wifi_bands[i].start = wifi_bands[j].start; 1370 end = wifi_bands[i].end = wifi_bands[j].end; 1371 wifi_bands[j].start = 0; 1372 wifi_bands[j].end = 0; 1373 num_of_wbrf_ranges = j; 1374 } 1375 1376 /* eliminate duplicate entries */ 1377 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1378 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1379 wifi_bands[j].start = 0; 1380 wifi_bands[j].end = 0; 1381 } 1382 } 1383 } 1384 1385 /* Send the sorted wifi_bands to PMFW */ 1386 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1387 /* Try to set the wifi_bands again */ 1388 if (unlikely(ret == -EBUSY)) { 1389 mdelay(5); 1390 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1391 } 1392 1393 return ret; 1394 } 1395 1396 /** 1397 * smu_wbrf_event_handler - handle notify events 1398 * 1399 * @nb: notifier block 1400 * @action: event type 1401 * @_arg: event data 1402 * 1403 * Calls relevant amdgpu function in response to wbrf event 1404 * notification from kernel. 1405 */ 1406 static int smu_wbrf_event_handler(struct notifier_block *nb, 1407 unsigned long action, void *_arg) 1408 { 1409 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1410 1411 switch (action) { 1412 case WBRF_CHANGED: 1413 schedule_delayed_work(&smu->wbrf_delayed_work, 1414 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1415 break; 1416 default: 1417 return NOTIFY_DONE; 1418 } 1419 1420 return NOTIFY_OK; 1421 } 1422 1423 /** 1424 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1425 * 1426 * @work: struct work_struct pointer 1427 * 1428 * Flood is over and driver will consume the latest exclusion ranges. 1429 */ 1430 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1431 { 1432 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1433 1434 smu_wbrf_handle_exclusion_ranges(smu); 1435 } 1436 1437 /** 1438 * smu_wbrf_support_check - check wbrf support 1439 * 1440 * @smu: smu_context pointer 1441 * 1442 * Verifies the ACPI interface whether wbrf is supported. 1443 */ 1444 static void smu_wbrf_support_check(struct smu_context *smu) 1445 { 1446 struct amdgpu_device *adev = smu->adev; 1447 1448 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1449 acpi_amd_wbrf_supported_consumer(adev->dev); 1450 1451 if (smu->wbrf_supported) 1452 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1453 } 1454 1455 /** 1456 * smu_wbrf_init - init driver wbrf support 1457 * 1458 * @smu: smu_context pointer 1459 * 1460 * Verifies the AMD ACPI interfaces and registers with the wbrf 1461 * notifier chain if wbrf feature is supported. 1462 * Returns 0 on success, error on failure. 1463 */ 1464 static int smu_wbrf_init(struct smu_context *smu) 1465 { 1466 int ret; 1467 1468 if (!smu->wbrf_supported) 1469 return 0; 1470 1471 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1472 1473 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1474 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1475 if (ret) 1476 return ret; 1477 1478 /* 1479 * Some wifiband exclusion ranges may be already there 1480 * before our driver loaded. To make sure our driver 1481 * is awared of those exclusion ranges. 1482 */ 1483 schedule_delayed_work(&smu->wbrf_delayed_work, 1484 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1485 1486 return 0; 1487 } 1488 1489 /** 1490 * smu_wbrf_fini - tear down driver wbrf support 1491 * 1492 * @smu: smu_context pointer 1493 * 1494 * Unregisters with the wbrf notifier chain. 1495 */ 1496 static void smu_wbrf_fini(struct smu_context *smu) 1497 { 1498 if (!smu->wbrf_supported) 1499 return; 1500 1501 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1502 1503 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1504 } 1505 1506 static int smu_smc_hw_setup(struct smu_context *smu) 1507 { 1508 struct smu_feature *feature = &smu->smu_feature; 1509 struct amdgpu_device *adev = smu->adev; 1510 uint8_t pcie_gen = 0, pcie_width = 0; 1511 uint64_t features_supported; 1512 int ret = 0; 1513 1514 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1515 case IP_VERSION(11, 0, 7): 1516 case IP_VERSION(11, 0, 11): 1517 case IP_VERSION(11, 5, 0): 1518 case IP_VERSION(11, 0, 12): 1519 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1520 dev_info(adev->dev, "dpm has been enabled\n"); 1521 ret = smu_system_features_control(smu, true); 1522 if (ret) 1523 dev_err(adev->dev, "Failed system features control!\n"); 1524 return ret; 1525 } 1526 break; 1527 default: 1528 break; 1529 } 1530 1531 ret = smu_init_display_count(smu, 0); 1532 if (ret) { 1533 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1534 return ret; 1535 } 1536 1537 ret = smu_set_driver_table_location(smu); 1538 if (ret) { 1539 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1540 return ret; 1541 } 1542 1543 /* 1544 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1545 */ 1546 ret = smu_set_tool_table_location(smu); 1547 if (ret) { 1548 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1549 return ret; 1550 } 1551 1552 /* 1553 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1554 * pool location. 1555 */ 1556 ret = smu_notify_memory_pool_location(smu); 1557 if (ret) { 1558 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1559 return ret; 1560 } 1561 1562 /* 1563 * It is assumed the pptable used before runpm is same as 1564 * the one used afterwards. Thus, we can reuse the stored 1565 * copy and do not need to resetup the pptable again. 1566 */ 1567 if (!adev->in_runpm) { 1568 ret = smu_setup_pptable(smu); 1569 if (ret) { 1570 dev_err(adev->dev, "Failed to setup pptable!\n"); 1571 return ret; 1572 } 1573 } 1574 1575 /* smu_dump_pptable(smu); */ 1576 1577 /* 1578 * With SCPM enabled, PSP is responsible for the PPTable transferring 1579 * (to SMU). Driver involvement is not needed and permitted. 1580 */ 1581 if (!adev->scpm_enabled) { 1582 /* 1583 * Copy pptable bo in the vram to smc with SMU MSGs such as 1584 * SetDriverDramAddr and TransferTableDram2Smu. 1585 */ 1586 ret = smu_write_pptable(smu); 1587 if (ret) { 1588 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1589 return ret; 1590 } 1591 } 1592 1593 /* issue Run*Btc msg */ 1594 ret = smu_run_btc(smu); 1595 if (ret) 1596 return ret; 1597 1598 /* Enable UclkShadow on wbrf supported */ 1599 if (smu->wbrf_supported) { 1600 ret = smu_enable_uclk_shadow(smu, true); 1601 if (ret) { 1602 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1603 return ret; 1604 } 1605 } 1606 1607 /* 1608 * With SCPM enabled, these actions(and relevant messages) are 1609 * not needed and permitted. 1610 */ 1611 if (!adev->scpm_enabled) { 1612 ret = smu_feature_set_allowed_mask(smu); 1613 if (ret) { 1614 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1615 return ret; 1616 } 1617 } 1618 1619 ret = smu_system_features_control(smu, true); 1620 if (ret) { 1621 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1622 return ret; 1623 } 1624 1625 smu_init_xgmi_plpd_mode(smu); 1626 1627 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1628 if (ret) { 1629 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1630 return ret; 1631 } 1632 bitmap_copy(feature->supported, 1633 (unsigned long *)&features_supported, 1634 feature->feature_num); 1635 1636 if (!smu_is_dpm_running(smu)) 1637 dev_info(adev->dev, "dpm has been disabled\n"); 1638 1639 /* 1640 * Set initialized values (get from vbios) to dpm tables context such as 1641 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1642 * type of clks. 1643 */ 1644 ret = smu_set_default_dpm_table(smu); 1645 if (ret) { 1646 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1647 return ret; 1648 } 1649 1650 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1651 pcie_gen = 3; 1652 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1653 pcie_gen = 2; 1654 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1655 pcie_gen = 1; 1656 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1657 pcie_gen = 0; 1658 1659 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1660 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1661 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1662 */ 1663 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1664 pcie_width = 6; 1665 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1666 pcie_width = 5; 1667 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1668 pcie_width = 4; 1669 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1670 pcie_width = 3; 1671 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1672 pcie_width = 2; 1673 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1674 pcie_width = 1; 1675 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1676 if (ret) { 1677 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1678 return ret; 1679 } 1680 1681 ret = smu_get_thermal_temperature_range(smu); 1682 if (ret) { 1683 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1684 return ret; 1685 } 1686 1687 ret = smu_enable_thermal_alert(smu); 1688 if (ret) { 1689 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1690 return ret; 1691 } 1692 1693 ret = smu_notify_display_change(smu); 1694 if (ret) { 1695 dev_err(adev->dev, "Failed to notify display change!\n"); 1696 return ret; 1697 } 1698 1699 /* 1700 * Set min deep sleep dce fclk with bootup value from vbios via 1701 * SetMinDeepSleepDcefclk MSG. 1702 */ 1703 ret = smu_set_min_dcef_deep_sleep(smu, 1704 smu->smu_table.boot_values.dcefclk / 100); 1705 if (ret) { 1706 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1707 return ret; 1708 } 1709 1710 /* Init wbrf support. Properly setup the notifier */ 1711 ret = smu_wbrf_init(smu); 1712 if (ret) 1713 dev_err(adev->dev, "Error during wbrf init call\n"); 1714 1715 return ret; 1716 } 1717 1718 static int smu_start_smc_engine(struct smu_context *smu) 1719 { 1720 struct amdgpu_device *adev = smu->adev; 1721 int ret = 0; 1722 1723 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1724 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1725 if (smu->ppt_funcs->load_microcode) { 1726 ret = smu->ppt_funcs->load_microcode(smu); 1727 if (ret) 1728 return ret; 1729 } 1730 } 1731 } 1732 1733 if (smu->ppt_funcs->check_fw_status) { 1734 ret = smu->ppt_funcs->check_fw_status(smu); 1735 if (ret) { 1736 dev_err(adev->dev, "SMC is not ready\n"); 1737 return ret; 1738 } 1739 } 1740 1741 /* 1742 * Send msg GetDriverIfVersion to check if the return value is equal 1743 * with DRIVER_IF_VERSION of smc header. 1744 */ 1745 ret = smu_check_fw_version(smu); 1746 if (ret) 1747 return ret; 1748 1749 return ret; 1750 } 1751 1752 static int smu_hw_init(void *handle) 1753 { 1754 int ret; 1755 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1756 struct smu_context *smu = adev->powerplay.pp_handle; 1757 1758 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1759 smu->pm_enabled = false; 1760 return 0; 1761 } 1762 1763 ret = smu_start_smc_engine(smu); 1764 if (ret) { 1765 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1766 return ret; 1767 } 1768 1769 /* 1770 * Check whether wbrf is supported. This needs to be done 1771 * before SMU setup starts since part of SMU configuration 1772 * relies on this. 1773 */ 1774 smu_wbrf_support_check(smu); 1775 1776 if (smu->is_apu) { 1777 ret = smu_set_gfx_imu_enable(smu); 1778 if (ret) 1779 return ret; 1780 smu_dpm_set_vcn_enable(smu, true); 1781 smu_dpm_set_jpeg_enable(smu, true); 1782 smu_dpm_set_vpe_enable(smu, true); 1783 smu_dpm_set_umsch_mm_enable(smu, true); 1784 smu_set_gfx_cgpg(smu, true); 1785 } 1786 1787 if (!smu->pm_enabled) 1788 return 0; 1789 1790 ret = smu_get_driver_allowed_feature_mask(smu); 1791 if (ret) 1792 return ret; 1793 1794 ret = smu_smc_hw_setup(smu); 1795 if (ret) { 1796 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1797 return ret; 1798 } 1799 1800 /* 1801 * Move maximum sustainable clock retrieving here considering 1802 * 1. It is not needed on resume(from S3). 1803 * 2. DAL settings come between .hw_init and .late_init of SMU. 1804 * And DAL needs to know the maximum sustainable clocks. Thus 1805 * it cannot be put in .late_init(). 1806 */ 1807 ret = smu_init_max_sustainable_clocks(smu); 1808 if (ret) { 1809 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1810 return ret; 1811 } 1812 1813 adev->pm.dpm_enabled = true; 1814 1815 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1816 1817 return 0; 1818 } 1819 1820 static int smu_disable_dpms(struct smu_context *smu) 1821 { 1822 struct amdgpu_device *adev = smu->adev; 1823 int ret = 0; 1824 bool use_baco = !smu->is_apu && 1825 ((amdgpu_in_reset(adev) && 1826 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1827 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1828 1829 /* 1830 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1831 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1832 */ 1833 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1834 case IP_VERSION(13, 0, 0): 1835 case IP_VERSION(13, 0, 7): 1836 case IP_VERSION(13, 0, 10): 1837 return 0; 1838 default: 1839 break; 1840 } 1841 1842 /* 1843 * For custom pptable uploading, skip the DPM features 1844 * disable process on Navi1x ASICs. 1845 * - As the gfx related features are under control of 1846 * RLC on those ASICs. RLC reinitialization will be 1847 * needed to reenable them. That will cost much more 1848 * efforts. 1849 * 1850 * - SMU firmware can handle the DPM reenablement 1851 * properly. 1852 */ 1853 if (smu->uploading_custom_pp_table) { 1854 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1855 case IP_VERSION(11, 0, 0): 1856 case IP_VERSION(11, 0, 5): 1857 case IP_VERSION(11, 0, 9): 1858 case IP_VERSION(11, 0, 7): 1859 case IP_VERSION(11, 0, 11): 1860 case IP_VERSION(11, 5, 0): 1861 case IP_VERSION(11, 0, 12): 1862 case IP_VERSION(11, 0, 13): 1863 return 0; 1864 default: 1865 break; 1866 } 1867 } 1868 1869 /* 1870 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1871 * on BACO in. Driver involvement is unnecessary. 1872 */ 1873 if (use_baco) { 1874 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1875 case IP_VERSION(11, 0, 7): 1876 case IP_VERSION(11, 0, 0): 1877 case IP_VERSION(11, 0, 5): 1878 case IP_VERSION(11, 0, 9): 1879 case IP_VERSION(13, 0, 7): 1880 return 0; 1881 default: 1882 break; 1883 } 1884 } 1885 1886 /* 1887 * For SMU 13.0.4/11 and 14.0.0, PMFW will handle the features disablement properly 1888 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1889 */ 1890 if (amdgpu_in_reset(adev) || adev->in_s0ix) { 1891 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1892 case IP_VERSION(13, 0, 4): 1893 case IP_VERSION(13, 0, 11): 1894 case IP_VERSION(14, 0, 0): 1895 return 0; 1896 default: 1897 break; 1898 } 1899 } 1900 1901 /* 1902 * For gpu reset, runpm and hibernation through BACO, 1903 * BACO feature has to be kept enabled. 1904 */ 1905 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1906 ret = smu_disable_all_features_with_exception(smu, 1907 SMU_FEATURE_BACO_BIT); 1908 if (ret) 1909 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1910 } else { 1911 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1912 if (!adev->scpm_enabled) { 1913 ret = smu_system_features_control(smu, false); 1914 if (ret) 1915 dev_err(adev->dev, "Failed to disable smu features.\n"); 1916 } 1917 } 1918 1919 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1920 * otherwise SMU will hang while interacting with RLC if RLC is halted 1921 * this is a WA for Vangogh asic which fix the SMU hang issue. 1922 */ 1923 ret = smu_notify_rlc_state(smu, false); 1924 if (ret) { 1925 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1926 return ret; 1927 } 1928 1929 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1930 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1931 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1932 adev->gfx.rlc.funcs->stop(adev); 1933 1934 return ret; 1935 } 1936 1937 static int smu_smc_hw_cleanup(struct smu_context *smu) 1938 { 1939 struct amdgpu_device *adev = smu->adev; 1940 int ret = 0; 1941 1942 smu_wbrf_fini(smu); 1943 1944 cancel_work_sync(&smu->throttling_logging_work); 1945 cancel_work_sync(&smu->interrupt_work); 1946 1947 ret = smu_disable_thermal_alert(smu); 1948 if (ret) { 1949 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1950 return ret; 1951 } 1952 1953 cancel_delayed_work_sync(&smu->swctf_delayed_work); 1954 1955 ret = smu_disable_dpms(smu); 1956 if (ret) { 1957 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1958 return ret; 1959 } 1960 1961 return 0; 1962 } 1963 1964 static int smu_reset_mp1_state(struct smu_context *smu) 1965 { 1966 struct amdgpu_device *adev = smu->adev; 1967 int ret = 0; 1968 1969 if ((!adev->in_runpm) && (!adev->in_suspend) && 1970 (!amdgpu_in_reset(adev))) 1971 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1972 case IP_VERSION(13, 0, 0): 1973 case IP_VERSION(13, 0, 7): 1974 case IP_VERSION(13, 0, 10): 1975 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 1976 break; 1977 default: 1978 break; 1979 } 1980 1981 return ret; 1982 } 1983 1984 static int smu_hw_fini(void *handle) 1985 { 1986 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1987 struct smu_context *smu = adev->powerplay.pp_handle; 1988 int ret; 1989 1990 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 1991 return 0; 1992 1993 smu_dpm_set_vcn_enable(smu, false); 1994 smu_dpm_set_jpeg_enable(smu, false); 1995 smu_dpm_set_vpe_enable(smu, false); 1996 smu_dpm_set_umsch_mm_enable(smu, false); 1997 1998 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1999 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2000 2001 if (!smu->pm_enabled) 2002 return 0; 2003 2004 adev->pm.dpm_enabled = false; 2005 2006 ret = smu_smc_hw_cleanup(smu); 2007 if (ret) 2008 return ret; 2009 2010 ret = smu_reset_mp1_state(smu); 2011 if (ret) 2012 return ret; 2013 2014 return 0; 2015 } 2016 2017 static void smu_late_fini(void *handle) 2018 { 2019 struct amdgpu_device *adev = handle; 2020 struct smu_context *smu = adev->powerplay.pp_handle; 2021 2022 kfree(smu); 2023 } 2024 2025 static int smu_reset(struct smu_context *smu) 2026 { 2027 struct amdgpu_device *adev = smu->adev; 2028 int ret; 2029 2030 ret = smu_hw_fini(adev); 2031 if (ret) 2032 return ret; 2033 2034 ret = smu_hw_init(adev); 2035 if (ret) 2036 return ret; 2037 2038 ret = smu_late_init(adev); 2039 if (ret) 2040 return ret; 2041 2042 return 0; 2043 } 2044 2045 static int smu_suspend(void *handle) 2046 { 2047 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2048 struct smu_context *smu = adev->powerplay.pp_handle; 2049 int ret; 2050 uint64_t count; 2051 2052 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2053 return 0; 2054 2055 if (!smu->pm_enabled) 2056 return 0; 2057 2058 adev->pm.dpm_enabled = false; 2059 2060 ret = smu_smc_hw_cleanup(smu); 2061 if (ret) 2062 return ret; 2063 2064 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2065 2066 smu_set_gfx_cgpg(smu, false); 2067 2068 /* 2069 * pwfw resets entrycount when device is suspended, so we save the 2070 * last value to be used when we resume to keep it consistent 2071 */ 2072 ret = smu_get_entrycount_gfxoff(smu, &count); 2073 if (!ret) 2074 adev->gfx.gfx_off_entrycount = count; 2075 2076 return 0; 2077 } 2078 2079 static int smu_resume(void *handle) 2080 { 2081 int ret; 2082 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2083 struct smu_context *smu = adev->powerplay.pp_handle; 2084 2085 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2086 return 0; 2087 2088 if (!smu->pm_enabled) 2089 return 0; 2090 2091 dev_info(adev->dev, "SMU is resuming...\n"); 2092 2093 ret = smu_start_smc_engine(smu); 2094 if (ret) { 2095 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2096 return ret; 2097 } 2098 2099 ret = smu_smc_hw_setup(smu); 2100 if (ret) { 2101 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2102 return ret; 2103 } 2104 2105 ret = smu_set_gfx_imu_enable(smu); 2106 if (ret) 2107 return ret; 2108 2109 smu_set_gfx_cgpg(smu, true); 2110 2111 smu->disable_uclk_switch = 0; 2112 2113 adev->pm.dpm_enabled = true; 2114 2115 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2116 2117 return 0; 2118 } 2119 2120 static int smu_display_configuration_change(void *handle, 2121 const struct amd_pp_display_configuration *display_config) 2122 { 2123 struct smu_context *smu = handle; 2124 2125 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2126 return -EOPNOTSUPP; 2127 2128 if (!display_config) 2129 return -EINVAL; 2130 2131 smu_set_min_dcef_deep_sleep(smu, 2132 display_config->min_dcef_deep_sleep_set_clk / 100); 2133 2134 return 0; 2135 } 2136 2137 static int smu_set_clockgating_state(void *handle, 2138 enum amd_clockgating_state state) 2139 { 2140 return 0; 2141 } 2142 2143 static int smu_set_powergating_state(void *handle, 2144 enum amd_powergating_state state) 2145 { 2146 return 0; 2147 } 2148 2149 static int smu_enable_umd_pstate(void *handle, 2150 enum amd_dpm_forced_level *level) 2151 { 2152 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2153 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2154 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2155 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2156 2157 struct smu_context *smu = (struct smu_context*)(handle); 2158 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2159 2160 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2161 return -EINVAL; 2162 2163 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2164 /* enter umd pstate, save current level, disable gfx cg*/ 2165 if (*level & profile_mode_mask) { 2166 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2167 smu_gpo_control(smu, false); 2168 smu_gfx_ulv_control(smu, false); 2169 smu_deep_sleep_control(smu, false); 2170 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2171 } 2172 } else { 2173 /* exit umd pstate, restore level, enable gfx cg*/ 2174 if (!(*level & profile_mode_mask)) { 2175 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2176 *level = smu_dpm_ctx->saved_dpm_level; 2177 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2178 smu_deep_sleep_control(smu, true); 2179 smu_gfx_ulv_control(smu, true); 2180 smu_gpo_control(smu, true); 2181 } 2182 } 2183 2184 return 0; 2185 } 2186 2187 static int smu_bump_power_profile_mode(struct smu_context *smu, 2188 long *param, 2189 uint32_t param_size) 2190 { 2191 int ret = 0; 2192 2193 if (smu->ppt_funcs->set_power_profile_mode) 2194 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2195 2196 return ret; 2197 } 2198 2199 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2200 enum amd_dpm_forced_level level, 2201 bool skip_display_settings) 2202 { 2203 int ret = 0; 2204 int index = 0; 2205 long workload; 2206 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2207 2208 if (!skip_display_settings) { 2209 ret = smu_display_config_changed(smu); 2210 if (ret) { 2211 dev_err(smu->adev->dev, "Failed to change display config!"); 2212 return ret; 2213 } 2214 } 2215 2216 ret = smu_apply_clocks_adjust_rules(smu); 2217 if (ret) { 2218 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2219 return ret; 2220 } 2221 2222 if (!skip_display_settings) { 2223 ret = smu_notify_smc_display_config(smu); 2224 if (ret) { 2225 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2226 return ret; 2227 } 2228 } 2229 2230 if (smu_dpm_ctx->dpm_level != level) { 2231 ret = smu_asic_set_performance_level(smu, level); 2232 if (ret) { 2233 dev_err(smu->adev->dev, "Failed to set performance level!"); 2234 return ret; 2235 } 2236 2237 /* update the saved copy */ 2238 smu_dpm_ctx->dpm_level = level; 2239 } 2240 2241 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2242 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2243 index = fls(smu->workload_mask); 2244 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2245 workload = smu->workload_setting[index]; 2246 2247 if (smu->power_profile_mode != workload) 2248 smu_bump_power_profile_mode(smu, &workload, 0); 2249 } 2250 2251 return ret; 2252 } 2253 2254 static int smu_handle_task(struct smu_context *smu, 2255 enum amd_dpm_forced_level level, 2256 enum amd_pp_task task_id) 2257 { 2258 int ret = 0; 2259 2260 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2261 return -EOPNOTSUPP; 2262 2263 switch (task_id) { 2264 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2265 ret = smu_pre_display_config_changed(smu); 2266 if (ret) 2267 return ret; 2268 ret = smu_adjust_power_state_dynamic(smu, level, false); 2269 break; 2270 case AMD_PP_TASK_COMPLETE_INIT: 2271 case AMD_PP_TASK_READJUST_POWER_STATE: 2272 ret = smu_adjust_power_state_dynamic(smu, level, true); 2273 break; 2274 default: 2275 break; 2276 } 2277 2278 return ret; 2279 } 2280 2281 static int smu_handle_dpm_task(void *handle, 2282 enum amd_pp_task task_id, 2283 enum amd_pm_state_type *user_state) 2284 { 2285 struct smu_context *smu = handle; 2286 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2287 2288 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2289 2290 } 2291 2292 static int smu_switch_power_profile(void *handle, 2293 enum PP_SMC_POWER_PROFILE type, 2294 bool en) 2295 { 2296 struct smu_context *smu = handle; 2297 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2298 long workload; 2299 uint32_t index; 2300 2301 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2302 return -EOPNOTSUPP; 2303 2304 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2305 return -EINVAL; 2306 2307 if (!en) { 2308 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 2309 index = fls(smu->workload_mask); 2310 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2311 workload = smu->workload_setting[index]; 2312 } else { 2313 smu->workload_mask |= (1 << smu->workload_prority[type]); 2314 index = fls(smu->workload_mask); 2315 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2316 workload = smu->workload_setting[index]; 2317 } 2318 2319 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2320 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2321 smu_bump_power_profile_mode(smu, &workload, 0); 2322 2323 return 0; 2324 } 2325 2326 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2327 { 2328 struct smu_context *smu = handle; 2329 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2330 2331 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2332 return -EOPNOTSUPP; 2333 2334 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2335 return -EINVAL; 2336 2337 return smu_dpm_ctx->dpm_level; 2338 } 2339 2340 static int smu_force_performance_level(void *handle, 2341 enum amd_dpm_forced_level level) 2342 { 2343 struct smu_context *smu = handle; 2344 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2345 int ret = 0; 2346 2347 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2348 return -EOPNOTSUPP; 2349 2350 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2351 return -EINVAL; 2352 2353 ret = smu_enable_umd_pstate(smu, &level); 2354 if (ret) 2355 return ret; 2356 2357 ret = smu_handle_task(smu, level, 2358 AMD_PP_TASK_READJUST_POWER_STATE); 2359 2360 /* reset user dpm clock state */ 2361 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2362 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2363 smu->user_dpm_profile.clk_dependency = 0; 2364 } 2365 2366 return ret; 2367 } 2368 2369 static int smu_set_display_count(void *handle, uint32_t count) 2370 { 2371 struct smu_context *smu = handle; 2372 2373 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2374 return -EOPNOTSUPP; 2375 2376 return smu_init_display_count(smu, count); 2377 } 2378 2379 static int smu_force_smuclk_levels(struct smu_context *smu, 2380 enum smu_clk_type clk_type, 2381 uint32_t mask) 2382 { 2383 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2384 int ret = 0; 2385 2386 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2387 return -EOPNOTSUPP; 2388 2389 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2390 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2391 return -EINVAL; 2392 } 2393 2394 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2395 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2396 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2397 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2398 smu_set_user_clk_dependencies(smu, clk_type); 2399 } 2400 } 2401 2402 return ret; 2403 } 2404 2405 static int smu_force_ppclk_levels(void *handle, 2406 enum pp_clock_type type, 2407 uint32_t mask) 2408 { 2409 struct smu_context *smu = handle; 2410 enum smu_clk_type clk_type; 2411 2412 switch (type) { 2413 case PP_SCLK: 2414 clk_type = SMU_SCLK; break; 2415 case PP_MCLK: 2416 clk_type = SMU_MCLK; break; 2417 case PP_PCIE: 2418 clk_type = SMU_PCIE; break; 2419 case PP_SOCCLK: 2420 clk_type = SMU_SOCCLK; break; 2421 case PP_FCLK: 2422 clk_type = SMU_FCLK; break; 2423 case PP_DCEFCLK: 2424 clk_type = SMU_DCEFCLK; break; 2425 case PP_VCLK: 2426 clk_type = SMU_VCLK; break; 2427 case PP_VCLK1: 2428 clk_type = SMU_VCLK1; break; 2429 case PP_DCLK: 2430 clk_type = SMU_DCLK; break; 2431 case PP_DCLK1: 2432 clk_type = SMU_DCLK1; break; 2433 case OD_SCLK: 2434 clk_type = SMU_OD_SCLK; break; 2435 case OD_MCLK: 2436 clk_type = SMU_OD_MCLK; break; 2437 case OD_VDDC_CURVE: 2438 clk_type = SMU_OD_VDDC_CURVE; break; 2439 case OD_RANGE: 2440 clk_type = SMU_OD_RANGE; break; 2441 default: 2442 return -EINVAL; 2443 } 2444 2445 return smu_force_smuclk_levels(smu, clk_type, mask); 2446 } 2447 2448 /* 2449 * On system suspending or resetting, the dpm_enabled 2450 * flag will be cleared. So that those SMU services which 2451 * are not supported will be gated. 2452 * However, the mp1 state setting should still be granted 2453 * even if the dpm_enabled cleared. 2454 */ 2455 static int smu_set_mp1_state(void *handle, 2456 enum pp_mp1_state mp1_state) 2457 { 2458 struct smu_context *smu = handle; 2459 int ret = 0; 2460 2461 if (!smu->pm_enabled) 2462 return -EOPNOTSUPP; 2463 2464 if (smu->ppt_funcs && 2465 smu->ppt_funcs->set_mp1_state) 2466 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2467 2468 return ret; 2469 } 2470 2471 static int smu_set_df_cstate(void *handle, 2472 enum pp_df_cstate state) 2473 { 2474 struct smu_context *smu = handle; 2475 int ret = 0; 2476 2477 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2478 return -EOPNOTSUPP; 2479 2480 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2481 return 0; 2482 2483 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2484 if (ret) 2485 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2486 2487 return ret; 2488 } 2489 2490 int smu_write_watermarks_table(struct smu_context *smu) 2491 { 2492 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2493 return -EOPNOTSUPP; 2494 2495 return smu_set_watermarks_table(smu, NULL); 2496 } 2497 2498 static int smu_set_watermarks_for_clock_ranges(void *handle, 2499 struct pp_smu_wm_range_sets *clock_ranges) 2500 { 2501 struct smu_context *smu = handle; 2502 2503 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2504 return -EOPNOTSUPP; 2505 2506 if (smu->disable_watermark) 2507 return 0; 2508 2509 return smu_set_watermarks_table(smu, clock_ranges); 2510 } 2511 2512 int smu_set_ac_dc(struct smu_context *smu) 2513 { 2514 int ret = 0; 2515 2516 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2517 return -EOPNOTSUPP; 2518 2519 /* controlled by firmware */ 2520 if (smu->dc_controlled_by_gpio) 2521 return 0; 2522 2523 ret = smu_set_power_source(smu, 2524 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2525 SMU_POWER_SOURCE_DC); 2526 if (ret) 2527 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2528 smu->adev->pm.ac_power ? "AC" : "DC"); 2529 2530 return ret; 2531 } 2532 2533 const struct amd_ip_funcs smu_ip_funcs = { 2534 .name = "smu", 2535 .early_init = smu_early_init, 2536 .late_init = smu_late_init, 2537 .sw_init = smu_sw_init, 2538 .sw_fini = smu_sw_fini, 2539 .hw_init = smu_hw_init, 2540 .hw_fini = smu_hw_fini, 2541 .late_fini = smu_late_fini, 2542 .suspend = smu_suspend, 2543 .resume = smu_resume, 2544 .is_idle = NULL, 2545 .check_soft_reset = NULL, 2546 .wait_for_idle = NULL, 2547 .soft_reset = NULL, 2548 .set_clockgating_state = smu_set_clockgating_state, 2549 .set_powergating_state = smu_set_powergating_state, 2550 }; 2551 2552 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2553 .type = AMD_IP_BLOCK_TYPE_SMC, 2554 .major = 11, 2555 .minor = 0, 2556 .rev = 0, 2557 .funcs = &smu_ip_funcs, 2558 }; 2559 2560 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2561 .type = AMD_IP_BLOCK_TYPE_SMC, 2562 .major = 12, 2563 .minor = 0, 2564 .rev = 0, 2565 .funcs = &smu_ip_funcs, 2566 }; 2567 2568 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2569 .type = AMD_IP_BLOCK_TYPE_SMC, 2570 .major = 13, 2571 .minor = 0, 2572 .rev = 0, 2573 .funcs = &smu_ip_funcs, 2574 }; 2575 2576 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2577 .type = AMD_IP_BLOCK_TYPE_SMC, 2578 .major = 14, 2579 .minor = 0, 2580 .rev = 0, 2581 .funcs = &smu_ip_funcs, 2582 }; 2583 2584 static int smu_load_microcode(void *handle) 2585 { 2586 struct smu_context *smu = handle; 2587 struct amdgpu_device *adev = smu->adev; 2588 int ret = 0; 2589 2590 if (!smu->pm_enabled) 2591 return -EOPNOTSUPP; 2592 2593 /* This should be used for non PSP loading */ 2594 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2595 return 0; 2596 2597 if (smu->ppt_funcs->load_microcode) { 2598 ret = smu->ppt_funcs->load_microcode(smu); 2599 if (ret) { 2600 dev_err(adev->dev, "Load microcode failed\n"); 2601 return ret; 2602 } 2603 } 2604 2605 if (smu->ppt_funcs->check_fw_status) { 2606 ret = smu->ppt_funcs->check_fw_status(smu); 2607 if (ret) { 2608 dev_err(adev->dev, "SMC is not ready\n"); 2609 return ret; 2610 } 2611 } 2612 2613 return ret; 2614 } 2615 2616 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2617 { 2618 int ret = 0; 2619 2620 if (smu->ppt_funcs->set_gfx_cgpg) 2621 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2622 2623 return ret; 2624 } 2625 2626 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2627 { 2628 struct smu_context *smu = handle; 2629 int ret = 0; 2630 2631 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2632 return -EOPNOTSUPP; 2633 2634 if (!smu->ppt_funcs->set_fan_speed_rpm) 2635 return -EOPNOTSUPP; 2636 2637 if (speed == U32_MAX) 2638 return -EINVAL; 2639 2640 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2641 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2642 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2643 smu->user_dpm_profile.fan_speed_rpm = speed; 2644 2645 /* Override custom PWM setting as they cannot co-exist */ 2646 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2647 smu->user_dpm_profile.fan_speed_pwm = 0; 2648 } 2649 2650 return ret; 2651 } 2652 2653 /** 2654 * smu_get_power_limit - Request one of the SMU Power Limits 2655 * 2656 * @handle: pointer to smu context 2657 * @limit: requested limit is written back to this variable 2658 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2659 * @pp_power_type: &pp_power_type type of power 2660 * Return: 0 on success, <0 on error 2661 * 2662 */ 2663 int smu_get_power_limit(void *handle, 2664 uint32_t *limit, 2665 enum pp_power_limit_level pp_limit_level, 2666 enum pp_power_type pp_power_type) 2667 { 2668 struct smu_context *smu = handle; 2669 struct amdgpu_device *adev = smu->adev; 2670 enum smu_ppt_limit_level limit_level; 2671 uint32_t limit_type; 2672 int ret = 0; 2673 2674 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2675 return -EOPNOTSUPP; 2676 2677 switch (pp_power_type) { 2678 case PP_PWR_TYPE_SUSTAINED: 2679 limit_type = SMU_DEFAULT_PPT_LIMIT; 2680 break; 2681 case PP_PWR_TYPE_FAST: 2682 limit_type = SMU_FAST_PPT_LIMIT; 2683 break; 2684 default: 2685 return -EOPNOTSUPP; 2686 } 2687 2688 switch (pp_limit_level) { 2689 case PP_PWR_LIMIT_CURRENT: 2690 limit_level = SMU_PPT_LIMIT_CURRENT; 2691 break; 2692 case PP_PWR_LIMIT_DEFAULT: 2693 limit_level = SMU_PPT_LIMIT_DEFAULT; 2694 break; 2695 case PP_PWR_LIMIT_MAX: 2696 limit_level = SMU_PPT_LIMIT_MAX; 2697 break; 2698 case PP_PWR_LIMIT_MIN: 2699 limit_level = SMU_PPT_LIMIT_MIN; 2700 break; 2701 default: 2702 return -EOPNOTSUPP; 2703 } 2704 2705 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2706 if (smu->ppt_funcs->get_ppt_limit) 2707 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2708 } else { 2709 switch (limit_level) { 2710 case SMU_PPT_LIMIT_CURRENT: 2711 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2712 case IP_VERSION(13, 0, 2): 2713 case IP_VERSION(11, 0, 7): 2714 case IP_VERSION(11, 0, 11): 2715 case IP_VERSION(11, 0, 12): 2716 case IP_VERSION(11, 0, 13): 2717 ret = smu_get_asic_power_limits(smu, 2718 &smu->current_power_limit, 2719 NULL, NULL, NULL); 2720 break; 2721 default: 2722 break; 2723 } 2724 *limit = smu->current_power_limit; 2725 break; 2726 case SMU_PPT_LIMIT_DEFAULT: 2727 *limit = smu->default_power_limit; 2728 break; 2729 case SMU_PPT_LIMIT_MAX: 2730 *limit = smu->max_power_limit; 2731 break; 2732 case SMU_PPT_LIMIT_MIN: 2733 *limit = smu->min_power_limit; 2734 break; 2735 default: 2736 return -EINVAL; 2737 } 2738 } 2739 2740 return ret; 2741 } 2742 2743 static int smu_set_power_limit(void *handle, uint32_t limit) 2744 { 2745 struct smu_context *smu = handle; 2746 uint32_t limit_type = limit >> 24; 2747 int ret = 0; 2748 2749 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2750 return -EOPNOTSUPP; 2751 2752 limit &= (1<<24)-1; 2753 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2754 if (smu->ppt_funcs->set_power_limit) 2755 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2756 2757 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2758 dev_err(smu->adev->dev, 2759 "New power limit (%d) is out of range [%d,%d]\n", 2760 limit, smu->min_power_limit, smu->max_power_limit); 2761 return -EINVAL; 2762 } 2763 2764 if (!limit) 2765 limit = smu->current_power_limit; 2766 2767 if (smu->ppt_funcs->set_power_limit) { 2768 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2769 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2770 smu->user_dpm_profile.power_limit = limit; 2771 } 2772 2773 return ret; 2774 } 2775 2776 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2777 { 2778 int ret = 0; 2779 2780 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2781 return -EOPNOTSUPP; 2782 2783 if (smu->ppt_funcs->print_clk_levels) 2784 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2785 2786 return ret; 2787 } 2788 2789 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2790 { 2791 enum smu_clk_type clk_type; 2792 2793 switch (type) { 2794 case PP_SCLK: 2795 clk_type = SMU_SCLK; break; 2796 case PP_MCLK: 2797 clk_type = SMU_MCLK; break; 2798 case PP_PCIE: 2799 clk_type = SMU_PCIE; break; 2800 case PP_SOCCLK: 2801 clk_type = SMU_SOCCLK; break; 2802 case PP_FCLK: 2803 clk_type = SMU_FCLK; break; 2804 case PP_DCEFCLK: 2805 clk_type = SMU_DCEFCLK; break; 2806 case PP_VCLK: 2807 clk_type = SMU_VCLK; break; 2808 case PP_VCLK1: 2809 clk_type = SMU_VCLK1; break; 2810 case PP_DCLK: 2811 clk_type = SMU_DCLK; break; 2812 case PP_DCLK1: 2813 clk_type = SMU_DCLK1; break; 2814 case OD_SCLK: 2815 clk_type = SMU_OD_SCLK; break; 2816 case OD_MCLK: 2817 clk_type = SMU_OD_MCLK; break; 2818 case OD_VDDC_CURVE: 2819 clk_type = SMU_OD_VDDC_CURVE; break; 2820 case OD_RANGE: 2821 clk_type = SMU_OD_RANGE; break; 2822 case OD_VDDGFX_OFFSET: 2823 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2824 case OD_CCLK: 2825 clk_type = SMU_OD_CCLK; break; 2826 case OD_FAN_CURVE: 2827 clk_type = SMU_OD_FAN_CURVE; break; 2828 case OD_ACOUSTIC_LIMIT: 2829 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2830 case OD_ACOUSTIC_TARGET: 2831 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2832 case OD_FAN_TARGET_TEMPERATURE: 2833 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2834 case OD_FAN_MINIMUM_PWM: 2835 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2836 default: 2837 clk_type = SMU_CLK_COUNT; break; 2838 } 2839 2840 return clk_type; 2841 } 2842 2843 static int smu_print_ppclk_levels(void *handle, 2844 enum pp_clock_type type, 2845 char *buf) 2846 { 2847 struct smu_context *smu = handle; 2848 enum smu_clk_type clk_type; 2849 2850 clk_type = smu_convert_to_smuclk(type); 2851 if (clk_type == SMU_CLK_COUNT) 2852 return -EINVAL; 2853 2854 return smu_print_smuclk_levels(smu, clk_type, buf); 2855 } 2856 2857 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2858 { 2859 struct smu_context *smu = handle; 2860 enum smu_clk_type clk_type; 2861 2862 clk_type = smu_convert_to_smuclk(type); 2863 if (clk_type == SMU_CLK_COUNT) 2864 return -EINVAL; 2865 2866 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2867 return -EOPNOTSUPP; 2868 2869 if (!smu->ppt_funcs->emit_clk_levels) 2870 return -ENOENT; 2871 2872 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2873 2874 } 2875 2876 static int smu_od_edit_dpm_table(void *handle, 2877 enum PP_OD_DPM_TABLE_COMMAND type, 2878 long *input, uint32_t size) 2879 { 2880 struct smu_context *smu = handle; 2881 int ret = 0; 2882 2883 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2884 return -EOPNOTSUPP; 2885 2886 if (smu->ppt_funcs->od_edit_dpm_table) { 2887 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2888 } 2889 2890 return ret; 2891 } 2892 2893 static int smu_read_sensor(void *handle, 2894 int sensor, 2895 void *data, 2896 int *size_arg) 2897 { 2898 struct smu_context *smu = handle; 2899 struct smu_umd_pstate_table *pstate_table = 2900 &smu->pstate_table; 2901 int ret = 0; 2902 uint32_t *size, size_val; 2903 2904 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2905 return -EOPNOTSUPP; 2906 2907 if (!data || !size_arg) 2908 return -EINVAL; 2909 2910 size_val = *size_arg; 2911 size = &size_val; 2912 2913 if (smu->ppt_funcs->read_sensor) 2914 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2915 goto unlock; 2916 2917 switch (sensor) { 2918 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2919 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2920 *size = 4; 2921 break; 2922 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2923 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2924 *size = 4; 2925 break; 2926 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2927 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2928 *size = 4; 2929 break; 2930 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2931 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2932 *size = 4; 2933 break; 2934 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2935 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2936 *size = 8; 2937 break; 2938 case AMDGPU_PP_SENSOR_UVD_POWER: 2939 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2940 *size = 4; 2941 break; 2942 case AMDGPU_PP_SENSOR_VCE_POWER: 2943 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2944 *size = 4; 2945 break; 2946 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2947 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 2948 *size = 4; 2949 break; 2950 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2951 *(uint32_t *)data = 0; 2952 *size = 4; 2953 break; 2954 default: 2955 *size = 0; 2956 ret = -EOPNOTSUPP; 2957 break; 2958 } 2959 2960 unlock: 2961 // assign uint32_t to int 2962 *size_arg = size_val; 2963 2964 return ret; 2965 } 2966 2967 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 2968 { 2969 int ret = -EOPNOTSUPP; 2970 struct smu_context *smu = handle; 2971 2972 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 2973 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 2974 2975 return ret; 2976 } 2977 2978 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 2979 { 2980 int ret = -EOPNOTSUPP; 2981 struct smu_context *smu = handle; 2982 2983 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 2984 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 2985 2986 return ret; 2987 } 2988 2989 static int smu_get_power_profile_mode(void *handle, char *buf) 2990 { 2991 struct smu_context *smu = handle; 2992 2993 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2994 !smu->ppt_funcs->get_power_profile_mode) 2995 return -EOPNOTSUPP; 2996 if (!buf) 2997 return -EINVAL; 2998 2999 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3000 } 3001 3002 static int smu_set_power_profile_mode(void *handle, 3003 long *param, 3004 uint32_t param_size) 3005 { 3006 struct smu_context *smu = handle; 3007 3008 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3009 !smu->ppt_funcs->set_power_profile_mode) 3010 return -EOPNOTSUPP; 3011 3012 return smu_bump_power_profile_mode(smu, param, param_size); 3013 } 3014 3015 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3016 { 3017 struct smu_context *smu = handle; 3018 3019 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3020 return -EOPNOTSUPP; 3021 3022 if (!smu->ppt_funcs->get_fan_control_mode) 3023 return -EOPNOTSUPP; 3024 3025 if (!fan_mode) 3026 return -EINVAL; 3027 3028 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3029 3030 return 0; 3031 } 3032 3033 static int smu_set_fan_control_mode(void *handle, u32 value) 3034 { 3035 struct smu_context *smu = handle; 3036 int ret = 0; 3037 3038 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3039 return -EOPNOTSUPP; 3040 3041 if (!smu->ppt_funcs->set_fan_control_mode) 3042 return -EOPNOTSUPP; 3043 3044 if (value == U32_MAX) 3045 return -EINVAL; 3046 3047 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3048 if (ret) 3049 goto out; 3050 3051 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3052 smu->user_dpm_profile.fan_mode = value; 3053 3054 /* reset user dpm fan speed */ 3055 if (value != AMD_FAN_CTRL_MANUAL) { 3056 smu->user_dpm_profile.fan_speed_pwm = 0; 3057 smu->user_dpm_profile.fan_speed_rpm = 0; 3058 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3059 } 3060 } 3061 3062 out: 3063 return ret; 3064 } 3065 3066 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3067 { 3068 struct smu_context *smu = handle; 3069 int ret = 0; 3070 3071 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3072 return -EOPNOTSUPP; 3073 3074 if (!smu->ppt_funcs->get_fan_speed_pwm) 3075 return -EOPNOTSUPP; 3076 3077 if (!speed) 3078 return -EINVAL; 3079 3080 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3081 3082 return ret; 3083 } 3084 3085 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3086 { 3087 struct smu_context *smu = handle; 3088 int ret = 0; 3089 3090 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3091 return -EOPNOTSUPP; 3092 3093 if (!smu->ppt_funcs->set_fan_speed_pwm) 3094 return -EOPNOTSUPP; 3095 3096 if (speed == U32_MAX) 3097 return -EINVAL; 3098 3099 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3100 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3101 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3102 smu->user_dpm_profile.fan_speed_pwm = speed; 3103 3104 /* Override custom RPM setting as they cannot co-exist */ 3105 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3106 smu->user_dpm_profile.fan_speed_rpm = 0; 3107 } 3108 3109 return ret; 3110 } 3111 3112 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3113 { 3114 struct smu_context *smu = handle; 3115 int ret = 0; 3116 3117 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3118 return -EOPNOTSUPP; 3119 3120 if (!smu->ppt_funcs->get_fan_speed_rpm) 3121 return -EOPNOTSUPP; 3122 3123 if (!speed) 3124 return -EINVAL; 3125 3126 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3127 3128 return ret; 3129 } 3130 3131 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3132 { 3133 struct smu_context *smu = handle; 3134 3135 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3136 return -EOPNOTSUPP; 3137 3138 return smu_set_min_dcef_deep_sleep(smu, clk); 3139 } 3140 3141 static int smu_get_clock_by_type_with_latency(void *handle, 3142 enum amd_pp_clock_type type, 3143 struct pp_clock_levels_with_latency *clocks) 3144 { 3145 struct smu_context *smu = handle; 3146 enum smu_clk_type clk_type; 3147 int ret = 0; 3148 3149 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3150 return -EOPNOTSUPP; 3151 3152 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3153 switch (type) { 3154 case amd_pp_sys_clock: 3155 clk_type = SMU_GFXCLK; 3156 break; 3157 case amd_pp_mem_clock: 3158 clk_type = SMU_MCLK; 3159 break; 3160 case amd_pp_dcef_clock: 3161 clk_type = SMU_DCEFCLK; 3162 break; 3163 case amd_pp_disp_clock: 3164 clk_type = SMU_DISPCLK; 3165 break; 3166 default: 3167 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3168 return -EINVAL; 3169 } 3170 3171 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3172 } 3173 3174 return ret; 3175 } 3176 3177 static int smu_display_clock_voltage_request(void *handle, 3178 struct pp_display_clock_request *clock_req) 3179 { 3180 struct smu_context *smu = handle; 3181 int ret = 0; 3182 3183 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3184 return -EOPNOTSUPP; 3185 3186 if (smu->ppt_funcs->display_clock_voltage_request) 3187 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3188 3189 return ret; 3190 } 3191 3192 3193 static int smu_display_disable_memory_clock_switch(void *handle, 3194 bool disable_memory_clock_switch) 3195 { 3196 struct smu_context *smu = handle; 3197 int ret = -EINVAL; 3198 3199 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3200 return -EOPNOTSUPP; 3201 3202 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3203 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3204 3205 return ret; 3206 } 3207 3208 static int smu_set_xgmi_pstate(void *handle, 3209 uint32_t pstate) 3210 { 3211 struct smu_context *smu = handle; 3212 int ret = 0; 3213 3214 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3215 return -EOPNOTSUPP; 3216 3217 if (smu->ppt_funcs->set_xgmi_pstate) 3218 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3219 3220 if (ret) 3221 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3222 3223 return ret; 3224 } 3225 3226 static bool smu_get_baco_capability(void *handle) 3227 { 3228 struct smu_context *smu = handle; 3229 3230 if (!smu->pm_enabled) 3231 return false; 3232 3233 if (!smu->ppt_funcs || !smu->ppt_funcs->baco_is_support) 3234 return false; 3235 3236 return smu->ppt_funcs->baco_is_support(smu); 3237 } 3238 3239 static int smu_baco_set_state(void *handle, int state) 3240 { 3241 struct smu_context *smu = handle; 3242 int ret = 0; 3243 3244 if (!smu->pm_enabled) 3245 return -EOPNOTSUPP; 3246 3247 if (state == 0) { 3248 if (smu->ppt_funcs->baco_exit) 3249 ret = smu->ppt_funcs->baco_exit(smu); 3250 } else if (state == 1) { 3251 if (smu->ppt_funcs->baco_enter) 3252 ret = smu->ppt_funcs->baco_enter(smu); 3253 } else { 3254 return -EINVAL; 3255 } 3256 3257 if (ret) 3258 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3259 (state)?"enter":"exit"); 3260 3261 return ret; 3262 } 3263 3264 bool smu_mode1_reset_is_support(struct smu_context *smu) 3265 { 3266 bool ret = false; 3267 3268 if (!smu->pm_enabled) 3269 return false; 3270 3271 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3272 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3273 3274 return ret; 3275 } 3276 3277 bool smu_mode2_reset_is_support(struct smu_context *smu) 3278 { 3279 bool ret = false; 3280 3281 if (!smu->pm_enabled) 3282 return false; 3283 3284 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3285 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3286 3287 return ret; 3288 } 3289 3290 int smu_mode1_reset(struct smu_context *smu) 3291 { 3292 int ret = 0; 3293 3294 if (!smu->pm_enabled) 3295 return -EOPNOTSUPP; 3296 3297 if (smu->ppt_funcs->mode1_reset) 3298 ret = smu->ppt_funcs->mode1_reset(smu); 3299 3300 return ret; 3301 } 3302 3303 static int smu_mode2_reset(void *handle) 3304 { 3305 struct smu_context *smu = handle; 3306 int ret = 0; 3307 3308 if (!smu->pm_enabled) 3309 return -EOPNOTSUPP; 3310 3311 if (smu->ppt_funcs->mode2_reset) 3312 ret = smu->ppt_funcs->mode2_reset(smu); 3313 3314 if (ret) 3315 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3316 3317 return ret; 3318 } 3319 3320 static int smu_enable_gfx_features(void *handle) 3321 { 3322 struct smu_context *smu = handle; 3323 int ret = 0; 3324 3325 if (!smu->pm_enabled) 3326 return -EOPNOTSUPP; 3327 3328 if (smu->ppt_funcs->enable_gfx_features) 3329 ret = smu->ppt_funcs->enable_gfx_features(smu); 3330 3331 if (ret) 3332 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3333 3334 return ret; 3335 } 3336 3337 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3338 struct pp_smu_nv_clock_table *max_clocks) 3339 { 3340 struct smu_context *smu = handle; 3341 int ret = 0; 3342 3343 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3344 return -EOPNOTSUPP; 3345 3346 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3347 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3348 3349 return ret; 3350 } 3351 3352 static int smu_get_uclk_dpm_states(void *handle, 3353 unsigned int *clock_values_in_khz, 3354 unsigned int *num_states) 3355 { 3356 struct smu_context *smu = handle; 3357 int ret = 0; 3358 3359 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3360 return -EOPNOTSUPP; 3361 3362 if (smu->ppt_funcs->get_uclk_dpm_states) 3363 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3364 3365 return ret; 3366 } 3367 3368 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3369 { 3370 struct smu_context *smu = handle; 3371 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3372 3373 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3374 return -EOPNOTSUPP; 3375 3376 if (smu->ppt_funcs->get_current_power_state) 3377 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3378 3379 return pm_state; 3380 } 3381 3382 static int smu_get_dpm_clock_table(void *handle, 3383 struct dpm_clocks *clock_table) 3384 { 3385 struct smu_context *smu = handle; 3386 int ret = 0; 3387 3388 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3389 return -EOPNOTSUPP; 3390 3391 if (smu->ppt_funcs->get_dpm_clock_table) 3392 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3393 3394 return ret; 3395 } 3396 3397 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3398 { 3399 struct smu_context *smu = handle; 3400 3401 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3402 return -EOPNOTSUPP; 3403 3404 if (!smu->ppt_funcs->get_gpu_metrics) 3405 return -EOPNOTSUPP; 3406 3407 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3408 } 3409 3410 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3411 size_t size) 3412 { 3413 struct smu_context *smu = handle; 3414 3415 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3416 return -EOPNOTSUPP; 3417 3418 if (!smu->ppt_funcs->get_pm_metrics) 3419 return -EOPNOTSUPP; 3420 3421 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3422 } 3423 3424 static int smu_enable_mgpu_fan_boost(void *handle) 3425 { 3426 struct smu_context *smu = handle; 3427 int ret = 0; 3428 3429 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3430 return -EOPNOTSUPP; 3431 3432 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3433 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3434 3435 return ret; 3436 } 3437 3438 static int smu_gfx_state_change_set(void *handle, 3439 uint32_t state) 3440 { 3441 struct smu_context *smu = handle; 3442 int ret = 0; 3443 3444 if (smu->ppt_funcs->gfx_state_change_set) 3445 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3446 3447 return ret; 3448 } 3449 3450 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3451 { 3452 int ret = 0; 3453 3454 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3455 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3456 3457 return ret; 3458 } 3459 3460 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3461 { 3462 int ret = -EOPNOTSUPP; 3463 3464 if (smu->ppt_funcs && 3465 smu->ppt_funcs->get_ecc_info) 3466 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3467 3468 return ret; 3469 3470 } 3471 3472 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3473 { 3474 struct smu_context *smu = handle; 3475 struct smu_table_context *smu_table = &smu->smu_table; 3476 struct smu_table *memory_pool = &smu_table->memory_pool; 3477 3478 if (!addr || !size) 3479 return -EINVAL; 3480 3481 *addr = NULL; 3482 *size = 0; 3483 if (memory_pool->bo) { 3484 *addr = memory_pool->cpu_addr; 3485 *size = memory_pool->size; 3486 } 3487 3488 return 0; 3489 } 3490 3491 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 3492 enum pp_xgmi_plpd_mode mode) 3493 { 3494 int ret = -EOPNOTSUPP; 3495 3496 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3497 return ret; 3498 3499 /* PLPD policy is not supported if it's NONE */ 3500 if (smu->plpd_mode == XGMI_PLPD_NONE) 3501 return ret; 3502 3503 if (smu->plpd_mode == mode) 3504 return 0; 3505 3506 if (smu->ppt_funcs && smu->ppt_funcs->select_xgmi_plpd_policy) 3507 ret = smu->ppt_funcs->select_xgmi_plpd_policy(smu, mode); 3508 3509 if (!ret) 3510 smu->plpd_mode = mode; 3511 3512 return ret; 3513 } 3514 3515 static const struct amd_pm_funcs swsmu_pm_funcs = { 3516 /* export for sysfs */ 3517 .set_fan_control_mode = smu_set_fan_control_mode, 3518 .get_fan_control_mode = smu_get_fan_control_mode, 3519 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3520 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3521 .force_clock_level = smu_force_ppclk_levels, 3522 .print_clock_levels = smu_print_ppclk_levels, 3523 .emit_clock_levels = smu_emit_ppclk_levels, 3524 .force_performance_level = smu_force_performance_level, 3525 .read_sensor = smu_read_sensor, 3526 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3527 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3528 .get_performance_level = smu_get_performance_level, 3529 .get_current_power_state = smu_get_current_power_state, 3530 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3531 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3532 .get_pp_num_states = smu_get_power_num_states, 3533 .get_pp_table = smu_sys_get_pp_table, 3534 .set_pp_table = smu_sys_set_pp_table, 3535 .switch_power_profile = smu_switch_power_profile, 3536 /* export to amdgpu */ 3537 .dispatch_tasks = smu_handle_dpm_task, 3538 .load_firmware = smu_load_microcode, 3539 .set_powergating_by_smu = smu_dpm_set_power_gate, 3540 .set_power_limit = smu_set_power_limit, 3541 .get_power_limit = smu_get_power_limit, 3542 .get_power_profile_mode = smu_get_power_profile_mode, 3543 .set_power_profile_mode = smu_set_power_profile_mode, 3544 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3545 .set_mp1_state = smu_set_mp1_state, 3546 .gfx_state_change_set = smu_gfx_state_change_set, 3547 /* export to DC */ 3548 .get_sclk = smu_get_sclk, 3549 .get_mclk = smu_get_mclk, 3550 .display_configuration_change = smu_display_configuration_change, 3551 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3552 .display_clock_voltage_request = smu_display_clock_voltage_request, 3553 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3554 .set_active_display_count = smu_set_display_count, 3555 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3556 .get_asic_baco_capability = smu_get_baco_capability, 3557 .set_asic_baco_state = smu_baco_set_state, 3558 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3559 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3560 .asic_reset_mode_2 = smu_mode2_reset, 3561 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3562 .set_df_cstate = smu_set_df_cstate, 3563 .set_xgmi_pstate = smu_set_xgmi_pstate, 3564 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3565 .get_pm_metrics = smu_sys_get_pm_metrics, 3566 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3567 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3568 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3569 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3570 .get_dpm_clock_table = smu_get_dpm_clock_table, 3571 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3572 }; 3573 3574 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3575 uint64_t event_arg) 3576 { 3577 int ret = -EINVAL; 3578 3579 if (smu->ppt_funcs->wait_for_event) 3580 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3581 3582 return ret; 3583 } 3584 3585 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3586 { 3587 3588 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3589 return -EOPNOTSUPP; 3590 3591 /* Confirm the buffer allocated is of correct size */ 3592 if (size != smu->stb_context.stb_buf_size) 3593 return -EINVAL; 3594 3595 /* 3596 * No need to lock smu mutex as we access STB directly through MMIO 3597 * and not going through SMU messaging route (for now at least). 3598 * For registers access rely on implementation internal locking. 3599 */ 3600 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3601 } 3602 3603 #if defined(CONFIG_DEBUG_FS) 3604 3605 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3606 { 3607 struct amdgpu_device *adev = filp->f_inode->i_private; 3608 struct smu_context *smu = adev->powerplay.pp_handle; 3609 unsigned char *buf; 3610 int r; 3611 3612 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3613 if (!buf) 3614 return -ENOMEM; 3615 3616 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3617 if (r) 3618 goto out; 3619 3620 filp->private_data = buf; 3621 3622 return 0; 3623 3624 out: 3625 kvfree(buf); 3626 return r; 3627 } 3628 3629 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3630 loff_t *pos) 3631 { 3632 struct amdgpu_device *adev = filp->f_inode->i_private; 3633 struct smu_context *smu = adev->powerplay.pp_handle; 3634 3635 3636 if (!filp->private_data) 3637 return -EINVAL; 3638 3639 return simple_read_from_buffer(buf, 3640 size, 3641 pos, filp->private_data, 3642 smu->stb_context.stb_buf_size); 3643 } 3644 3645 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3646 { 3647 kvfree(filp->private_data); 3648 filp->private_data = NULL; 3649 3650 return 0; 3651 } 3652 3653 /* 3654 * We have to define not only read method but also 3655 * open and release because .read takes up to PAGE_SIZE 3656 * data each time so and so is invoked multiple times. 3657 * We allocate the STB buffer in .open and release it 3658 * in .release 3659 */ 3660 static const struct file_operations smu_stb_debugfs_fops = { 3661 .owner = THIS_MODULE, 3662 .open = smu_stb_debugfs_open, 3663 .read = smu_stb_debugfs_read, 3664 .release = smu_stb_debugfs_release, 3665 .llseek = default_llseek, 3666 }; 3667 3668 #endif 3669 3670 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3671 { 3672 #if defined(CONFIG_DEBUG_FS) 3673 3674 struct smu_context *smu = adev->powerplay.pp_handle; 3675 3676 if (!smu || (!smu->stb_context.stb_buf_size)) 3677 return; 3678 3679 debugfs_create_file_size("amdgpu_smu_stb_dump", 3680 S_IRUSR, 3681 adev_to_drm(adev)->primary->debugfs_root, 3682 adev, 3683 &smu_stb_debugfs_fops, 3684 smu->stb_context.stb_buf_size); 3685 #endif 3686 } 3687 3688 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3689 { 3690 int ret = 0; 3691 3692 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3693 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3694 3695 return ret; 3696 } 3697 3698 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3699 { 3700 int ret = 0; 3701 3702 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3703 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3704 3705 return ret; 3706 } 3707