1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 76 static int smu_sys_get_pp_feature_mask(void *handle, 77 char *buf) 78 { 79 struct smu_context *smu = handle; 80 81 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 82 return -EOPNOTSUPP; 83 84 return smu_get_pp_feature_mask(smu, buf); 85 } 86 87 static int smu_sys_set_pp_feature_mask(void *handle, 88 uint64_t new_mask) 89 { 90 struct smu_context *smu = handle; 91 92 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 93 return -EOPNOTSUPP; 94 95 return smu_set_pp_feature_mask(smu, new_mask); 96 } 97 98 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 99 { 100 if (!smu->ppt_funcs->set_gfx_off_residency) 101 return -EINVAL; 102 103 return smu_set_gfx_off_residency(smu, value); 104 } 105 106 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 107 { 108 if (!smu->ppt_funcs->get_gfx_off_residency) 109 return -EINVAL; 110 111 return smu_get_gfx_off_residency(smu, value); 112 } 113 114 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 115 { 116 if (!smu->ppt_funcs->get_gfx_off_entrycount) 117 return -EINVAL; 118 119 return smu_get_gfx_off_entrycount(smu, value); 120 } 121 122 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 123 { 124 if (!smu->ppt_funcs->get_gfx_off_status) 125 return -EINVAL; 126 127 *value = smu_get_gfx_off_status(smu); 128 129 return 0; 130 } 131 132 int smu_set_soft_freq_range(struct smu_context *smu, 133 enum smu_clk_type clk_type, 134 uint32_t min, 135 uint32_t max) 136 { 137 int ret = 0; 138 139 if (smu->ppt_funcs->set_soft_freq_limited_range) 140 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 141 clk_type, 142 min, 143 max, 144 false); 145 146 return ret; 147 } 148 149 int smu_get_dpm_freq_range(struct smu_context *smu, 150 enum smu_clk_type clk_type, 151 uint32_t *min, 152 uint32_t *max) 153 { 154 int ret = -ENOTSUPP; 155 156 if (!min && !max) 157 return -EINVAL; 158 159 if (smu->ppt_funcs->get_dpm_ultimate_freq) 160 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 161 clk_type, 162 min, 163 max); 164 165 return ret; 166 } 167 168 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 169 { 170 int ret = 0; 171 struct amdgpu_device *adev = smu->adev; 172 173 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 174 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 175 if (ret) 176 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 177 } 178 return ret; 179 } 180 181 static u32 smu_get_mclk(void *handle, bool low) 182 { 183 struct smu_context *smu = handle; 184 uint32_t clk_freq; 185 int ret = 0; 186 187 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 188 low ? &clk_freq : NULL, 189 !low ? &clk_freq : NULL); 190 if (ret) 191 return 0; 192 return clk_freq * 100; 193 } 194 195 static u32 smu_get_sclk(void *handle, bool low) 196 { 197 struct smu_context *smu = handle; 198 uint32_t clk_freq; 199 int ret = 0; 200 201 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 202 low ? &clk_freq : NULL, 203 !low ? &clk_freq : NULL); 204 if (ret) 205 return 0; 206 return clk_freq * 100; 207 } 208 209 static int smu_set_gfx_imu_enable(struct smu_context *smu) 210 { 211 struct amdgpu_device *adev = smu->adev; 212 213 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 214 return 0; 215 216 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 217 return 0; 218 219 return smu_set_gfx_power_up_by_imu(smu); 220 } 221 222 static bool is_vcn_enabled(struct amdgpu_device *adev) 223 { 224 int i; 225 226 for (i = 0; i < adev->num_ip_blocks; i++) { 227 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 228 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 229 !adev->ip_blocks[i].status.valid) 230 return false; 231 } 232 233 return true; 234 } 235 236 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 237 bool enable) 238 { 239 struct smu_power_context *smu_power = &smu->smu_power; 240 struct smu_power_gate *power_gate = &smu_power->power_gate; 241 int ret = 0; 242 243 /* 244 * don't poweron vcn/jpeg when they are skipped. 245 */ 246 if (!is_vcn_enabled(smu->adev)) 247 return 0; 248 249 if (!smu->ppt_funcs->dpm_set_vcn_enable) 250 return 0; 251 252 if (atomic_read(&power_gate->vcn_gated) ^ enable) 253 return 0; 254 255 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, 0xff); 256 if (!ret) 257 atomic_set(&power_gate->vcn_gated, !enable); 258 259 return ret; 260 } 261 262 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 263 bool enable) 264 { 265 struct smu_power_context *smu_power = &smu->smu_power; 266 struct smu_power_gate *power_gate = &smu_power->power_gate; 267 int ret = 0; 268 269 if (!is_vcn_enabled(smu->adev)) 270 return 0; 271 272 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 273 return 0; 274 275 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 276 return 0; 277 278 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 279 if (!ret) 280 atomic_set(&power_gate->jpeg_gated, !enable); 281 282 return ret; 283 } 284 285 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 286 bool enable) 287 { 288 struct smu_power_context *smu_power = &smu->smu_power; 289 struct smu_power_gate *power_gate = &smu_power->power_gate; 290 int ret = 0; 291 292 if (!smu->ppt_funcs->dpm_set_vpe_enable) 293 return 0; 294 295 if (atomic_read(&power_gate->vpe_gated) ^ enable) 296 return 0; 297 298 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 299 if (!ret) 300 atomic_set(&power_gate->vpe_gated, !enable); 301 302 return ret; 303 } 304 305 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 306 bool enable) 307 { 308 struct smu_power_context *smu_power = &smu->smu_power; 309 struct smu_power_gate *power_gate = &smu_power->power_gate; 310 int ret = 0; 311 312 if (!smu->adev->enable_umsch_mm) 313 return 0; 314 315 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 316 return 0; 317 318 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 319 return 0; 320 321 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 322 if (!ret) 323 atomic_set(&power_gate->umsch_mm_gated, !enable); 324 325 return ret; 326 } 327 328 static int smu_set_mall_enable(struct smu_context *smu) 329 { 330 int ret = 0; 331 332 if (!smu->ppt_funcs->set_mall_enable) 333 return 0; 334 335 ret = smu->ppt_funcs->set_mall_enable(smu); 336 337 return ret; 338 } 339 340 /** 341 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 342 * 343 * @handle: smu_context pointer 344 * @block_type: the IP block to power gate/ungate 345 * @gate: to power gate if true, ungate otherwise 346 * 347 * This API uses no smu->mutex lock protection due to: 348 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 349 * This is guarded to be race condition free by the caller. 350 * 2. Or get called on user setting request of power_dpm_force_performance_level. 351 * Under this case, the smu->mutex lock protection is already enforced on 352 * the parent API smu_force_performance_level of the call path. 353 */ 354 static int smu_dpm_set_power_gate(void *handle, 355 uint32_t block_type, 356 bool gate) 357 { 358 struct smu_context *smu = handle; 359 int ret = 0; 360 361 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 362 dev_WARN(smu->adev->dev, 363 "SMU uninitialized but power %s requested for %u!\n", 364 gate ? "gate" : "ungate", block_type); 365 return -EOPNOTSUPP; 366 } 367 368 switch (block_type) { 369 /* 370 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 371 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 372 */ 373 case AMD_IP_BLOCK_TYPE_UVD: 374 case AMD_IP_BLOCK_TYPE_VCN: 375 ret = smu_dpm_set_vcn_enable(smu, !gate); 376 if (ret) 377 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 378 gate ? "gate" : "ungate"); 379 break; 380 case AMD_IP_BLOCK_TYPE_GFX: 381 ret = smu_gfx_off_control(smu, gate); 382 if (ret) 383 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 384 gate ? "enable" : "disable"); 385 break; 386 case AMD_IP_BLOCK_TYPE_SDMA: 387 ret = smu_powergate_sdma(smu, gate); 388 if (ret) 389 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 390 gate ? "gate" : "ungate"); 391 break; 392 case AMD_IP_BLOCK_TYPE_JPEG: 393 ret = smu_dpm_set_jpeg_enable(smu, !gate); 394 if (ret) 395 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 396 gate ? "gate" : "ungate"); 397 break; 398 case AMD_IP_BLOCK_TYPE_VPE: 399 ret = smu_dpm_set_vpe_enable(smu, !gate); 400 if (ret) 401 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 402 gate ? "gate" : "ungate"); 403 break; 404 default: 405 dev_err(smu->adev->dev, "Unsupported block type!\n"); 406 return -EINVAL; 407 } 408 409 return ret; 410 } 411 412 /** 413 * smu_set_user_clk_dependencies - set user profile clock dependencies 414 * 415 * @smu: smu_context pointer 416 * @clk: enum smu_clk_type type 417 * 418 * Enable/Disable the clock dependency for the @clk type. 419 */ 420 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 421 { 422 if (smu->adev->in_suspend) 423 return; 424 425 if (clk == SMU_MCLK) { 426 smu->user_dpm_profile.clk_dependency = 0; 427 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 428 } else if (clk == SMU_FCLK) { 429 /* MCLK takes precedence over FCLK */ 430 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 431 return; 432 433 smu->user_dpm_profile.clk_dependency = 0; 434 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 435 } else if (clk == SMU_SOCCLK) { 436 /* MCLK takes precedence over SOCCLK */ 437 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 438 return; 439 440 smu->user_dpm_profile.clk_dependency = 0; 441 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 442 } else 443 /* Add clk dependencies here, if any */ 444 return; 445 } 446 447 /** 448 * smu_restore_dpm_user_profile - reinstate user dpm profile 449 * 450 * @smu: smu_context pointer 451 * 452 * Restore the saved user power configurations include power limit, 453 * clock frequencies, fan control mode and fan speed. 454 */ 455 static void smu_restore_dpm_user_profile(struct smu_context *smu) 456 { 457 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 458 int ret = 0; 459 460 if (!smu->adev->in_suspend) 461 return; 462 463 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 464 return; 465 466 /* Enable restore flag */ 467 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 468 469 /* set the user dpm power limit */ 470 if (smu->user_dpm_profile.power_limit) { 471 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 472 if (ret) 473 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 474 } 475 476 /* set the user dpm clock configurations */ 477 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 478 enum smu_clk_type clk_type; 479 480 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 481 /* 482 * Iterate over smu clk type and force the saved user clk 483 * configs, skip if clock dependency is enabled 484 */ 485 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 486 smu->user_dpm_profile.clk_mask[clk_type]) { 487 ret = smu_force_smuclk_levels(smu, clk_type, 488 smu->user_dpm_profile.clk_mask[clk_type]); 489 if (ret) 490 dev_err(smu->adev->dev, 491 "Failed to set clock type = %d\n", clk_type); 492 } 493 } 494 } 495 496 /* set the user dpm fan configurations */ 497 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 498 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 499 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 500 if (ret != -EOPNOTSUPP) { 501 smu->user_dpm_profile.fan_speed_pwm = 0; 502 smu->user_dpm_profile.fan_speed_rpm = 0; 503 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 504 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 505 } 506 507 if (smu->user_dpm_profile.fan_speed_pwm) { 508 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 509 if (ret != -EOPNOTSUPP) 510 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 511 } 512 513 if (smu->user_dpm_profile.fan_speed_rpm) { 514 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 515 if (ret != -EOPNOTSUPP) 516 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 517 } 518 } 519 520 /* Restore user customized OD settings */ 521 if (smu->user_dpm_profile.user_od) { 522 if (smu->ppt_funcs->restore_user_od_settings) { 523 ret = smu->ppt_funcs->restore_user_od_settings(smu); 524 if (ret) 525 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 526 } 527 } 528 529 /* Disable restore flag */ 530 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 531 } 532 533 static int smu_get_power_num_states(void *handle, 534 struct pp_states_info *state_info) 535 { 536 if (!state_info) 537 return -EINVAL; 538 539 /* not support power state */ 540 memset(state_info, 0, sizeof(struct pp_states_info)); 541 state_info->nums = 1; 542 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 543 544 return 0; 545 } 546 547 bool is_support_sw_smu(struct amdgpu_device *adev) 548 { 549 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 550 if (adev->asic_type == CHIP_VEGA20) 551 return false; 552 553 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && 554 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) 555 return true; 556 557 return false; 558 } 559 560 bool is_support_cclk_dpm(struct amdgpu_device *adev) 561 { 562 struct smu_context *smu = adev->powerplay.pp_handle; 563 564 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 565 return false; 566 567 return true; 568 } 569 570 571 static int smu_sys_get_pp_table(void *handle, 572 char **table) 573 { 574 struct smu_context *smu = handle; 575 struct smu_table_context *smu_table = &smu->smu_table; 576 577 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 578 return -EOPNOTSUPP; 579 580 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 581 return -EINVAL; 582 583 if (smu_table->hardcode_pptable) 584 *table = smu_table->hardcode_pptable; 585 else 586 *table = smu_table->power_play_table; 587 588 return smu_table->power_play_table_size; 589 } 590 591 static int smu_sys_set_pp_table(void *handle, 592 const char *buf, 593 size_t size) 594 { 595 struct smu_context *smu = handle; 596 struct smu_table_context *smu_table = &smu->smu_table; 597 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 598 int ret = 0; 599 600 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 601 return -EOPNOTSUPP; 602 603 if (header->usStructureSize != size) { 604 dev_err(smu->adev->dev, "pp table size not matched !\n"); 605 return -EIO; 606 } 607 608 if (!smu_table->hardcode_pptable) { 609 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 610 if (!smu_table->hardcode_pptable) 611 return -ENOMEM; 612 } 613 614 memcpy(smu_table->hardcode_pptable, buf, size); 615 smu_table->power_play_table = smu_table->hardcode_pptable; 616 smu_table->power_play_table_size = size; 617 618 /* 619 * Special hw_fini action(for Navi1x, the DPMs disablement will be 620 * skipped) may be needed for custom pptable uploading. 621 */ 622 smu->uploading_custom_pp_table = true; 623 624 ret = smu_reset(smu); 625 if (ret) 626 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 627 628 smu->uploading_custom_pp_table = false; 629 630 return ret; 631 } 632 633 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 634 { 635 struct smu_feature *feature = &smu->smu_feature; 636 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 637 int ret = 0; 638 639 /* 640 * With SCPM enabled, the allowed featuremasks setting(via 641 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 642 * That means there is no way to let PMFW knows the settings below. 643 * Thus, we just assume all the features are allowed under 644 * such scenario. 645 */ 646 if (smu->adev->scpm_enabled) { 647 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 648 return 0; 649 } 650 651 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 652 653 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 654 SMU_FEATURE_MAX/32); 655 if (ret) 656 return ret; 657 658 bitmap_or(feature->allowed, feature->allowed, 659 (unsigned long *)allowed_feature_mask, 660 feature->feature_num); 661 662 return ret; 663 } 664 665 static int smu_set_funcs(struct amdgpu_device *adev) 666 { 667 struct smu_context *smu = adev->powerplay.pp_handle; 668 669 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 670 smu->od_enabled = true; 671 672 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 673 case IP_VERSION(11, 0, 0): 674 case IP_VERSION(11, 0, 5): 675 case IP_VERSION(11, 0, 9): 676 navi10_set_ppt_funcs(smu); 677 break; 678 case IP_VERSION(11, 0, 7): 679 case IP_VERSION(11, 0, 11): 680 case IP_VERSION(11, 0, 12): 681 case IP_VERSION(11, 0, 13): 682 sienna_cichlid_set_ppt_funcs(smu); 683 break; 684 case IP_VERSION(12, 0, 0): 685 case IP_VERSION(12, 0, 1): 686 renoir_set_ppt_funcs(smu); 687 break; 688 case IP_VERSION(11, 5, 0): 689 vangogh_set_ppt_funcs(smu); 690 break; 691 case IP_VERSION(13, 0, 1): 692 case IP_VERSION(13, 0, 3): 693 case IP_VERSION(13, 0, 8): 694 yellow_carp_set_ppt_funcs(smu); 695 break; 696 case IP_VERSION(13, 0, 4): 697 case IP_VERSION(13, 0, 11): 698 smu_v13_0_4_set_ppt_funcs(smu); 699 break; 700 case IP_VERSION(13, 0, 5): 701 smu_v13_0_5_set_ppt_funcs(smu); 702 break; 703 case IP_VERSION(11, 0, 8): 704 cyan_skillfish_set_ppt_funcs(smu); 705 break; 706 case IP_VERSION(11, 0, 2): 707 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 708 arcturus_set_ppt_funcs(smu); 709 /* OD is not supported on Arcturus */ 710 smu->od_enabled = false; 711 break; 712 case IP_VERSION(13, 0, 2): 713 aldebaran_set_ppt_funcs(smu); 714 /* Enable pp_od_clk_voltage node */ 715 smu->od_enabled = true; 716 break; 717 case IP_VERSION(13, 0, 0): 718 case IP_VERSION(13, 0, 10): 719 smu_v13_0_0_set_ppt_funcs(smu); 720 break; 721 case IP_VERSION(13, 0, 6): 722 case IP_VERSION(13, 0, 14): 723 smu_v13_0_6_set_ppt_funcs(smu); 724 /* Enable pp_od_clk_voltage node */ 725 smu->od_enabled = true; 726 break; 727 case IP_VERSION(13, 0, 7): 728 smu_v13_0_7_set_ppt_funcs(smu); 729 break; 730 case IP_VERSION(14, 0, 0): 731 case IP_VERSION(14, 0, 1): 732 case IP_VERSION(14, 0, 4): 733 smu_v14_0_0_set_ppt_funcs(smu); 734 break; 735 case IP_VERSION(14, 0, 2): 736 case IP_VERSION(14, 0, 3): 737 smu_v14_0_2_set_ppt_funcs(smu); 738 break; 739 default: 740 return -EINVAL; 741 } 742 743 return 0; 744 } 745 746 static int smu_early_init(struct amdgpu_ip_block *ip_block) 747 { 748 struct amdgpu_device *adev = ip_block->adev; 749 struct smu_context *smu; 750 int r; 751 752 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 753 if (!smu) 754 return -ENOMEM; 755 756 smu->adev = adev; 757 smu->pm_enabled = !!amdgpu_dpm; 758 smu->is_apu = false; 759 smu->smu_baco.state = SMU_BACO_STATE_NONE; 760 smu->smu_baco.platform_support = false; 761 smu->smu_baco.maco_support = false; 762 smu->user_dpm_profile.fan_mode = -1; 763 764 mutex_init(&smu->message_lock); 765 766 adev->powerplay.pp_handle = smu; 767 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 768 769 r = smu_set_funcs(adev); 770 if (r) 771 return r; 772 return smu_init_microcode(smu); 773 } 774 775 static int smu_set_default_dpm_table(struct smu_context *smu) 776 { 777 struct amdgpu_device *adev = smu->adev; 778 struct smu_power_context *smu_power = &smu->smu_power; 779 struct smu_power_gate *power_gate = &smu_power->power_gate; 780 int vcn_gate, jpeg_gate; 781 int ret = 0; 782 783 if (!smu->ppt_funcs->set_default_dpm_table) 784 return 0; 785 786 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 787 vcn_gate = atomic_read(&power_gate->vcn_gated); 788 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 789 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 790 791 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 792 ret = smu_dpm_set_vcn_enable(smu, true); 793 if (ret) 794 return ret; 795 } 796 797 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 798 ret = smu_dpm_set_jpeg_enable(smu, true); 799 if (ret) 800 goto err_out; 801 } 802 803 ret = smu->ppt_funcs->set_default_dpm_table(smu); 804 if (ret) 805 dev_err(smu->adev->dev, 806 "Failed to setup default dpm clock tables!\n"); 807 808 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 809 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 810 err_out: 811 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 812 smu_dpm_set_vcn_enable(smu, !vcn_gate); 813 814 return ret; 815 } 816 817 static int smu_apply_default_config_table_settings(struct smu_context *smu) 818 { 819 struct amdgpu_device *adev = smu->adev; 820 int ret = 0; 821 822 ret = smu_get_default_config_table_settings(smu, 823 &adev->pm.config_table); 824 if (ret) 825 return ret; 826 827 return smu_set_config_table(smu, &adev->pm.config_table); 828 } 829 830 static int smu_late_init(struct amdgpu_ip_block *ip_block) 831 { 832 struct amdgpu_device *adev = ip_block->adev; 833 struct smu_context *smu = adev->powerplay.pp_handle; 834 int ret = 0; 835 836 smu_set_fine_grain_gfx_freq_parameters(smu); 837 838 if (!smu->pm_enabled) 839 return 0; 840 841 ret = smu_post_init(smu); 842 if (ret) { 843 dev_err(adev->dev, "Failed to post smu init!\n"); 844 return ret; 845 } 846 847 /* 848 * Explicitly notify PMFW the power mode the system in. Since 849 * the PMFW may boot the ASIC with a different mode. 850 * For those supporting ACDC switch via gpio, PMFW will 851 * handle the switch automatically. Driver involvement 852 * is unnecessary. 853 */ 854 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 855 smu_set_ac_dc(smu); 856 857 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 858 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 859 return 0; 860 861 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 862 ret = smu_set_default_od_settings(smu); 863 if (ret) { 864 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 865 return ret; 866 } 867 } 868 869 ret = smu_populate_umd_state_clk(smu); 870 if (ret) { 871 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 872 return ret; 873 } 874 875 ret = smu_get_asic_power_limits(smu, 876 &smu->current_power_limit, 877 &smu->default_power_limit, 878 &smu->max_power_limit, 879 &smu->min_power_limit); 880 if (ret) { 881 dev_err(adev->dev, "Failed to get asic power limits!\n"); 882 return ret; 883 } 884 885 if (!amdgpu_sriov_vf(adev)) 886 smu_get_unique_id(smu); 887 888 smu_get_fan_parameters(smu); 889 890 smu_handle_task(smu, 891 smu->smu_dpm.dpm_level, 892 AMD_PP_TASK_COMPLETE_INIT); 893 894 ret = smu_apply_default_config_table_settings(smu); 895 if (ret && (ret != -EOPNOTSUPP)) { 896 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 897 return ret; 898 } 899 900 smu_restore_dpm_user_profile(smu); 901 902 return 0; 903 } 904 905 static int smu_init_fb_allocations(struct smu_context *smu) 906 { 907 struct amdgpu_device *adev = smu->adev; 908 struct smu_table_context *smu_table = &smu->smu_table; 909 struct smu_table *tables = smu_table->tables; 910 struct smu_table *driver_table = &(smu_table->driver_table); 911 uint32_t max_table_size = 0; 912 int ret, i; 913 914 /* VRAM allocation for tool table */ 915 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 916 ret = amdgpu_bo_create_kernel(adev, 917 tables[SMU_TABLE_PMSTATUSLOG].size, 918 tables[SMU_TABLE_PMSTATUSLOG].align, 919 tables[SMU_TABLE_PMSTATUSLOG].domain, 920 &tables[SMU_TABLE_PMSTATUSLOG].bo, 921 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 922 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 923 if (ret) { 924 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 925 return ret; 926 } 927 } 928 929 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 930 /* VRAM allocation for driver table */ 931 for (i = 0; i < SMU_TABLE_COUNT; i++) { 932 if (tables[i].size == 0) 933 continue; 934 935 /* If one of the tables has VRAM domain restriction, keep it in 936 * VRAM 937 */ 938 if ((tables[i].domain & 939 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 940 AMDGPU_GEM_DOMAIN_VRAM) 941 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 942 943 if (i == SMU_TABLE_PMSTATUSLOG) 944 continue; 945 946 if (max_table_size < tables[i].size) 947 max_table_size = tables[i].size; 948 } 949 950 driver_table->size = max_table_size; 951 driver_table->align = PAGE_SIZE; 952 953 ret = amdgpu_bo_create_kernel(adev, 954 driver_table->size, 955 driver_table->align, 956 driver_table->domain, 957 &driver_table->bo, 958 &driver_table->mc_address, 959 &driver_table->cpu_addr); 960 if (ret) { 961 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 962 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 963 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 964 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 965 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 966 } 967 968 return ret; 969 } 970 971 static int smu_fini_fb_allocations(struct smu_context *smu) 972 { 973 struct smu_table_context *smu_table = &smu->smu_table; 974 struct smu_table *tables = smu_table->tables; 975 struct smu_table *driver_table = &(smu_table->driver_table); 976 977 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 978 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 979 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 980 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 981 982 amdgpu_bo_free_kernel(&driver_table->bo, 983 &driver_table->mc_address, 984 &driver_table->cpu_addr); 985 986 return 0; 987 } 988 989 /** 990 * smu_alloc_memory_pool - allocate memory pool in the system memory 991 * 992 * @smu: amdgpu_device pointer 993 * 994 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 995 * and DramLogSetDramAddr can notify it changed. 996 * 997 * Returns 0 on success, error on failure. 998 */ 999 static int smu_alloc_memory_pool(struct smu_context *smu) 1000 { 1001 struct amdgpu_device *adev = smu->adev; 1002 struct smu_table_context *smu_table = &smu->smu_table; 1003 struct smu_table *memory_pool = &smu_table->memory_pool; 1004 uint64_t pool_size = smu->pool_size; 1005 int ret = 0; 1006 1007 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1008 return ret; 1009 1010 memory_pool->size = pool_size; 1011 memory_pool->align = PAGE_SIZE; 1012 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 1013 1014 switch (pool_size) { 1015 case SMU_MEMORY_POOL_SIZE_256_MB: 1016 case SMU_MEMORY_POOL_SIZE_512_MB: 1017 case SMU_MEMORY_POOL_SIZE_1_GB: 1018 case SMU_MEMORY_POOL_SIZE_2_GB: 1019 ret = amdgpu_bo_create_kernel(adev, 1020 memory_pool->size, 1021 memory_pool->align, 1022 memory_pool->domain, 1023 &memory_pool->bo, 1024 &memory_pool->mc_address, 1025 &memory_pool->cpu_addr); 1026 if (ret) 1027 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1028 break; 1029 default: 1030 break; 1031 } 1032 1033 return ret; 1034 } 1035 1036 static int smu_free_memory_pool(struct smu_context *smu) 1037 { 1038 struct smu_table_context *smu_table = &smu->smu_table; 1039 struct smu_table *memory_pool = &smu_table->memory_pool; 1040 1041 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1042 return 0; 1043 1044 amdgpu_bo_free_kernel(&memory_pool->bo, 1045 &memory_pool->mc_address, 1046 &memory_pool->cpu_addr); 1047 1048 memset(memory_pool, 0, sizeof(struct smu_table)); 1049 1050 return 0; 1051 } 1052 1053 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1054 { 1055 struct smu_table_context *smu_table = &smu->smu_table; 1056 struct smu_table *dummy_read_1_table = 1057 &smu_table->dummy_read_1_table; 1058 struct amdgpu_device *adev = smu->adev; 1059 int ret = 0; 1060 1061 if (!dummy_read_1_table->size) 1062 return 0; 1063 1064 ret = amdgpu_bo_create_kernel(adev, 1065 dummy_read_1_table->size, 1066 dummy_read_1_table->align, 1067 dummy_read_1_table->domain, 1068 &dummy_read_1_table->bo, 1069 &dummy_read_1_table->mc_address, 1070 &dummy_read_1_table->cpu_addr); 1071 if (ret) 1072 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1073 1074 return ret; 1075 } 1076 1077 static void smu_free_dummy_read_table(struct smu_context *smu) 1078 { 1079 struct smu_table_context *smu_table = &smu->smu_table; 1080 struct smu_table *dummy_read_1_table = 1081 &smu_table->dummy_read_1_table; 1082 1083 1084 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1085 &dummy_read_1_table->mc_address, 1086 &dummy_read_1_table->cpu_addr); 1087 1088 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1089 } 1090 1091 static int smu_smc_table_sw_init(struct smu_context *smu) 1092 { 1093 int ret; 1094 1095 /** 1096 * Create smu_table structure, and init smc tables such as 1097 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1098 */ 1099 ret = smu_init_smc_tables(smu); 1100 if (ret) { 1101 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1102 return ret; 1103 } 1104 1105 /** 1106 * Create smu_power_context structure, and allocate smu_dpm_context and 1107 * context size to fill the smu_power_context data. 1108 */ 1109 ret = smu_init_power(smu); 1110 if (ret) { 1111 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1112 return ret; 1113 } 1114 1115 /* 1116 * allocate vram bos to store smc table contents. 1117 */ 1118 ret = smu_init_fb_allocations(smu); 1119 if (ret) 1120 return ret; 1121 1122 ret = smu_alloc_memory_pool(smu); 1123 if (ret) 1124 return ret; 1125 1126 ret = smu_alloc_dummy_read_table(smu); 1127 if (ret) 1128 return ret; 1129 1130 ret = smu_i2c_init(smu); 1131 if (ret) 1132 return ret; 1133 1134 return 0; 1135 } 1136 1137 static int smu_smc_table_sw_fini(struct smu_context *smu) 1138 { 1139 int ret; 1140 1141 smu_i2c_fini(smu); 1142 1143 smu_free_dummy_read_table(smu); 1144 1145 ret = smu_free_memory_pool(smu); 1146 if (ret) 1147 return ret; 1148 1149 ret = smu_fini_fb_allocations(smu); 1150 if (ret) 1151 return ret; 1152 1153 ret = smu_fini_power(smu); 1154 if (ret) { 1155 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1156 return ret; 1157 } 1158 1159 ret = smu_fini_smc_tables(smu); 1160 if (ret) { 1161 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1162 return ret; 1163 } 1164 1165 return 0; 1166 } 1167 1168 static void smu_throttling_logging_work_fn(struct work_struct *work) 1169 { 1170 struct smu_context *smu = container_of(work, struct smu_context, 1171 throttling_logging_work); 1172 1173 smu_log_thermal_throttling(smu); 1174 } 1175 1176 static void smu_interrupt_work_fn(struct work_struct *work) 1177 { 1178 struct smu_context *smu = container_of(work, struct smu_context, 1179 interrupt_work); 1180 1181 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1182 smu->ppt_funcs->interrupt_work(smu); 1183 } 1184 1185 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1186 { 1187 struct smu_context *smu = 1188 container_of(work, struct smu_context, swctf_delayed_work.work); 1189 struct smu_temperature_range *range = 1190 &smu->thermal_range; 1191 struct amdgpu_device *adev = smu->adev; 1192 uint32_t hotspot_tmp, size; 1193 1194 /* 1195 * If the hotspot temperature is confirmed as below SW CTF setting point 1196 * after the delay enforced, nothing will be done. 1197 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1198 */ 1199 if (range->software_shutdown_temp && 1200 smu->ppt_funcs->read_sensor && 1201 !smu->ppt_funcs->read_sensor(smu, 1202 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1203 &hotspot_tmp, 1204 &size) && 1205 hotspot_tmp / 1000 < range->software_shutdown_temp) 1206 return; 1207 1208 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1209 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1210 orderly_poweroff(true); 1211 } 1212 1213 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1214 { 1215 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1216 struct smu_dpm_policy_ctxt *policy_ctxt; 1217 struct smu_dpm_policy *policy; 1218 1219 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1220 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1221 if (policy) 1222 policy->current_level = XGMI_PLPD_DEFAULT; 1223 return; 1224 } 1225 1226 /* PMFW put PLPD into default policy after enabling the feature */ 1227 if (smu_feature_is_enabled(smu, 1228 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1229 if (policy) 1230 policy->current_level = XGMI_PLPD_DEFAULT; 1231 } else { 1232 policy_ctxt = dpm_ctxt->dpm_policies; 1233 if (policy_ctxt) 1234 policy_ctxt->policy_mask &= 1235 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1236 } 1237 } 1238 1239 static bool smu_is_workload_profile_available(struct smu_context *smu, 1240 u32 profile) 1241 { 1242 if (profile >= PP_SMC_POWER_PROFILE_COUNT) 1243 return false; 1244 return smu->workload_map && smu->workload_map[profile].valid_mapping; 1245 } 1246 1247 static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1248 { 1249 struct amdgpu_device *adev = ip_block->adev; 1250 struct smu_context *smu = adev->powerplay.pp_handle; 1251 int ret; 1252 1253 smu->pool_size = adev->pm.smu_prv_buffer_size; 1254 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1255 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1256 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1257 1258 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1259 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1260 atomic64_set(&smu->throttle_int_counter, 0); 1261 smu->watermarks_bitmap = 0; 1262 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1263 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1264 smu->user_dpm_profile.user_workload_mask = 0; 1265 1266 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1267 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1268 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1269 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1270 1271 smu->workload_priority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1272 smu->workload_priority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1273 smu->workload_priority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1274 smu->workload_priority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1275 smu->workload_priority[PP_SMC_POWER_PROFILE_VR] = 4; 1276 smu->workload_priority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1277 smu->workload_priority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1278 1279 if (smu->is_apu || 1280 !smu_is_workload_profile_available(smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D)) { 1281 smu->driver_workload_mask = 1282 1 << smu->workload_priority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1283 } else { 1284 smu->driver_workload_mask = 1285 1 << smu->workload_priority[PP_SMC_POWER_PROFILE_FULLSCREEN3D]; 1286 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1287 } 1288 1289 smu->workload_mask = smu->driver_workload_mask | 1290 smu->user_dpm_profile.user_workload_mask; 1291 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1292 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1293 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1294 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1295 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1296 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1297 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1298 smu->display_config = &adev->pm.pm_display_cfg; 1299 1300 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1301 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1302 1303 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1304 smu_swctf_delayed_work_handler); 1305 1306 ret = smu_smc_table_sw_init(smu); 1307 if (ret) { 1308 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1309 return ret; 1310 } 1311 1312 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1313 ret = smu_get_vbios_bootup_values(smu); 1314 if (ret) { 1315 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1316 return ret; 1317 } 1318 1319 ret = smu_init_pptable_microcode(smu); 1320 if (ret) { 1321 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1322 return ret; 1323 } 1324 1325 ret = smu_register_irq_handler(smu); 1326 if (ret) { 1327 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1328 return ret; 1329 } 1330 1331 /* If there is no way to query fan control mode, fan control is not supported */ 1332 if (!smu->ppt_funcs->get_fan_control_mode) 1333 smu->adev->pm.no_fan = true; 1334 1335 return 0; 1336 } 1337 1338 static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1339 { 1340 struct amdgpu_device *adev = ip_block->adev; 1341 struct smu_context *smu = adev->powerplay.pp_handle; 1342 int ret; 1343 1344 ret = smu_smc_table_sw_fini(smu); 1345 if (ret) { 1346 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1347 return ret; 1348 } 1349 1350 smu_fini_microcode(smu); 1351 1352 return 0; 1353 } 1354 1355 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1356 { 1357 struct amdgpu_device *adev = smu->adev; 1358 struct smu_temperature_range *range = 1359 &smu->thermal_range; 1360 int ret = 0; 1361 1362 if (!smu->ppt_funcs->get_thermal_temperature_range) 1363 return 0; 1364 1365 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1366 if (ret) 1367 return ret; 1368 1369 adev->pm.dpm.thermal.min_temp = range->min; 1370 adev->pm.dpm.thermal.max_temp = range->max; 1371 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1372 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1373 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1374 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1375 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1376 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1377 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1378 1379 return ret; 1380 } 1381 1382 /** 1383 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1384 * 1385 * @smu: smu_context pointer 1386 * 1387 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1388 * Returns 0 on success, error on failure. 1389 */ 1390 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1391 { 1392 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1393 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1394 struct amdgpu_device *adev = smu->adev; 1395 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1396 uint64_t start, end; 1397 int ret, i, j; 1398 1399 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1400 if (ret) { 1401 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1402 return ret; 1403 } 1404 1405 /* 1406 * The exclusion ranges array we got might be filled with holes and duplicate 1407 * entries. For example: 1408 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1409 * We need to do some sortups to eliminate those holes and duplicate entries. 1410 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1411 */ 1412 for (i = 0; i < num_of_wbrf_ranges; i++) { 1413 start = wifi_bands[i].start; 1414 end = wifi_bands[i].end; 1415 1416 /* get the last valid entry to fill the intermediate hole */ 1417 if (!start && !end) { 1418 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1419 if (wifi_bands[j].start && wifi_bands[j].end) 1420 break; 1421 1422 /* no valid entry left */ 1423 if (j <= i) 1424 break; 1425 1426 start = wifi_bands[i].start = wifi_bands[j].start; 1427 end = wifi_bands[i].end = wifi_bands[j].end; 1428 wifi_bands[j].start = 0; 1429 wifi_bands[j].end = 0; 1430 num_of_wbrf_ranges = j; 1431 } 1432 1433 /* eliminate duplicate entries */ 1434 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1435 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1436 wifi_bands[j].start = 0; 1437 wifi_bands[j].end = 0; 1438 } 1439 } 1440 } 1441 1442 /* Send the sorted wifi_bands to PMFW */ 1443 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1444 /* Try to set the wifi_bands again */ 1445 if (unlikely(ret == -EBUSY)) { 1446 mdelay(5); 1447 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1448 } 1449 1450 return ret; 1451 } 1452 1453 /** 1454 * smu_wbrf_event_handler - handle notify events 1455 * 1456 * @nb: notifier block 1457 * @action: event type 1458 * @_arg: event data 1459 * 1460 * Calls relevant amdgpu function in response to wbrf event 1461 * notification from kernel. 1462 */ 1463 static int smu_wbrf_event_handler(struct notifier_block *nb, 1464 unsigned long action, void *_arg) 1465 { 1466 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1467 1468 switch (action) { 1469 case WBRF_CHANGED: 1470 schedule_delayed_work(&smu->wbrf_delayed_work, 1471 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1472 break; 1473 default: 1474 return NOTIFY_DONE; 1475 } 1476 1477 return NOTIFY_OK; 1478 } 1479 1480 /** 1481 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1482 * 1483 * @work: struct work_struct pointer 1484 * 1485 * Flood is over and driver will consume the latest exclusion ranges. 1486 */ 1487 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1488 { 1489 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1490 1491 smu_wbrf_handle_exclusion_ranges(smu); 1492 } 1493 1494 /** 1495 * smu_wbrf_support_check - check wbrf support 1496 * 1497 * @smu: smu_context pointer 1498 * 1499 * Verifies the ACPI interface whether wbrf is supported. 1500 */ 1501 static void smu_wbrf_support_check(struct smu_context *smu) 1502 { 1503 struct amdgpu_device *adev = smu->adev; 1504 1505 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1506 acpi_amd_wbrf_supported_consumer(adev->dev); 1507 1508 if (smu->wbrf_supported) 1509 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1510 } 1511 1512 /** 1513 * smu_wbrf_init - init driver wbrf support 1514 * 1515 * @smu: smu_context pointer 1516 * 1517 * Verifies the AMD ACPI interfaces and registers with the wbrf 1518 * notifier chain if wbrf feature is supported. 1519 * Returns 0 on success, error on failure. 1520 */ 1521 static int smu_wbrf_init(struct smu_context *smu) 1522 { 1523 int ret; 1524 1525 if (!smu->wbrf_supported) 1526 return 0; 1527 1528 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1529 1530 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1531 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1532 if (ret) 1533 return ret; 1534 1535 /* 1536 * Some wifiband exclusion ranges may be already there 1537 * before our driver loaded. To make sure our driver 1538 * is awared of those exclusion ranges. 1539 */ 1540 schedule_delayed_work(&smu->wbrf_delayed_work, 1541 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1542 1543 return 0; 1544 } 1545 1546 /** 1547 * smu_wbrf_fini - tear down driver wbrf support 1548 * 1549 * @smu: smu_context pointer 1550 * 1551 * Unregisters with the wbrf notifier chain. 1552 */ 1553 static void smu_wbrf_fini(struct smu_context *smu) 1554 { 1555 if (!smu->wbrf_supported) 1556 return; 1557 1558 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1559 1560 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1561 } 1562 1563 static int smu_smc_hw_setup(struct smu_context *smu) 1564 { 1565 struct smu_feature *feature = &smu->smu_feature; 1566 struct amdgpu_device *adev = smu->adev; 1567 uint8_t pcie_gen = 0, pcie_width = 0; 1568 uint64_t features_supported; 1569 int ret = 0; 1570 1571 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1572 case IP_VERSION(11, 0, 7): 1573 case IP_VERSION(11, 0, 11): 1574 case IP_VERSION(11, 5, 0): 1575 case IP_VERSION(11, 0, 12): 1576 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1577 dev_info(adev->dev, "dpm has been enabled\n"); 1578 ret = smu_system_features_control(smu, true); 1579 if (ret) 1580 dev_err(adev->dev, "Failed system features control!\n"); 1581 return ret; 1582 } 1583 break; 1584 default: 1585 break; 1586 } 1587 1588 ret = smu_init_display_count(smu, 0); 1589 if (ret) { 1590 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1591 return ret; 1592 } 1593 1594 ret = smu_set_driver_table_location(smu); 1595 if (ret) { 1596 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1597 return ret; 1598 } 1599 1600 /* 1601 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1602 */ 1603 ret = smu_set_tool_table_location(smu); 1604 if (ret) { 1605 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1606 return ret; 1607 } 1608 1609 /* 1610 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1611 * pool location. 1612 */ 1613 ret = smu_notify_memory_pool_location(smu); 1614 if (ret) { 1615 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1616 return ret; 1617 } 1618 1619 /* 1620 * It is assumed the pptable used before runpm is same as 1621 * the one used afterwards. Thus, we can reuse the stored 1622 * copy and do not need to resetup the pptable again. 1623 */ 1624 if (!adev->in_runpm) { 1625 ret = smu_setup_pptable(smu); 1626 if (ret) { 1627 dev_err(adev->dev, "Failed to setup pptable!\n"); 1628 return ret; 1629 } 1630 } 1631 1632 /* smu_dump_pptable(smu); */ 1633 1634 /* 1635 * With SCPM enabled, PSP is responsible for the PPTable transferring 1636 * (to SMU). Driver involvement is not needed and permitted. 1637 */ 1638 if (!adev->scpm_enabled) { 1639 /* 1640 * Copy pptable bo in the vram to smc with SMU MSGs such as 1641 * SetDriverDramAddr and TransferTableDram2Smu. 1642 */ 1643 ret = smu_write_pptable(smu); 1644 if (ret) { 1645 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1646 return ret; 1647 } 1648 } 1649 1650 /* issue Run*Btc msg */ 1651 ret = smu_run_btc(smu); 1652 if (ret) 1653 return ret; 1654 1655 /* Enable UclkShadow on wbrf supported */ 1656 if (smu->wbrf_supported) { 1657 ret = smu_enable_uclk_shadow(smu, true); 1658 if (ret) { 1659 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1660 return ret; 1661 } 1662 } 1663 1664 /* 1665 * With SCPM enabled, these actions(and relevant messages) are 1666 * not needed and permitted. 1667 */ 1668 if (!adev->scpm_enabled) { 1669 ret = smu_feature_set_allowed_mask(smu); 1670 if (ret) { 1671 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1672 return ret; 1673 } 1674 } 1675 1676 ret = smu_system_features_control(smu, true); 1677 if (ret) { 1678 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1679 return ret; 1680 } 1681 1682 smu_init_xgmi_plpd_mode(smu); 1683 1684 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1685 if (ret) { 1686 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1687 return ret; 1688 } 1689 bitmap_copy(feature->supported, 1690 (unsigned long *)&features_supported, 1691 feature->feature_num); 1692 1693 if (!smu_is_dpm_running(smu)) 1694 dev_info(adev->dev, "dpm has been disabled\n"); 1695 1696 /* 1697 * Set initialized values (get from vbios) to dpm tables context such as 1698 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1699 * type of clks. 1700 */ 1701 ret = smu_set_default_dpm_table(smu); 1702 if (ret) { 1703 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1704 return ret; 1705 } 1706 1707 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) 1708 pcie_gen = 4; 1709 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1710 pcie_gen = 3; 1711 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1712 pcie_gen = 2; 1713 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1714 pcie_gen = 1; 1715 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1716 pcie_gen = 0; 1717 1718 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1719 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1720 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1721 */ 1722 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) 1723 pcie_width = 7; 1724 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1725 pcie_width = 6; 1726 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1727 pcie_width = 5; 1728 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1729 pcie_width = 4; 1730 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1731 pcie_width = 3; 1732 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1733 pcie_width = 2; 1734 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1735 pcie_width = 1; 1736 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1737 if (ret) { 1738 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1739 return ret; 1740 } 1741 1742 ret = smu_get_thermal_temperature_range(smu); 1743 if (ret) { 1744 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1745 return ret; 1746 } 1747 1748 ret = smu_enable_thermal_alert(smu); 1749 if (ret) { 1750 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1751 return ret; 1752 } 1753 1754 ret = smu_notify_display_change(smu); 1755 if (ret) { 1756 dev_err(adev->dev, "Failed to notify display change!\n"); 1757 return ret; 1758 } 1759 1760 /* 1761 * Set min deep sleep dce fclk with bootup value from vbios via 1762 * SetMinDeepSleepDcefclk MSG. 1763 */ 1764 ret = smu_set_min_dcef_deep_sleep(smu, 1765 smu->smu_table.boot_values.dcefclk / 100); 1766 if (ret) { 1767 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1768 return ret; 1769 } 1770 1771 /* Init wbrf support. Properly setup the notifier */ 1772 ret = smu_wbrf_init(smu); 1773 if (ret) 1774 dev_err(adev->dev, "Error during wbrf init call\n"); 1775 1776 return ret; 1777 } 1778 1779 static int smu_start_smc_engine(struct smu_context *smu) 1780 { 1781 struct amdgpu_device *adev = smu->adev; 1782 int ret = 0; 1783 1784 smu->smc_fw_state = SMU_FW_INIT; 1785 1786 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1787 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1788 if (smu->ppt_funcs->load_microcode) { 1789 ret = smu->ppt_funcs->load_microcode(smu); 1790 if (ret) 1791 return ret; 1792 } 1793 } 1794 } 1795 1796 if (smu->ppt_funcs->check_fw_status) { 1797 ret = smu->ppt_funcs->check_fw_status(smu); 1798 if (ret) { 1799 dev_err(adev->dev, "SMC is not ready\n"); 1800 return ret; 1801 } 1802 } 1803 1804 /* 1805 * Send msg GetDriverIfVersion to check if the return value is equal 1806 * with DRIVER_IF_VERSION of smc header. 1807 */ 1808 ret = smu_check_fw_version(smu); 1809 if (ret) 1810 return ret; 1811 1812 return ret; 1813 } 1814 1815 static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1816 { 1817 int ret; 1818 struct amdgpu_device *adev = ip_block->adev; 1819 struct smu_context *smu = adev->powerplay.pp_handle; 1820 1821 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1822 smu->pm_enabled = false; 1823 return 0; 1824 } 1825 1826 ret = smu_start_smc_engine(smu); 1827 if (ret) { 1828 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1829 return ret; 1830 } 1831 1832 /* 1833 * Check whether wbrf is supported. This needs to be done 1834 * before SMU setup starts since part of SMU configuration 1835 * relies on this. 1836 */ 1837 smu_wbrf_support_check(smu); 1838 1839 if (smu->is_apu) { 1840 ret = smu_set_gfx_imu_enable(smu); 1841 if (ret) 1842 return ret; 1843 smu_dpm_set_vcn_enable(smu, true); 1844 smu_dpm_set_jpeg_enable(smu, true); 1845 smu_dpm_set_vpe_enable(smu, true); 1846 smu_dpm_set_umsch_mm_enable(smu, true); 1847 smu_set_mall_enable(smu); 1848 smu_set_gfx_cgpg(smu, true); 1849 } 1850 1851 if (!smu->pm_enabled) 1852 return 0; 1853 1854 ret = smu_get_driver_allowed_feature_mask(smu); 1855 if (ret) 1856 return ret; 1857 1858 ret = smu_smc_hw_setup(smu); 1859 if (ret) { 1860 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1861 return ret; 1862 } 1863 1864 /* 1865 * Move maximum sustainable clock retrieving here considering 1866 * 1. It is not needed on resume(from S3). 1867 * 2. DAL settings come between .hw_init and .late_init of SMU. 1868 * And DAL needs to know the maximum sustainable clocks. Thus 1869 * it cannot be put in .late_init(). 1870 */ 1871 ret = smu_init_max_sustainable_clocks(smu); 1872 if (ret) { 1873 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1874 return ret; 1875 } 1876 1877 adev->pm.dpm_enabled = true; 1878 1879 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1880 1881 return 0; 1882 } 1883 1884 static int smu_disable_dpms(struct smu_context *smu) 1885 { 1886 struct amdgpu_device *adev = smu->adev; 1887 int ret = 0; 1888 bool use_baco = !smu->is_apu && 1889 ((amdgpu_in_reset(adev) && 1890 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1891 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1892 1893 /* 1894 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1895 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1896 */ 1897 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1898 case IP_VERSION(13, 0, 0): 1899 case IP_VERSION(13, 0, 7): 1900 case IP_VERSION(13, 0, 10): 1901 case IP_VERSION(14, 0, 2): 1902 case IP_VERSION(14, 0, 3): 1903 return 0; 1904 default: 1905 break; 1906 } 1907 1908 /* 1909 * For custom pptable uploading, skip the DPM features 1910 * disable process on Navi1x ASICs. 1911 * - As the gfx related features are under control of 1912 * RLC on those ASICs. RLC reinitialization will be 1913 * needed to reenable them. That will cost much more 1914 * efforts. 1915 * 1916 * - SMU firmware can handle the DPM reenablement 1917 * properly. 1918 */ 1919 if (smu->uploading_custom_pp_table) { 1920 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1921 case IP_VERSION(11, 0, 0): 1922 case IP_VERSION(11, 0, 5): 1923 case IP_VERSION(11, 0, 9): 1924 case IP_VERSION(11, 0, 7): 1925 case IP_VERSION(11, 0, 11): 1926 case IP_VERSION(11, 5, 0): 1927 case IP_VERSION(11, 0, 12): 1928 case IP_VERSION(11, 0, 13): 1929 return 0; 1930 default: 1931 break; 1932 } 1933 } 1934 1935 /* 1936 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1937 * on BACO in. Driver involvement is unnecessary. 1938 */ 1939 if (use_baco) { 1940 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1941 case IP_VERSION(11, 0, 7): 1942 case IP_VERSION(11, 0, 0): 1943 case IP_VERSION(11, 0, 5): 1944 case IP_VERSION(11, 0, 9): 1945 case IP_VERSION(13, 0, 7): 1946 return 0; 1947 default: 1948 break; 1949 } 1950 } 1951 1952 /* 1953 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 1954 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1955 */ 1956 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 1957 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 1958 return 0; 1959 1960 /* 1961 * For gpu reset, runpm and hibernation through BACO, 1962 * BACO feature has to be kept enabled. 1963 */ 1964 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1965 ret = smu_disable_all_features_with_exception(smu, 1966 SMU_FEATURE_BACO_BIT); 1967 if (ret) 1968 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1969 } else { 1970 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1971 if (!adev->scpm_enabled) { 1972 ret = smu_system_features_control(smu, false); 1973 if (ret) 1974 dev_err(adev->dev, "Failed to disable smu features.\n"); 1975 } 1976 } 1977 1978 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1979 * otherwise SMU will hang while interacting with RLC if RLC is halted 1980 * this is a WA for Vangogh asic which fix the SMU hang issue. 1981 */ 1982 ret = smu_notify_rlc_state(smu, false); 1983 if (ret) { 1984 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1985 return ret; 1986 } 1987 1988 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1989 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1990 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1991 adev->gfx.rlc.funcs->stop(adev); 1992 1993 return ret; 1994 } 1995 1996 static int smu_smc_hw_cleanup(struct smu_context *smu) 1997 { 1998 struct amdgpu_device *adev = smu->adev; 1999 int ret = 0; 2000 2001 smu_wbrf_fini(smu); 2002 2003 cancel_work_sync(&smu->throttling_logging_work); 2004 cancel_work_sync(&smu->interrupt_work); 2005 2006 ret = smu_disable_thermal_alert(smu); 2007 if (ret) { 2008 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 2009 return ret; 2010 } 2011 2012 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2013 2014 ret = smu_disable_dpms(smu); 2015 if (ret) { 2016 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2017 return ret; 2018 } 2019 2020 return 0; 2021 } 2022 2023 static int smu_reset_mp1_state(struct smu_context *smu) 2024 { 2025 struct amdgpu_device *adev = smu->adev; 2026 int ret = 0; 2027 2028 if ((!adev->in_runpm) && (!adev->in_suspend) && 2029 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 2030 IP_VERSION(13, 0, 10) && 2031 !amdgpu_device_has_display_hardware(adev)) 2032 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2033 2034 return ret; 2035 } 2036 2037 static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2038 { 2039 struct amdgpu_device *adev = ip_block->adev; 2040 struct smu_context *smu = adev->powerplay.pp_handle; 2041 int ret; 2042 2043 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2044 return 0; 2045 2046 smu_dpm_set_vcn_enable(smu, false); 2047 smu_dpm_set_jpeg_enable(smu, false); 2048 smu_dpm_set_vpe_enable(smu, false); 2049 smu_dpm_set_umsch_mm_enable(smu, false); 2050 2051 adev->vcn.cur_state = AMD_PG_STATE_GATE; 2052 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2053 2054 if (!smu->pm_enabled) 2055 return 0; 2056 2057 adev->pm.dpm_enabled = false; 2058 2059 ret = smu_smc_hw_cleanup(smu); 2060 if (ret) 2061 return ret; 2062 2063 ret = smu_reset_mp1_state(smu); 2064 if (ret) 2065 return ret; 2066 2067 return 0; 2068 } 2069 2070 static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2071 { 2072 struct amdgpu_device *adev = ip_block->adev; 2073 struct smu_context *smu = adev->powerplay.pp_handle; 2074 2075 kfree(smu); 2076 } 2077 2078 static int smu_reset(struct smu_context *smu) 2079 { 2080 struct amdgpu_device *adev = smu->adev; 2081 struct amdgpu_ip_block *ip_block; 2082 int ret; 2083 2084 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2085 if (!ip_block) 2086 return -EINVAL; 2087 2088 ret = smu_hw_fini(ip_block); 2089 if (ret) 2090 return ret; 2091 2092 ret = smu_hw_init(ip_block); 2093 if (ret) 2094 return ret; 2095 2096 ret = smu_late_init(ip_block); 2097 if (ret) 2098 return ret; 2099 2100 return 0; 2101 } 2102 2103 static int smu_suspend(struct amdgpu_ip_block *ip_block) 2104 { 2105 struct amdgpu_device *adev = ip_block->adev; 2106 struct smu_context *smu = adev->powerplay.pp_handle; 2107 int ret; 2108 uint64_t count; 2109 2110 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2111 return 0; 2112 2113 if (!smu->pm_enabled) 2114 return 0; 2115 2116 adev->pm.dpm_enabled = false; 2117 2118 ret = smu_smc_hw_cleanup(smu); 2119 if (ret) 2120 return ret; 2121 2122 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2123 2124 smu_set_gfx_cgpg(smu, false); 2125 2126 /* 2127 * pwfw resets entrycount when device is suspended, so we save the 2128 * last value to be used when we resume to keep it consistent 2129 */ 2130 ret = smu_get_entrycount_gfxoff(smu, &count); 2131 if (!ret) 2132 adev->gfx.gfx_off_entrycount = count; 2133 2134 return 0; 2135 } 2136 2137 static int smu_resume(struct amdgpu_ip_block *ip_block) 2138 { 2139 int ret; 2140 struct amdgpu_device *adev = ip_block->adev; 2141 struct smu_context *smu = adev->powerplay.pp_handle; 2142 2143 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2144 return 0; 2145 2146 if (!smu->pm_enabled) 2147 return 0; 2148 2149 dev_info(adev->dev, "SMU is resuming...\n"); 2150 2151 ret = smu_start_smc_engine(smu); 2152 if (ret) { 2153 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2154 return ret; 2155 } 2156 2157 ret = smu_smc_hw_setup(smu); 2158 if (ret) { 2159 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2160 return ret; 2161 } 2162 2163 ret = smu_set_gfx_imu_enable(smu); 2164 if (ret) 2165 return ret; 2166 2167 smu_set_gfx_cgpg(smu, true); 2168 2169 smu->disable_uclk_switch = 0; 2170 2171 adev->pm.dpm_enabled = true; 2172 2173 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2174 2175 return 0; 2176 } 2177 2178 static int smu_display_configuration_change(void *handle, 2179 const struct amd_pp_display_configuration *display_config) 2180 { 2181 struct smu_context *smu = handle; 2182 2183 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2184 return -EOPNOTSUPP; 2185 2186 if (!display_config) 2187 return -EINVAL; 2188 2189 smu_set_min_dcef_deep_sleep(smu, 2190 display_config->min_dcef_deep_sleep_set_clk / 100); 2191 2192 return 0; 2193 } 2194 2195 static int smu_set_clockgating_state(void *handle, 2196 enum amd_clockgating_state state) 2197 { 2198 return 0; 2199 } 2200 2201 static int smu_set_powergating_state(void *handle, 2202 enum amd_powergating_state state) 2203 { 2204 return 0; 2205 } 2206 2207 static int smu_enable_umd_pstate(void *handle, 2208 enum amd_dpm_forced_level *level) 2209 { 2210 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2211 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2212 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2213 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2214 2215 struct smu_context *smu = (struct smu_context*)(handle); 2216 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2217 2218 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2219 return -EINVAL; 2220 2221 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2222 /* enter umd pstate, save current level, disable gfx cg*/ 2223 if (*level & profile_mode_mask) { 2224 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2225 smu_gpo_control(smu, false); 2226 smu_gfx_ulv_control(smu, false); 2227 smu_deep_sleep_control(smu, false); 2228 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2229 } 2230 } else { 2231 /* exit umd pstate, restore level, enable gfx cg*/ 2232 if (!(*level & profile_mode_mask)) { 2233 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2234 *level = smu_dpm_ctx->saved_dpm_level; 2235 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2236 smu_deep_sleep_control(smu, true); 2237 smu_gfx_ulv_control(smu, true); 2238 smu_gpo_control(smu, true); 2239 } 2240 } 2241 2242 return 0; 2243 } 2244 2245 static int smu_bump_power_profile_mode(struct smu_context *smu, 2246 long *param, 2247 uint32_t param_size) 2248 { 2249 int ret = 0; 2250 2251 if (smu->ppt_funcs->set_power_profile_mode) 2252 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2253 2254 return ret; 2255 } 2256 2257 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2258 enum amd_dpm_forced_level level, 2259 bool skip_display_settings, 2260 bool init) 2261 { 2262 int ret = 0; 2263 int index = 0; 2264 long workload[1]; 2265 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2266 2267 if (!skip_display_settings) { 2268 ret = smu_display_config_changed(smu); 2269 if (ret) { 2270 dev_err(smu->adev->dev, "Failed to change display config!"); 2271 return ret; 2272 } 2273 } 2274 2275 ret = smu_apply_clocks_adjust_rules(smu); 2276 if (ret) { 2277 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2278 return ret; 2279 } 2280 2281 if (!skip_display_settings) { 2282 ret = smu_notify_smc_display_config(smu); 2283 if (ret) { 2284 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2285 return ret; 2286 } 2287 } 2288 2289 if (smu_dpm_ctx->dpm_level != level) { 2290 ret = smu_asic_set_performance_level(smu, level); 2291 if (ret) { 2292 dev_err(smu->adev->dev, "Failed to set performance level!"); 2293 return ret; 2294 } 2295 2296 /* update the saved copy */ 2297 smu_dpm_ctx->dpm_level = level; 2298 } 2299 2300 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2301 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2302 index = fls(smu->workload_mask); 2303 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2304 workload[0] = smu->workload_setting[index]; 2305 2306 if (init || smu->power_profile_mode != workload[0]) 2307 smu_bump_power_profile_mode(smu, workload, 0); 2308 } 2309 2310 return ret; 2311 } 2312 2313 static int smu_handle_task(struct smu_context *smu, 2314 enum amd_dpm_forced_level level, 2315 enum amd_pp_task task_id) 2316 { 2317 int ret = 0; 2318 2319 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2320 return -EOPNOTSUPP; 2321 2322 switch (task_id) { 2323 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2324 ret = smu_pre_display_config_changed(smu); 2325 if (ret) 2326 return ret; 2327 ret = smu_adjust_power_state_dynamic(smu, level, false, false); 2328 break; 2329 case AMD_PP_TASK_COMPLETE_INIT: 2330 ret = smu_adjust_power_state_dynamic(smu, level, true, true); 2331 break; 2332 case AMD_PP_TASK_READJUST_POWER_STATE: 2333 ret = smu_adjust_power_state_dynamic(smu, level, true, false); 2334 break; 2335 default: 2336 break; 2337 } 2338 2339 return ret; 2340 } 2341 2342 static int smu_handle_dpm_task(void *handle, 2343 enum amd_pp_task task_id, 2344 enum amd_pm_state_type *user_state) 2345 { 2346 struct smu_context *smu = handle; 2347 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2348 2349 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2350 2351 } 2352 2353 static int smu_switch_power_profile(void *handle, 2354 enum PP_SMC_POWER_PROFILE type, 2355 bool en) 2356 { 2357 struct smu_context *smu = handle; 2358 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2359 long workload[1]; 2360 uint32_t index; 2361 2362 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2363 return -EOPNOTSUPP; 2364 2365 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2366 return -EINVAL; 2367 2368 if (!en) { 2369 smu->driver_workload_mask &= ~(1 << smu->workload_priority[type]); 2370 index = fls(smu->workload_mask); 2371 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2372 workload[0] = smu->workload_setting[index]; 2373 } else { 2374 smu->driver_workload_mask |= (1 << smu->workload_priority[type]); 2375 index = fls(smu->workload_mask); 2376 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2377 workload[0] = smu->workload_setting[index]; 2378 } 2379 2380 smu->workload_mask = smu->driver_workload_mask | 2381 smu->user_dpm_profile.user_workload_mask; 2382 2383 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2384 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2385 smu_bump_power_profile_mode(smu, workload, 0); 2386 2387 return 0; 2388 } 2389 2390 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2391 { 2392 struct smu_context *smu = handle; 2393 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2394 2395 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2396 return -EOPNOTSUPP; 2397 2398 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2399 return -EINVAL; 2400 2401 return smu_dpm_ctx->dpm_level; 2402 } 2403 2404 static int smu_force_performance_level(void *handle, 2405 enum amd_dpm_forced_level level) 2406 { 2407 struct smu_context *smu = handle; 2408 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2409 int ret = 0; 2410 2411 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2412 return -EOPNOTSUPP; 2413 2414 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2415 return -EINVAL; 2416 2417 ret = smu_enable_umd_pstate(smu, &level); 2418 if (ret) 2419 return ret; 2420 2421 ret = smu_handle_task(smu, level, 2422 AMD_PP_TASK_READJUST_POWER_STATE); 2423 2424 /* reset user dpm clock state */ 2425 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2426 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2427 smu->user_dpm_profile.clk_dependency = 0; 2428 } 2429 2430 return ret; 2431 } 2432 2433 static int smu_set_display_count(void *handle, uint32_t count) 2434 { 2435 struct smu_context *smu = handle; 2436 2437 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2438 return -EOPNOTSUPP; 2439 2440 return smu_init_display_count(smu, count); 2441 } 2442 2443 static int smu_force_smuclk_levels(struct smu_context *smu, 2444 enum smu_clk_type clk_type, 2445 uint32_t mask) 2446 { 2447 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2448 int ret = 0; 2449 2450 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2451 return -EOPNOTSUPP; 2452 2453 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2454 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2455 return -EINVAL; 2456 } 2457 2458 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2459 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2460 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2461 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2462 smu_set_user_clk_dependencies(smu, clk_type); 2463 } 2464 } 2465 2466 return ret; 2467 } 2468 2469 static int smu_force_ppclk_levels(void *handle, 2470 enum pp_clock_type type, 2471 uint32_t mask) 2472 { 2473 struct smu_context *smu = handle; 2474 enum smu_clk_type clk_type; 2475 2476 switch (type) { 2477 case PP_SCLK: 2478 clk_type = SMU_SCLK; break; 2479 case PP_MCLK: 2480 clk_type = SMU_MCLK; break; 2481 case PP_PCIE: 2482 clk_type = SMU_PCIE; break; 2483 case PP_SOCCLK: 2484 clk_type = SMU_SOCCLK; break; 2485 case PP_FCLK: 2486 clk_type = SMU_FCLK; break; 2487 case PP_DCEFCLK: 2488 clk_type = SMU_DCEFCLK; break; 2489 case PP_VCLK: 2490 clk_type = SMU_VCLK; break; 2491 case PP_VCLK1: 2492 clk_type = SMU_VCLK1; break; 2493 case PP_DCLK: 2494 clk_type = SMU_DCLK; break; 2495 case PP_DCLK1: 2496 clk_type = SMU_DCLK1; break; 2497 case OD_SCLK: 2498 clk_type = SMU_OD_SCLK; break; 2499 case OD_MCLK: 2500 clk_type = SMU_OD_MCLK; break; 2501 case OD_VDDC_CURVE: 2502 clk_type = SMU_OD_VDDC_CURVE; break; 2503 case OD_RANGE: 2504 clk_type = SMU_OD_RANGE; break; 2505 default: 2506 return -EINVAL; 2507 } 2508 2509 return smu_force_smuclk_levels(smu, clk_type, mask); 2510 } 2511 2512 /* 2513 * On system suspending or resetting, the dpm_enabled 2514 * flag will be cleared. So that those SMU services which 2515 * are not supported will be gated. 2516 * However, the mp1 state setting should still be granted 2517 * even if the dpm_enabled cleared. 2518 */ 2519 static int smu_set_mp1_state(void *handle, 2520 enum pp_mp1_state mp1_state) 2521 { 2522 struct smu_context *smu = handle; 2523 int ret = 0; 2524 2525 if (!smu->pm_enabled) 2526 return -EOPNOTSUPP; 2527 2528 if (smu->ppt_funcs && 2529 smu->ppt_funcs->set_mp1_state) 2530 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2531 2532 return ret; 2533 } 2534 2535 static int smu_set_df_cstate(void *handle, 2536 enum pp_df_cstate state) 2537 { 2538 struct smu_context *smu = handle; 2539 int ret = 0; 2540 2541 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2542 return -EOPNOTSUPP; 2543 2544 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2545 return 0; 2546 2547 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2548 if (ret) 2549 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2550 2551 return ret; 2552 } 2553 2554 int smu_write_watermarks_table(struct smu_context *smu) 2555 { 2556 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2557 return -EOPNOTSUPP; 2558 2559 return smu_set_watermarks_table(smu, NULL); 2560 } 2561 2562 static int smu_set_watermarks_for_clock_ranges(void *handle, 2563 struct pp_smu_wm_range_sets *clock_ranges) 2564 { 2565 struct smu_context *smu = handle; 2566 2567 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2568 return -EOPNOTSUPP; 2569 2570 if (smu->disable_watermark) 2571 return 0; 2572 2573 return smu_set_watermarks_table(smu, clock_ranges); 2574 } 2575 2576 int smu_set_ac_dc(struct smu_context *smu) 2577 { 2578 int ret = 0; 2579 2580 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2581 return -EOPNOTSUPP; 2582 2583 /* controlled by firmware */ 2584 if (smu->dc_controlled_by_gpio) 2585 return 0; 2586 2587 ret = smu_set_power_source(smu, 2588 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2589 SMU_POWER_SOURCE_DC); 2590 if (ret) 2591 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2592 smu->adev->pm.ac_power ? "AC" : "DC"); 2593 2594 return ret; 2595 } 2596 2597 const struct amd_ip_funcs smu_ip_funcs = { 2598 .name = "smu", 2599 .early_init = smu_early_init, 2600 .late_init = smu_late_init, 2601 .sw_init = smu_sw_init, 2602 .sw_fini = smu_sw_fini, 2603 .hw_init = smu_hw_init, 2604 .hw_fini = smu_hw_fini, 2605 .late_fini = smu_late_fini, 2606 .suspend = smu_suspend, 2607 .resume = smu_resume, 2608 .is_idle = NULL, 2609 .check_soft_reset = NULL, 2610 .wait_for_idle = NULL, 2611 .soft_reset = NULL, 2612 .set_clockgating_state = smu_set_clockgating_state, 2613 .set_powergating_state = smu_set_powergating_state, 2614 }; 2615 2616 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2617 .type = AMD_IP_BLOCK_TYPE_SMC, 2618 .major = 11, 2619 .minor = 0, 2620 .rev = 0, 2621 .funcs = &smu_ip_funcs, 2622 }; 2623 2624 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2625 .type = AMD_IP_BLOCK_TYPE_SMC, 2626 .major = 12, 2627 .minor = 0, 2628 .rev = 0, 2629 .funcs = &smu_ip_funcs, 2630 }; 2631 2632 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2633 .type = AMD_IP_BLOCK_TYPE_SMC, 2634 .major = 13, 2635 .minor = 0, 2636 .rev = 0, 2637 .funcs = &smu_ip_funcs, 2638 }; 2639 2640 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2641 .type = AMD_IP_BLOCK_TYPE_SMC, 2642 .major = 14, 2643 .minor = 0, 2644 .rev = 0, 2645 .funcs = &smu_ip_funcs, 2646 }; 2647 2648 static int smu_load_microcode(void *handle) 2649 { 2650 struct smu_context *smu = handle; 2651 struct amdgpu_device *adev = smu->adev; 2652 int ret = 0; 2653 2654 if (!smu->pm_enabled) 2655 return -EOPNOTSUPP; 2656 2657 /* This should be used for non PSP loading */ 2658 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2659 return 0; 2660 2661 if (smu->ppt_funcs->load_microcode) { 2662 ret = smu->ppt_funcs->load_microcode(smu); 2663 if (ret) { 2664 dev_err(adev->dev, "Load microcode failed\n"); 2665 return ret; 2666 } 2667 } 2668 2669 if (smu->ppt_funcs->check_fw_status) { 2670 ret = smu->ppt_funcs->check_fw_status(smu); 2671 if (ret) { 2672 dev_err(adev->dev, "SMC is not ready\n"); 2673 return ret; 2674 } 2675 } 2676 2677 return ret; 2678 } 2679 2680 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2681 { 2682 int ret = 0; 2683 2684 if (smu->ppt_funcs->set_gfx_cgpg) 2685 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2686 2687 return ret; 2688 } 2689 2690 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2691 { 2692 struct smu_context *smu = handle; 2693 int ret = 0; 2694 2695 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2696 return -EOPNOTSUPP; 2697 2698 if (!smu->ppt_funcs->set_fan_speed_rpm) 2699 return -EOPNOTSUPP; 2700 2701 if (speed == U32_MAX) 2702 return -EINVAL; 2703 2704 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2705 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2706 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2707 smu->user_dpm_profile.fan_speed_rpm = speed; 2708 2709 /* Override custom PWM setting as they cannot co-exist */ 2710 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2711 smu->user_dpm_profile.fan_speed_pwm = 0; 2712 } 2713 2714 return ret; 2715 } 2716 2717 /** 2718 * smu_get_power_limit - Request one of the SMU Power Limits 2719 * 2720 * @handle: pointer to smu context 2721 * @limit: requested limit is written back to this variable 2722 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2723 * @pp_power_type: &pp_power_type type of power 2724 * Return: 0 on success, <0 on error 2725 * 2726 */ 2727 int smu_get_power_limit(void *handle, 2728 uint32_t *limit, 2729 enum pp_power_limit_level pp_limit_level, 2730 enum pp_power_type pp_power_type) 2731 { 2732 struct smu_context *smu = handle; 2733 struct amdgpu_device *adev = smu->adev; 2734 enum smu_ppt_limit_level limit_level; 2735 uint32_t limit_type; 2736 int ret = 0; 2737 2738 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2739 return -EOPNOTSUPP; 2740 2741 switch (pp_power_type) { 2742 case PP_PWR_TYPE_SUSTAINED: 2743 limit_type = SMU_DEFAULT_PPT_LIMIT; 2744 break; 2745 case PP_PWR_TYPE_FAST: 2746 limit_type = SMU_FAST_PPT_LIMIT; 2747 break; 2748 default: 2749 return -EOPNOTSUPP; 2750 } 2751 2752 switch (pp_limit_level) { 2753 case PP_PWR_LIMIT_CURRENT: 2754 limit_level = SMU_PPT_LIMIT_CURRENT; 2755 break; 2756 case PP_PWR_LIMIT_DEFAULT: 2757 limit_level = SMU_PPT_LIMIT_DEFAULT; 2758 break; 2759 case PP_PWR_LIMIT_MAX: 2760 limit_level = SMU_PPT_LIMIT_MAX; 2761 break; 2762 case PP_PWR_LIMIT_MIN: 2763 limit_level = SMU_PPT_LIMIT_MIN; 2764 break; 2765 default: 2766 return -EOPNOTSUPP; 2767 } 2768 2769 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2770 if (smu->ppt_funcs->get_ppt_limit) 2771 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2772 } else { 2773 switch (limit_level) { 2774 case SMU_PPT_LIMIT_CURRENT: 2775 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2776 case IP_VERSION(13, 0, 2): 2777 case IP_VERSION(13, 0, 6): 2778 case IP_VERSION(13, 0, 14): 2779 case IP_VERSION(11, 0, 7): 2780 case IP_VERSION(11, 0, 11): 2781 case IP_VERSION(11, 0, 12): 2782 case IP_VERSION(11, 0, 13): 2783 ret = smu_get_asic_power_limits(smu, 2784 &smu->current_power_limit, 2785 NULL, NULL, NULL); 2786 break; 2787 default: 2788 break; 2789 } 2790 *limit = smu->current_power_limit; 2791 break; 2792 case SMU_PPT_LIMIT_DEFAULT: 2793 *limit = smu->default_power_limit; 2794 break; 2795 case SMU_PPT_LIMIT_MAX: 2796 *limit = smu->max_power_limit; 2797 break; 2798 case SMU_PPT_LIMIT_MIN: 2799 *limit = smu->min_power_limit; 2800 break; 2801 default: 2802 return -EINVAL; 2803 } 2804 } 2805 2806 return ret; 2807 } 2808 2809 static int smu_set_power_limit(void *handle, uint32_t limit) 2810 { 2811 struct smu_context *smu = handle; 2812 uint32_t limit_type = limit >> 24; 2813 int ret = 0; 2814 2815 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2816 return -EOPNOTSUPP; 2817 2818 limit &= (1<<24)-1; 2819 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2820 if (smu->ppt_funcs->set_power_limit) 2821 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2822 2823 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2824 dev_err(smu->adev->dev, 2825 "New power limit (%d) is out of range [%d,%d]\n", 2826 limit, smu->min_power_limit, smu->max_power_limit); 2827 return -EINVAL; 2828 } 2829 2830 if (!limit) 2831 limit = smu->current_power_limit; 2832 2833 if (smu->ppt_funcs->set_power_limit) { 2834 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2835 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2836 smu->user_dpm_profile.power_limit = limit; 2837 } 2838 2839 return ret; 2840 } 2841 2842 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2843 { 2844 int ret = 0; 2845 2846 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2847 return -EOPNOTSUPP; 2848 2849 if (smu->ppt_funcs->print_clk_levels) 2850 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2851 2852 return ret; 2853 } 2854 2855 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2856 { 2857 enum smu_clk_type clk_type; 2858 2859 switch (type) { 2860 case PP_SCLK: 2861 clk_type = SMU_SCLK; break; 2862 case PP_MCLK: 2863 clk_type = SMU_MCLK; break; 2864 case PP_PCIE: 2865 clk_type = SMU_PCIE; break; 2866 case PP_SOCCLK: 2867 clk_type = SMU_SOCCLK; break; 2868 case PP_FCLK: 2869 clk_type = SMU_FCLK; break; 2870 case PP_DCEFCLK: 2871 clk_type = SMU_DCEFCLK; break; 2872 case PP_VCLK: 2873 clk_type = SMU_VCLK; break; 2874 case PP_VCLK1: 2875 clk_type = SMU_VCLK1; break; 2876 case PP_DCLK: 2877 clk_type = SMU_DCLK; break; 2878 case PP_DCLK1: 2879 clk_type = SMU_DCLK1; break; 2880 case OD_SCLK: 2881 clk_type = SMU_OD_SCLK; break; 2882 case OD_MCLK: 2883 clk_type = SMU_OD_MCLK; break; 2884 case OD_VDDC_CURVE: 2885 clk_type = SMU_OD_VDDC_CURVE; break; 2886 case OD_RANGE: 2887 clk_type = SMU_OD_RANGE; break; 2888 case OD_VDDGFX_OFFSET: 2889 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2890 case OD_CCLK: 2891 clk_type = SMU_OD_CCLK; break; 2892 case OD_FAN_CURVE: 2893 clk_type = SMU_OD_FAN_CURVE; break; 2894 case OD_ACOUSTIC_LIMIT: 2895 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2896 case OD_ACOUSTIC_TARGET: 2897 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2898 case OD_FAN_TARGET_TEMPERATURE: 2899 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2900 case OD_FAN_MINIMUM_PWM: 2901 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2902 case OD_FAN_ZERO_RPM_ENABLE: 2903 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 2904 case OD_FAN_ZERO_RPM_STOP_TEMP: 2905 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 2906 default: 2907 clk_type = SMU_CLK_COUNT; break; 2908 } 2909 2910 return clk_type; 2911 } 2912 2913 static int smu_print_ppclk_levels(void *handle, 2914 enum pp_clock_type type, 2915 char *buf) 2916 { 2917 struct smu_context *smu = handle; 2918 enum smu_clk_type clk_type; 2919 2920 clk_type = smu_convert_to_smuclk(type); 2921 if (clk_type == SMU_CLK_COUNT) 2922 return -EINVAL; 2923 2924 return smu_print_smuclk_levels(smu, clk_type, buf); 2925 } 2926 2927 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2928 { 2929 struct smu_context *smu = handle; 2930 enum smu_clk_type clk_type; 2931 2932 clk_type = smu_convert_to_smuclk(type); 2933 if (clk_type == SMU_CLK_COUNT) 2934 return -EINVAL; 2935 2936 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2937 return -EOPNOTSUPP; 2938 2939 if (!smu->ppt_funcs->emit_clk_levels) 2940 return -ENOENT; 2941 2942 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2943 2944 } 2945 2946 static int smu_od_edit_dpm_table(void *handle, 2947 enum PP_OD_DPM_TABLE_COMMAND type, 2948 long *input, uint32_t size) 2949 { 2950 struct smu_context *smu = handle; 2951 int ret = 0; 2952 2953 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2954 return -EOPNOTSUPP; 2955 2956 if (smu->ppt_funcs->od_edit_dpm_table) { 2957 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2958 } 2959 2960 return ret; 2961 } 2962 2963 static int smu_read_sensor(void *handle, 2964 int sensor, 2965 void *data, 2966 int *size_arg) 2967 { 2968 struct smu_context *smu = handle; 2969 struct smu_umd_pstate_table *pstate_table = 2970 &smu->pstate_table; 2971 int ret = 0; 2972 uint32_t *size, size_val; 2973 2974 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2975 return -EOPNOTSUPP; 2976 2977 if (!data || !size_arg) 2978 return -EINVAL; 2979 2980 size_val = *size_arg; 2981 size = &size_val; 2982 2983 if (smu->ppt_funcs->read_sensor) 2984 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2985 goto unlock; 2986 2987 switch (sensor) { 2988 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2989 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2990 *size = 4; 2991 break; 2992 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2993 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2994 *size = 4; 2995 break; 2996 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2997 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2998 *size = 4; 2999 break; 3000 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 3001 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3002 *size = 4; 3003 break; 3004 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 3005 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 3006 *size = 8; 3007 break; 3008 case AMDGPU_PP_SENSOR_UVD_POWER: 3009 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3010 *size = 4; 3011 break; 3012 case AMDGPU_PP_SENSOR_VCE_POWER: 3013 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 3014 *size = 4; 3015 break; 3016 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3017 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 3018 *size = 4; 3019 break; 3020 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3021 *(uint32_t *)data = 0; 3022 *size = 4; 3023 break; 3024 default: 3025 *size = 0; 3026 ret = -EOPNOTSUPP; 3027 break; 3028 } 3029 3030 unlock: 3031 // assign uint32_t to int 3032 *size_arg = size_val; 3033 3034 return ret; 3035 } 3036 3037 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3038 { 3039 int ret = -EOPNOTSUPP; 3040 struct smu_context *smu = handle; 3041 3042 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3043 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3044 3045 return ret; 3046 } 3047 3048 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3049 { 3050 int ret = -EOPNOTSUPP; 3051 struct smu_context *smu = handle; 3052 3053 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3054 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3055 3056 return ret; 3057 } 3058 3059 static int smu_get_power_profile_mode(void *handle, char *buf) 3060 { 3061 struct smu_context *smu = handle; 3062 3063 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3064 !smu->ppt_funcs->get_power_profile_mode) 3065 return -EOPNOTSUPP; 3066 if (!buf) 3067 return -EINVAL; 3068 3069 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3070 } 3071 3072 static int smu_set_power_profile_mode(void *handle, 3073 long *param, 3074 uint32_t param_size) 3075 { 3076 struct smu_context *smu = handle; 3077 int ret; 3078 3079 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3080 !smu->ppt_funcs->set_power_profile_mode) 3081 return -EOPNOTSUPP; 3082 3083 if (smu->user_dpm_profile.user_workload_mask & 3084 (1 << smu->workload_priority[param[param_size]])) 3085 return 0; 3086 3087 smu->user_dpm_profile.user_workload_mask = 3088 (1 << smu->workload_priority[param[param_size]]); 3089 smu->workload_mask = smu->user_dpm_profile.user_workload_mask | 3090 smu->driver_workload_mask; 3091 ret = smu_bump_power_profile_mode(smu, param, param_size); 3092 3093 return ret; 3094 } 3095 3096 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3097 { 3098 struct smu_context *smu = handle; 3099 3100 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3101 return -EOPNOTSUPP; 3102 3103 if (!smu->ppt_funcs->get_fan_control_mode) 3104 return -EOPNOTSUPP; 3105 3106 if (!fan_mode) 3107 return -EINVAL; 3108 3109 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3110 3111 return 0; 3112 } 3113 3114 static int smu_set_fan_control_mode(void *handle, u32 value) 3115 { 3116 struct smu_context *smu = handle; 3117 int ret = 0; 3118 3119 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3120 return -EOPNOTSUPP; 3121 3122 if (!smu->ppt_funcs->set_fan_control_mode) 3123 return -EOPNOTSUPP; 3124 3125 if (value == U32_MAX) 3126 return -EINVAL; 3127 3128 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3129 if (ret) 3130 goto out; 3131 3132 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3133 smu->user_dpm_profile.fan_mode = value; 3134 3135 /* reset user dpm fan speed */ 3136 if (value != AMD_FAN_CTRL_MANUAL) { 3137 smu->user_dpm_profile.fan_speed_pwm = 0; 3138 smu->user_dpm_profile.fan_speed_rpm = 0; 3139 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3140 } 3141 } 3142 3143 out: 3144 return ret; 3145 } 3146 3147 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3148 { 3149 struct smu_context *smu = handle; 3150 int ret = 0; 3151 3152 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3153 return -EOPNOTSUPP; 3154 3155 if (!smu->ppt_funcs->get_fan_speed_pwm) 3156 return -EOPNOTSUPP; 3157 3158 if (!speed) 3159 return -EINVAL; 3160 3161 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3162 3163 return ret; 3164 } 3165 3166 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3167 { 3168 struct smu_context *smu = handle; 3169 int ret = 0; 3170 3171 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3172 return -EOPNOTSUPP; 3173 3174 if (!smu->ppt_funcs->set_fan_speed_pwm) 3175 return -EOPNOTSUPP; 3176 3177 if (speed == U32_MAX) 3178 return -EINVAL; 3179 3180 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3181 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3182 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3183 smu->user_dpm_profile.fan_speed_pwm = speed; 3184 3185 /* Override custom RPM setting as they cannot co-exist */ 3186 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3187 smu->user_dpm_profile.fan_speed_rpm = 0; 3188 } 3189 3190 return ret; 3191 } 3192 3193 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3194 { 3195 struct smu_context *smu = handle; 3196 int ret = 0; 3197 3198 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3199 return -EOPNOTSUPP; 3200 3201 if (!smu->ppt_funcs->get_fan_speed_rpm) 3202 return -EOPNOTSUPP; 3203 3204 if (!speed) 3205 return -EINVAL; 3206 3207 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3208 3209 return ret; 3210 } 3211 3212 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3213 { 3214 struct smu_context *smu = handle; 3215 3216 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3217 return -EOPNOTSUPP; 3218 3219 return smu_set_min_dcef_deep_sleep(smu, clk); 3220 } 3221 3222 static int smu_get_clock_by_type_with_latency(void *handle, 3223 enum amd_pp_clock_type type, 3224 struct pp_clock_levels_with_latency *clocks) 3225 { 3226 struct smu_context *smu = handle; 3227 enum smu_clk_type clk_type; 3228 int ret = 0; 3229 3230 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3231 return -EOPNOTSUPP; 3232 3233 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3234 switch (type) { 3235 case amd_pp_sys_clock: 3236 clk_type = SMU_GFXCLK; 3237 break; 3238 case amd_pp_mem_clock: 3239 clk_type = SMU_MCLK; 3240 break; 3241 case amd_pp_dcef_clock: 3242 clk_type = SMU_DCEFCLK; 3243 break; 3244 case amd_pp_disp_clock: 3245 clk_type = SMU_DISPCLK; 3246 break; 3247 default: 3248 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3249 return -EINVAL; 3250 } 3251 3252 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3253 } 3254 3255 return ret; 3256 } 3257 3258 static int smu_display_clock_voltage_request(void *handle, 3259 struct pp_display_clock_request *clock_req) 3260 { 3261 struct smu_context *smu = handle; 3262 int ret = 0; 3263 3264 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3265 return -EOPNOTSUPP; 3266 3267 if (smu->ppt_funcs->display_clock_voltage_request) 3268 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3269 3270 return ret; 3271 } 3272 3273 3274 static int smu_display_disable_memory_clock_switch(void *handle, 3275 bool disable_memory_clock_switch) 3276 { 3277 struct smu_context *smu = handle; 3278 int ret = -EINVAL; 3279 3280 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3281 return -EOPNOTSUPP; 3282 3283 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3284 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3285 3286 return ret; 3287 } 3288 3289 static int smu_set_xgmi_pstate(void *handle, 3290 uint32_t pstate) 3291 { 3292 struct smu_context *smu = handle; 3293 int ret = 0; 3294 3295 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3296 return -EOPNOTSUPP; 3297 3298 if (smu->ppt_funcs->set_xgmi_pstate) 3299 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3300 3301 if (ret) 3302 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3303 3304 return ret; 3305 } 3306 3307 static int smu_get_baco_capability(void *handle) 3308 { 3309 struct smu_context *smu = handle; 3310 3311 if (!smu->pm_enabled) 3312 return false; 3313 3314 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3315 return false; 3316 3317 return smu->ppt_funcs->get_bamaco_support(smu); 3318 } 3319 3320 static int smu_baco_set_state(void *handle, int state) 3321 { 3322 struct smu_context *smu = handle; 3323 int ret = 0; 3324 3325 if (!smu->pm_enabled) 3326 return -EOPNOTSUPP; 3327 3328 if (state == 0) { 3329 if (smu->ppt_funcs->baco_exit) 3330 ret = smu->ppt_funcs->baco_exit(smu); 3331 } else if (state == 1) { 3332 if (smu->ppt_funcs->baco_enter) 3333 ret = smu->ppt_funcs->baco_enter(smu); 3334 } else { 3335 return -EINVAL; 3336 } 3337 3338 if (ret) 3339 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3340 (state)?"enter":"exit"); 3341 3342 return ret; 3343 } 3344 3345 bool smu_mode1_reset_is_support(struct smu_context *smu) 3346 { 3347 bool ret = false; 3348 3349 if (!smu->pm_enabled) 3350 return false; 3351 3352 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3353 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3354 3355 return ret; 3356 } 3357 3358 bool smu_mode2_reset_is_support(struct smu_context *smu) 3359 { 3360 bool ret = false; 3361 3362 if (!smu->pm_enabled) 3363 return false; 3364 3365 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3366 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3367 3368 return ret; 3369 } 3370 3371 int smu_mode1_reset(struct smu_context *smu) 3372 { 3373 int ret = 0; 3374 3375 if (!smu->pm_enabled) 3376 return -EOPNOTSUPP; 3377 3378 if (smu->ppt_funcs->mode1_reset) 3379 ret = smu->ppt_funcs->mode1_reset(smu); 3380 3381 return ret; 3382 } 3383 3384 static int smu_mode2_reset(void *handle) 3385 { 3386 struct smu_context *smu = handle; 3387 int ret = 0; 3388 3389 if (!smu->pm_enabled) 3390 return -EOPNOTSUPP; 3391 3392 if (smu->ppt_funcs->mode2_reset) 3393 ret = smu->ppt_funcs->mode2_reset(smu); 3394 3395 if (ret) 3396 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3397 3398 return ret; 3399 } 3400 3401 static int smu_enable_gfx_features(void *handle) 3402 { 3403 struct smu_context *smu = handle; 3404 int ret = 0; 3405 3406 if (!smu->pm_enabled) 3407 return -EOPNOTSUPP; 3408 3409 if (smu->ppt_funcs->enable_gfx_features) 3410 ret = smu->ppt_funcs->enable_gfx_features(smu); 3411 3412 if (ret) 3413 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3414 3415 return ret; 3416 } 3417 3418 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3419 struct pp_smu_nv_clock_table *max_clocks) 3420 { 3421 struct smu_context *smu = handle; 3422 int ret = 0; 3423 3424 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3425 return -EOPNOTSUPP; 3426 3427 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3428 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3429 3430 return ret; 3431 } 3432 3433 static int smu_get_uclk_dpm_states(void *handle, 3434 unsigned int *clock_values_in_khz, 3435 unsigned int *num_states) 3436 { 3437 struct smu_context *smu = handle; 3438 int ret = 0; 3439 3440 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3441 return -EOPNOTSUPP; 3442 3443 if (smu->ppt_funcs->get_uclk_dpm_states) 3444 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3445 3446 return ret; 3447 } 3448 3449 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3450 { 3451 struct smu_context *smu = handle; 3452 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3453 3454 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3455 return -EOPNOTSUPP; 3456 3457 if (smu->ppt_funcs->get_current_power_state) 3458 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3459 3460 return pm_state; 3461 } 3462 3463 static int smu_get_dpm_clock_table(void *handle, 3464 struct dpm_clocks *clock_table) 3465 { 3466 struct smu_context *smu = handle; 3467 int ret = 0; 3468 3469 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3470 return -EOPNOTSUPP; 3471 3472 if (smu->ppt_funcs->get_dpm_clock_table) 3473 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3474 3475 return ret; 3476 } 3477 3478 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3479 { 3480 struct smu_context *smu = handle; 3481 3482 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3483 return -EOPNOTSUPP; 3484 3485 if (!smu->ppt_funcs->get_gpu_metrics) 3486 return -EOPNOTSUPP; 3487 3488 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3489 } 3490 3491 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3492 size_t size) 3493 { 3494 struct smu_context *smu = handle; 3495 3496 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3497 return -EOPNOTSUPP; 3498 3499 if (!smu->ppt_funcs->get_pm_metrics) 3500 return -EOPNOTSUPP; 3501 3502 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3503 } 3504 3505 static int smu_enable_mgpu_fan_boost(void *handle) 3506 { 3507 struct smu_context *smu = handle; 3508 int ret = 0; 3509 3510 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3511 return -EOPNOTSUPP; 3512 3513 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3514 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3515 3516 return ret; 3517 } 3518 3519 static int smu_gfx_state_change_set(void *handle, 3520 uint32_t state) 3521 { 3522 struct smu_context *smu = handle; 3523 int ret = 0; 3524 3525 if (smu->ppt_funcs->gfx_state_change_set) 3526 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3527 3528 return ret; 3529 } 3530 3531 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3532 { 3533 int ret = 0; 3534 3535 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3536 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3537 3538 return ret; 3539 } 3540 3541 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3542 { 3543 int ret = -EOPNOTSUPP; 3544 3545 if (smu->ppt_funcs && 3546 smu->ppt_funcs->get_ecc_info) 3547 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3548 3549 return ret; 3550 3551 } 3552 3553 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3554 { 3555 struct smu_context *smu = handle; 3556 struct smu_table_context *smu_table = &smu->smu_table; 3557 struct smu_table *memory_pool = &smu_table->memory_pool; 3558 3559 if (!addr || !size) 3560 return -EINVAL; 3561 3562 *addr = NULL; 3563 *size = 0; 3564 if (memory_pool->bo) { 3565 *addr = memory_pool->cpu_addr; 3566 *size = memory_pool->size; 3567 } 3568 3569 return 0; 3570 } 3571 3572 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3573 size_t *size) 3574 { 3575 size_t offset = *size; 3576 int level; 3577 3578 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3579 if (level == policy->current_level) 3580 offset += sysfs_emit_at(sysbuf, offset, 3581 "%d : %s*\n", level, 3582 policy->desc->get_desc(policy, level)); 3583 else 3584 offset += sysfs_emit_at(sysbuf, offset, 3585 "%d : %s\n", level, 3586 policy->desc->get_desc(policy, level)); 3587 } 3588 3589 *size = offset; 3590 } 3591 3592 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3593 enum pp_pm_policy p_type, char *sysbuf) 3594 { 3595 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3596 struct smu_dpm_policy_ctxt *policy_ctxt; 3597 struct smu_dpm_policy *dpm_policy; 3598 size_t offset = 0; 3599 3600 policy_ctxt = dpm_ctxt->dpm_policies; 3601 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3602 !policy_ctxt->policy_mask) 3603 return -EOPNOTSUPP; 3604 3605 if (p_type == PP_PM_POLICY_NONE) 3606 return -EINVAL; 3607 3608 dpm_policy = smu_get_pm_policy(smu, p_type); 3609 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3610 return -ENOENT; 3611 3612 if (!sysbuf) 3613 return -EINVAL; 3614 3615 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3616 3617 return offset; 3618 } 3619 3620 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3621 enum pp_pm_policy p_type) 3622 { 3623 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3624 struct smu_dpm_policy_ctxt *policy_ctxt; 3625 int i; 3626 3627 policy_ctxt = dpm_ctxt->dpm_policies; 3628 if (!policy_ctxt) 3629 return NULL; 3630 3631 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3632 if (policy_ctxt->policies[i].policy_type == p_type) 3633 return &policy_ctxt->policies[i]; 3634 } 3635 3636 return NULL; 3637 } 3638 3639 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3640 int level) 3641 { 3642 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3643 struct smu_dpm_policy *dpm_policy = NULL; 3644 struct smu_dpm_policy_ctxt *policy_ctxt; 3645 int ret = -EOPNOTSUPP; 3646 3647 policy_ctxt = dpm_ctxt->dpm_policies; 3648 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3649 !policy_ctxt->policy_mask) 3650 return ret; 3651 3652 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3653 return -EINVAL; 3654 3655 dpm_policy = smu_get_pm_policy(smu, p_type); 3656 3657 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3658 return ret; 3659 3660 if (dpm_policy->current_level == level) 3661 return 0; 3662 3663 ret = dpm_policy->set_policy(smu, level); 3664 3665 if (!ret) 3666 dpm_policy->current_level = level; 3667 3668 return ret; 3669 } 3670 3671 static const struct amd_pm_funcs swsmu_pm_funcs = { 3672 /* export for sysfs */ 3673 .set_fan_control_mode = smu_set_fan_control_mode, 3674 .get_fan_control_mode = smu_get_fan_control_mode, 3675 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3676 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3677 .force_clock_level = smu_force_ppclk_levels, 3678 .print_clock_levels = smu_print_ppclk_levels, 3679 .emit_clock_levels = smu_emit_ppclk_levels, 3680 .force_performance_level = smu_force_performance_level, 3681 .read_sensor = smu_read_sensor, 3682 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3683 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3684 .get_performance_level = smu_get_performance_level, 3685 .get_current_power_state = smu_get_current_power_state, 3686 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3687 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3688 .get_pp_num_states = smu_get_power_num_states, 3689 .get_pp_table = smu_sys_get_pp_table, 3690 .set_pp_table = smu_sys_set_pp_table, 3691 .switch_power_profile = smu_switch_power_profile, 3692 /* export to amdgpu */ 3693 .dispatch_tasks = smu_handle_dpm_task, 3694 .load_firmware = smu_load_microcode, 3695 .set_powergating_by_smu = smu_dpm_set_power_gate, 3696 .set_power_limit = smu_set_power_limit, 3697 .get_power_limit = smu_get_power_limit, 3698 .get_power_profile_mode = smu_get_power_profile_mode, 3699 .set_power_profile_mode = smu_set_power_profile_mode, 3700 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3701 .set_mp1_state = smu_set_mp1_state, 3702 .gfx_state_change_set = smu_gfx_state_change_set, 3703 /* export to DC */ 3704 .get_sclk = smu_get_sclk, 3705 .get_mclk = smu_get_mclk, 3706 .display_configuration_change = smu_display_configuration_change, 3707 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3708 .display_clock_voltage_request = smu_display_clock_voltage_request, 3709 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3710 .set_active_display_count = smu_set_display_count, 3711 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3712 .get_asic_baco_capability = smu_get_baco_capability, 3713 .set_asic_baco_state = smu_baco_set_state, 3714 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3715 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3716 .asic_reset_mode_2 = smu_mode2_reset, 3717 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3718 .set_df_cstate = smu_set_df_cstate, 3719 .set_xgmi_pstate = smu_set_xgmi_pstate, 3720 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3721 .get_pm_metrics = smu_sys_get_pm_metrics, 3722 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3723 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3724 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3725 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3726 .get_dpm_clock_table = smu_get_dpm_clock_table, 3727 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3728 }; 3729 3730 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3731 uint64_t event_arg) 3732 { 3733 int ret = -EINVAL; 3734 3735 if (smu->ppt_funcs->wait_for_event) 3736 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3737 3738 return ret; 3739 } 3740 3741 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3742 { 3743 3744 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3745 return -EOPNOTSUPP; 3746 3747 /* Confirm the buffer allocated is of correct size */ 3748 if (size != smu->stb_context.stb_buf_size) 3749 return -EINVAL; 3750 3751 /* 3752 * No need to lock smu mutex as we access STB directly through MMIO 3753 * and not going through SMU messaging route (for now at least). 3754 * For registers access rely on implementation internal locking. 3755 */ 3756 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3757 } 3758 3759 #if defined(CONFIG_DEBUG_FS) 3760 3761 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3762 { 3763 struct amdgpu_device *adev = filp->f_inode->i_private; 3764 struct smu_context *smu = adev->powerplay.pp_handle; 3765 unsigned char *buf; 3766 int r; 3767 3768 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3769 if (!buf) 3770 return -ENOMEM; 3771 3772 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3773 if (r) 3774 goto out; 3775 3776 filp->private_data = buf; 3777 3778 return 0; 3779 3780 out: 3781 kvfree(buf); 3782 return r; 3783 } 3784 3785 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3786 loff_t *pos) 3787 { 3788 struct amdgpu_device *adev = filp->f_inode->i_private; 3789 struct smu_context *smu = adev->powerplay.pp_handle; 3790 3791 3792 if (!filp->private_data) 3793 return -EINVAL; 3794 3795 return simple_read_from_buffer(buf, 3796 size, 3797 pos, filp->private_data, 3798 smu->stb_context.stb_buf_size); 3799 } 3800 3801 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3802 { 3803 kvfree(filp->private_data); 3804 filp->private_data = NULL; 3805 3806 return 0; 3807 } 3808 3809 /* 3810 * We have to define not only read method but also 3811 * open and release because .read takes up to PAGE_SIZE 3812 * data each time so and so is invoked multiple times. 3813 * We allocate the STB buffer in .open and release it 3814 * in .release 3815 */ 3816 static const struct file_operations smu_stb_debugfs_fops = { 3817 .owner = THIS_MODULE, 3818 .open = smu_stb_debugfs_open, 3819 .read = smu_stb_debugfs_read, 3820 .release = smu_stb_debugfs_release, 3821 .llseek = default_llseek, 3822 }; 3823 3824 #endif 3825 3826 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3827 { 3828 #if defined(CONFIG_DEBUG_FS) 3829 3830 struct smu_context *smu = adev->powerplay.pp_handle; 3831 3832 if (!smu || (!smu->stb_context.stb_buf_size)) 3833 return; 3834 3835 debugfs_create_file_size("amdgpu_smu_stb_dump", 3836 S_IRUSR, 3837 adev_to_drm(adev)->primary->debugfs_root, 3838 adev, 3839 &smu_stb_debugfs_fops, 3840 smu->stb_context.stb_buf_size); 3841 #endif 3842 } 3843 3844 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3845 { 3846 int ret = 0; 3847 3848 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3849 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3850 3851 return ret; 3852 } 3853 3854 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3855 { 3856 int ret = 0; 3857 3858 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3859 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3860 3861 return ret; 3862 } 3863 3864 int smu_send_rma_reason(struct smu_context *smu) 3865 { 3866 int ret = 0; 3867 3868 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3869 ret = smu->ppt_funcs->send_rma_reason(smu); 3870 3871 return ret; 3872 } 3873