1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 static void smu_power_profile_mode_get(struct smu_context *smu, 76 enum PP_SMC_POWER_PROFILE profile_mode); 77 static void smu_power_profile_mode_put(struct smu_context *smu, 78 enum PP_SMC_POWER_PROFILE profile_mode); 79 80 static int smu_sys_get_pp_feature_mask(void *handle, 81 char *buf) 82 { 83 struct smu_context *smu = handle; 84 85 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 86 return -EOPNOTSUPP; 87 88 return smu_get_pp_feature_mask(smu, buf); 89 } 90 91 static int smu_sys_set_pp_feature_mask(void *handle, 92 uint64_t new_mask) 93 { 94 struct smu_context *smu = handle; 95 96 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 97 return -EOPNOTSUPP; 98 99 return smu_set_pp_feature_mask(smu, new_mask); 100 } 101 102 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 103 { 104 if (!smu->ppt_funcs->set_gfx_off_residency) 105 return -EINVAL; 106 107 return smu_set_gfx_off_residency(smu, value); 108 } 109 110 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 111 { 112 if (!smu->ppt_funcs->get_gfx_off_residency) 113 return -EINVAL; 114 115 return smu_get_gfx_off_residency(smu, value); 116 } 117 118 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 119 { 120 if (!smu->ppt_funcs->get_gfx_off_entrycount) 121 return -EINVAL; 122 123 return smu_get_gfx_off_entrycount(smu, value); 124 } 125 126 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 127 { 128 if (!smu->ppt_funcs->get_gfx_off_status) 129 return -EINVAL; 130 131 *value = smu_get_gfx_off_status(smu); 132 133 return 0; 134 } 135 136 int smu_set_soft_freq_range(struct smu_context *smu, 137 enum smu_clk_type clk_type, 138 uint32_t min, 139 uint32_t max) 140 { 141 int ret = 0; 142 143 if (smu->ppt_funcs->set_soft_freq_limited_range) 144 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 145 clk_type, 146 min, 147 max, 148 false); 149 150 return ret; 151 } 152 153 int smu_get_dpm_freq_range(struct smu_context *smu, 154 enum smu_clk_type clk_type, 155 uint32_t *min, 156 uint32_t *max) 157 { 158 int ret = -ENOTSUPP; 159 160 if (!min && !max) 161 return -EINVAL; 162 163 if (smu->ppt_funcs->get_dpm_ultimate_freq) 164 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 165 clk_type, 166 min, 167 max); 168 169 return ret; 170 } 171 172 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 173 { 174 int ret = 0; 175 struct amdgpu_device *adev = smu->adev; 176 177 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 178 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 179 if (ret) 180 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 181 } 182 return ret; 183 } 184 185 static u32 smu_get_mclk(void *handle, bool low) 186 { 187 struct smu_context *smu = handle; 188 uint32_t clk_freq; 189 int ret = 0; 190 191 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 192 low ? &clk_freq : NULL, 193 !low ? &clk_freq : NULL); 194 if (ret) 195 return 0; 196 return clk_freq * 100; 197 } 198 199 static u32 smu_get_sclk(void *handle, bool low) 200 { 201 struct smu_context *smu = handle; 202 uint32_t clk_freq; 203 int ret = 0; 204 205 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 206 low ? &clk_freq : NULL, 207 !low ? &clk_freq : NULL); 208 if (ret) 209 return 0; 210 return clk_freq * 100; 211 } 212 213 static int smu_set_gfx_imu_enable(struct smu_context *smu) 214 { 215 struct amdgpu_device *adev = smu->adev; 216 217 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 218 return 0; 219 220 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 221 return 0; 222 223 return smu_set_gfx_power_up_by_imu(smu); 224 } 225 226 static bool is_vcn_enabled(struct amdgpu_device *adev) 227 { 228 int i; 229 230 for (i = 0; i < adev->num_ip_blocks; i++) { 231 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 232 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 233 !adev->ip_blocks[i].status.valid) 234 return false; 235 } 236 237 return true; 238 } 239 240 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 241 bool enable, 242 int inst) 243 { 244 struct smu_power_context *smu_power = &smu->smu_power; 245 struct smu_power_gate *power_gate = &smu_power->power_gate; 246 int ret = 0; 247 248 /* 249 * don't poweron vcn/jpeg when they are skipped. 250 */ 251 if (!is_vcn_enabled(smu->adev)) 252 return 0; 253 254 if (!smu->ppt_funcs->dpm_set_vcn_enable) 255 return 0; 256 257 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable) 258 return 0; 259 260 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst); 261 if (!ret) 262 atomic_set(&power_gate->vcn_gated[inst], !enable); 263 264 return ret; 265 } 266 267 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 268 bool enable) 269 { 270 struct smu_power_context *smu_power = &smu->smu_power; 271 struct smu_power_gate *power_gate = &smu_power->power_gate; 272 int ret = 0; 273 274 if (!is_vcn_enabled(smu->adev)) 275 return 0; 276 277 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 278 return 0; 279 280 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 281 return 0; 282 283 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 284 if (!ret) 285 atomic_set(&power_gate->jpeg_gated, !enable); 286 287 return ret; 288 } 289 290 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 291 bool enable) 292 { 293 struct smu_power_context *smu_power = &smu->smu_power; 294 struct smu_power_gate *power_gate = &smu_power->power_gate; 295 int ret = 0; 296 297 if (!smu->ppt_funcs->dpm_set_vpe_enable) 298 return 0; 299 300 if (atomic_read(&power_gate->vpe_gated) ^ enable) 301 return 0; 302 303 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 304 if (!ret) 305 atomic_set(&power_gate->vpe_gated, !enable); 306 307 return ret; 308 } 309 310 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 311 bool enable) 312 { 313 struct smu_power_context *smu_power = &smu->smu_power; 314 struct smu_power_gate *power_gate = &smu_power->power_gate; 315 int ret = 0; 316 317 if (!smu->adev->enable_umsch_mm) 318 return 0; 319 320 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 321 return 0; 322 323 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 324 return 0; 325 326 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 327 if (!ret) 328 atomic_set(&power_gate->umsch_mm_gated, !enable); 329 330 return ret; 331 } 332 333 static int smu_set_mall_enable(struct smu_context *smu) 334 { 335 int ret = 0; 336 337 if (!smu->ppt_funcs->set_mall_enable) 338 return 0; 339 340 ret = smu->ppt_funcs->set_mall_enable(smu); 341 342 return ret; 343 } 344 345 /** 346 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 347 * 348 * @handle: smu_context pointer 349 * @block_type: the IP block to power gate/ungate 350 * @gate: to power gate if true, ungate otherwise 351 * @inst: the instance of the IP block to power gate/ungate 352 * 353 * This API uses no smu->mutex lock protection due to: 354 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 355 * This is guarded to be race condition free by the caller. 356 * 2. Or get called on user setting request of power_dpm_force_performance_level. 357 * Under this case, the smu->mutex lock protection is already enforced on 358 * the parent API smu_force_performance_level of the call path. 359 */ 360 static int smu_dpm_set_power_gate(void *handle, 361 uint32_t block_type, 362 bool gate, 363 int inst) 364 { 365 struct smu_context *smu = handle; 366 int ret = 0; 367 368 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 369 dev_WARN(smu->adev->dev, 370 "SMU uninitialized but power %s requested for %u!\n", 371 gate ? "gate" : "ungate", block_type); 372 return -EOPNOTSUPP; 373 } 374 375 switch (block_type) { 376 /* 377 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 378 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 379 */ 380 case AMD_IP_BLOCK_TYPE_UVD: 381 case AMD_IP_BLOCK_TYPE_VCN: 382 ret = smu_dpm_set_vcn_enable(smu, !gate, inst); 383 if (ret) 384 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n", 385 gate ? "gate" : "ungate", inst); 386 break; 387 case AMD_IP_BLOCK_TYPE_GFX: 388 ret = smu_gfx_off_control(smu, gate); 389 if (ret) 390 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 391 gate ? "enable" : "disable"); 392 break; 393 case AMD_IP_BLOCK_TYPE_SDMA: 394 ret = smu_powergate_sdma(smu, gate); 395 if (ret) 396 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 397 gate ? "gate" : "ungate"); 398 break; 399 case AMD_IP_BLOCK_TYPE_JPEG: 400 ret = smu_dpm_set_jpeg_enable(smu, !gate); 401 if (ret) 402 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 403 gate ? "gate" : "ungate"); 404 break; 405 case AMD_IP_BLOCK_TYPE_VPE: 406 ret = smu_dpm_set_vpe_enable(smu, !gate); 407 if (ret) 408 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 409 gate ? "gate" : "ungate"); 410 break; 411 default: 412 dev_err(smu->adev->dev, "Unsupported block type!\n"); 413 return -EINVAL; 414 } 415 416 return ret; 417 } 418 419 /** 420 * smu_set_user_clk_dependencies - set user profile clock dependencies 421 * 422 * @smu: smu_context pointer 423 * @clk: enum smu_clk_type type 424 * 425 * Enable/Disable the clock dependency for the @clk type. 426 */ 427 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 428 { 429 if (smu->adev->in_suspend) 430 return; 431 432 if (clk == SMU_MCLK) { 433 smu->user_dpm_profile.clk_dependency = 0; 434 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 435 } else if (clk == SMU_FCLK) { 436 /* MCLK takes precedence over FCLK */ 437 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 438 return; 439 440 smu->user_dpm_profile.clk_dependency = 0; 441 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 442 } else if (clk == SMU_SOCCLK) { 443 /* MCLK takes precedence over SOCCLK */ 444 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 445 return; 446 447 smu->user_dpm_profile.clk_dependency = 0; 448 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 449 } else 450 /* Add clk dependencies here, if any */ 451 return; 452 } 453 454 /** 455 * smu_restore_dpm_user_profile - reinstate user dpm profile 456 * 457 * @smu: smu_context pointer 458 * 459 * Restore the saved user power configurations include power limit, 460 * clock frequencies, fan control mode and fan speed. 461 */ 462 static void smu_restore_dpm_user_profile(struct smu_context *smu) 463 { 464 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 465 int ret = 0; 466 467 if (!smu->adev->in_suspend) 468 return; 469 470 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 471 return; 472 473 /* Enable restore flag */ 474 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 475 476 /* set the user dpm power limit */ 477 if (smu->user_dpm_profile.power_limit) { 478 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 479 if (ret) 480 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 481 } 482 483 /* set the user dpm clock configurations */ 484 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 485 enum smu_clk_type clk_type; 486 487 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 488 /* 489 * Iterate over smu clk type and force the saved user clk 490 * configs, skip if clock dependency is enabled 491 */ 492 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 493 smu->user_dpm_profile.clk_mask[clk_type]) { 494 ret = smu_force_smuclk_levels(smu, clk_type, 495 smu->user_dpm_profile.clk_mask[clk_type]); 496 if (ret) 497 dev_err(smu->adev->dev, 498 "Failed to set clock type = %d\n", clk_type); 499 } 500 } 501 } 502 503 /* set the user dpm fan configurations */ 504 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 505 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 506 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 507 if (ret != -EOPNOTSUPP) { 508 smu->user_dpm_profile.fan_speed_pwm = 0; 509 smu->user_dpm_profile.fan_speed_rpm = 0; 510 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 511 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 512 } 513 514 if (smu->user_dpm_profile.fan_speed_pwm) { 515 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 516 if (ret != -EOPNOTSUPP) 517 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 518 } 519 520 if (smu->user_dpm_profile.fan_speed_rpm) { 521 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 522 if (ret != -EOPNOTSUPP) 523 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 524 } 525 } 526 527 /* Restore user customized OD settings */ 528 if (smu->user_dpm_profile.user_od) { 529 if (smu->ppt_funcs->restore_user_od_settings) { 530 ret = smu->ppt_funcs->restore_user_od_settings(smu); 531 if (ret) 532 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 533 } 534 } 535 536 /* Disable restore flag */ 537 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 538 } 539 540 static int smu_get_power_num_states(void *handle, 541 struct pp_states_info *state_info) 542 { 543 if (!state_info) 544 return -EINVAL; 545 546 /* not support power state */ 547 memset(state_info, 0, sizeof(struct pp_states_info)); 548 state_info->nums = 1; 549 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 550 551 return 0; 552 } 553 554 bool is_support_sw_smu(struct amdgpu_device *adev) 555 { 556 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 557 if (adev->asic_type == CHIP_VEGA20) 558 return false; 559 560 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && 561 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) 562 return true; 563 564 return false; 565 } 566 567 bool is_support_cclk_dpm(struct amdgpu_device *adev) 568 { 569 struct smu_context *smu = adev->powerplay.pp_handle; 570 571 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 572 return false; 573 574 return true; 575 } 576 577 578 static int smu_sys_get_pp_table(void *handle, 579 char **table) 580 { 581 struct smu_context *smu = handle; 582 struct smu_table_context *smu_table = &smu->smu_table; 583 584 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 585 return -EOPNOTSUPP; 586 587 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 588 return -EINVAL; 589 590 if (smu_table->hardcode_pptable) 591 *table = smu_table->hardcode_pptable; 592 else 593 *table = smu_table->power_play_table; 594 595 return smu_table->power_play_table_size; 596 } 597 598 static int smu_sys_set_pp_table(void *handle, 599 const char *buf, 600 size_t size) 601 { 602 struct smu_context *smu = handle; 603 struct smu_table_context *smu_table = &smu->smu_table; 604 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 605 int ret = 0; 606 607 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 608 return -EOPNOTSUPP; 609 610 if (header->usStructureSize != size) { 611 dev_err(smu->adev->dev, "pp table size not matched !\n"); 612 return -EIO; 613 } 614 615 if (!smu_table->hardcode_pptable || smu_table->power_play_table_size < size) { 616 kfree(smu_table->hardcode_pptable); 617 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 618 if (!smu_table->hardcode_pptable) 619 return -ENOMEM; 620 } 621 622 memcpy(smu_table->hardcode_pptable, buf, size); 623 smu_table->power_play_table = smu_table->hardcode_pptable; 624 smu_table->power_play_table_size = size; 625 626 /* 627 * Special hw_fini action(for Navi1x, the DPMs disablement will be 628 * skipped) may be needed for custom pptable uploading. 629 */ 630 smu->uploading_custom_pp_table = true; 631 632 ret = smu_reset(smu); 633 if (ret) 634 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 635 636 smu->uploading_custom_pp_table = false; 637 638 return ret; 639 } 640 641 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 642 { 643 struct smu_feature *feature = &smu->smu_feature; 644 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 645 int ret = 0; 646 647 /* 648 * With SCPM enabled, the allowed featuremasks setting(via 649 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 650 * That means there is no way to let PMFW knows the settings below. 651 * Thus, we just assume all the features are allowed under 652 * such scenario. 653 */ 654 if (smu->adev->scpm_enabled) { 655 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 656 return 0; 657 } 658 659 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 660 661 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 662 SMU_FEATURE_MAX/32); 663 if (ret) 664 return ret; 665 666 bitmap_or(feature->allowed, feature->allowed, 667 (unsigned long *)allowed_feature_mask, 668 feature->feature_num); 669 670 return ret; 671 } 672 673 static int smu_set_funcs(struct amdgpu_device *adev) 674 { 675 struct smu_context *smu = adev->powerplay.pp_handle; 676 677 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 678 smu->od_enabled = true; 679 680 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 681 case IP_VERSION(11, 0, 0): 682 case IP_VERSION(11, 0, 5): 683 case IP_VERSION(11, 0, 9): 684 navi10_set_ppt_funcs(smu); 685 break; 686 case IP_VERSION(11, 0, 7): 687 case IP_VERSION(11, 0, 11): 688 case IP_VERSION(11, 0, 12): 689 case IP_VERSION(11, 0, 13): 690 sienna_cichlid_set_ppt_funcs(smu); 691 break; 692 case IP_VERSION(12, 0, 0): 693 case IP_VERSION(12, 0, 1): 694 renoir_set_ppt_funcs(smu); 695 break; 696 case IP_VERSION(11, 5, 0): 697 vangogh_set_ppt_funcs(smu); 698 break; 699 case IP_VERSION(13, 0, 1): 700 case IP_VERSION(13, 0, 3): 701 case IP_VERSION(13, 0, 8): 702 yellow_carp_set_ppt_funcs(smu); 703 break; 704 case IP_VERSION(13, 0, 4): 705 case IP_VERSION(13, 0, 11): 706 smu_v13_0_4_set_ppt_funcs(smu); 707 break; 708 case IP_VERSION(13, 0, 5): 709 smu_v13_0_5_set_ppt_funcs(smu); 710 break; 711 case IP_VERSION(11, 0, 8): 712 cyan_skillfish_set_ppt_funcs(smu); 713 break; 714 case IP_VERSION(11, 0, 2): 715 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 716 arcturus_set_ppt_funcs(smu); 717 /* OD is not supported on Arcturus */ 718 smu->od_enabled = false; 719 break; 720 case IP_VERSION(13, 0, 2): 721 aldebaran_set_ppt_funcs(smu); 722 /* Enable pp_od_clk_voltage node */ 723 smu->od_enabled = true; 724 break; 725 case IP_VERSION(13, 0, 0): 726 case IP_VERSION(13, 0, 10): 727 smu_v13_0_0_set_ppt_funcs(smu); 728 break; 729 case IP_VERSION(13, 0, 6): 730 case IP_VERSION(13, 0, 14): 731 case IP_VERSION(13, 0, 12): 732 smu_v13_0_6_set_ppt_funcs(smu); 733 /* Enable pp_od_clk_voltage node */ 734 smu->od_enabled = true; 735 break; 736 case IP_VERSION(13, 0, 7): 737 smu_v13_0_7_set_ppt_funcs(smu); 738 break; 739 case IP_VERSION(14, 0, 0): 740 case IP_VERSION(14, 0, 1): 741 case IP_VERSION(14, 0, 4): 742 case IP_VERSION(14, 0, 5): 743 smu_v14_0_0_set_ppt_funcs(smu); 744 break; 745 case IP_VERSION(14, 0, 2): 746 case IP_VERSION(14, 0, 3): 747 smu_v14_0_2_set_ppt_funcs(smu); 748 break; 749 default: 750 return -EINVAL; 751 } 752 753 return 0; 754 } 755 756 static int smu_early_init(struct amdgpu_ip_block *ip_block) 757 { 758 struct amdgpu_device *adev = ip_block->adev; 759 struct smu_context *smu; 760 int r; 761 762 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 763 if (!smu) 764 return -ENOMEM; 765 766 smu->adev = adev; 767 smu->pm_enabled = !!amdgpu_dpm; 768 smu->is_apu = false; 769 smu->smu_baco.state = SMU_BACO_STATE_NONE; 770 smu->smu_baco.platform_support = false; 771 smu->smu_baco.maco_support = false; 772 smu->user_dpm_profile.fan_mode = -1; 773 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN; 774 775 mutex_init(&smu->message_lock); 776 777 adev->powerplay.pp_handle = smu; 778 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 779 780 r = smu_set_funcs(adev); 781 if (r) 782 return r; 783 return smu_init_microcode(smu); 784 } 785 786 static int smu_set_default_dpm_table(struct smu_context *smu) 787 { 788 struct amdgpu_device *adev = smu->adev; 789 struct smu_power_context *smu_power = &smu->smu_power; 790 struct smu_power_gate *power_gate = &smu_power->power_gate; 791 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i; 792 int ret = 0; 793 794 if (!smu->ppt_funcs->set_default_dpm_table) 795 return 0; 796 797 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 798 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 799 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]); 800 } 801 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 802 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 803 804 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 805 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 806 ret = smu_dpm_set_vcn_enable(smu, true, i); 807 if (ret) 808 return ret; 809 } 810 } 811 812 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 813 ret = smu_dpm_set_jpeg_enable(smu, true); 814 if (ret) 815 goto err_out; 816 } 817 818 ret = smu->ppt_funcs->set_default_dpm_table(smu); 819 if (ret) 820 dev_err(smu->adev->dev, 821 "Failed to setup default dpm clock tables!\n"); 822 823 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 824 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 825 err_out: 826 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 827 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 828 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i); 829 } 830 831 return ret; 832 } 833 834 static int smu_apply_default_config_table_settings(struct smu_context *smu) 835 { 836 struct amdgpu_device *adev = smu->adev; 837 int ret = 0; 838 839 ret = smu_get_default_config_table_settings(smu, 840 &adev->pm.config_table); 841 if (ret) 842 return ret; 843 844 return smu_set_config_table(smu, &adev->pm.config_table); 845 } 846 847 static int smu_late_init(struct amdgpu_ip_block *ip_block) 848 { 849 struct amdgpu_device *adev = ip_block->adev; 850 struct smu_context *smu = adev->powerplay.pp_handle; 851 int ret = 0; 852 853 smu_set_fine_grain_gfx_freq_parameters(smu); 854 855 if (!smu->pm_enabled) 856 return 0; 857 858 ret = smu_post_init(smu); 859 if (ret) { 860 dev_err(adev->dev, "Failed to post smu init!\n"); 861 return ret; 862 } 863 864 /* 865 * Explicitly notify PMFW the power mode the system in. Since 866 * the PMFW may boot the ASIC with a different mode. 867 * For those supporting ACDC switch via gpio, PMFW will 868 * handle the switch automatically. Driver involvement 869 * is unnecessary. 870 */ 871 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 872 smu_set_ac_dc(smu); 873 874 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 875 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 876 return 0; 877 878 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 879 ret = smu_set_default_od_settings(smu); 880 if (ret) { 881 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 882 return ret; 883 } 884 } 885 886 ret = smu_populate_umd_state_clk(smu); 887 if (ret) { 888 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 889 return ret; 890 } 891 892 ret = smu_get_asic_power_limits(smu, 893 &smu->current_power_limit, 894 &smu->default_power_limit, 895 &smu->max_power_limit, 896 &smu->min_power_limit); 897 if (ret) { 898 dev_err(adev->dev, "Failed to get asic power limits!\n"); 899 return ret; 900 } 901 902 if (!amdgpu_sriov_vf(adev)) 903 smu_get_unique_id(smu); 904 905 smu_get_fan_parameters(smu); 906 907 smu_handle_task(smu, 908 smu->smu_dpm.dpm_level, 909 AMD_PP_TASK_COMPLETE_INIT); 910 911 ret = smu_apply_default_config_table_settings(smu); 912 if (ret && (ret != -EOPNOTSUPP)) { 913 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 914 return ret; 915 } 916 917 smu_restore_dpm_user_profile(smu); 918 919 return 0; 920 } 921 922 static int smu_init_fb_allocations(struct smu_context *smu) 923 { 924 struct amdgpu_device *adev = smu->adev; 925 struct smu_table_context *smu_table = &smu->smu_table; 926 struct smu_table *tables = smu_table->tables; 927 struct smu_table *driver_table = &(smu_table->driver_table); 928 uint32_t max_table_size = 0; 929 int ret, i; 930 931 /* VRAM allocation for tool table */ 932 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 933 ret = amdgpu_bo_create_kernel(adev, 934 tables[SMU_TABLE_PMSTATUSLOG].size, 935 tables[SMU_TABLE_PMSTATUSLOG].align, 936 tables[SMU_TABLE_PMSTATUSLOG].domain, 937 &tables[SMU_TABLE_PMSTATUSLOG].bo, 938 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 939 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 940 if (ret) { 941 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 942 return ret; 943 } 944 } 945 946 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 947 /* VRAM allocation for driver table */ 948 for (i = 0; i < SMU_TABLE_COUNT; i++) { 949 if (tables[i].size == 0) 950 continue; 951 952 /* If one of the tables has VRAM domain restriction, keep it in 953 * VRAM 954 */ 955 if ((tables[i].domain & 956 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 957 AMDGPU_GEM_DOMAIN_VRAM) 958 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 959 960 if (i == SMU_TABLE_PMSTATUSLOG) 961 continue; 962 963 if (max_table_size < tables[i].size) 964 max_table_size = tables[i].size; 965 } 966 967 driver_table->size = max_table_size; 968 driver_table->align = PAGE_SIZE; 969 970 ret = amdgpu_bo_create_kernel(adev, 971 driver_table->size, 972 driver_table->align, 973 driver_table->domain, 974 &driver_table->bo, 975 &driver_table->mc_address, 976 &driver_table->cpu_addr); 977 if (ret) { 978 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 979 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 980 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 981 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 982 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 983 } 984 985 return ret; 986 } 987 988 static int smu_fini_fb_allocations(struct smu_context *smu) 989 { 990 struct smu_table_context *smu_table = &smu->smu_table; 991 struct smu_table *tables = smu_table->tables; 992 struct smu_table *driver_table = &(smu_table->driver_table); 993 994 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 995 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 996 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 997 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 998 999 amdgpu_bo_free_kernel(&driver_table->bo, 1000 &driver_table->mc_address, 1001 &driver_table->cpu_addr); 1002 1003 return 0; 1004 } 1005 1006 /** 1007 * smu_alloc_memory_pool - allocate memory pool in the system memory 1008 * 1009 * @smu: amdgpu_device pointer 1010 * 1011 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 1012 * and DramLogSetDramAddr can notify it changed. 1013 * 1014 * Returns 0 on success, error on failure. 1015 */ 1016 static int smu_alloc_memory_pool(struct smu_context *smu) 1017 { 1018 struct amdgpu_device *adev = smu->adev; 1019 struct smu_table_context *smu_table = &smu->smu_table; 1020 struct smu_table *memory_pool = &smu_table->memory_pool; 1021 uint64_t pool_size = smu->pool_size; 1022 int ret = 0; 1023 1024 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1025 return ret; 1026 1027 memory_pool->size = pool_size; 1028 memory_pool->align = PAGE_SIZE; 1029 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 1030 1031 switch (pool_size) { 1032 case SMU_MEMORY_POOL_SIZE_256_MB: 1033 case SMU_MEMORY_POOL_SIZE_512_MB: 1034 case SMU_MEMORY_POOL_SIZE_1_GB: 1035 case SMU_MEMORY_POOL_SIZE_2_GB: 1036 ret = amdgpu_bo_create_kernel(adev, 1037 memory_pool->size, 1038 memory_pool->align, 1039 memory_pool->domain, 1040 &memory_pool->bo, 1041 &memory_pool->mc_address, 1042 &memory_pool->cpu_addr); 1043 if (ret) 1044 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1045 break; 1046 default: 1047 break; 1048 } 1049 1050 return ret; 1051 } 1052 1053 static int smu_free_memory_pool(struct smu_context *smu) 1054 { 1055 struct smu_table_context *smu_table = &smu->smu_table; 1056 struct smu_table *memory_pool = &smu_table->memory_pool; 1057 1058 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1059 return 0; 1060 1061 amdgpu_bo_free_kernel(&memory_pool->bo, 1062 &memory_pool->mc_address, 1063 &memory_pool->cpu_addr); 1064 1065 memset(memory_pool, 0, sizeof(struct smu_table)); 1066 1067 return 0; 1068 } 1069 1070 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1071 { 1072 struct smu_table_context *smu_table = &smu->smu_table; 1073 struct smu_table *dummy_read_1_table = 1074 &smu_table->dummy_read_1_table; 1075 struct amdgpu_device *adev = smu->adev; 1076 int ret = 0; 1077 1078 if (!dummy_read_1_table->size) 1079 return 0; 1080 1081 ret = amdgpu_bo_create_kernel(adev, 1082 dummy_read_1_table->size, 1083 dummy_read_1_table->align, 1084 dummy_read_1_table->domain, 1085 &dummy_read_1_table->bo, 1086 &dummy_read_1_table->mc_address, 1087 &dummy_read_1_table->cpu_addr); 1088 if (ret) 1089 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1090 1091 return ret; 1092 } 1093 1094 static void smu_free_dummy_read_table(struct smu_context *smu) 1095 { 1096 struct smu_table_context *smu_table = &smu->smu_table; 1097 struct smu_table *dummy_read_1_table = 1098 &smu_table->dummy_read_1_table; 1099 1100 1101 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1102 &dummy_read_1_table->mc_address, 1103 &dummy_read_1_table->cpu_addr); 1104 1105 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1106 } 1107 1108 static int smu_smc_table_sw_init(struct smu_context *smu) 1109 { 1110 int ret; 1111 1112 /** 1113 * Create smu_table structure, and init smc tables such as 1114 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1115 */ 1116 ret = smu_init_smc_tables(smu); 1117 if (ret) { 1118 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1119 return ret; 1120 } 1121 1122 /** 1123 * Create smu_power_context structure, and allocate smu_dpm_context and 1124 * context size to fill the smu_power_context data. 1125 */ 1126 ret = smu_init_power(smu); 1127 if (ret) { 1128 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1129 return ret; 1130 } 1131 1132 /* 1133 * allocate vram bos to store smc table contents. 1134 */ 1135 ret = smu_init_fb_allocations(smu); 1136 if (ret) 1137 return ret; 1138 1139 ret = smu_alloc_memory_pool(smu); 1140 if (ret) 1141 return ret; 1142 1143 ret = smu_alloc_dummy_read_table(smu); 1144 if (ret) 1145 return ret; 1146 1147 ret = smu_i2c_init(smu); 1148 if (ret) 1149 return ret; 1150 1151 return 0; 1152 } 1153 1154 static int smu_smc_table_sw_fini(struct smu_context *smu) 1155 { 1156 int ret; 1157 1158 smu_i2c_fini(smu); 1159 1160 smu_free_dummy_read_table(smu); 1161 1162 ret = smu_free_memory_pool(smu); 1163 if (ret) 1164 return ret; 1165 1166 ret = smu_fini_fb_allocations(smu); 1167 if (ret) 1168 return ret; 1169 1170 ret = smu_fini_power(smu); 1171 if (ret) { 1172 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1173 return ret; 1174 } 1175 1176 ret = smu_fini_smc_tables(smu); 1177 if (ret) { 1178 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1179 return ret; 1180 } 1181 1182 return 0; 1183 } 1184 1185 static void smu_throttling_logging_work_fn(struct work_struct *work) 1186 { 1187 struct smu_context *smu = container_of(work, struct smu_context, 1188 throttling_logging_work); 1189 1190 smu_log_thermal_throttling(smu); 1191 } 1192 1193 static void smu_interrupt_work_fn(struct work_struct *work) 1194 { 1195 struct smu_context *smu = container_of(work, struct smu_context, 1196 interrupt_work); 1197 1198 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1199 smu->ppt_funcs->interrupt_work(smu); 1200 } 1201 1202 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1203 { 1204 struct smu_context *smu = 1205 container_of(work, struct smu_context, swctf_delayed_work.work); 1206 struct smu_temperature_range *range = 1207 &smu->thermal_range; 1208 struct amdgpu_device *adev = smu->adev; 1209 uint32_t hotspot_tmp, size; 1210 1211 /* 1212 * If the hotspot temperature is confirmed as below SW CTF setting point 1213 * after the delay enforced, nothing will be done. 1214 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1215 */ 1216 if (range->software_shutdown_temp && 1217 smu->ppt_funcs->read_sensor && 1218 !smu->ppt_funcs->read_sensor(smu, 1219 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1220 &hotspot_tmp, 1221 &size) && 1222 hotspot_tmp / 1000 < range->software_shutdown_temp) 1223 return; 1224 1225 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1226 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1227 orderly_poweroff(true); 1228 } 1229 1230 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1231 { 1232 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1233 struct smu_dpm_policy_ctxt *policy_ctxt; 1234 struct smu_dpm_policy *policy; 1235 1236 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1237 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1238 if (policy) 1239 policy->current_level = XGMI_PLPD_DEFAULT; 1240 return; 1241 } 1242 1243 /* PMFW put PLPD into default policy after enabling the feature */ 1244 if (smu_feature_is_enabled(smu, 1245 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1246 if (policy) 1247 policy->current_level = XGMI_PLPD_DEFAULT; 1248 } else { 1249 policy_ctxt = dpm_ctxt->dpm_policies; 1250 if (policy_ctxt) 1251 policy_ctxt->policy_mask &= 1252 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1253 } 1254 } 1255 1256 static void smu_init_power_profile(struct smu_context *smu) 1257 { 1258 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) 1259 smu->power_profile_mode = 1260 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1261 smu_power_profile_mode_get(smu, smu->power_profile_mode); 1262 } 1263 1264 static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1265 { 1266 struct amdgpu_device *adev = ip_block->adev; 1267 struct smu_context *smu = adev->powerplay.pp_handle; 1268 int i, ret; 1269 1270 smu->pool_size = adev->pm.smu_prv_buffer_size; 1271 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1272 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1273 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1274 1275 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1276 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1277 atomic64_set(&smu->throttle_int_counter, 0); 1278 smu->watermarks_bitmap = 0; 1279 1280 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1281 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1); 1282 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1283 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1284 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1285 1286 smu_init_power_profile(smu); 1287 smu->display_config = &adev->pm.pm_display_cfg; 1288 1289 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1290 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1291 1292 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1293 smu_swctf_delayed_work_handler); 1294 1295 ret = smu_smc_table_sw_init(smu); 1296 if (ret) { 1297 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1298 return ret; 1299 } 1300 1301 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1302 ret = smu_get_vbios_bootup_values(smu); 1303 if (ret) { 1304 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1305 return ret; 1306 } 1307 1308 ret = smu_init_pptable_microcode(smu); 1309 if (ret) { 1310 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1311 return ret; 1312 } 1313 1314 ret = smu_register_irq_handler(smu); 1315 if (ret) { 1316 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1317 return ret; 1318 } 1319 1320 /* If there is no way to query fan control mode, fan control is not supported */ 1321 if (!smu->ppt_funcs->get_fan_control_mode) 1322 smu->adev->pm.no_fan = true; 1323 1324 return 0; 1325 } 1326 1327 static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1328 { 1329 struct amdgpu_device *adev = ip_block->adev; 1330 struct smu_context *smu = adev->powerplay.pp_handle; 1331 int ret; 1332 1333 ret = smu_smc_table_sw_fini(smu); 1334 if (ret) { 1335 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1336 return ret; 1337 } 1338 1339 if (smu->custom_profile_params) { 1340 kfree(smu->custom_profile_params); 1341 smu->custom_profile_params = NULL; 1342 } 1343 1344 smu_fini_microcode(smu); 1345 1346 return 0; 1347 } 1348 1349 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1350 { 1351 struct amdgpu_device *adev = smu->adev; 1352 struct smu_temperature_range *range = 1353 &smu->thermal_range; 1354 int ret = 0; 1355 1356 if (!smu->ppt_funcs->get_thermal_temperature_range) 1357 return 0; 1358 1359 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1360 if (ret) 1361 return ret; 1362 1363 adev->pm.dpm.thermal.min_temp = range->min; 1364 adev->pm.dpm.thermal.max_temp = range->max; 1365 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1366 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1367 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1368 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1369 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1370 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1371 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1372 1373 return ret; 1374 } 1375 1376 /** 1377 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1378 * 1379 * @smu: smu_context pointer 1380 * 1381 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1382 * Returns 0 on success, error on failure. 1383 */ 1384 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1385 { 1386 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1387 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1388 struct amdgpu_device *adev = smu->adev; 1389 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1390 uint64_t start, end; 1391 int ret, i, j; 1392 1393 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1394 if (ret) { 1395 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1396 return ret; 1397 } 1398 1399 /* 1400 * The exclusion ranges array we got might be filled with holes and duplicate 1401 * entries. For example: 1402 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1403 * We need to do some sortups to eliminate those holes and duplicate entries. 1404 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1405 */ 1406 for (i = 0; i < num_of_wbrf_ranges; i++) { 1407 start = wifi_bands[i].start; 1408 end = wifi_bands[i].end; 1409 1410 /* get the last valid entry to fill the intermediate hole */ 1411 if (!start && !end) { 1412 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1413 if (wifi_bands[j].start && wifi_bands[j].end) 1414 break; 1415 1416 /* no valid entry left */ 1417 if (j <= i) 1418 break; 1419 1420 start = wifi_bands[i].start = wifi_bands[j].start; 1421 end = wifi_bands[i].end = wifi_bands[j].end; 1422 wifi_bands[j].start = 0; 1423 wifi_bands[j].end = 0; 1424 num_of_wbrf_ranges = j; 1425 } 1426 1427 /* eliminate duplicate entries */ 1428 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1429 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1430 wifi_bands[j].start = 0; 1431 wifi_bands[j].end = 0; 1432 } 1433 } 1434 } 1435 1436 /* Send the sorted wifi_bands to PMFW */ 1437 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1438 /* Try to set the wifi_bands again */ 1439 if (unlikely(ret == -EBUSY)) { 1440 mdelay(5); 1441 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1442 } 1443 1444 return ret; 1445 } 1446 1447 /** 1448 * smu_wbrf_event_handler - handle notify events 1449 * 1450 * @nb: notifier block 1451 * @action: event type 1452 * @_arg: event data 1453 * 1454 * Calls relevant amdgpu function in response to wbrf event 1455 * notification from kernel. 1456 */ 1457 static int smu_wbrf_event_handler(struct notifier_block *nb, 1458 unsigned long action, void *_arg) 1459 { 1460 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1461 1462 switch (action) { 1463 case WBRF_CHANGED: 1464 schedule_delayed_work(&smu->wbrf_delayed_work, 1465 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1466 break; 1467 default: 1468 return NOTIFY_DONE; 1469 } 1470 1471 return NOTIFY_OK; 1472 } 1473 1474 /** 1475 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1476 * 1477 * @work: struct work_struct pointer 1478 * 1479 * Flood is over and driver will consume the latest exclusion ranges. 1480 */ 1481 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1482 { 1483 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1484 1485 smu_wbrf_handle_exclusion_ranges(smu); 1486 } 1487 1488 /** 1489 * smu_wbrf_support_check - check wbrf support 1490 * 1491 * @smu: smu_context pointer 1492 * 1493 * Verifies the ACPI interface whether wbrf is supported. 1494 */ 1495 static void smu_wbrf_support_check(struct smu_context *smu) 1496 { 1497 struct amdgpu_device *adev = smu->adev; 1498 1499 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1500 acpi_amd_wbrf_supported_consumer(adev->dev); 1501 1502 if (smu->wbrf_supported) 1503 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1504 } 1505 1506 /** 1507 * smu_wbrf_init - init driver wbrf support 1508 * 1509 * @smu: smu_context pointer 1510 * 1511 * Verifies the AMD ACPI interfaces and registers with the wbrf 1512 * notifier chain if wbrf feature is supported. 1513 * Returns 0 on success, error on failure. 1514 */ 1515 static int smu_wbrf_init(struct smu_context *smu) 1516 { 1517 int ret; 1518 1519 if (!smu->wbrf_supported) 1520 return 0; 1521 1522 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1523 1524 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1525 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1526 if (ret) 1527 return ret; 1528 1529 /* 1530 * Some wifiband exclusion ranges may be already there 1531 * before our driver loaded. To make sure our driver 1532 * is awared of those exclusion ranges. 1533 */ 1534 schedule_delayed_work(&smu->wbrf_delayed_work, 1535 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1536 1537 return 0; 1538 } 1539 1540 /** 1541 * smu_wbrf_fini - tear down driver wbrf support 1542 * 1543 * @smu: smu_context pointer 1544 * 1545 * Unregisters with the wbrf notifier chain. 1546 */ 1547 static void smu_wbrf_fini(struct smu_context *smu) 1548 { 1549 if (!smu->wbrf_supported) 1550 return; 1551 1552 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1553 1554 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1555 } 1556 1557 static int smu_smc_hw_setup(struct smu_context *smu) 1558 { 1559 struct smu_feature *feature = &smu->smu_feature; 1560 struct amdgpu_device *adev = smu->adev; 1561 uint8_t pcie_gen = 0, pcie_width = 0; 1562 uint64_t features_supported; 1563 int ret = 0; 1564 1565 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1566 case IP_VERSION(11, 0, 7): 1567 case IP_VERSION(11, 0, 11): 1568 case IP_VERSION(11, 5, 0): 1569 case IP_VERSION(11, 0, 12): 1570 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1571 dev_info(adev->dev, "dpm has been enabled\n"); 1572 ret = smu_system_features_control(smu, true); 1573 if (ret) 1574 dev_err(adev->dev, "Failed system features control!\n"); 1575 return ret; 1576 } 1577 break; 1578 default: 1579 break; 1580 } 1581 1582 ret = smu_init_display_count(smu, 0); 1583 if (ret) { 1584 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1585 return ret; 1586 } 1587 1588 ret = smu_set_driver_table_location(smu); 1589 if (ret) { 1590 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1591 return ret; 1592 } 1593 1594 /* 1595 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1596 */ 1597 ret = smu_set_tool_table_location(smu); 1598 if (ret) { 1599 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1600 return ret; 1601 } 1602 1603 /* 1604 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1605 * pool location. 1606 */ 1607 ret = smu_notify_memory_pool_location(smu); 1608 if (ret) { 1609 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1610 return ret; 1611 } 1612 1613 /* 1614 * It is assumed the pptable used before runpm is same as 1615 * the one used afterwards. Thus, we can reuse the stored 1616 * copy and do not need to resetup the pptable again. 1617 */ 1618 if (!adev->in_runpm) { 1619 ret = smu_setup_pptable(smu); 1620 if (ret) { 1621 dev_err(adev->dev, "Failed to setup pptable!\n"); 1622 return ret; 1623 } 1624 } 1625 1626 /* smu_dump_pptable(smu); */ 1627 1628 /* 1629 * With SCPM enabled, PSP is responsible for the PPTable transferring 1630 * (to SMU). Driver involvement is not needed and permitted. 1631 */ 1632 if (!adev->scpm_enabled) { 1633 /* 1634 * Copy pptable bo in the vram to smc with SMU MSGs such as 1635 * SetDriverDramAddr and TransferTableDram2Smu. 1636 */ 1637 ret = smu_write_pptable(smu); 1638 if (ret) { 1639 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1640 return ret; 1641 } 1642 } 1643 1644 /* issue Run*Btc msg */ 1645 ret = smu_run_btc(smu); 1646 if (ret) 1647 return ret; 1648 1649 /* Enable UclkShadow on wbrf supported */ 1650 if (smu->wbrf_supported) { 1651 ret = smu_enable_uclk_shadow(smu, true); 1652 if (ret) { 1653 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1654 return ret; 1655 } 1656 } 1657 1658 /* 1659 * With SCPM enabled, these actions(and relevant messages) are 1660 * not needed and permitted. 1661 */ 1662 if (!adev->scpm_enabled) { 1663 ret = smu_feature_set_allowed_mask(smu); 1664 if (ret) { 1665 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1666 return ret; 1667 } 1668 } 1669 1670 ret = smu_system_features_control(smu, true); 1671 if (ret) { 1672 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1673 return ret; 1674 } 1675 1676 smu_init_xgmi_plpd_mode(smu); 1677 1678 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1679 if (ret) { 1680 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1681 return ret; 1682 } 1683 bitmap_copy(feature->supported, 1684 (unsigned long *)&features_supported, 1685 feature->feature_num); 1686 1687 if (!smu_is_dpm_running(smu)) 1688 dev_info(adev->dev, "dpm has been disabled\n"); 1689 1690 /* 1691 * Set initialized values (get from vbios) to dpm tables context such as 1692 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1693 * type of clks. 1694 */ 1695 ret = smu_set_default_dpm_table(smu); 1696 if (ret) { 1697 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1698 return ret; 1699 } 1700 1701 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) 1702 pcie_gen = 4; 1703 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1704 pcie_gen = 3; 1705 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1706 pcie_gen = 2; 1707 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1708 pcie_gen = 1; 1709 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1710 pcie_gen = 0; 1711 1712 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1713 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1714 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1715 */ 1716 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) 1717 pcie_width = 7; 1718 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1719 pcie_width = 6; 1720 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1721 pcie_width = 5; 1722 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1723 pcie_width = 4; 1724 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1725 pcie_width = 3; 1726 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1727 pcie_width = 2; 1728 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1729 pcie_width = 1; 1730 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1731 if (ret) { 1732 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1733 return ret; 1734 } 1735 1736 ret = smu_get_thermal_temperature_range(smu); 1737 if (ret) { 1738 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1739 return ret; 1740 } 1741 1742 ret = smu_enable_thermal_alert(smu); 1743 if (ret) { 1744 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1745 return ret; 1746 } 1747 1748 ret = smu_notify_display_change(smu); 1749 if (ret) { 1750 dev_err(adev->dev, "Failed to notify display change!\n"); 1751 return ret; 1752 } 1753 1754 /* 1755 * Set min deep sleep dce fclk with bootup value from vbios via 1756 * SetMinDeepSleepDcefclk MSG. 1757 */ 1758 ret = smu_set_min_dcef_deep_sleep(smu, 1759 smu->smu_table.boot_values.dcefclk / 100); 1760 if (ret) { 1761 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1762 return ret; 1763 } 1764 1765 /* Init wbrf support. Properly setup the notifier */ 1766 ret = smu_wbrf_init(smu); 1767 if (ret) 1768 dev_err(adev->dev, "Error during wbrf init call\n"); 1769 1770 return ret; 1771 } 1772 1773 static int smu_start_smc_engine(struct smu_context *smu) 1774 { 1775 struct amdgpu_device *adev = smu->adev; 1776 int ret = 0; 1777 1778 smu->smc_fw_state = SMU_FW_INIT; 1779 1780 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1781 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1782 if (smu->ppt_funcs->load_microcode) { 1783 ret = smu->ppt_funcs->load_microcode(smu); 1784 if (ret) 1785 return ret; 1786 } 1787 } 1788 } 1789 1790 if (smu->ppt_funcs->check_fw_status) { 1791 ret = smu->ppt_funcs->check_fw_status(smu); 1792 if (ret) { 1793 dev_err(adev->dev, "SMC is not ready\n"); 1794 return ret; 1795 } 1796 } 1797 1798 /* 1799 * Send msg GetDriverIfVersion to check if the return value is equal 1800 * with DRIVER_IF_VERSION of smc header. 1801 */ 1802 ret = smu_check_fw_version(smu); 1803 if (ret) 1804 return ret; 1805 1806 return ret; 1807 } 1808 1809 static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1810 { 1811 int i, ret; 1812 struct amdgpu_device *adev = ip_block->adev; 1813 struct smu_context *smu = adev->powerplay.pp_handle; 1814 1815 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1816 smu->pm_enabled = false; 1817 return 0; 1818 } 1819 1820 ret = smu_start_smc_engine(smu); 1821 if (ret) { 1822 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1823 return ret; 1824 } 1825 1826 /* 1827 * Check whether wbrf is supported. This needs to be done 1828 * before SMU setup starts since part of SMU configuration 1829 * relies on this. 1830 */ 1831 smu_wbrf_support_check(smu); 1832 1833 if (smu->is_apu) { 1834 ret = smu_set_gfx_imu_enable(smu); 1835 if (ret) 1836 return ret; 1837 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1838 smu_dpm_set_vcn_enable(smu, true, i); 1839 smu_dpm_set_jpeg_enable(smu, true); 1840 smu_dpm_set_vpe_enable(smu, true); 1841 smu_dpm_set_umsch_mm_enable(smu, true); 1842 smu_set_mall_enable(smu); 1843 smu_set_gfx_cgpg(smu, true); 1844 } 1845 1846 if (!smu->pm_enabled) 1847 return 0; 1848 1849 ret = smu_get_driver_allowed_feature_mask(smu); 1850 if (ret) 1851 return ret; 1852 1853 ret = smu_smc_hw_setup(smu); 1854 if (ret) { 1855 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1856 return ret; 1857 } 1858 1859 /* 1860 * Move maximum sustainable clock retrieving here considering 1861 * 1. It is not needed on resume(from S3). 1862 * 2. DAL settings come between .hw_init and .late_init of SMU. 1863 * And DAL needs to know the maximum sustainable clocks. Thus 1864 * it cannot be put in .late_init(). 1865 */ 1866 ret = smu_init_max_sustainable_clocks(smu); 1867 if (ret) { 1868 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1869 return ret; 1870 } 1871 1872 adev->pm.dpm_enabled = true; 1873 1874 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1875 1876 return 0; 1877 } 1878 1879 static int smu_disable_dpms(struct smu_context *smu) 1880 { 1881 struct amdgpu_device *adev = smu->adev; 1882 int ret = 0; 1883 bool use_baco = !smu->is_apu && 1884 ((amdgpu_in_reset(adev) && 1885 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1886 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1887 1888 /* 1889 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1890 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1891 */ 1892 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1893 case IP_VERSION(13, 0, 0): 1894 case IP_VERSION(13, 0, 7): 1895 case IP_VERSION(13, 0, 10): 1896 case IP_VERSION(14, 0, 2): 1897 case IP_VERSION(14, 0, 3): 1898 return 0; 1899 default: 1900 break; 1901 } 1902 1903 /* 1904 * For custom pptable uploading, skip the DPM features 1905 * disable process on Navi1x ASICs. 1906 * - As the gfx related features are under control of 1907 * RLC on those ASICs. RLC reinitialization will be 1908 * needed to reenable them. That will cost much more 1909 * efforts. 1910 * 1911 * - SMU firmware can handle the DPM reenablement 1912 * properly. 1913 */ 1914 if (smu->uploading_custom_pp_table) { 1915 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1916 case IP_VERSION(11, 0, 0): 1917 case IP_VERSION(11, 0, 5): 1918 case IP_VERSION(11, 0, 9): 1919 case IP_VERSION(11, 0, 7): 1920 case IP_VERSION(11, 0, 11): 1921 case IP_VERSION(11, 5, 0): 1922 case IP_VERSION(11, 0, 12): 1923 case IP_VERSION(11, 0, 13): 1924 return 0; 1925 default: 1926 break; 1927 } 1928 } 1929 1930 /* 1931 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1932 * on BACO in. Driver involvement is unnecessary. 1933 */ 1934 if (use_baco) { 1935 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1936 case IP_VERSION(11, 0, 7): 1937 case IP_VERSION(11, 0, 0): 1938 case IP_VERSION(11, 0, 5): 1939 case IP_VERSION(11, 0, 9): 1940 case IP_VERSION(13, 0, 7): 1941 return 0; 1942 default: 1943 break; 1944 } 1945 } 1946 1947 /* 1948 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 1949 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1950 */ 1951 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 1952 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 1953 return 0; 1954 1955 /* 1956 * For gpu reset, runpm and hibernation through BACO, 1957 * BACO feature has to be kept enabled. 1958 */ 1959 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1960 ret = smu_disable_all_features_with_exception(smu, 1961 SMU_FEATURE_BACO_BIT); 1962 if (ret) 1963 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1964 } else { 1965 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1966 if (!adev->scpm_enabled) { 1967 ret = smu_system_features_control(smu, false); 1968 if (ret) 1969 dev_err(adev->dev, "Failed to disable smu features.\n"); 1970 } 1971 } 1972 1973 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1974 * otherwise SMU will hang while interacting with RLC if RLC is halted 1975 * this is a WA for Vangogh asic which fix the SMU hang issue. 1976 */ 1977 ret = smu_notify_rlc_state(smu, false); 1978 if (ret) { 1979 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1980 return ret; 1981 } 1982 1983 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1984 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1985 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1986 adev->gfx.rlc.funcs->stop(adev); 1987 1988 return ret; 1989 } 1990 1991 static int smu_smc_hw_cleanup(struct smu_context *smu) 1992 { 1993 struct amdgpu_device *adev = smu->adev; 1994 int ret = 0; 1995 1996 smu_wbrf_fini(smu); 1997 1998 cancel_work_sync(&smu->throttling_logging_work); 1999 cancel_work_sync(&smu->interrupt_work); 2000 2001 ret = smu_disable_thermal_alert(smu); 2002 if (ret) { 2003 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 2004 return ret; 2005 } 2006 2007 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2008 2009 ret = smu_disable_dpms(smu); 2010 if (ret) { 2011 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2012 return ret; 2013 } 2014 2015 return 0; 2016 } 2017 2018 static int smu_reset_mp1_state(struct smu_context *smu) 2019 { 2020 struct amdgpu_device *adev = smu->adev; 2021 int ret = 0; 2022 2023 if ((!adev->in_runpm) && (!adev->in_suspend) && 2024 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 2025 IP_VERSION(13, 0, 10) && 2026 !amdgpu_device_has_display_hardware(adev)) 2027 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2028 2029 return ret; 2030 } 2031 2032 static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2033 { 2034 struct amdgpu_device *adev = ip_block->adev; 2035 struct smu_context *smu = adev->powerplay.pp_handle; 2036 int i, ret; 2037 2038 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2039 return 0; 2040 2041 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 2042 smu_dpm_set_vcn_enable(smu, false, i); 2043 smu_dpm_set_jpeg_enable(smu, false); 2044 smu_dpm_set_vpe_enable(smu, false); 2045 smu_dpm_set_umsch_mm_enable(smu, false); 2046 2047 adev->vcn.cur_state = AMD_PG_STATE_GATE; 2048 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2049 2050 if (!smu->pm_enabled) 2051 return 0; 2052 2053 adev->pm.dpm_enabled = false; 2054 2055 ret = smu_smc_hw_cleanup(smu); 2056 if (ret) 2057 return ret; 2058 2059 ret = smu_reset_mp1_state(smu); 2060 if (ret) 2061 return ret; 2062 2063 return 0; 2064 } 2065 2066 static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2067 { 2068 struct amdgpu_device *adev = ip_block->adev; 2069 struct smu_context *smu = adev->powerplay.pp_handle; 2070 2071 kfree(smu); 2072 } 2073 2074 static int smu_reset(struct smu_context *smu) 2075 { 2076 struct amdgpu_device *adev = smu->adev; 2077 struct amdgpu_ip_block *ip_block; 2078 int ret; 2079 2080 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2081 if (!ip_block) 2082 return -EINVAL; 2083 2084 ret = smu_hw_fini(ip_block); 2085 if (ret) 2086 return ret; 2087 2088 ret = smu_hw_init(ip_block); 2089 if (ret) 2090 return ret; 2091 2092 ret = smu_late_init(ip_block); 2093 if (ret) 2094 return ret; 2095 2096 return 0; 2097 } 2098 2099 static int smu_suspend(struct amdgpu_ip_block *ip_block) 2100 { 2101 struct amdgpu_device *adev = ip_block->adev; 2102 struct smu_context *smu = adev->powerplay.pp_handle; 2103 int ret; 2104 uint64_t count; 2105 2106 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2107 return 0; 2108 2109 if (!smu->pm_enabled) 2110 return 0; 2111 2112 adev->pm.dpm_enabled = false; 2113 2114 ret = smu_smc_hw_cleanup(smu); 2115 if (ret) 2116 return ret; 2117 2118 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2119 2120 smu_set_gfx_cgpg(smu, false); 2121 2122 /* 2123 * pwfw resets entrycount when device is suspended, so we save the 2124 * last value to be used when we resume to keep it consistent 2125 */ 2126 ret = smu_get_entrycount_gfxoff(smu, &count); 2127 if (!ret) 2128 adev->gfx.gfx_off_entrycount = count; 2129 2130 /* clear this on suspend so it will get reprogrammed on resume */ 2131 smu->workload_mask = 0; 2132 2133 return 0; 2134 } 2135 2136 static int smu_resume(struct amdgpu_ip_block *ip_block) 2137 { 2138 int ret; 2139 struct amdgpu_device *adev = ip_block->adev; 2140 struct smu_context *smu = adev->powerplay.pp_handle; 2141 2142 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2143 return 0; 2144 2145 if (!smu->pm_enabled) 2146 return 0; 2147 2148 dev_info(adev->dev, "SMU is resuming...\n"); 2149 2150 ret = smu_start_smc_engine(smu); 2151 if (ret) { 2152 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2153 return ret; 2154 } 2155 2156 ret = smu_smc_hw_setup(smu); 2157 if (ret) { 2158 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2159 return ret; 2160 } 2161 2162 ret = smu_set_gfx_imu_enable(smu); 2163 if (ret) 2164 return ret; 2165 2166 smu_set_gfx_cgpg(smu, true); 2167 2168 smu->disable_uclk_switch = 0; 2169 2170 adev->pm.dpm_enabled = true; 2171 2172 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2173 2174 return 0; 2175 } 2176 2177 static int smu_display_configuration_change(void *handle, 2178 const struct amd_pp_display_configuration *display_config) 2179 { 2180 struct smu_context *smu = handle; 2181 2182 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2183 return -EOPNOTSUPP; 2184 2185 if (!display_config) 2186 return -EINVAL; 2187 2188 smu_set_min_dcef_deep_sleep(smu, 2189 display_config->min_dcef_deep_sleep_set_clk / 100); 2190 2191 return 0; 2192 } 2193 2194 static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2195 enum amd_clockgating_state state) 2196 { 2197 return 0; 2198 } 2199 2200 static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block, 2201 enum amd_powergating_state state) 2202 { 2203 return 0; 2204 } 2205 2206 static int smu_enable_umd_pstate(void *handle, 2207 enum amd_dpm_forced_level *level) 2208 { 2209 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2210 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2211 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2212 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2213 2214 struct smu_context *smu = (struct smu_context*)(handle); 2215 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2216 2217 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2218 return -EINVAL; 2219 2220 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2221 /* enter umd pstate, save current level, disable gfx cg*/ 2222 if (*level & profile_mode_mask) { 2223 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2224 smu_gpo_control(smu, false); 2225 smu_gfx_ulv_control(smu, false); 2226 smu_deep_sleep_control(smu, false); 2227 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2228 } 2229 } else { 2230 /* exit umd pstate, restore level, enable gfx cg*/ 2231 if (!(*level & profile_mode_mask)) { 2232 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2233 *level = smu_dpm_ctx->saved_dpm_level; 2234 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2235 smu_deep_sleep_control(smu, true); 2236 smu_gfx_ulv_control(smu, true); 2237 smu_gpo_control(smu, true); 2238 } 2239 } 2240 2241 return 0; 2242 } 2243 2244 static int smu_bump_power_profile_mode(struct smu_context *smu, 2245 long *custom_params, 2246 u32 custom_params_max_idx) 2247 { 2248 u32 workload_mask = 0; 2249 int i, ret = 0; 2250 2251 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2252 if (smu->workload_refcount[i]) 2253 workload_mask |= 1 << i; 2254 } 2255 2256 if (smu->workload_mask == workload_mask) 2257 return 0; 2258 2259 if (smu->ppt_funcs->set_power_profile_mode) 2260 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask, 2261 custom_params, 2262 custom_params_max_idx); 2263 2264 if (!ret) 2265 smu->workload_mask = workload_mask; 2266 2267 return ret; 2268 } 2269 2270 static void smu_power_profile_mode_get(struct smu_context *smu, 2271 enum PP_SMC_POWER_PROFILE profile_mode) 2272 { 2273 smu->workload_refcount[profile_mode]++; 2274 } 2275 2276 static void smu_power_profile_mode_put(struct smu_context *smu, 2277 enum PP_SMC_POWER_PROFILE profile_mode) 2278 { 2279 if (smu->workload_refcount[profile_mode]) 2280 smu->workload_refcount[profile_mode]--; 2281 } 2282 2283 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2284 enum amd_dpm_forced_level level, 2285 bool skip_display_settings) 2286 { 2287 int ret = 0; 2288 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2289 2290 if (!skip_display_settings) { 2291 ret = smu_display_config_changed(smu); 2292 if (ret) { 2293 dev_err(smu->adev->dev, "Failed to change display config!"); 2294 return ret; 2295 } 2296 } 2297 2298 ret = smu_apply_clocks_adjust_rules(smu); 2299 if (ret) { 2300 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2301 return ret; 2302 } 2303 2304 if (!skip_display_settings) { 2305 ret = smu_notify_smc_display_config(smu); 2306 if (ret) { 2307 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2308 return ret; 2309 } 2310 } 2311 2312 if (smu_dpm_ctx->dpm_level != level) { 2313 ret = smu_asic_set_performance_level(smu, level); 2314 if (ret) { 2315 dev_err(smu->adev->dev, "Failed to set performance level!"); 2316 return ret; 2317 } 2318 2319 /* update the saved copy */ 2320 smu_dpm_ctx->dpm_level = level; 2321 } 2322 2323 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2324 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2325 smu_bump_power_profile_mode(smu, NULL, 0); 2326 2327 return ret; 2328 } 2329 2330 static int smu_handle_task(struct smu_context *smu, 2331 enum amd_dpm_forced_level level, 2332 enum amd_pp_task task_id) 2333 { 2334 int ret = 0; 2335 2336 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2337 return -EOPNOTSUPP; 2338 2339 switch (task_id) { 2340 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2341 ret = smu_pre_display_config_changed(smu); 2342 if (ret) 2343 return ret; 2344 ret = smu_adjust_power_state_dynamic(smu, level, false); 2345 break; 2346 case AMD_PP_TASK_COMPLETE_INIT: 2347 ret = smu_adjust_power_state_dynamic(smu, level, true); 2348 break; 2349 case AMD_PP_TASK_READJUST_POWER_STATE: 2350 ret = smu_adjust_power_state_dynamic(smu, level, true); 2351 break; 2352 default: 2353 break; 2354 } 2355 2356 return ret; 2357 } 2358 2359 static int smu_handle_dpm_task(void *handle, 2360 enum amd_pp_task task_id, 2361 enum amd_pm_state_type *user_state) 2362 { 2363 struct smu_context *smu = handle; 2364 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2365 2366 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2367 2368 } 2369 2370 static int smu_switch_power_profile(void *handle, 2371 enum PP_SMC_POWER_PROFILE type, 2372 bool enable) 2373 { 2374 struct smu_context *smu = handle; 2375 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2376 int ret; 2377 2378 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2379 return -EOPNOTSUPP; 2380 2381 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2382 return -EINVAL; 2383 2384 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2385 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2386 if (enable) 2387 smu_power_profile_mode_get(smu, type); 2388 else 2389 smu_power_profile_mode_put(smu, type); 2390 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2391 if (ret) { 2392 if (enable) 2393 smu_power_profile_mode_put(smu, type); 2394 else 2395 smu_power_profile_mode_get(smu, type); 2396 return ret; 2397 } 2398 } 2399 2400 return 0; 2401 } 2402 2403 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2404 { 2405 struct smu_context *smu = handle; 2406 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2407 2408 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2409 return -EOPNOTSUPP; 2410 2411 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2412 return -EINVAL; 2413 2414 return smu_dpm_ctx->dpm_level; 2415 } 2416 2417 static int smu_force_performance_level(void *handle, 2418 enum amd_dpm_forced_level level) 2419 { 2420 struct smu_context *smu = handle; 2421 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2422 int ret = 0; 2423 2424 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2425 return -EOPNOTSUPP; 2426 2427 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2428 return -EINVAL; 2429 2430 ret = smu_enable_umd_pstate(smu, &level); 2431 if (ret) 2432 return ret; 2433 2434 ret = smu_handle_task(smu, level, 2435 AMD_PP_TASK_READJUST_POWER_STATE); 2436 2437 /* reset user dpm clock state */ 2438 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2439 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2440 smu->user_dpm_profile.clk_dependency = 0; 2441 } 2442 2443 return ret; 2444 } 2445 2446 static int smu_set_display_count(void *handle, uint32_t count) 2447 { 2448 struct smu_context *smu = handle; 2449 2450 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2451 return -EOPNOTSUPP; 2452 2453 return smu_init_display_count(smu, count); 2454 } 2455 2456 static int smu_force_smuclk_levels(struct smu_context *smu, 2457 enum smu_clk_type clk_type, 2458 uint32_t mask) 2459 { 2460 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2461 int ret = 0; 2462 2463 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2464 return -EOPNOTSUPP; 2465 2466 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2467 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2468 return -EINVAL; 2469 } 2470 2471 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2472 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2473 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2474 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2475 smu_set_user_clk_dependencies(smu, clk_type); 2476 } 2477 } 2478 2479 return ret; 2480 } 2481 2482 static int smu_force_ppclk_levels(void *handle, 2483 enum pp_clock_type type, 2484 uint32_t mask) 2485 { 2486 struct smu_context *smu = handle; 2487 enum smu_clk_type clk_type; 2488 2489 switch (type) { 2490 case PP_SCLK: 2491 clk_type = SMU_SCLK; break; 2492 case PP_MCLK: 2493 clk_type = SMU_MCLK; break; 2494 case PP_PCIE: 2495 clk_type = SMU_PCIE; break; 2496 case PP_SOCCLK: 2497 clk_type = SMU_SOCCLK; break; 2498 case PP_FCLK: 2499 clk_type = SMU_FCLK; break; 2500 case PP_DCEFCLK: 2501 clk_type = SMU_DCEFCLK; break; 2502 case PP_VCLK: 2503 clk_type = SMU_VCLK; break; 2504 case PP_VCLK1: 2505 clk_type = SMU_VCLK1; break; 2506 case PP_DCLK: 2507 clk_type = SMU_DCLK; break; 2508 case PP_DCLK1: 2509 clk_type = SMU_DCLK1; break; 2510 case OD_SCLK: 2511 clk_type = SMU_OD_SCLK; break; 2512 case OD_MCLK: 2513 clk_type = SMU_OD_MCLK; break; 2514 case OD_VDDC_CURVE: 2515 clk_type = SMU_OD_VDDC_CURVE; break; 2516 case OD_RANGE: 2517 clk_type = SMU_OD_RANGE; break; 2518 default: 2519 return -EINVAL; 2520 } 2521 2522 return smu_force_smuclk_levels(smu, clk_type, mask); 2523 } 2524 2525 /* 2526 * On system suspending or resetting, the dpm_enabled 2527 * flag will be cleared. So that those SMU services which 2528 * are not supported will be gated. 2529 * However, the mp1 state setting should still be granted 2530 * even if the dpm_enabled cleared. 2531 */ 2532 static int smu_set_mp1_state(void *handle, 2533 enum pp_mp1_state mp1_state) 2534 { 2535 struct smu_context *smu = handle; 2536 int ret = 0; 2537 2538 if (!smu->pm_enabled) 2539 return -EOPNOTSUPP; 2540 2541 if (smu->ppt_funcs && 2542 smu->ppt_funcs->set_mp1_state) 2543 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2544 2545 return ret; 2546 } 2547 2548 static int smu_set_df_cstate(void *handle, 2549 enum pp_df_cstate state) 2550 { 2551 struct smu_context *smu = handle; 2552 int ret = 0; 2553 2554 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2555 return -EOPNOTSUPP; 2556 2557 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2558 return 0; 2559 2560 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2561 if (ret) 2562 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2563 2564 return ret; 2565 } 2566 2567 int smu_write_watermarks_table(struct smu_context *smu) 2568 { 2569 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2570 return -EOPNOTSUPP; 2571 2572 return smu_set_watermarks_table(smu, NULL); 2573 } 2574 2575 static int smu_set_watermarks_for_clock_ranges(void *handle, 2576 struct pp_smu_wm_range_sets *clock_ranges) 2577 { 2578 struct smu_context *smu = handle; 2579 2580 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2581 return -EOPNOTSUPP; 2582 2583 if (smu->disable_watermark) 2584 return 0; 2585 2586 return smu_set_watermarks_table(smu, clock_ranges); 2587 } 2588 2589 int smu_set_ac_dc(struct smu_context *smu) 2590 { 2591 int ret = 0; 2592 2593 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2594 return -EOPNOTSUPP; 2595 2596 /* controlled by firmware */ 2597 if (smu->dc_controlled_by_gpio) 2598 return 0; 2599 2600 ret = smu_set_power_source(smu, 2601 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2602 SMU_POWER_SOURCE_DC); 2603 if (ret) 2604 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2605 smu->adev->pm.ac_power ? "AC" : "DC"); 2606 2607 return ret; 2608 } 2609 2610 const struct amd_ip_funcs smu_ip_funcs = { 2611 .name = "smu", 2612 .early_init = smu_early_init, 2613 .late_init = smu_late_init, 2614 .sw_init = smu_sw_init, 2615 .sw_fini = smu_sw_fini, 2616 .hw_init = smu_hw_init, 2617 .hw_fini = smu_hw_fini, 2618 .late_fini = smu_late_fini, 2619 .suspend = smu_suspend, 2620 .resume = smu_resume, 2621 .is_idle = NULL, 2622 .check_soft_reset = NULL, 2623 .wait_for_idle = NULL, 2624 .soft_reset = NULL, 2625 .set_clockgating_state = smu_set_clockgating_state, 2626 .set_powergating_state = smu_set_powergating_state, 2627 }; 2628 2629 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2630 .type = AMD_IP_BLOCK_TYPE_SMC, 2631 .major = 11, 2632 .minor = 0, 2633 .rev = 0, 2634 .funcs = &smu_ip_funcs, 2635 }; 2636 2637 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2638 .type = AMD_IP_BLOCK_TYPE_SMC, 2639 .major = 12, 2640 .minor = 0, 2641 .rev = 0, 2642 .funcs = &smu_ip_funcs, 2643 }; 2644 2645 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2646 .type = AMD_IP_BLOCK_TYPE_SMC, 2647 .major = 13, 2648 .minor = 0, 2649 .rev = 0, 2650 .funcs = &smu_ip_funcs, 2651 }; 2652 2653 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2654 .type = AMD_IP_BLOCK_TYPE_SMC, 2655 .major = 14, 2656 .minor = 0, 2657 .rev = 0, 2658 .funcs = &smu_ip_funcs, 2659 }; 2660 2661 static int smu_load_microcode(void *handle) 2662 { 2663 struct smu_context *smu = handle; 2664 struct amdgpu_device *adev = smu->adev; 2665 int ret = 0; 2666 2667 if (!smu->pm_enabled) 2668 return -EOPNOTSUPP; 2669 2670 /* This should be used for non PSP loading */ 2671 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2672 return 0; 2673 2674 if (smu->ppt_funcs->load_microcode) { 2675 ret = smu->ppt_funcs->load_microcode(smu); 2676 if (ret) { 2677 dev_err(adev->dev, "Load microcode failed\n"); 2678 return ret; 2679 } 2680 } 2681 2682 if (smu->ppt_funcs->check_fw_status) { 2683 ret = smu->ppt_funcs->check_fw_status(smu); 2684 if (ret) { 2685 dev_err(adev->dev, "SMC is not ready\n"); 2686 return ret; 2687 } 2688 } 2689 2690 return ret; 2691 } 2692 2693 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2694 { 2695 int ret = 0; 2696 2697 if (smu->ppt_funcs->set_gfx_cgpg) 2698 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2699 2700 return ret; 2701 } 2702 2703 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2704 { 2705 struct smu_context *smu = handle; 2706 int ret = 0; 2707 2708 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2709 return -EOPNOTSUPP; 2710 2711 if (!smu->ppt_funcs->set_fan_speed_rpm) 2712 return -EOPNOTSUPP; 2713 2714 if (speed == U32_MAX) 2715 return -EINVAL; 2716 2717 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2718 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2719 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2720 smu->user_dpm_profile.fan_speed_rpm = speed; 2721 2722 /* Override custom PWM setting as they cannot co-exist */ 2723 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2724 smu->user_dpm_profile.fan_speed_pwm = 0; 2725 } 2726 2727 return ret; 2728 } 2729 2730 /** 2731 * smu_get_power_limit - Request one of the SMU Power Limits 2732 * 2733 * @handle: pointer to smu context 2734 * @limit: requested limit is written back to this variable 2735 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2736 * @pp_power_type: &pp_power_type type of power 2737 * Return: 0 on success, <0 on error 2738 * 2739 */ 2740 int smu_get_power_limit(void *handle, 2741 uint32_t *limit, 2742 enum pp_power_limit_level pp_limit_level, 2743 enum pp_power_type pp_power_type) 2744 { 2745 struct smu_context *smu = handle; 2746 struct amdgpu_device *adev = smu->adev; 2747 enum smu_ppt_limit_level limit_level; 2748 uint32_t limit_type; 2749 int ret = 0; 2750 2751 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2752 return -EOPNOTSUPP; 2753 2754 switch (pp_power_type) { 2755 case PP_PWR_TYPE_SUSTAINED: 2756 limit_type = SMU_DEFAULT_PPT_LIMIT; 2757 break; 2758 case PP_PWR_TYPE_FAST: 2759 limit_type = SMU_FAST_PPT_LIMIT; 2760 break; 2761 default: 2762 return -EOPNOTSUPP; 2763 } 2764 2765 switch (pp_limit_level) { 2766 case PP_PWR_LIMIT_CURRENT: 2767 limit_level = SMU_PPT_LIMIT_CURRENT; 2768 break; 2769 case PP_PWR_LIMIT_DEFAULT: 2770 limit_level = SMU_PPT_LIMIT_DEFAULT; 2771 break; 2772 case PP_PWR_LIMIT_MAX: 2773 limit_level = SMU_PPT_LIMIT_MAX; 2774 break; 2775 case PP_PWR_LIMIT_MIN: 2776 limit_level = SMU_PPT_LIMIT_MIN; 2777 break; 2778 default: 2779 return -EOPNOTSUPP; 2780 } 2781 2782 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2783 if (smu->ppt_funcs->get_ppt_limit) 2784 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2785 } else { 2786 switch (limit_level) { 2787 case SMU_PPT_LIMIT_CURRENT: 2788 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2789 case IP_VERSION(13, 0, 2): 2790 case IP_VERSION(13, 0, 6): 2791 case IP_VERSION(13, 0, 14): 2792 case IP_VERSION(11, 0, 7): 2793 case IP_VERSION(11, 0, 11): 2794 case IP_VERSION(11, 0, 12): 2795 case IP_VERSION(11, 0, 13): 2796 ret = smu_get_asic_power_limits(smu, 2797 &smu->current_power_limit, 2798 NULL, NULL, NULL); 2799 break; 2800 default: 2801 break; 2802 } 2803 *limit = smu->current_power_limit; 2804 break; 2805 case SMU_PPT_LIMIT_DEFAULT: 2806 *limit = smu->default_power_limit; 2807 break; 2808 case SMU_PPT_LIMIT_MAX: 2809 *limit = smu->max_power_limit; 2810 break; 2811 case SMU_PPT_LIMIT_MIN: 2812 *limit = smu->min_power_limit; 2813 break; 2814 default: 2815 return -EINVAL; 2816 } 2817 } 2818 2819 return ret; 2820 } 2821 2822 static int smu_set_power_limit(void *handle, uint32_t limit) 2823 { 2824 struct smu_context *smu = handle; 2825 uint32_t limit_type = limit >> 24; 2826 int ret = 0; 2827 2828 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2829 return -EOPNOTSUPP; 2830 2831 limit &= (1<<24)-1; 2832 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2833 if (smu->ppt_funcs->set_power_limit) 2834 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2835 2836 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2837 dev_err(smu->adev->dev, 2838 "New power limit (%d) is out of range [%d,%d]\n", 2839 limit, smu->min_power_limit, smu->max_power_limit); 2840 return -EINVAL; 2841 } 2842 2843 if (!limit) 2844 limit = smu->current_power_limit; 2845 2846 if (smu->ppt_funcs->set_power_limit) { 2847 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2848 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2849 smu->user_dpm_profile.power_limit = limit; 2850 } 2851 2852 return ret; 2853 } 2854 2855 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2856 { 2857 int ret = 0; 2858 2859 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2860 return -EOPNOTSUPP; 2861 2862 if (smu->ppt_funcs->print_clk_levels) 2863 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2864 2865 return ret; 2866 } 2867 2868 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2869 { 2870 enum smu_clk_type clk_type; 2871 2872 switch (type) { 2873 case PP_SCLK: 2874 clk_type = SMU_SCLK; break; 2875 case PP_MCLK: 2876 clk_type = SMU_MCLK; break; 2877 case PP_PCIE: 2878 clk_type = SMU_PCIE; break; 2879 case PP_SOCCLK: 2880 clk_type = SMU_SOCCLK; break; 2881 case PP_FCLK: 2882 clk_type = SMU_FCLK; break; 2883 case PP_DCEFCLK: 2884 clk_type = SMU_DCEFCLK; break; 2885 case PP_VCLK: 2886 clk_type = SMU_VCLK; break; 2887 case PP_VCLK1: 2888 clk_type = SMU_VCLK1; break; 2889 case PP_DCLK: 2890 clk_type = SMU_DCLK; break; 2891 case PP_DCLK1: 2892 clk_type = SMU_DCLK1; break; 2893 case OD_SCLK: 2894 clk_type = SMU_OD_SCLK; break; 2895 case OD_MCLK: 2896 clk_type = SMU_OD_MCLK; break; 2897 case OD_VDDC_CURVE: 2898 clk_type = SMU_OD_VDDC_CURVE; break; 2899 case OD_RANGE: 2900 clk_type = SMU_OD_RANGE; break; 2901 case OD_VDDGFX_OFFSET: 2902 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2903 case OD_CCLK: 2904 clk_type = SMU_OD_CCLK; break; 2905 case OD_FAN_CURVE: 2906 clk_type = SMU_OD_FAN_CURVE; break; 2907 case OD_ACOUSTIC_LIMIT: 2908 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2909 case OD_ACOUSTIC_TARGET: 2910 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2911 case OD_FAN_TARGET_TEMPERATURE: 2912 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2913 case OD_FAN_MINIMUM_PWM: 2914 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2915 case OD_FAN_ZERO_RPM_ENABLE: 2916 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 2917 case OD_FAN_ZERO_RPM_STOP_TEMP: 2918 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 2919 default: 2920 clk_type = SMU_CLK_COUNT; break; 2921 } 2922 2923 return clk_type; 2924 } 2925 2926 static int smu_print_ppclk_levels(void *handle, 2927 enum pp_clock_type type, 2928 char *buf) 2929 { 2930 struct smu_context *smu = handle; 2931 enum smu_clk_type clk_type; 2932 2933 clk_type = smu_convert_to_smuclk(type); 2934 if (clk_type == SMU_CLK_COUNT) 2935 return -EINVAL; 2936 2937 return smu_print_smuclk_levels(smu, clk_type, buf); 2938 } 2939 2940 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2941 { 2942 struct smu_context *smu = handle; 2943 enum smu_clk_type clk_type; 2944 2945 clk_type = smu_convert_to_smuclk(type); 2946 if (clk_type == SMU_CLK_COUNT) 2947 return -EINVAL; 2948 2949 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2950 return -EOPNOTSUPP; 2951 2952 if (!smu->ppt_funcs->emit_clk_levels) 2953 return -ENOENT; 2954 2955 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2956 2957 } 2958 2959 static int smu_od_edit_dpm_table(void *handle, 2960 enum PP_OD_DPM_TABLE_COMMAND type, 2961 long *input, uint32_t size) 2962 { 2963 struct smu_context *smu = handle; 2964 int ret = 0; 2965 2966 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2967 return -EOPNOTSUPP; 2968 2969 if (smu->ppt_funcs->od_edit_dpm_table) { 2970 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2971 } 2972 2973 return ret; 2974 } 2975 2976 static int smu_read_sensor(void *handle, 2977 int sensor, 2978 void *data, 2979 int *size_arg) 2980 { 2981 struct smu_context *smu = handle; 2982 struct amdgpu_device *adev = smu->adev; 2983 struct smu_umd_pstate_table *pstate_table = 2984 &smu->pstate_table; 2985 int i, ret = 0; 2986 uint32_t *size, size_val; 2987 2988 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2989 return -EOPNOTSUPP; 2990 2991 if (!data || !size_arg) 2992 return -EINVAL; 2993 2994 size_val = *size_arg; 2995 size = &size_val; 2996 2997 if (smu->ppt_funcs->read_sensor) 2998 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2999 goto unlock; 3000 3001 switch (sensor) { 3002 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 3003 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 3004 *size = 4; 3005 break; 3006 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 3007 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 3008 *size = 4; 3009 break; 3010 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 3011 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 3012 *size = 4; 3013 break; 3014 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 3015 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3016 *size = 4; 3017 break; 3018 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 3019 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 3020 *size = 8; 3021 break; 3022 case AMDGPU_PP_SENSOR_UVD_POWER: 3023 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3024 *size = 4; 3025 break; 3026 case AMDGPU_PP_SENSOR_VCE_POWER: 3027 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 3028 *size = 4; 3029 break; 3030 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3031 *(uint32_t *)data = 0; 3032 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 3033 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) { 3034 *(uint32_t *)data = 1; 3035 break; 3036 } 3037 } 3038 *size = 4; 3039 break; 3040 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3041 *(uint32_t *)data = 0; 3042 *size = 4; 3043 break; 3044 default: 3045 *size = 0; 3046 ret = -EOPNOTSUPP; 3047 break; 3048 } 3049 3050 unlock: 3051 // assign uint32_t to int 3052 *size_arg = size_val; 3053 3054 return ret; 3055 } 3056 3057 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3058 { 3059 int ret = -EOPNOTSUPP; 3060 struct smu_context *smu = handle; 3061 3062 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3063 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3064 3065 return ret; 3066 } 3067 3068 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3069 { 3070 int ret = -EOPNOTSUPP; 3071 struct smu_context *smu = handle; 3072 3073 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3074 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3075 3076 return ret; 3077 } 3078 3079 static int smu_get_power_profile_mode(void *handle, char *buf) 3080 { 3081 struct smu_context *smu = handle; 3082 3083 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3084 !smu->ppt_funcs->get_power_profile_mode) 3085 return -EOPNOTSUPP; 3086 if (!buf) 3087 return -EINVAL; 3088 3089 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3090 } 3091 3092 static int smu_set_power_profile_mode(void *handle, 3093 long *param, 3094 uint32_t param_size) 3095 { 3096 struct smu_context *smu = handle; 3097 bool custom = false; 3098 int ret = 0; 3099 3100 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3101 !smu->ppt_funcs->set_power_profile_mode) 3102 return -EOPNOTSUPP; 3103 3104 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) { 3105 custom = true; 3106 /* clear frontend mask so custom changes propogate */ 3107 smu->workload_mask = 0; 3108 } 3109 3110 if ((param[param_size] != smu->power_profile_mode) || custom) { 3111 /* clear the old user preference */ 3112 smu_power_profile_mode_put(smu, smu->power_profile_mode); 3113 /* set the new user preference */ 3114 smu_power_profile_mode_get(smu, param[param_size]); 3115 ret = smu_bump_power_profile_mode(smu, 3116 custom ? param : NULL, 3117 custom ? param_size : 0); 3118 if (ret) 3119 smu_power_profile_mode_put(smu, param[param_size]); 3120 else 3121 /* store the user's preference */ 3122 smu->power_profile_mode = param[param_size]; 3123 } 3124 3125 return ret; 3126 } 3127 3128 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3129 { 3130 struct smu_context *smu = handle; 3131 3132 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3133 return -EOPNOTSUPP; 3134 3135 if (!smu->ppt_funcs->get_fan_control_mode) 3136 return -EOPNOTSUPP; 3137 3138 if (!fan_mode) 3139 return -EINVAL; 3140 3141 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3142 3143 return 0; 3144 } 3145 3146 static int smu_set_fan_control_mode(void *handle, u32 value) 3147 { 3148 struct smu_context *smu = handle; 3149 int ret = 0; 3150 3151 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3152 return -EOPNOTSUPP; 3153 3154 if (!smu->ppt_funcs->set_fan_control_mode) 3155 return -EOPNOTSUPP; 3156 3157 if (value == U32_MAX) 3158 return -EINVAL; 3159 3160 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3161 if (ret) 3162 goto out; 3163 3164 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3165 smu->user_dpm_profile.fan_mode = value; 3166 3167 /* reset user dpm fan speed */ 3168 if (value != AMD_FAN_CTRL_MANUAL) { 3169 smu->user_dpm_profile.fan_speed_pwm = 0; 3170 smu->user_dpm_profile.fan_speed_rpm = 0; 3171 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3172 } 3173 } 3174 3175 out: 3176 return ret; 3177 } 3178 3179 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3180 { 3181 struct smu_context *smu = handle; 3182 int ret = 0; 3183 3184 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3185 return -EOPNOTSUPP; 3186 3187 if (!smu->ppt_funcs->get_fan_speed_pwm) 3188 return -EOPNOTSUPP; 3189 3190 if (!speed) 3191 return -EINVAL; 3192 3193 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3194 3195 return ret; 3196 } 3197 3198 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3199 { 3200 struct smu_context *smu = handle; 3201 int ret = 0; 3202 3203 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3204 return -EOPNOTSUPP; 3205 3206 if (!smu->ppt_funcs->set_fan_speed_pwm) 3207 return -EOPNOTSUPP; 3208 3209 if (speed == U32_MAX) 3210 return -EINVAL; 3211 3212 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3213 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3214 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3215 smu->user_dpm_profile.fan_speed_pwm = speed; 3216 3217 /* Override custom RPM setting as they cannot co-exist */ 3218 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3219 smu->user_dpm_profile.fan_speed_rpm = 0; 3220 } 3221 3222 return ret; 3223 } 3224 3225 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3226 { 3227 struct smu_context *smu = handle; 3228 int ret = 0; 3229 3230 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3231 return -EOPNOTSUPP; 3232 3233 if (!smu->ppt_funcs->get_fan_speed_rpm) 3234 return -EOPNOTSUPP; 3235 3236 if (!speed) 3237 return -EINVAL; 3238 3239 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3240 3241 return ret; 3242 } 3243 3244 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3245 { 3246 struct smu_context *smu = handle; 3247 3248 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3249 return -EOPNOTSUPP; 3250 3251 return smu_set_min_dcef_deep_sleep(smu, clk); 3252 } 3253 3254 static int smu_get_clock_by_type_with_latency(void *handle, 3255 enum amd_pp_clock_type type, 3256 struct pp_clock_levels_with_latency *clocks) 3257 { 3258 struct smu_context *smu = handle; 3259 enum smu_clk_type clk_type; 3260 int ret = 0; 3261 3262 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3263 return -EOPNOTSUPP; 3264 3265 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3266 switch (type) { 3267 case amd_pp_sys_clock: 3268 clk_type = SMU_GFXCLK; 3269 break; 3270 case amd_pp_mem_clock: 3271 clk_type = SMU_MCLK; 3272 break; 3273 case amd_pp_dcef_clock: 3274 clk_type = SMU_DCEFCLK; 3275 break; 3276 case amd_pp_disp_clock: 3277 clk_type = SMU_DISPCLK; 3278 break; 3279 default: 3280 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3281 return -EINVAL; 3282 } 3283 3284 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3285 } 3286 3287 return ret; 3288 } 3289 3290 static int smu_display_clock_voltage_request(void *handle, 3291 struct pp_display_clock_request *clock_req) 3292 { 3293 struct smu_context *smu = handle; 3294 int ret = 0; 3295 3296 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3297 return -EOPNOTSUPP; 3298 3299 if (smu->ppt_funcs->display_clock_voltage_request) 3300 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3301 3302 return ret; 3303 } 3304 3305 3306 static int smu_display_disable_memory_clock_switch(void *handle, 3307 bool disable_memory_clock_switch) 3308 { 3309 struct smu_context *smu = handle; 3310 int ret = -EINVAL; 3311 3312 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3313 return -EOPNOTSUPP; 3314 3315 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3316 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3317 3318 return ret; 3319 } 3320 3321 static int smu_set_xgmi_pstate(void *handle, 3322 uint32_t pstate) 3323 { 3324 struct smu_context *smu = handle; 3325 int ret = 0; 3326 3327 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3328 return -EOPNOTSUPP; 3329 3330 if (smu->ppt_funcs->set_xgmi_pstate) 3331 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3332 3333 if (ret) 3334 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3335 3336 return ret; 3337 } 3338 3339 static int smu_get_baco_capability(void *handle) 3340 { 3341 struct smu_context *smu = handle; 3342 3343 if (!smu->pm_enabled) 3344 return false; 3345 3346 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3347 return false; 3348 3349 return smu->ppt_funcs->get_bamaco_support(smu); 3350 } 3351 3352 static int smu_baco_set_state(void *handle, int state) 3353 { 3354 struct smu_context *smu = handle; 3355 int ret = 0; 3356 3357 if (!smu->pm_enabled) 3358 return -EOPNOTSUPP; 3359 3360 if (state == 0) { 3361 if (smu->ppt_funcs->baco_exit) 3362 ret = smu->ppt_funcs->baco_exit(smu); 3363 } else if (state == 1) { 3364 if (smu->ppt_funcs->baco_enter) 3365 ret = smu->ppt_funcs->baco_enter(smu); 3366 } else { 3367 return -EINVAL; 3368 } 3369 3370 if (ret) 3371 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3372 (state)?"enter":"exit"); 3373 3374 return ret; 3375 } 3376 3377 bool smu_mode1_reset_is_support(struct smu_context *smu) 3378 { 3379 bool ret = false; 3380 3381 if (!smu->pm_enabled) 3382 return false; 3383 3384 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3385 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3386 3387 return ret; 3388 } 3389 3390 bool smu_mode2_reset_is_support(struct smu_context *smu) 3391 { 3392 bool ret = false; 3393 3394 if (!smu->pm_enabled) 3395 return false; 3396 3397 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3398 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3399 3400 return ret; 3401 } 3402 3403 int smu_mode1_reset(struct smu_context *smu) 3404 { 3405 int ret = 0; 3406 3407 if (!smu->pm_enabled) 3408 return -EOPNOTSUPP; 3409 3410 if (smu->ppt_funcs->mode1_reset) 3411 ret = smu->ppt_funcs->mode1_reset(smu); 3412 3413 return ret; 3414 } 3415 3416 static int smu_mode2_reset(void *handle) 3417 { 3418 struct smu_context *smu = handle; 3419 int ret = 0; 3420 3421 if (!smu->pm_enabled) 3422 return -EOPNOTSUPP; 3423 3424 if (smu->ppt_funcs->mode2_reset) 3425 ret = smu->ppt_funcs->mode2_reset(smu); 3426 3427 if (ret) 3428 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3429 3430 return ret; 3431 } 3432 3433 static int smu_enable_gfx_features(void *handle) 3434 { 3435 struct smu_context *smu = handle; 3436 int ret = 0; 3437 3438 if (!smu->pm_enabled) 3439 return -EOPNOTSUPP; 3440 3441 if (smu->ppt_funcs->enable_gfx_features) 3442 ret = smu->ppt_funcs->enable_gfx_features(smu); 3443 3444 if (ret) 3445 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3446 3447 return ret; 3448 } 3449 3450 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3451 struct pp_smu_nv_clock_table *max_clocks) 3452 { 3453 struct smu_context *smu = handle; 3454 int ret = 0; 3455 3456 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3457 return -EOPNOTSUPP; 3458 3459 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3460 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3461 3462 return ret; 3463 } 3464 3465 static int smu_get_uclk_dpm_states(void *handle, 3466 unsigned int *clock_values_in_khz, 3467 unsigned int *num_states) 3468 { 3469 struct smu_context *smu = handle; 3470 int ret = 0; 3471 3472 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3473 return -EOPNOTSUPP; 3474 3475 if (smu->ppt_funcs->get_uclk_dpm_states) 3476 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3477 3478 return ret; 3479 } 3480 3481 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3482 { 3483 struct smu_context *smu = handle; 3484 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3485 3486 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3487 return -EOPNOTSUPP; 3488 3489 if (smu->ppt_funcs->get_current_power_state) 3490 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3491 3492 return pm_state; 3493 } 3494 3495 static int smu_get_dpm_clock_table(void *handle, 3496 struct dpm_clocks *clock_table) 3497 { 3498 struct smu_context *smu = handle; 3499 int ret = 0; 3500 3501 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3502 return -EOPNOTSUPP; 3503 3504 if (smu->ppt_funcs->get_dpm_clock_table) 3505 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3506 3507 return ret; 3508 } 3509 3510 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3511 { 3512 struct smu_context *smu = handle; 3513 3514 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3515 return -EOPNOTSUPP; 3516 3517 if (!smu->ppt_funcs->get_gpu_metrics) 3518 return -EOPNOTSUPP; 3519 3520 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3521 } 3522 3523 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3524 size_t size) 3525 { 3526 struct smu_context *smu = handle; 3527 3528 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3529 return -EOPNOTSUPP; 3530 3531 if (!smu->ppt_funcs->get_pm_metrics) 3532 return -EOPNOTSUPP; 3533 3534 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3535 } 3536 3537 static int smu_enable_mgpu_fan_boost(void *handle) 3538 { 3539 struct smu_context *smu = handle; 3540 int ret = 0; 3541 3542 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3543 return -EOPNOTSUPP; 3544 3545 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3546 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3547 3548 return ret; 3549 } 3550 3551 static int smu_gfx_state_change_set(void *handle, 3552 uint32_t state) 3553 { 3554 struct smu_context *smu = handle; 3555 int ret = 0; 3556 3557 if (smu->ppt_funcs->gfx_state_change_set) 3558 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3559 3560 return ret; 3561 } 3562 3563 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3564 { 3565 int ret = 0; 3566 3567 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3568 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3569 3570 return ret; 3571 } 3572 3573 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3574 { 3575 int ret = -EOPNOTSUPP; 3576 3577 if (smu->ppt_funcs && 3578 smu->ppt_funcs->get_ecc_info) 3579 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3580 3581 return ret; 3582 3583 } 3584 3585 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3586 { 3587 struct smu_context *smu = handle; 3588 struct smu_table_context *smu_table = &smu->smu_table; 3589 struct smu_table *memory_pool = &smu_table->memory_pool; 3590 3591 if (!addr || !size) 3592 return -EINVAL; 3593 3594 *addr = NULL; 3595 *size = 0; 3596 if (memory_pool->bo) { 3597 *addr = memory_pool->cpu_addr; 3598 *size = memory_pool->size; 3599 } 3600 3601 return 0; 3602 } 3603 3604 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3605 size_t *size) 3606 { 3607 size_t offset = *size; 3608 int level; 3609 3610 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3611 if (level == policy->current_level) 3612 offset += sysfs_emit_at(sysbuf, offset, 3613 "%d : %s*\n", level, 3614 policy->desc->get_desc(policy, level)); 3615 else 3616 offset += sysfs_emit_at(sysbuf, offset, 3617 "%d : %s\n", level, 3618 policy->desc->get_desc(policy, level)); 3619 } 3620 3621 *size = offset; 3622 } 3623 3624 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3625 enum pp_pm_policy p_type, char *sysbuf) 3626 { 3627 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3628 struct smu_dpm_policy_ctxt *policy_ctxt; 3629 struct smu_dpm_policy *dpm_policy; 3630 size_t offset = 0; 3631 3632 policy_ctxt = dpm_ctxt->dpm_policies; 3633 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3634 !policy_ctxt->policy_mask) 3635 return -EOPNOTSUPP; 3636 3637 if (p_type == PP_PM_POLICY_NONE) 3638 return -EINVAL; 3639 3640 dpm_policy = smu_get_pm_policy(smu, p_type); 3641 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3642 return -ENOENT; 3643 3644 if (!sysbuf) 3645 return -EINVAL; 3646 3647 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3648 3649 return offset; 3650 } 3651 3652 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3653 enum pp_pm_policy p_type) 3654 { 3655 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3656 struct smu_dpm_policy_ctxt *policy_ctxt; 3657 int i; 3658 3659 policy_ctxt = dpm_ctxt->dpm_policies; 3660 if (!policy_ctxt) 3661 return NULL; 3662 3663 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3664 if (policy_ctxt->policies[i].policy_type == p_type) 3665 return &policy_ctxt->policies[i]; 3666 } 3667 3668 return NULL; 3669 } 3670 3671 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3672 int level) 3673 { 3674 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3675 struct smu_dpm_policy *dpm_policy = NULL; 3676 struct smu_dpm_policy_ctxt *policy_ctxt; 3677 int ret = -EOPNOTSUPP; 3678 3679 policy_ctxt = dpm_ctxt->dpm_policies; 3680 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3681 !policy_ctxt->policy_mask) 3682 return ret; 3683 3684 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3685 return -EINVAL; 3686 3687 dpm_policy = smu_get_pm_policy(smu, p_type); 3688 3689 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3690 return ret; 3691 3692 if (dpm_policy->current_level == level) 3693 return 0; 3694 3695 ret = dpm_policy->set_policy(smu, level); 3696 3697 if (!ret) 3698 dpm_policy->current_level = level; 3699 3700 return ret; 3701 } 3702 3703 static const struct amd_pm_funcs swsmu_pm_funcs = { 3704 /* export for sysfs */ 3705 .set_fan_control_mode = smu_set_fan_control_mode, 3706 .get_fan_control_mode = smu_get_fan_control_mode, 3707 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3708 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3709 .force_clock_level = smu_force_ppclk_levels, 3710 .print_clock_levels = smu_print_ppclk_levels, 3711 .emit_clock_levels = smu_emit_ppclk_levels, 3712 .force_performance_level = smu_force_performance_level, 3713 .read_sensor = smu_read_sensor, 3714 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3715 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3716 .get_performance_level = smu_get_performance_level, 3717 .get_current_power_state = smu_get_current_power_state, 3718 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3719 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3720 .get_pp_num_states = smu_get_power_num_states, 3721 .get_pp_table = smu_sys_get_pp_table, 3722 .set_pp_table = smu_sys_set_pp_table, 3723 .switch_power_profile = smu_switch_power_profile, 3724 /* export to amdgpu */ 3725 .dispatch_tasks = smu_handle_dpm_task, 3726 .load_firmware = smu_load_microcode, 3727 .set_powergating_by_smu = smu_dpm_set_power_gate, 3728 .set_power_limit = smu_set_power_limit, 3729 .get_power_limit = smu_get_power_limit, 3730 .get_power_profile_mode = smu_get_power_profile_mode, 3731 .set_power_profile_mode = smu_set_power_profile_mode, 3732 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3733 .set_mp1_state = smu_set_mp1_state, 3734 .gfx_state_change_set = smu_gfx_state_change_set, 3735 /* export to DC */ 3736 .get_sclk = smu_get_sclk, 3737 .get_mclk = smu_get_mclk, 3738 .display_configuration_change = smu_display_configuration_change, 3739 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3740 .display_clock_voltage_request = smu_display_clock_voltage_request, 3741 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3742 .set_active_display_count = smu_set_display_count, 3743 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3744 .get_asic_baco_capability = smu_get_baco_capability, 3745 .set_asic_baco_state = smu_baco_set_state, 3746 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3747 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3748 .asic_reset_mode_2 = smu_mode2_reset, 3749 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3750 .set_df_cstate = smu_set_df_cstate, 3751 .set_xgmi_pstate = smu_set_xgmi_pstate, 3752 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3753 .get_pm_metrics = smu_sys_get_pm_metrics, 3754 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3755 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3756 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3757 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3758 .get_dpm_clock_table = smu_get_dpm_clock_table, 3759 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3760 }; 3761 3762 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3763 uint64_t event_arg) 3764 { 3765 int ret = -EINVAL; 3766 3767 if (smu->ppt_funcs->wait_for_event) 3768 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3769 3770 return ret; 3771 } 3772 3773 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3774 { 3775 3776 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3777 return -EOPNOTSUPP; 3778 3779 /* Confirm the buffer allocated is of correct size */ 3780 if (size != smu->stb_context.stb_buf_size) 3781 return -EINVAL; 3782 3783 /* 3784 * No need to lock smu mutex as we access STB directly through MMIO 3785 * and not going through SMU messaging route (for now at least). 3786 * For registers access rely on implementation internal locking. 3787 */ 3788 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3789 } 3790 3791 #if defined(CONFIG_DEBUG_FS) 3792 3793 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3794 { 3795 struct amdgpu_device *adev = filp->f_inode->i_private; 3796 struct smu_context *smu = adev->powerplay.pp_handle; 3797 unsigned char *buf; 3798 int r; 3799 3800 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3801 if (!buf) 3802 return -ENOMEM; 3803 3804 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3805 if (r) 3806 goto out; 3807 3808 filp->private_data = buf; 3809 3810 return 0; 3811 3812 out: 3813 kvfree(buf); 3814 return r; 3815 } 3816 3817 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3818 loff_t *pos) 3819 { 3820 struct amdgpu_device *adev = filp->f_inode->i_private; 3821 struct smu_context *smu = adev->powerplay.pp_handle; 3822 3823 3824 if (!filp->private_data) 3825 return -EINVAL; 3826 3827 return simple_read_from_buffer(buf, 3828 size, 3829 pos, filp->private_data, 3830 smu->stb_context.stb_buf_size); 3831 } 3832 3833 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3834 { 3835 kvfree(filp->private_data); 3836 filp->private_data = NULL; 3837 3838 return 0; 3839 } 3840 3841 /* 3842 * We have to define not only read method but also 3843 * open and release because .read takes up to PAGE_SIZE 3844 * data each time so and so is invoked multiple times. 3845 * We allocate the STB buffer in .open and release it 3846 * in .release 3847 */ 3848 static const struct file_operations smu_stb_debugfs_fops = { 3849 .owner = THIS_MODULE, 3850 .open = smu_stb_debugfs_open, 3851 .read = smu_stb_debugfs_read, 3852 .release = smu_stb_debugfs_release, 3853 .llseek = default_llseek, 3854 }; 3855 3856 #endif 3857 3858 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3859 { 3860 #if defined(CONFIG_DEBUG_FS) 3861 3862 struct smu_context *smu = adev->powerplay.pp_handle; 3863 3864 if (!smu || (!smu->stb_context.stb_buf_size)) 3865 return; 3866 3867 debugfs_create_file_size("amdgpu_smu_stb_dump", 3868 S_IRUSR, 3869 adev_to_drm(adev)->primary->debugfs_root, 3870 adev, 3871 &smu_stb_debugfs_fops, 3872 smu->stb_context.stb_buf_size); 3873 #endif 3874 } 3875 3876 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3877 { 3878 int ret = 0; 3879 3880 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3881 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3882 3883 return ret; 3884 } 3885 3886 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3887 { 3888 int ret = 0; 3889 3890 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3891 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3892 3893 return ret; 3894 } 3895 3896 int smu_send_rma_reason(struct smu_context *smu) 3897 { 3898 int ret = 0; 3899 3900 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3901 ret = smu->ppt_funcs->send_rma_reason(smu); 3902 3903 return ret; 3904 } 3905 3906 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask) 3907 { 3908 int ret = 0; 3909 3910 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma) 3911 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask); 3912 3913 return ret; 3914 } 3915