1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 76 static int smu_sys_get_pp_feature_mask(void *handle, 77 char *buf) 78 { 79 struct smu_context *smu = handle; 80 81 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 82 return -EOPNOTSUPP; 83 84 return smu_get_pp_feature_mask(smu, buf); 85 } 86 87 static int smu_sys_set_pp_feature_mask(void *handle, 88 uint64_t new_mask) 89 { 90 struct smu_context *smu = handle; 91 92 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 93 return -EOPNOTSUPP; 94 95 return smu_set_pp_feature_mask(smu, new_mask); 96 } 97 98 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 99 { 100 if (!smu->ppt_funcs->set_gfx_off_residency) 101 return -EINVAL; 102 103 return smu_set_gfx_off_residency(smu, value); 104 } 105 106 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 107 { 108 if (!smu->ppt_funcs->get_gfx_off_residency) 109 return -EINVAL; 110 111 return smu_get_gfx_off_residency(smu, value); 112 } 113 114 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 115 { 116 if (!smu->ppt_funcs->get_gfx_off_entrycount) 117 return -EINVAL; 118 119 return smu_get_gfx_off_entrycount(smu, value); 120 } 121 122 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 123 { 124 if (!smu->ppt_funcs->get_gfx_off_status) 125 return -EINVAL; 126 127 *value = smu_get_gfx_off_status(smu); 128 129 return 0; 130 } 131 132 int smu_set_soft_freq_range(struct smu_context *smu, 133 enum smu_clk_type clk_type, 134 uint32_t min, 135 uint32_t max) 136 { 137 int ret = 0; 138 139 if (smu->ppt_funcs->set_soft_freq_limited_range) 140 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 141 clk_type, 142 min, 143 max); 144 145 return ret; 146 } 147 148 int smu_get_dpm_freq_range(struct smu_context *smu, 149 enum smu_clk_type clk_type, 150 uint32_t *min, 151 uint32_t *max) 152 { 153 int ret = -ENOTSUPP; 154 155 if (!min && !max) 156 return -EINVAL; 157 158 if (smu->ppt_funcs->get_dpm_ultimate_freq) 159 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 160 clk_type, 161 min, 162 max); 163 164 return ret; 165 } 166 167 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 168 { 169 int ret = 0; 170 struct amdgpu_device *adev = smu->adev; 171 172 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 173 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 174 if (ret) 175 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 176 } 177 return ret; 178 } 179 180 static u32 smu_get_mclk(void *handle, bool low) 181 { 182 struct smu_context *smu = handle; 183 uint32_t clk_freq; 184 int ret = 0; 185 186 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 187 low ? &clk_freq : NULL, 188 !low ? &clk_freq : NULL); 189 if (ret) 190 return 0; 191 return clk_freq * 100; 192 } 193 194 static u32 smu_get_sclk(void *handle, bool low) 195 { 196 struct smu_context *smu = handle; 197 uint32_t clk_freq; 198 int ret = 0; 199 200 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 201 low ? &clk_freq : NULL, 202 !low ? &clk_freq : NULL); 203 if (ret) 204 return 0; 205 return clk_freq * 100; 206 } 207 208 static int smu_set_gfx_imu_enable(struct smu_context *smu) 209 { 210 struct amdgpu_device *adev = smu->adev; 211 212 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 213 return 0; 214 215 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 216 return 0; 217 218 return smu_set_gfx_power_up_by_imu(smu); 219 } 220 221 static bool is_vcn_enabled(struct amdgpu_device *adev) 222 { 223 int i; 224 225 for (i = 0; i < adev->num_ip_blocks; i++) { 226 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 227 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 228 !adev->ip_blocks[i].status.valid) 229 return false; 230 } 231 232 return true; 233 } 234 235 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 236 bool enable) 237 { 238 struct smu_power_context *smu_power = &smu->smu_power; 239 struct smu_power_gate *power_gate = &smu_power->power_gate; 240 int ret = 0; 241 242 /* 243 * don't poweron vcn/jpeg when they are skipped. 244 */ 245 if (!is_vcn_enabled(smu->adev)) 246 return 0; 247 248 if (!smu->ppt_funcs->dpm_set_vcn_enable) 249 return 0; 250 251 if (atomic_read(&power_gate->vcn_gated) ^ enable) 252 return 0; 253 254 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 255 if (!ret) 256 atomic_set(&power_gate->vcn_gated, !enable); 257 258 return ret; 259 } 260 261 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 262 bool enable) 263 { 264 struct smu_power_context *smu_power = &smu->smu_power; 265 struct smu_power_gate *power_gate = &smu_power->power_gate; 266 int ret = 0; 267 268 if (!is_vcn_enabled(smu->adev)) 269 return 0; 270 271 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 272 return 0; 273 274 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 275 return 0; 276 277 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 278 if (!ret) 279 atomic_set(&power_gate->jpeg_gated, !enable); 280 281 return ret; 282 } 283 284 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 285 bool enable) 286 { 287 struct smu_power_context *smu_power = &smu->smu_power; 288 struct smu_power_gate *power_gate = &smu_power->power_gate; 289 int ret = 0; 290 291 if (!smu->ppt_funcs->dpm_set_vpe_enable) 292 return 0; 293 294 if (atomic_read(&power_gate->vpe_gated) ^ enable) 295 return 0; 296 297 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 298 if (!ret) 299 atomic_set(&power_gate->vpe_gated, !enable); 300 301 return ret; 302 } 303 304 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 305 bool enable) 306 { 307 struct smu_power_context *smu_power = &smu->smu_power; 308 struct smu_power_gate *power_gate = &smu_power->power_gate; 309 int ret = 0; 310 311 if (!smu->adev->enable_umsch_mm) 312 return 0; 313 314 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 315 return 0; 316 317 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 318 return 0; 319 320 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 321 if (!ret) 322 atomic_set(&power_gate->umsch_mm_gated, !enable); 323 324 return ret; 325 } 326 327 /** 328 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 329 * 330 * @handle: smu_context pointer 331 * @block_type: the IP block to power gate/ungate 332 * @gate: to power gate if true, ungate otherwise 333 * 334 * This API uses no smu->mutex lock protection due to: 335 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 336 * This is guarded to be race condition free by the caller. 337 * 2. Or get called on user setting request of power_dpm_force_performance_level. 338 * Under this case, the smu->mutex lock protection is already enforced on 339 * the parent API smu_force_performance_level of the call path. 340 */ 341 static int smu_dpm_set_power_gate(void *handle, 342 uint32_t block_type, 343 bool gate) 344 { 345 struct smu_context *smu = handle; 346 int ret = 0; 347 348 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 349 dev_WARN(smu->adev->dev, 350 "SMU uninitialized but power %s requested for %u!\n", 351 gate ? "gate" : "ungate", block_type); 352 return -EOPNOTSUPP; 353 } 354 355 switch (block_type) { 356 /* 357 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 358 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 359 */ 360 case AMD_IP_BLOCK_TYPE_UVD: 361 case AMD_IP_BLOCK_TYPE_VCN: 362 ret = smu_dpm_set_vcn_enable(smu, !gate); 363 if (ret) 364 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 365 gate ? "gate" : "ungate"); 366 break; 367 case AMD_IP_BLOCK_TYPE_GFX: 368 ret = smu_gfx_off_control(smu, gate); 369 if (ret) 370 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 371 gate ? "enable" : "disable"); 372 break; 373 case AMD_IP_BLOCK_TYPE_SDMA: 374 ret = smu_powergate_sdma(smu, gate); 375 if (ret) 376 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 377 gate ? "gate" : "ungate"); 378 break; 379 case AMD_IP_BLOCK_TYPE_JPEG: 380 ret = smu_dpm_set_jpeg_enable(smu, !gate); 381 if (ret) 382 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 383 gate ? "gate" : "ungate"); 384 break; 385 case AMD_IP_BLOCK_TYPE_VPE: 386 ret = smu_dpm_set_vpe_enable(smu, !gate); 387 if (ret) 388 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 389 gate ? "gate" : "ungate"); 390 break; 391 default: 392 dev_err(smu->adev->dev, "Unsupported block type!\n"); 393 return -EINVAL; 394 } 395 396 return ret; 397 } 398 399 /** 400 * smu_set_user_clk_dependencies - set user profile clock dependencies 401 * 402 * @smu: smu_context pointer 403 * @clk: enum smu_clk_type type 404 * 405 * Enable/Disable the clock dependency for the @clk type. 406 */ 407 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 408 { 409 if (smu->adev->in_suspend) 410 return; 411 412 if (clk == SMU_MCLK) { 413 smu->user_dpm_profile.clk_dependency = 0; 414 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 415 } else if (clk == SMU_FCLK) { 416 /* MCLK takes precedence over FCLK */ 417 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 418 return; 419 420 smu->user_dpm_profile.clk_dependency = 0; 421 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 422 } else if (clk == SMU_SOCCLK) { 423 /* MCLK takes precedence over SOCCLK */ 424 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 425 return; 426 427 smu->user_dpm_profile.clk_dependency = 0; 428 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 429 } else 430 /* Add clk dependencies here, if any */ 431 return; 432 } 433 434 /** 435 * smu_restore_dpm_user_profile - reinstate user dpm profile 436 * 437 * @smu: smu_context pointer 438 * 439 * Restore the saved user power configurations include power limit, 440 * clock frequencies, fan control mode and fan speed. 441 */ 442 static void smu_restore_dpm_user_profile(struct smu_context *smu) 443 { 444 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 445 int ret = 0; 446 447 if (!smu->adev->in_suspend) 448 return; 449 450 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 451 return; 452 453 /* Enable restore flag */ 454 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 455 456 /* set the user dpm power limit */ 457 if (smu->user_dpm_profile.power_limit) { 458 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 459 if (ret) 460 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 461 } 462 463 /* set the user dpm clock configurations */ 464 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 465 enum smu_clk_type clk_type; 466 467 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 468 /* 469 * Iterate over smu clk type and force the saved user clk 470 * configs, skip if clock dependency is enabled 471 */ 472 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 473 smu->user_dpm_profile.clk_mask[clk_type]) { 474 ret = smu_force_smuclk_levels(smu, clk_type, 475 smu->user_dpm_profile.clk_mask[clk_type]); 476 if (ret) 477 dev_err(smu->adev->dev, 478 "Failed to set clock type = %d\n", clk_type); 479 } 480 } 481 } 482 483 /* set the user dpm fan configurations */ 484 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 485 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 486 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 487 if (ret != -EOPNOTSUPP) { 488 smu->user_dpm_profile.fan_speed_pwm = 0; 489 smu->user_dpm_profile.fan_speed_rpm = 0; 490 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 491 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 492 } 493 494 if (smu->user_dpm_profile.fan_speed_pwm) { 495 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 496 if (ret != -EOPNOTSUPP) 497 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 498 } 499 500 if (smu->user_dpm_profile.fan_speed_rpm) { 501 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 502 if (ret != -EOPNOTSUPP) 503 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 504 } 505 } 506 507 /* Restore user customized OD settings */ 508 if (smu->user_dpm_profile.user_od) { 509 if (smu->ppt_funcs->restore_user_od_settings) { 510 ret = smu->ppt_funcs->restore_user_od_settings(smu); 511 if (ret) 512 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 513 } 514 } 515 516 /* Disable restore flag */ 517 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 518 } 519 520 static int smu_get_power_num_states(void *handle, 521 struct pp_states_info *state_info) 522 { 523 if (!state_info) 524 return -EINVAL; 525 526 /* not support power state */ 527 memset(state_info, 0, sizeof(struct pp_states_info)); 528 state_info->nums = 1; 529 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 530 531 return 0; 532 } 533 534 bool is_support_sw_smu(struct amdgpu_device *adev) 535 { 536 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 537 if (adev->asic_type == CHIP_VEGA20) 538 return false; 539 540 if (amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) 541 return true; 542 543 return false; 544 } 545 546 bool is_support_cclk_dpm(struct amdgpu_device *adev) 547 { 548 struct smu_context *smu = adev->powerplay.pp_handle; 549 550 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 551 return false; 552 553 return true; 554 } 555 556 557 static int smu_sys_get_pp_table(void *handle, 558 char **table) 559 { 560 struct smu_context *smu = handle; 561 struct smu_table_context *smu_table = &smu->smu_table; 562 563 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 564 return -EOPNOTSUPP; 565 566 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 567 return -EINVAL; 568 569 if (smu_table->hardcode_pptable) 570 *table = smu_table->hardcode_pptable; 571 else 572 *table = smu_table->power_play_table; 573 574 return smu_table->power_play_table_size; 575 } 576 577 static int smu_sys_set_pp_table(void *handle, 578 const char *buf, 579 size_t size) 580 { 581 struct smu_context *smu = handle; 582 struct smu_table_context *smu_table = &smu->smu_table; 583 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 584 int ret = 0; 585 586 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 587 return -EOPNOTSUPP; 588 589 if (header->usStructureSize != size) { 590 dev_err(smu->adev->dev, "pp table size not matched !\n"); 591 return -EIO; 592 } 593 594 if (!smu_table->hardcode_pptable) { 595 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 596 if (!smu_table->hardcode_pptable) 597 return -ENOMEM; 598 } 599 600 memcpy(smu_table->hardcode_pptable, buf, size); 601 smu_table->power_play_table = smu_table->hardcode_pptable; 602 smu_table->power_play_table_size = size; 603 604 /* 605 * Special hw_fini action(for Navi1x, the DPMs disablement will be 606 * skipped) may be needed for custom pptable uploading. 607 */ 608 smu->uploading_custom_pp_table = true; 609 610 ret = smu_reset(smu); 611 if (ret) 612 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 613 614 smu->uploading_custom_pp_table = false; 615 616 return ret; 617 } 618 619 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 620 { 621 struct smu_feature *feature = &smu->smu_feature; 622 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 623 int ret = 0; 624 625 /* 626 * With SCPM enabled, the allowed featuremasks setting(via 627 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 628 * That means there is no way to let PMFW knows the settings below. 629 * Thus, we just assume all the features are allowed under 630 * such scenario. 631 */ 632 if (smu->adev->scpm_enabled) { 633 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 634 return 0; 635 } 636 637 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 638 639 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 640 SMU_FEATURE_MAX/32); 641 if (ret) 642 return ret; 643 644 bitmap_or(feature->allowed, feature->allowed, 645 (unsigned long *)allowed_feature_mask, 646 feature->feature_num); 647 648 return ret; 649 } 650 651 static int smu_set_funcs(struct amdgpu_device *adev) 652 { 653 struct smu_context *smu = adev->powerplay.pp_handle; 654 655 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 656 smu->od_enabled = true; 657 658 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 659 case IP_VERSION(11, 0, 0): 660 case IP_VERSION(11, 0, 5): 661 case IP_VERSION(11, 0, 9): 662 navi10_set_ppt_funcs(smu); 663 break; 664 case IP_VERSION(11, 0, 7): 665 case IP_VERSION(11, 0, 11): 666 case IP_VERSION(11, 0, 12): 667 case IP_VERSION(11, 0, 13): 668 sienna_cichlid_set_ppt_funcs(smu); 669 break; 670 case IP_VERSION(12, 0, 0): 671 case IP_VERSION(12, 0, 1): 672 renoir_set_ppt_funcs(smu); 673 break; 674 case IP_VERSION(11, 5, 0): 675 vangogh_set_ppt_funcs(smu); 676 break; 677 case IP_VERSION(13, 0, 1): 678 case IP_VERSION(13, 0, 3): 679 case IP_VERSION(13, 0, 8): 680 yellow_carp_set_ppt_funcs(smu); 681 break; 682 case IP_VERSION(13, 0, 4): 683 case IP_VERSION(13, 0, 11): 684 smu_v13_0_4_set_ppt_funcs(smu); 685 break; 686 case IP_VERSION(13, 0, 5): 687 smu_v13_0_5_set_ppt_funcs(smu); 688 break; 689 case IP_VERSION(11, 0, 8): 690 cyan_skillfish_set_ppt_funcs(smu); 691 break; 692 case IP_VERSION(11, 0, 2): 693 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 694 arcturus_set_ppt_funcs(smu); 695 /* OD is not supported on Arcturus */ 696 smu->od_enabled = false; 697 break; 698 case IP_VERSION(13, 0, 2): 699 aldebaran_set_ppt_funcs(smu); 700 /* Enable pp_od_clk_voltage node */ 701 smu->od_enabled = true; 702 break; 703 case IP_VERSION(13, 0, 0): 704 case IP_VERSION(13, 0, 10): 705 smu_v13_0_0_set_ppt_funcs(smu); 706 break; 707 case IP_VERSION(13, 0, 6): 708 case IP_VERSION(13, 0, 14): 709 smu_v13_0_6_set_ppt_funcs(smu); 710 /* Enable pp_od_clk_voltage node */ 711 smu->od_enabled = true; 712 break; 713 case IP_VERSION(13, 0, 7): 714 smu_v13_0_7_set_ppt_funcs(smu); 715 break; 716 case IP_VERSION(14, 0, 0): 717 case IP_VERSION(14, 0, 1): 718 smu_v14_0_0_set_ppt_funcs(smu); 719 break; 720 case IP_VERSION(14, 0, 2): 721 case IP_VERSION(14, 0, 3): 722 smu_v14_0_2_set_ppt_funcs(smu); 723 break; 724 default: 725 return -EINVAL; 726 } 727 728 return 0; 729 } 730 731 static int smu_early_init(void *handle) 732 { 733 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 734 struct smu_context *smu; 735 int r; 736 737 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 738 if (!smu) 739 return -ENOMEM; 740 741 smu->adev = adev; 742 smu->pm_enabled = !!amdgpu_dpm; 743 smu->is_apu = false; 744 smu->smu_baco.state = SMU_BACO_STATE_NONE; 745 smu->smu_baco.platform_support = false; 746 smu->smu_baco.maco_support = false; 747 smu->user_dpm_profile.fan_mode = -1; 748 749 mutex_init(&smu->message_lock); 750 751 adev->powerplay.pp_handle = smu; 752 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 753 754 r = smu_set_funcs(adev); 755 if (r) 756 return r; 757 return smu_init_microcode(smu); 758 } 759 760 static int smu_set_default_dpm_table(struct smu_context *smu) 761 { 762 struct amdgpu_device *adev = smu->adev; 763 struct smu_power_context *smu_power = &smu->smu_power; 764 struct smu_power_gate *power_gate = &smu_power->power_gate; 765 int vcn_gate, jpeg_gate; 766 int ret = 0; 767 768 if (!smu->ppt_funcs->set_default_dpm_table) 769 return 0; 770 771 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 772 vcn_gate = atomic_read(&power_gate->vcn_gated); 773 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 774 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 775 776 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 777 ret = smu_dpm_set_vcn_enable(smu, true); 778 if (ret) 779 return ret; 780 } 781 782 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 783 ret = smu_dpm_set_jpeg_enable(smu, true); 784 if (ret) 785 goto err_out; 786 } 787 788 ret = smu->ppt_funcs->set_default_dpm_table(smu); 789 if (ret) 790 dev_err(smu->adev->dev, 791 "Failed to setup default dpm clock tables!\n"); 792 793 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 794 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 795 err_out: 796 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 797 smu_dpm_set_vcn_enable(smu, !vcn_gate); 798 799 return ret; 800 } 801 802 static int smu_apply_default_config_table_settings(struct smu_context *smu) 803 { 804 struct amdgpu_device *adev = smu->adev; 805 int ret = 0; 806 807 ret = smu_get_default_config_table_settings(smu, 808 &adev->pm.config_table); 809 if (ret) 810 return ret; 811 812 return smu_set_config_table(smu, &adev->pm.config_table); 813 } 814 815 static int smu_late_init(void *handle) 816 { 817 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 818 struct smu_context *smu = adev->powerplay.pp_handle; 819 int ret = 0; 820 821 smu_set_fine_grain_gfx_freq_parameters(smu); 822 823 if (!smu->pm_enabled) 824 return 0; 825 826 ret = smu_post_init(smu); 827 if (ret) { 828 dev_err(adev->dev, "Failed to post smu init!\n"); 829 return ret; 830 } 831 832 /* 833 * Explicitly notify PMFW the power mode the system in. Since 834 * the PMFW may boot the ASIC with a different mode. 835 * For those supporting ACDC switch via gpio, PMFW will 836 * handle the switch automatically. Driver involvement 837 * is unnecessary. 838 */ 839 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 840 smu_set_ac_dc(smu); 841 842 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 843 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 844 return 0; 845 846 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 847 ret = smu_set_default_od_settings(smu); 848 if (ret) { 849 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 850 return ret; 851 } 852 } 853 854 ret = smu_populate_umd_state_clk(smu); 855 if (ret) { 856 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 857 return ret; 858 } 859 860 ret = smu_get_asic_power_limits(smu, 861 &smu->current_power_limit, 862 &smu->default_power_limit, 863 &smu->max_power_limit, 864 &smu->min_power_limit); 865 if (ret) { 866 dev_err(adev->dev, "Failed to get asic power limits!\n"); 867 return ret; 868 } 869 870 if (!amdgpu_sriov_vf(adev)) 871 smu_get_unique_id(smu); 872 873 smu_get_fan_parameters(smu); 874 875 smu_handle_task(smu, 876 smu->smu_dpm.dpm_level, 877 AMD_PP_TASK_COMPLETE_INIT); 878 879 ret = smu_apply_default_config_table_settings(smu); 880 if (ret && (ret != -EOPNOTSUPP)) { 881 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 882 return ret; 883 } 884 885 smu_restore_dpm_user_profile(smu); 886 887 return 0; 888 } 889 890 static int smu_init_fb_allocations(struct smu_context *smu) 891 { 892 struct amdgpu_device *adev = smu->adev; 893 struct smu_table_context *smu_table = &smu->smu_table; 894 struct smu_table *tables = smu_table->tables; 895 struct smu_table *driver_table = &(smu_table->driver_table); 896 uint32_t max_table_size = 0; 897 int ret, i; 898 899 /* VRAM allocation for tool table */ 900 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 901 ret = amdgpu_bo_create_kernel(adev, 902 tables[SMU_TABLE_PMSTATUSLOG].size, 903 tables[SMU_TABLE_PMSTATUSLOG].align, 904 tables[SMU_TABLE_PMSTATUSLOG].domain, 905 &tables[SMU_TABLE_PMSTATUSLOG].bo, 906 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 907 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 908 if (ret) { 909 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 910 return ret; 911 } 912 } 913 914 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 915 /* VRAM allocation for driver table */ 916 for (i = 0; i < SMU_TABLE_COUNT; i++) { 917 if (tables[i].size == 0) 918 continue; 919 920 /* If one of the tables has VRAM domain restriction, keep it in 921 * VRAM 922 */ 923 if ((tables[i].domain & 924 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 925 AMDGPU_GEM_DOMAIN_VRAM) 926 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 927 928 if (i == SMU_TABLE_PMSTATUSLOG) 929 continue; 930 931 if (max_table_size < tables[i].size) 932 max_table_size = tables[i].size; 933 } 934 935 driver_table->size = max_table_size; 936 driver_table->align = PAGE_SIZE; 937 938 ret = amdgpu_bo_create_kernel(adev, 939 driver_table->size, 940 driver_table->align, 941 driver_table->domain, 942 &driver_table->bo, 943 &driver_table->mc_address, 944 &driver_table->cpu_addr); 945 if (ret) { 946 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 947 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 948 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 949 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 950 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 951 } 952 953 return ret; 954 } 955 956 static int smu_fini_fb_allocations(struct smu_context *smu) 957 { 958 struct smu_table_context *smu_table = &smu->smu_table; 959 struct smu_table *tables = smu_table->tables; 960 struct smu_table *driver_table = &(smu_table->driver_table); 961 962 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 963 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 964 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 965 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 966 967 amdgpu_bo_free_kernel(&driver_table->bo, 968 &driver_table->mc_address, 969 &driver_table->cpu_addr); 970 971 return 0; 972 } 973 974 /** 975 * smu_alloc_memory_pool - allocate memory pool in the system memory 976 * 977 * @smu: amdgpu_device pointer 978 * 979 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 980 * and DramLogSetDramAddr can notify it changed. 981 * 982 * Returns 0 on success, error on failure. 983 */ 984 static int smu_alloc_memory_pool(struct smu_context *smu) 985 { 986 struct amdgpu_device *adev = smu->adev; 987 struct smu_table_context *smu_table = &smu->smu_table; 988 struct smu_table *memory_pool = &smu_table->memory_pool; 989 uint64_t pool_size = smu->pool_size; 990 int ret = 0; 991 992 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 993 return ret; 994 995 memory_pool->size = pool_size; 996 memory_pool->align = PAGE_SIZE; 997 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 998 999 switch (pool_size) { 1000 case SMU_MEMORY_POOL_SIZE_256_MB: 1001 case SMU_MEMORY_POOL_SIZE_512_MB: 1002 case SMU_MEMORY_POOL_SIZE_1_GB: 1003 case SMU_MEMORY_POOL_SIZE_2_GB: 1004 ret = amdgpu_bo_create_kernel(adev, 1005 memory_pool->size, 1006 memory_pool->align, 1007 memory_pool->domain, 1008 &memory_pool->bo, 1009 &memory_pool->mc_address, 1010 &memory_pool->cpu_addr); 1011 if (ret) 1012 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1013 break; 1014 default: 1015 break; 1016 } 1017 1018 return ret; 1019 } 1020 1021 static int smu_free_memory_pool(struct smu_context *smu) 1022 { 1023 struct smu_table_context *smu_table = &smu->smu_table; 1024 struct smu_table *memory_pool = &smu_table->memory_pool; 1025 1026 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1027 return 0; 1028 1029 amdgpu_bo_free_kernel(&memory_pool->bo, 1030 &memory_pool->mc_address, 1031 &memory_pool->cpu_addr); 1032 1033 memset(memory_pool, 0, sizeof(struct smu_table)); 1034 1035 return 0; 1036 } 1037 1038 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1039 { 1040 struct smu_table_context *smu_table = &smu->smu_table; 1041 struct smu_table *dummy_read_1_table = 1042 &smu_table->dummy_read_1_table; 1043 struct amdgpu_device *adev = smu->adev; 1044 int ret = 0; 1045 1046 if (!dummy_read_1_table->size) 1047 return 0; 1048 1049 ret = amdgpu_bo_create_kernel(adev, 1050 dummy_read_1_table->size, 1051 dummy_read_1_table->align, 1052 dummy_read_1_table->domain, 1053 &dummy_read_1_table->bo, 1054 &dummy_read_1_table->mc_address, 1055 &dummy_read_1_table->cpu_addr); 1056 if (ret) 1057 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1058 1059 return ret; 1060 } 1061 1062 static void smu_free_dummy_read_table(struct smu_context *smu) 1063 { 1064 struct smu_table_context *smu_table = &smu->smu_table; 1065 struct smu_table *dummy_read_1_table = 1066 &smu_table->dummy_read_1_table; 1067 1068 1069 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1070 &dummy_read_1_table->mc_address, 1071 &dummy_read_1_table->cpu_addr); 1072 1073 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1074 } 1075 1076 static int smu_smc_table_sw_init(struct smu_context *smu) 1077 { 1078 int ret; 1079 1080 /** 1081 * Create smu_table structure, and init smc tables such as 1082 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1083 */ 1084 ret = smu_init_smc_tables(smu); 1085 if (ret) { 1086 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1087 return ret; 1088 } 1089 1090 /** 1091 * Create smu_power_context structure, and allocate smu_dpm_context and 1092 * context size to fill the smu_power_context data. 1093 */ 1094 ret = smu_init_power(smu); 1095 if (ret) { 1096 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1097 return ret; 1098 } 1099 1100 /* 1101 * allocate vram bos to store smc table contents. 1102 */ 1103 ret = smu_init_fb_allocations(smu); 1104 if (ret) 1105 return ret; 1106 1107 ret = smu_alloc_memory_pool(smu); 1108 if (ret) 1109 return ret; 1110 1111 ret = smu_alloc_dummy_read_table(smu); 1112 if (ret) 1113 return ret; 1114 1115 ret = smu_i2c_init(smu); 1116 if (ret) 1117 return ret; 1118 1119 return 0; 1120 } 1121 1122 static int smu_smc_table_sw_fini(struct smu_context *smu) 1123 { 1124 int ret; 1125 1126 smu_i2c_fini(smu); 1127 1128 smu_free_dummy_read_table(smu); 1129 1130 ret = smu_free_memory_pool(smu); 1131 if (ret) 1132 return ret; 1133 1134 ret = smu_fini_fb_allocations(smu); 1135 if (ret) 1136 return ret; 1137 1138 ret = smu_fini_power(smu); 1139 if (ret) { 1140 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1141 return ret; 1142 } 1143 1144 ret = smu_fini_smc_tables(smu); 1145 if (ret) { 1146 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1147 return ret; 1148 } 1149 1150 return 0; 1151 } 1152 1153 static void smu_throttling_logging_work_fn(struct work_struct *work) 1154 { 1155 struct smu_context *smu = container_of(work, struct smu_context, 1156 throttling_logging_work); 1157 1158 smu_log_thermal_throttling(smu); 1159 } 1160 1161 static void smu_interrupt_work_fn(struct work_struct *work) 1162 { 1163 struct smu_context *smu = container_of(work, struct smu_context, 1164 interrupt_work); 1165 1166 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1167 smu->ppt_funcs->interrupt_work(smu); 1168 } 1169 1170 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1171 { 1172 struct smu_context *smu = 1173 container_of(work, struct smu_context, swctf_delayed_work.work); 1174 struct smu_temperature_range *range = 1175 &smu->thermal_range; 1176 struct amdgpu_device *adev = smu->adev; 1177 uint32_t hotspot_tmp, size; 1178 1179 /* 1180 * If the hotspot temperature is confirmed as below SW CTF setting point 1181 * after the delay enforced, nothing will be done. 1182 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1183 */ 1184 if (range->software_shutdown_temp && 1185 smu->ppt_funcs->read_sensor && 1186 !smu->ppt_funcs->read_sensor(smu, 1187 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1188 &hotspot_tmp, 1189 &size) && 1190 hotspot_tmp / 1000 < range->software_shutdown_temp) 1191 return; 1192 1193 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1194 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1195 orderly_poweroff(true); 1196 } 1197 1198 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1199 { 1200 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1201 smu->plpd_mode = XGMI_PLPD_DEFAULT; 1202 return; 1203 } 1204 1205 /* PMFW put PLPD into default policy after enabling the feature */ 1206 if (smu_feature_is_enabled(smu, 1207 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) 1208 smu->plpd_mode = XGMI_PLPD_DEFAULT; 1209 else 1210 smu->plpd_mode = XGMI_PLPD_NONE; 1211 } 1212 1213 static int smu_sw_init(void *handle) 1214 { 1215 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1216 struct smu_context *smu = adev->powerplay.pp_handle; 1217 int ret; 1218 1219 smu->pool_size = adev->pm.smu_prv_buffer_size; 1220 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1221 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1222 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1223 1224 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1225 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1226 atomic64_set(&smu->throttle_int_counter, 0); 1227 smu->watermarks_bitmap = 0; 1228 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1229 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1230 1231 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1232 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1233 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1234 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1235 1236 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1237 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1238 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1239 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1240 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1241 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1242 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1243 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1244 1245 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1246 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1247 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1248 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1249 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1250 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1251 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1252 smu->display_config = &adev->pm.pm_display_cfg; 1253 1254 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1255 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1256 1257 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1258 smu_swctf_delayed_work_handler); 1259 1260 ret = smu_smc_table_sw_init(smu); 1261 if (ret) { 1262 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1263 return ret; 1264 } 1265 1266 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1267 ret = smu_get_vbios_bootup_values(smu); 1268 if (ret) { 1269 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1270 return ret; 1271 } 1272 1273 ret = smu_init_pptable_microcode(smu); 1274 if (ret) { 1275 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1276 return ret; 1277 } 1278 1279 ret = smu_register_irq_handler(smu); 1280 if (ret) { 1281 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1282 return ret; 1283 } 1284 1285 /* If there is no way to query fan control mode, fan control is not supported */ 1286 if (!smu->ppt_funcs->get_fan_control_mode) 1287 smu->adev->pm.no_fan = true; 1288 1289 return 0; 1290 } 1291 1292 static int smu_sw_fini(void *handle) 1293 { 1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1295 struct smu_context *smu = adev->powerplay.pp_handle; 1296 int ret; 1297 1298 ret = smu_smc_table_sw_fini(smu); 1299 if (ret) { 1300 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1301 return ret; 1302 } 1303 1304 smu_fini_microcode(smu); 1305 1306 return 0; 1307 } 1308 1309 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1310 { 1311 struct amdgpu_device *adev = smu->adev; 1312 struct smu_temperature_range *range = 1313 &smu->thermal_range; 1314 int ret = 0; 1315 1316 if (!smu->ppt_funcs->get_thermal_temperature_range) 1317 return 0; 1318 1319 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1320 if (ret) 1321 return ret; 1322 1323 adev->pm.dpm.thermal.min_temp = range->min; 1324 adev->pm.dpm.thermal.max_temp = range->max; 1325 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1326 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1327 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1328 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1329 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1330 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1331 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1332 1333 return ret; 1334 } 1335 1336 /** 1337 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1338 * 1339 * @smu: smu_context pointer 1340 * 1341 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1342 * Returns 0 on success, error on failure. 1343 */ 1344 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1345 { 1346 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1347 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1348 struct amdgpu_device *adev = smu->adev; 1349 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1350 uint64_t start, end; 1351 int ret, i, j; 1352 1353 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1354 if (ret) { 1355 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1356 return ret; 1357 } 1358 1359 /* 1360 * The exclusion ranges array we got might be filled with holes and duplicate 1361 * entries. For example: 1362 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1363 * We need to do some sortups to eliminate those holes and duplicate entries. 1364 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1365 */ 1366 for (i = 0; i < num_of_wbrf_ranges; i++) { 1367 start = wifi_bands[i].start; 1368 end = wifi_bands[i].end; 1369 1370 /* get the last valid entry to fill the intermediate hole */ 1371 if (!start && !end) { 1372 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1373 if (wifi_bands[j].start && wifi_bands[j].end) 1374 break; 1375 1376 /* no valid entry left */ 1377 if (j <= i) 1378 break; 1379 1380 start = wifi_bands[i].start = wifi_bands[j].start; 1381 end = wifi_bands[i].end = wifi_bands[j].end; 1382 wifi_bands[j].start = 0; 1383 wifi_bands[j].end = 0; 1384 num_of_wbrf_ranges = j; 1385 } 1386 1387 /* eliminate duplicate entries */ 1388 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1389 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1390 wifi_bands[j].start = 0; 1391 wifi_bands[j].end = 0; 1392 } 1393 } 1394 } 1395 1396 /* Send the sorted wifi_bands to PMFW */ 1397 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1398 /* Try to set the wifi_bands again */ 1399 if (unlikely(ret == -EBUSY)) { 1400 mdelay(5); 1401 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1402 } 1403 1404 return ret; 1405 } 1406 1407 /** 1408 * smu_wbrf_event_handler - handle notify events 1409 * 1410 * @nb: notifier block 1411 * @action: event type 1412 * @_arg: event data 1413 * 1414 * Calls relevant amdgpu function in response to wbrf event 1415 * notification from kernel. 1416 */ 1417 static int smu_wbrf_event_handler(struct notifier_block *nb, 1418 unsigned long action, void *_arg) 1419 { 1420 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1421 1422 switch (action) { 1423 case WBRF_CHANGED: 1424 schedule_delayed_work(&smu->wbrf_delayed_work, 1425 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1426 break; 1427 default: 1428 return NOTIFY_DONE; 1429 } 1430 1431 return NOTIFY_OK; 1432 } 1433 1434 /** 1435 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1436 * 1437 * @work: struct work_struct pointer 1438 * 1439 * Flood is over and driver will consume the latest exclusion ranges. 1440 */ 1441 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1442 { 1443 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1444 1445 smu_wbrf_handle_exclusion_ranges(smu); 1446 } 1447 1448 /** 1449 * smu_wbrf_support_check - check wbrf support 1450 * 1451 * @smu: smu_context pointer 1452 * 1453 * Verifies the ACPI interface whether wbrf is supported. 1454 */ 1455 static void smu_wbrf_support_check(struct smu_context *smu) 1456 { 1457 struct amdgpu_device *adev = smu->adev; 1458 1459 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1460 acpi_amd_wbrf_supported_consumer(adev->dev); 1461 1462 if (smu->wbrf_supported) 1463 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1464 } 1465 1466 /** 1467 * smu_wbrf_init - init driver wbrf support 1468 * 1469 * @smu: smu_context pointer 1470 * 1471 * Verifies the AMD ACPI interfaces and registers with the wbrf 1472 * notifier chain if wbrf feature is supported. 1473 * Returns 0 on success, error on failure. 1474 */ 1475 static int smu_wbrf_init(struct smu_context *smu) 1476 { 1477 int ret; 1478 1479 if (!smu->wbrf_supported) 1480 return 0; 1481 1482 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1483 1484 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1485 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1486 if (ret) 1487 return ret; 1488 1489 /* 1490 * Some wifiband exclusion ranges may be already there 1491 * before our driver loaded. To make sure our driver 1492 * is awared of those exclusion ranges. 1493 */ 1494 schedule_delayed_work(&smu->wbrf_delayed_work, 1495 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1496 1497 return 0; 1498 } 1499 1500 /** 1501 * smu_wbrf_fini - tear down driver wbrf support 1502 * 1503 * @smu: smu_context pointer 1504 * 1505 * Unregisters with the wbrf notifier chain. 1506 */ 1507 static void smu_wbrf_fini(struct smu_context *smu) 1508 { 1509 if (!smu->wbrf_supported) 1510 return; 1511 1512 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1513 1514 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1515 } 1516 1517 static int smu_smc_hw_setup(struct smu_context *smu) 1518 { 1519 struct smu_feature *feature = &smu->smu_feature; 1520 struct amdgpu_device *adev = smu->adev; 1521 uint8_t pcie_gen = 0, pcie_width = 0; 1522 uint64_t features_supported; 1523 int ret = 0; 1524 1525 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1526 case IP_VERSION(11, 0, 7): 1527 case IP_VERSION(11, 0, 11): 1528 case IP_VERSION(11, 5, 0): 1529 case IP_VERSION(11, 0, 12): 1530 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1531 dev_info(adev->dev, "dpm has been enabled\n"); 1532 ret = smu_system_features_control(smu, true); 1533 if (ret) 1534 dev_err(adev->dev, "Failed system features control!\n"); 1535 return ret; 1536 } 1537 break; 1538 default: 1539 break; 1540 } 1541 1542 ret = smu_init_display_count(smu, 0); 1543 if (ret) { 1544 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1545 return ret; 1546 } 1547 1548 ret = smu_set_driver_table_location(smu); 1549 if (ret) { 1550 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1551 return ret; 1552 } 1553 1554 /* 1555 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1556 */ 1557 ret = smu_set_tool_table_location(smu); 1558 if (ret) { 1559 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1560 return ret; 1561 } 1562 1563 /* 1564 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1565 * pool location. 1566 */ 1567 ret = smu_notify_memory_pool_location(smu); 1568 if (ret) { 1569 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1570 return ret; 1571 } 1572 1573 /* 1574 * It is assumed the pptable used before runpm is same as 1575 * the one used afterwards. Thus, we can reuse the stored 1576 * copy and do not need to resetup the pptable again. 1577 */ 1578 if (!adev->in_runpm) { 1579 ret = smu_setup_pptable(smu); 1580 if (ret) { 1581 dev_err(adev->dev, "Failed to setup pptable!\n"); 1582 return ret; 1583 } 1584 } 1585 1586 /* smu_dump_pptable(smu); */ 1587 1588 /* 1589 * With SCPM enabled, PSP is responsible for the PPTable transferring 1590 * (to SMU). Driver involvement is not needed and permitted. 1591 */ 1592 if (!adev->scpm_enabled) { 1593 /* 1594 * Copy pptable bo in the vram to smc with SMU MSGs such as 1595 * SetDriverDramAddr and TransferTableDram2Smu. 1596 */ 1597 ret = smu_write_pptable(smu); 1598 if (ret) { 1599 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1600 return ret; 1601 } 1602 } 1603 1604 /* issue Run*Btc msg */ 1605 ret = smu_run_btc(smu); 1606 if (ret) 1607 return ret; 1608 1609 /* Enable UclkShadow on wbrf supported */ 1610 if (smu->wbrf_supported) { 1611 ret = smu_enable_uclk_shadow(smu, true); 1612 if (ret) { 1613 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1614 return ret; 1615 } 1616 } 1617 1618 /* 1619 * With SCPM enabled, these actions(and relevant messages) are 1620 * not needed and permitted. 1621 */ 1622 if (!adev->scpm_enabled) { 1623 ret = smu_feature_set_allowed_mask(smu); 1624 if (ret) { 1625 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1626 return ret; 1627 } 1628 } 1629 1630 ret = smu_system_features_control(smu, true); 1631 if (ret) { 1632 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1633 return ret; 1634 } 1635 1636 smu_init_xgmi_plpd_mode(smu); 1637 1638 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1639 if (ret) { 1640 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1641 return ret; 1642 } 1643 bitmap_copy(feature->supported, 1644 (unsigned long *)&features_supported, 1645 feature->feature_num); 1646 1647 if (!smu_is_dpm_running(smu)) 1648 dev_info(adev->dev, "dpm has been disabled\n"); 1649 1650 /* 1651 * Set initialized values (get from vbios) to dpm tables context such as 1652 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1653 * type of clks. 1654 */ 1655 ret = smu_set_default_dpm_table(smu); 1656 if (ret) { 1657 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1658 return ret; 1659 } 1660 1661 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1662 pcie_gen = 3; 1663 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1664 pcie_gen = 2; 1665 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1666 pcie_gen = 1; 1667 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1668 pcie_gen = 0; 1669 1670 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1671 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1672 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1673 */ 1674 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1675 pcie_width = 6; 1676 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1677 pcie_width = 5; 1678 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1679 pcie_width = 4; 1680 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1681 pcie_width = 3; 1682 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1683 pcie_width = 2; 1684 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1685 pcie_width = 1; 1686 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1687 if (ret) { 1688 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1689 return ret; 1690 } 1691 1692 ret = smu_get_thermal_temperature_range(smu); 1693 if (ret) { 1694 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1695 return ret; 1696 } 1697 1698 ret = smu_enable_thermal_alert(smu); 1699 if (ret) { 1700 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1701 return ret; 1702 } 1703 1704 ret = smu_notify_display_change(smu); 1705 if (ret) { 1706 dev_err(adev->dev, "Failed to notify display change!\n"); 1707 return ret; 1708 } 1709 1710 /* 1711 * Set min deep sleep dce fclk with bootup value from vbios via 1712 * SetMinDeepSleepDcefclk MSG. 1713 */ 1714 ret = smu_set_min_dcef_deep_sleep(smu, 1715 smu->smu_table.boot_values.dcefclk / 100); 1716 if (ret) { 1717 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1718 return ret; 1719 } 1720 1721 /* Init wbrf support. Properly setup the notifier */ 1722 ret = smu_wbrf_init(smu); 1723 if (ret) 1724 dev_err(adev->dev, "Error during wbrf init call\n"); 1725 1726 return ret; 1727 } 1728 1729 static int smu_start_smc_engine(struct smu_context *smu) 1730 { 1731 struct amdgpu_device *adev = smu->adev; 1732 int ret = 0; 1733 1734 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1735 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1736 if (smu->ppt_funcs->load_microcode) { 1737 ret = smu->ppt_funcs->load_microcode(smu); 1738 if (ret) 1739 return ret; 1740 } 1741 } 1742 } 1743 1744 if (smu->ppt_funcs->check_fw_status) { 1745 ret = smu->ppt_funcs->check_fw_status(smu); 1746 if (ret) { 1747 dev_err(adev->dev, "SMC is not ready\n"); 1748 return ret; 1749 } 1750 } 1751 1752 /* 1753 * Send msg GetDriverIfVersion to check if the return value is equal 1754 * with DRIVER_IF_VERSION of smc header. 1755 */ 1756 ret = smu_check_fw_version(smu); 1757 if (ret) 1758 return ret; 1759 1760 return ret; 1761 } 1762 1763 static int smu_hw_init(void *handle) 1764 { 1765 int ret; 1766 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1767 struct smu_context *smu = adev->powerplay.pp_handle; 1768 1769 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1770 smu->pm_enabled = false; 1771 return 0; 1772 } 1773 1774 ret = smu_start_smc_engine(smu); 1775 if (ret) { 1776 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1777 return ret; 1778 } 1779 1780 /* 1781 * Check whether wbrf is supported. This needs to be done 1782 * before SMU setup starts since part of SMU configuration 1783 * relies on this. 1784 */ 1785 smu_wbrf_support_check(smu); 1786 1787 if (smu->is_apu) { 1788 ret = smu_set_gfx_imu_enable(smu); 1789 if (ret) 1790 return ret; 1791 smu_dpm_set_vcn_enable(smu, true); 1792 smu_dpm_set_jpeg_enable(smu, true); 1793 smu_dpm_set_vpe_enable(smu, true); 1794 smu_dpm_set_umsch_mm_enable(smu, true); 1795 smu_set_gfx_cgpg(smu, true); 1796 } 1797 1798 if (!smu->pm_enabled) 1799 return 0; 1800 1801 ret = smu_get_driver_allowed_feature_mask(smu); 1802 if (ret) 1803 return ret; 1804 1805 ret = smu_smc_hw_setup(smu); 1806 if (ret) { 1807 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1808 return ret; 1809 } 1810 1811 /* 1812 * Move maximum sustainable clock retrieving here considering 1813 * 1. It is not needed on resume(from S3). 1814 * 2. DAL settings come between .hw_init and .late_init of SMU. 1815 * And DAL needs to know the maximum sustainable clocks. Thus 1816 * it cannot be put in .late_init(). 1817 */ 1818 ret = smu_init_max_sustainable_clocks(smu); 1819 if (ret) { 1820 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1821 return ret; 1822 } 1823 1824 adev->pm.dpm_enabled = true; 1825 1826 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1827 1828 return 0; 1829 } 1830 1831 static int smu_disable_dpms(struct smu_context *smu) 1832 { 1833 struct amdgpu_device *adev = smu->adev; 1834 int ret = 0; 1835 bool use_baco = !smu->is_apu && 1836 ((amdgpu_in_reset(adev) && 1837 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1838 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1839 1840 /* 1841 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1842 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1843 */ 1844 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1845 case IP_VERSION(13, 0, 0): 1846 case IP_VERSION(13, 0, 7): 1847 case IP_VERSION(13, 0, 10): 1848 case IP_VERSION(14, 0, 2): 1849 case IP_VERSION(14, 0, 3): 1850 return 0; 1851 default: 1852 break; 1853 } 1854 1855 /* 1856 * For custom pptable uploading, skip the DPM features 1857 * disable process on Navi1x ASICs. 1858 * - As the gfx related features are under control of 1859 * RLC on those ASICs. RLC reinitialization will be 1860 * needed to reenable them. That will cost much more 1861 * efforts. 1862 * 1863 * - SMU firmware can handle the DPM reenablement 1864 * properly. 1865 */ 1866 if (smu->uploading_custom_pp_table) { 1867 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1868 case IP_VERSION(11, 0, 0): 1869 case IP_VERSION(11, 0, 5): 1870 case IP_VERSION(11, 0, 9): 1871 case IP_VERSION(11, 0, 7): 1872 case IP_VERSION(11, 0, 11): 1873 case IP_VERSION(11, 5, 0): 1874 case IP_VERSION(11, 0, 12): 1875 case IP_VERSION(11, 0, 13): 1876 return 0; 1877 default: 1878 break; 1879 } 1880 } 1881 1882 /* 1883 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1884 * on BACO in. Driver involvement is unnecessary. 1885 */ 1886 if (use_baco) { 1887 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1888 case IP_VERSION(11, 0, 7): 1889 case IP_VERSION(11, 0, 0): 1890 case IP_VERSION(11, 0, 5): 1891 case IP_VERSION(11, 0, 9): 1892 case IP_VERSION(13, 0, 7): 1893 return 0; 1894 default: 1895 break; 1896 } 1897 } 1898 1899 /* 1900 * For SMU 13.0.4/11 and 14.0.0, PMFW will handle the features disablement properly 1901 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1902 */ 1903 if (amdgpu_in_reset(adev) || adev->in_s0ix) { 1904 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1905 case IP_VERSION(13, 0, 4): 1906 case IP_VERSION(13, 0, 11): 1907 case IP_VERSION(14, 0, 0): 1908 case IP_VERSION(14, 0, 1): 1909 return 0; 1910 default: 1911 break; 1912 } 1913 } 1914 1915 /* 1916 * For gpu reset, runpm and hibernation through BACO, 1917 * BACO feature has to be kept enabled. 1918 */ 1919 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1920 ret = smu_disable_all_features_with_exception(smu, 1921 SMU_FEATURE_BACO_BIT); 1922 if (ret) 1923 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1924 } else { 1925 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1926 if (!adev->scpm_enabled) { 1927 ret = smu_system_features_control(smu, false); 1928 if (ret) 1929 dev_err(adev->dev, "Failed to disable smu features.\n"); 1930 } 1931 } 1932 1933 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1934 * otherwise SMU will hang while interacting with RLC if RLC is halted 1935 * this is a WA for Vangogh asic which fix the SMU hang issue. 1936 */ 1937 ret = smu_notify_rlc_state(smu, false); 1938 if (ret) { 1939 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1940 return ret; 1941 } 1942 1943 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1944 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1945 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1946 adev->gfx.rlc.funcs->stop(adev); 1947 1948 return ret; 1949 } 1950 1951 static int smu_smc_hw_cleanup(struct smu_context *smu) 1952 { 1953 struct amdgpu_device *adev = smu->adev; 1954 int ret = 0; 1955 1956 smu_wbrf_fini(smu); 1957 1958 cancel_work_sync(&smu->throttling_logging_work); 1959 cancel_work_sync(&smu->interrupt_work); 1960 1961 ret = smu_disable_thermal_alert(smu); 1962 if (ret) { 1963 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1964 return ret; 1965 } 1966 1967 cancel_delayed_work_sync(&smu->swctf_delayed_work); 1968 1969 ret = smu_disable_dpms(smu); 1970 if (ret) { 1971 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1972 return ret; 1973 } 1974 1975 return 0; 1976 } 1977 1978 static int smu_reset_mp1_state(struct smu_context *smu) 1979 { 1980 struct amdgpu_device *adev = smu->adev; 1981 int ret = 0; 1982 1983 if ((!adev->in_runpm) && (!adev->in_suspend) && 1984 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 1985 IP_VERSION(13, 0, 10) && 1986 !amdgpu_device_has_display_hardware(adev)) 1987 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 1988 1989 return ret; 1990 } 1991 1992 static int smu_hw_fini(void *handle) 1993 { 1994 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1995 struct smu_context *smu = adev->powerplay.pp_handle; 1996 int ret; 1997 1998 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 1999 return 0; 2000 2001 smu_dpm_set_vcn_enable(smu, false); 2002 smu_dpm_set_jpeg_enable(smu, false); 2003 smu_dpm_set_vpe_enable(smu, false); 2004 smu_dpm_set_umsch_mm_enable(smu, false); 2005 2006 adev->vcn.cur_state = AMD_PG_STATE_GATE; 2007 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2008 2009 if (!smu->pm_enabled) 2010 return 0; 2011 2012 adev->pm.dpm_enabled = false; 2013 2014 ret = smu_smc_hw_cleanup(smu); 2015 if (ret) 2016 return ret; 2017 2018 ret = smu_reset_mp1_state(smu); 2019 if (ret) 2020 return ret; 2021 2022 return 0; 2023 } 2024 2025 static void smu_late_fini(void *handle) 2026 { 2027 struct amdgpu_device *adev = handle; 2028 struct smu_context *smu = adev->powerplay.pp_handle; 2029 2030 kfree(smu); 2031 } 2032 2033 static int smu_reset(struct smu_context *smu) 2034 { 2035 struct amdgpu_device *adev = smu->adev; 2036 int ret; 2037 2038 ret = smu_hw_fini(adev); 2039 if (ret) 2040 return ret; 2041 2042 ret = smu_hw_init(adev); 2043 if (ret) 2044 return ret; 2045 2046 ret = smu_late_init(adev); 2047 if (ret) 2048 return ret; 2049 2050 return 0; 2051 } 2052 2053 static int smu_suspend(void *handle) 2054 { 2055 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2056 struct smu_context *smu = adev->powerplay.pp_handle; 2057 int ret; 2058 uint64_t count; 2059 2060 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2061 return 0; 2062 2063 if (!smu->pm_enabled) 2064 return 0; 2065 2066 adev->pm.dpm_enabled = false; 2067 2068 ret = smu_smc_hw_cleanup(smu); 2069 if (ret) 2070 return ret; 2071 2072 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2073 2074 smu_set_gfx_cgpg(smu, false); 2075 2076 /* 2077 * pwfw resets entrycount when device is suspended, so we save the 2078 * last value to be used when we resume to keep it consistent 2079 */ 2080 ret = smu_get_entrycount_gfxoff(smu, &count); 2081 if (!ret) 2082 adev->gfx.gfx_off_entrycount = count; 2083 2084 return 0; 2085 } 2086 2087 static int smu_resume(void *handle) 2088 { 2089 int ret; 2090 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2091 struct smu_context *smu = adev->powerplay.pp_handle; 2092 2093 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2094 return 0; 2095 2096 if (!smu->pm_enabled) 2097 return 0; 2098 2099 dev_info(adev->dev, "SMU is resuming...\n"); 2100 2101 ret = smu_start_smc_engine(smu); 2102 if (ret) { 2103 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2104 return ret; 2105 } 2106 2107 ret = smu_smc_hw_setup(smu); 2108 if (ret) { 2109 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2110 return ret; 2111 } 2112 2113 ret = smu_set_gfx_imu_enable(smu); 2114 if (ret) 2115 return ret; 2116 2117 smu_set_gfx_cgpg(smu, true); 2118 2119 smu->disable_uclk_switch = 0; 2120 2121 adev->pm.dpm_enabled = true; 2122 2123 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2124 2125 return 0; 2126 } 2127 2128 static int smu_display_configuration_change(void *handle, 2129 const struct amd_pp_display_configuration *display_config) 2130 { 2131 struct smu_context *smu = handle; 2132 2133 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2134 return -EOPNOTSUPP; 2135 2136 if (!display_config) 2137 return -EINVAL; 2138 2139 smu_set_min_dcef_deep_sleep(smu, 2140 display_config->min_dcef_deep_sleep_set_clk / 100); 2141 2142 return 0; 2143 } 2144 2145 static int smu_set_clockgating_state(void *handle, 2146 enum amd_clockgating_state state) 2147 { 2148 return 0; 2149 } 2150 2151 static int smu_set_powergating_state(void *handle, 2152 enum amd_powergating_state state) 2153 { 2154 return 0; 2155 } 2156 2157 static int smu_enable_umd_pstate(void *handle, 2158 enum amd_dpm_forced_level *level) 2159 { 2160 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2161 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2162 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2163 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2164 2165 struct smu_context *smu = (struct smu_context*)(handle); 2166 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2167 2168 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2169 return -EINVAL; 2170 2171 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2172 /* enter umd pstate, save current level, disable gfx cg*/ 2173 if (*level & profile_mode_mask) { 2174 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2175 smu_gpo_control(smu, false); 2176 smu_gfx_ulv_control(smu, false); 2177 smu_deep_sleep_control(smu, false); 2178 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2179 } 2180 } else { 2181 /* exit umd pstate, restore level, enable gfx cg*/ 2182 if (!(*level & profile_mode_mask)) { 2183 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2184 *level = smu_dpm_ctx->saved_dpm_level; 2185 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2186 smu_deep_sleep_control(smu, true); 2187 smu_gfx_ulv_control(smu, true); 2188 smu_gpo_control(smu, true); 2189 } 2190 } 2191 2192 return 0; 2193 } 2194 2195 static int smu_bump_power_profile_mode(struct smu_context *smu, 2196 long *param, 2197 uint32_t param_size) 2198 { 2199 int ret = 0; 2200 2201 if (smu->ppt_funcs->set_power_profile_mode) 2202 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2203 2204 return ret; 2205 } 2206 2207 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2208 enum amd_dpm_forced_level level, 2209 bool skip_display_settings) 2210 { 2211 int ret = 0; 2212 int index = 0; 2213 long workload[1]; 2214 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2215 2216 if (!skip_display_settings) { 2217 ret = smu_display_config_changed(smu); 2218 if (ret) { 2219 dev_err(smu->adev->dev, "Failed to change display config!"); 2220 return ret; 2221 } 2222 } 2223 2224 ret = smu_apply_clocks_adjust_rules(smu); 2225 if (ret) { 2226 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2227 return ret; 2228 } 2229 2230 if (!skip_display_settings) { 2231 ret = smu_notify_smc_display_config(smu); 2232 if (ret) { 2233 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2234 return ret; 2235 } 2236 } 2237 2238 if (smu_dpm_ctx->dpm_level != level) { 2239 ret = smu_asic_set_performance_level(smu, level); 2240 if (ret) { 2241 dev_err(smu->adev->dev, "Failed to set performance level!"); 2242 return ret; 2243 } 2244 2245 /* update the saved copy */ 2246 smu_dpm_ctx->dpm_level = level; 2247 } 2248 2249 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2250 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2251 index = fls(smu->workload_mask); 2252 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2253 workload[0] = smu->workload_setting[index]; 2254 2255 if (smu->power_profile_mode != workload[0]) 2256 smu_bump_power_profile_mode(smu, workload, 0); 2257 } 2258 2259 return ret; 2260 } 2261 2262 static int smu_handle_task(struct smu_context *smu, 2263 enum amd_dpm_forced_level level, 2264 enum amd_pp_task task_id) 2265 { 2266 int ret = 0; 2267 2268 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2269 return -EOPNOTSUPP; 2270 2271 switch (task_id) { 2272 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2273 ret = smu_pre_display_config_changed(smu); 2274 if (ret) 2275 return ret; 2276 ret = smu_adjust_power_state_dynamic(smu, level, false); 2277 break; 2278 case AMD_PP_TASK_COMPLETE_INIT: 2279 case AMD_PP_TASK_READJUST_POWER_STATE: 2280 ret = smu_adjust_power_state_dynamic(smu, level, true); 2281 break; 2282 default: 2283 break; 2284 } 2285 2286 return ret; 2287 } 2288 2289 static int smu_handle_dpm_task(void *handle, 2290 enum amd_pp_task task_id, 2291 enum amd_pm_state_type *user_state) 2292 { 2293 struct smu_context *smu = handle; 2294 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2295 2296 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2297 2298 } 2299 2300 static int smu_switch_power_profile(void *handle, 2301 enum PP_SMC_POWER_PROFILE type, 2302 bool en) 2303 { 2304 struct smu_context *smu = handle; 2305 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2306 long workload[1]; 2307 uint32_t index; 2308 2309 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2310 return -EOPNOTSUPP; 2311 2312 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2313 return -EINVAL; 2314 2315 if (!en) { 2316 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 2317 index = fls(smu->workload_mask); 2318 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2319 workload[0] = smu->workload_setting[index]; 2320 } else { 2321 smu->workload_mask |= (1 << smu->workload_prority[type]); 2322 index = fls(smu->workload_mask); 2323 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2324 workload[0] = smu->workload_setting[index]; 2325 } 2326 2327 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2328 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2329 smu_bump_power_profile_mode(smu, workload, 0); 2330 2331 return 0; 2332 } 2333 2334 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2335 { 2336 struct smu_context *smu = handle; 2337 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2338 2339 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2340 return -EOPNOTSUPP; 2341 2342 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2343 return -EINVAL; 2344 2345 return smu_dpm_ctx->dpm_level; 2346 } 2347 2348 static int smu_force_performance_level(void *handle, 2349 enum amd_dpm_forced_level level) 2350 { 2351 struct smu_context *smu = handle; 2352 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2353 int ret = 0; 2354 2355 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2356 return -EOPNOTSUPP; 2357 2358 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2359 return -EINVAL; 2360 2361 ret = smu_enable_umd_pstate(smu, &level); 2362 if (ret) 2363 return ret; 2364 2365 ret = smu_handle_task(smu, level, 2366 AMD_PP_TASK_READJUST_POWER_STATE); 2367 2368 /* reset user dpm clock state */ 2369 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2370 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2371 smu->user_dpm_profile.clk_dependency = 0; 2372 } 2373 2374 return ret; 2375 } 2376 2377 static int smu_set_display_count(void *handle, uint32_t count) 2378 { 2379 struct smu_context *smu = handle; 2380 2381 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2382 return -EOPNOTSUPP; 2383 2384 return smu_init_display_count(smu, count); 2385 } 2386 2387 static int smu_force_smuclk_levels(struct smu_context *smu, 2388 enum smu_clk_type clk_type, 2389 uint32_t mask) 2390 { 2391 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2392 int ret = 0; 2393 2394 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2395 return -EOPNOTSUPP; 2396 2397 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2398 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2399 return -EINVAL; 2400 } 2401 2402 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2403 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2404 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2405 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2406 smu_set_user_clk_dependencies(smu, clk_type); 2407 } 2408 } 2409 2410 return ret; 2411 } 2412 2413 static int smu_force_ppclk_levels(void *handle, 2414 enum pp_clock_type type, 2415 uint32_t mask) 2416 { 2417 struct smu_context *smu = handle; 2418 enum smu_clk_type clk_type; 2419 2420 switch (type) { 2421 case PP_SCLK: 2422 clk_type = SMU_SCLK; break; 2423 case PP_MCLK: 2424 clk_type = SMU_MCLK; break; 2425 case PP_PCIE: 2426 clk_type = SMU_PCIE; break; 2427 case PP_SOCCLK: 2428 clk_type = SMU_SOCCLK; break; 2429 case PP_FCLK: 2430 clk_type = SMU_FCLK; break; 2431 case PP_DCEFCLK: 2432 clk_type = SMU_DCEFCLK; break; 2433 case PP_VCLK: 2434 clk_type = SMU_VCLK; break; 2435 case PP_VCLK1: 2436 clk_type = SMU_VCLK1; break; 2437 case PP_DCLK: 2438 clk_type = SMU_DCLK; break; 2439 case PP_DCLK1: 2440 clk_type = SMU_DCLK1; break; 2441 case OD_SCLK: 2442 clk_type = SMU_OD_SCLK; break; 2443 case OD_MCLK: 2444 clk_type = SMU_OD_MCLK; break; 2445 case OD_VDDC_CURVE: 2446 clk_type = SMU_OD_VDDC_CURVE; break; 2447 case OD_RANGE: 2448 clk_type = SMU_OD_RANGE; break; 2449 default: 2450 return -EINVAL; 2451 } 2452 2453 return smu_force_smuclk_levels(smu, clk_type, mask); 2454 } 2455 2456 /* 2457 * On system suspending or resetting, the dpm_enabled 2458 * flag will be cleared. So that those SMU services which 2459 * are not supported will be gated. 2460 * However, the mp1 state setting should still be granted 2461 * even if the dpm_enabled cleared. 2462 */ 2463 static int smu_set_mp1_state(void *handle, 2464 enum pp_mp1_state mp1_state) 2465 { 2466 struct smu_context *smu = handle; 2467 int ret = 0; 2468 2469 if (!smu->pm_enabled) 2470 return -EOPNOTSUPP; 2471 2472 if (smu->ppt_funcs && 2473 smu->ppt_funcs->set_mp1_state) 2474 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2475 2476 return ret; 2477 } 2478 2479 static int smu_set_df_cstate(void *handle, 2480 enum pp_df_cstate state) 2481 { 2482 struct smu_context *smu = handle; 2483 int ret = 0; 2484 2485 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2486 return -EOPNOTSUPP; 2487 2488 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2489 return 0; 2490 2491 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2492 if (ret) 2493 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2494 2495 return ret; 2496 } 2497 2498 int smu_write_watermarks_table(struct smu_context *smu) 2499 { 2500 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2501 return -EOPNOTSUPP; 2502 2503 return smu_set_watermarks_table(smu, NULL); 2504 } 2505 2506 static int smu_set_watermarks_for_clock_ranges(void *handle, 2507 struct pp_smu_wm_range_sets *clock_ranges) 2508 { 2509 struct smu_context *smu = handle; 2510 2511 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2512 return -EOPNOTSUPP; 2513 2514 if (smu->disable_watermark) 2515 return 0; 2516 2517 return smu_set_watermarks_table(smu, clock_ranges); 2518 } 2519 2520 int smu_set_ac_dc(struct smu_context *smu) 2521 { 2522 int ret = 0; 2523 2524 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2525 return -EOPNOTSUPP; 2526 2527 /* controlled by firmware */ 2528 if (smu->dc_controlled_by_gpio) 2529 return 0; 2530 2531 ret = smu_set_power_source(smu, 2532 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2533 SMU_POWER_SOURCE_DC); 2534 if (ret) 2535 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2536 smu->adev->pm.ac_power ? "AC" : "DC"); 2537 2538 return ret; 2539 } 2540 2541 const struct amd_ip_funcs smu_ip_funcs = { 2542 .name = "smu", 2543 .early_init = smu_early_init, 2544 .late_init = smu_late_init, 2545 .sw_init = smu_sw_init, 2546 .sw_fini = smu_sw_fini, 2547 .hw_init = smu_hw_init, 2548 .hw_fini = smu_hw_fini, 2549 .late_fini = smu_late_fini, 2550 .suspend = smu_suspend, 2551 .resume = smu_resume, 2552 .is_idle = NULL, 2553 .check_soft_reset = NULL, 2554 .wait_for_idle = NULL, 2555 .soft_reset = NULL, 2556 .set_clockgating_state = smu_set_clockgating_state, 2557 .set_powergating_state = smu_set_powergating_state, 2558 }; 2559 2560 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2561 .type = AMD_IP_BLOCK_TYPE_SMC, 2562 .major = 11, 2563 .minor = 0, 2564 .rev = 0, 2565 .funcs = &smu_ip_funcs, 2566 }; 2567 2568 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2569 .type = AMD_IP_BLOCK_TYPE_SMC, 2570 .major = 12, 2571 .minor = 0, 2572 .rev = 0, 2573 .funcs = &smu_ip_funcs, 2574 }; 2575 2576 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2577 .type = AMD_IP_BLOCK_TYPE_SMC, 2578 .major = 13, 2579 .minor = 0, 2580 .rev = 0, 2581 .funcs = &smu_ip_funcs, 2582 }; 2583 2584 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2585 .type = AMD_IP_BLOCK_TYPE_SMC, 2586 .major = 14, 2587 .minor = 0, 2588 .rev = 0, 2589 .funcs = &smu_ip_funcs, 2590 }; 2591 2592 static int smu_load_microcode(void *handle) 2593 { 2594 struct smu_context *smu = handle; 2595 struct amdgpu_device *adev = smu->adev; 2596 int ret = 0; 2597 2598 if (!smu->pm_enabled) 2599 return -EOPNOTSUPP; 2600 2601 /* This should be used for non PSP loading */ 2602 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2603 return 0; 2604 2605 if (smu->ppt_funcs->load_microcode) { 2606 ret = smu->ppt_funcs->load_microcode(smu); 2607 if (ret) { 2608 dev_err(adev->dev, "Load microcode failed\n"); 2609 return ret; 2610 } 2611 } 2612 2613 if (smu->ppt_funcs->check_fw_status) { 2614 ret = smu->ppt_funcs->check_fw_status(smu); 2615 if (ret) { 2616 dev_err(adev->dev, "SMC is not ready\n"); 2617 return ret; 2618 } 2619 } 2620 2621 return ret; 2622 } 2623 2624 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2625 { 2626 int ret = 0; 2627 2628 if (smu->ppt_funcs->set_gfx_cgpg) 2629 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2630 2631 return ret; 2632 } 2633 2634 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2635 { 2636 struct smu_context *smu = handle; 2637 int ret = 0; 2638 2639 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2640 return -EOPNOTSUPP; 2641 2642 if (!smu->ppt_funcs->set_fan_speed_rpm) 2643 return -EOPNOTSUPP; 2644 2645 if (speed == U32_MAX) 2646 return -EINVAL; 2647 2648 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2649 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2650 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2651 smu->user_dpm_profile.fan_speed_rpm = speed; 2652 2653 /* Override custom PWM setting as they cannot co-exist */ 2654 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2655 smu->user_dpm_profile.fan_speed_pwm = 0; 2656 } 2657 2658 return ret; 2659 } 2660 2661 /** 2662 * smu_get_power_limit - Request one of the SMU Power Limits 2663 * 2664 * @handle: pointer to smu context 2665 * @limit: requested limit is written back to this variable 2666 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2667 * @pp_power_type: &pp_power_type type of power 2668 * Return: 0 on success, <0 on error 2669 * 2670 */ 2671 int smu_get_power_limit(void *handle, 2672 uint32_t *limit, 2673 enum pp_power_limit_level pp_limit_level, 2674 enum pp_power_type pp_power_type) 2675 { 2676 struct smu_context *smu = handle; 2677 struct amdgpu_device *adev = smu->adev; 2678 enum smu_ppt_limit_level limit_level; 2679 uint32_t limit_type; 2680 int ret = 0; 2681 2682 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2683 return -EOPNOTSUPP; 2684 2685 switch (pp_power_type) { 2686 case PP_PWR_TYPE_SUSTAINED: 2687 limit_type = SMU_DEFAULT_PPT_LIMIT; 2688 break; 2689 case PP_PWR_TYPE_FAST: 2690 limit_type = SMU_FAST_PPT_LIMIT; 2691 break; 2692 default: 2693 return -EOPNOTSUPP; 2694 } 2695 2696 switch (pp_limit_level) { 2697 case PP_PWR_LIMIT_CURRENT: 2698 limit_level = SMU_PPT_LIMIT_CURRENT; 2699 break; 2700 case PP_PWR_LIMIT_DEFAULT: 2701 limit_level = SMU_PPT_LIMIT_DEFAULT; 2702 break; 2703 case PP_PWR_LIMIT_MAX: 2704 limit_level = SMU_PPT_LIMIT_MAX; 2705 break; 2706 case PP_PWR_LIMIT_MIN: 2707 limit_level = SMU_PPT_LIMIT_MIN; 2708 break; 2709 default: 2710 return -EOPNOTSUPP; 2711 } 2712 2713 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2714 if (smu->ppt_funcs->get_ppt_limit) 2715 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2716 } else { 2717 switch (limit_level) { 2718 case SMU_PPT_LIMIT_CURRENT: 2719 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2720 case IP_VERSION(13, 0, 2): 2721 case IP_VERSION(13, 0, 6): 2722 case IP_VERSION(13, 0, 14): 2723 case IP_VERSION(11, 0, 7): 2724 case IP_VERSION(11, 0, 11): 2725 case IP_VERSION(11, 0, 12): 2726 case IP_VERSION(11, 0, 13): 2727 ret = smu_get_asic_power_limits(smu, 2728 &smu->current_power_limit, 2729 NULL, NULL, NULL); 2730 break; 2731 default: 2732 break; 2733 } 2734 *limit = smu->current_power_limit; 2735 break; 2736 case SMU_PPT_LIMIT_DEFAULT: 2737 *limit = smu->default_power_limit; 2738 break; 2739 case SMU_PPT_LIMIT_MAX: 2740 *limit = smu->max_power_limit; 2741 break; 2742 case SMU_PPT_LIMIT_MIN: 2743 *limit = smu->min_power_limit; 2744 break; 2745 default: 2746 return -EINVAL; 2747 } 2748 } 2749 2750 return ret; 2751 } 2752 2753 static int smu_set_power_limit(void *handle, uint32_t limit) 2754 { 2755 struct smu_context *smu = handle; 2756 uint32_t limit_type = limit >> 24; 2757 int ret = 0; 2758 2759 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2760 return -EOPNOTSUPP; 2761 2762 limit &= (1<<24)-1; 2763 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2764 if (smu->ppt_funcs->set_power_limit) 2765 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2766 2767 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2768 dev_err(smu->adev->dev, 2769 "New power limit (%d) is out of range [%d,%d]\n", 2770 limit, smu->min_power_limit, smu->max_power_limit); 2771 return -EINVAL; 2772 } 2773 2774 if (!limit) 2775 limit = smu->current_power_limit; 2776 2777 if (smu->ppt_funcs->set_power_limit) { 2778 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2779 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2780 smu->user_dpm_profile.power_limit = limit; 2781 } 2782 2783 return ret; 2784 } 2785 2786 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2787 { 2788 int ret = 0; 2789 2790 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2791 return -EOPNOTSUPP; 2792 2793 if (smu->ppt_funcs->print_clk_levels) 2794 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2795 2796 return ret; 2797 } 2798 2799 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2800 { 2801 enum smu_clk_type clk_type; 2802 2803 switch (type) { 2804 case PP_SCLK: 2805 clk_type = SMU_SCLK; break; 2806 case PP_MCLK: 2807 clk_type = SMU_MCLK; break; 2808 case PP_PCIE: 2809 clk_type = SMU_PCIE; break; 2810 case PP_SOCCLK: 2811 clk_type = SMU_SOCCLK; break; 2812 case PP_FCLK: 2813 clk_type = SMU_FCLK; break; 2814 case PP_DCEFCLK: 2815 clk_type = SMU_DCEFCLK; break; 2816 case PP_VCLK: 2817 clk_type = SMU_VCLK; break; 2818 case PP_VCLK1: 2819 clk_type = SMU_VCLK1; break; 2820 case PP_DCLK: 2821 clk_type = SMU_DCLK; break; 2822 case PP_DCLK1: 2823 clk_type = SMU_DCLK1; break; 2824 case OD_SCLK: 2825 clk_type = SMU_OD_SCLK; break; 2826 case OD_MCLK: 2827 clk_type = SMU_OD_MCLK; break; 2828 case OD_VDDC_CURVE: 2829 clk_type = SMU_OD_VDDC_CURVE; break; 2830 case OD_RANGE: 2831 clk_type = SMU_OD_RANGE; break; 2832 case OD_VDDGFX_OFFSET: 2833 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2834 case OD_CCLK: 2835 clk_type = SMU_OD_CCLK; break; 2836 case OD_FAN_CURVE: 2837 clk_type = SMU_OD_FAN_CURVE; break; 2838 case OD_ACOUSTIC_LIMIT: 2839 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2840 case OD_ACOUSTIC_TARGET: 2841 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2842 case OD_FAN_TARGET_TEMPERATURE: 2843 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2844 case OD_FAN_MINIMUM_PWM: 2845 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2846 default: 2847 clk_type = SMU_CLK_COUNT; break; 2848 } 2849 2850 return clk_type; 2851 } 2852 2853 static int smu_print_ppclk_levels(void *handle, 2854 enum pp_clock_type type, 2855 char *buf) 2856 { 2857 struct smu_context *smu = handle; 2858 enum smu_clk_type clk_type; 2859 2860 clk_type = smu_convert_to_smuclk(type); 2861 if (clk_type == SMU_CLK_COUNT) 2862 return -EINVAL; 2863 2864 return smu_print_smuclk_levels(smu, clk_type, buf); 2865 } 2866 2867 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2868 { 2869 struct smu_context *smu = handle; 2870 enum smu_clk_type clk_type; 2871 2872 clk_type = smu_convert_to_smuclk(type); 2873 if (clk_type == SMU_CLK_COUNT) 2874 return -EINVAL; 2875 2876 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2877 return -EOPNOTSUPP; 2878 2879 if (!smu->ppt_funcs->emit_clk_levels) 2880 return -ENOENT; 2881 2882 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2883 2884 } 2885 2886 static int smu_od_edit_dpm_table(void *handle, 2887 enum PP_OD_DPM_TABLE_COMMAND type, 2888 long *input, uint32_t size) 2889 { 2890 struct smu_context *smu = handle; 2891 int ret = 0; 2892 2893 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2894 return -EOPNOTSUPP; 2895 2896 if (smu->ppt_funcs->od_edit_dpm_table) { 2897 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2898 } 2899 2900 return ret; 2901 } 2902 2903 static int smu_read_sensor(void *handle, 2904 int sensor, 2905 void *data, 2906 int *size_arg) 2907 { 2908 struct smu_context *smu = handle; 2909 struct smu_umd_pstate_table *pstate_table = 2910 &smu->pstate_table; 2911 int ret = 0; 2912 uint32_t *size, size_val; 2913 2914 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2915 return -EOPNOTSUPP; 2916 2917 if (!data || !size_arg) 2918 return -EINVAL; 2919 2920 size_val = *size_arg; 2921 size = &size_val; 2922 2923 if (smu->ppt_funcs->read_sensor) 2924 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2925 goto unlock; 2926 2927 switch (sensor) { 2928 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2929 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2930 *size = 4; 2931 break; 2932 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2933 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2934 *size = 4; 2935 break; 2936 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2937 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2938 *size = 4; 2939 break; 2940 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2941 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2942 *size = 4; 2943 break; 2944 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2945 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2946 *size = 8; 2947 break; 2948 case AMDGPU_PP_SENSOR_UVD_POWER: 2949 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2950 *size = 4; 2951 break; 2952 case AMDGPU_PP_SENSOR_VCE_POWER: 2953 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2954 *size = 4; 2955 break; 2956 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2957 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 2958 *size = 4; 2959 break; 2960 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2961 *(uint32_t *)data = 0; 2962 *size = 4; 2963 break; 2964 default: 2965 *size = 0; 2966 ret = -EOPNOTSUPP; 2967 break; 2968 } 2969 2970 unlock: 2971 // assign uint32_t to int 2972 *size_arg = size_val; 2973 2974 return ret; 2975 } 2976 2977 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 2978 { 2979 int ret = -EOPNOTSUPP; 2980 struct smu_context *smu = handle; 2981 2982 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 2983 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 2984 2985 return ret; 2986 } 2987 2988 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 2989 { 2990 int ret = -EOPNOTSUPP; 2991 struct smu_context *smu = handle; 2992 2993 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 2994 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 2995 2996 return ret; 2997 } 2998 2999 static int smu_get_power_profile_mode(void *handle, char *buf) 3000 { 3001 struct smu_context *smu = handle; 3002 3003 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3004 !smu->ppt_funcs->get_power_profile_mode) 3005 return -EOPNOTSUPP; 3006 if (!buf) 3007 return -EINVAL; 3008 3009 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3010 } 3011 3012 static int smu_set_power_profile_mode(void *handle, 3013 long *param, 3014 uint32_t param_size) 3015 { 3016 struct smu_context *smu = handle; 3017 3018 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3019 !smu->ppt_funcs->set_power_profile_mode) 3020 return -EOPNOTSUPP; 3021 3022 return smu_bump_power_profile_mode(smu, param, param_size); 3023 } 3024 3025 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3026 { 3027 struct smu_context *smu = handle; 3028 3029 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3030 return -EOPNOTSUPP; 3031 3032 if (!smu->ppt_funcs->get_fan_control_mode) 3033 return -EOPNOTSUPP; 3034 3035 if (!fan_mode) 3036 return -EINVAL; 3037 3038 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3039 3040 return 0; 3041 } 3042 3043 static int smu_set_fan_control_mode(void *handle, u32 value) 3044 { 3045 struct smu_context *smu = handle; 3046 int ret = 0; 3047 3048 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3049 return -EOPNOTSUPP; 3050 3051 if (!smu->ppt_funcs->set_fan_control_mode) 3052 return -EOPNOTSUPP; 3053 3054 if (value == U32_MAX) 3055 return -EINVAL; 3056 3057 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3058 if (ret) 3059 goto out; 3060 3061 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3062 smu->user_dpm_profile.fan_mode = value; 3063 3064 /* reset user dpm fan speed */ 3065 if (value != AMD_FAN_CTRL_MANUAL) { 3066 smu->user_dpm_profile.fan_speed_pwm = 0; 3067 smu->user_dpm_profile.fan_speed_rpm = 0; 3068 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3069 } 3070 } 3071 3072 out: 3073 return ret; 3074 } 3075 3076 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3077 { 3078 struct smu_context *smu = handle; 3079 int ret = 0; 3080 3081 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3082 return -EOPNOTSUPP; 3083 3084 if (!smu->ppt_funcs->get_fan_speed_pwm) 3085 return -EOPNOTSUPP; 3086 3087 if (!speed) 3088 return -EINVAL; 3089 3090 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3091 3092 return ret; 3093 } 3094 3095 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3096 { 3097 struct smu_context *smu = handle; 3098 int ret = 0; 3099 3100 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3101 return -EOPNOTSUPP; 3102 3103 if (!smu->ppt_funcs->set_fan_speed_pwm) 3104 return -EOPNOTSUPP; 3105 3106 if (speed == U32_MAX) 3107 return -EINVAL; 3108 3109 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3110 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3111 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3112 smu->user_dpm_profile.fan_speed_pwm = speed; 3113 3114 /* Override custom RPM setting as they cannot co-exist */ 3115 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3116 smu->user_dpm_profile.fan_speed_rpm = 0; 3117 } 3118 3119 return ret; 3120 } 3121 3122 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3123 { 3124 struct smu_context *smu = handle; 3125 int ret = 0; 3126 3127 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3128 return -EOPNOTSUPP; 3129 3130 if (!smu->ppt_funcs->get_fan_speed_rpm) 3131 return -EOPNOTSUPP; 3132 3133 if (!speed) 3134 return -EINVAL; 3135 3136 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3137 3138 return ret; 3139 } 3140 3141 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3142 { 3143 struct smu_context *smu = handle; 3144 3145 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3146 return -EOPNOTSUPP; 3147 3148 return smu_set_min_dcef_deep_sleep(smu, clk); 3149 } 3150 3151 static int smu_get_clock_by_type_with_latency(void *handle, 3152 enum amd_pp_clock_type type, 3153 struct pp_clock_levels_with_latency *clocks) 3154 { 3155 struct smu_context *smu = handle; 3156 enum smu_clk_type clk_type; 3157 int ret = 0; 3158 3159 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3160 return -EOPNOTSUPP; 3161 3162 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3163 switch (type) { 3164 case amd_pp_sys_clock: 3165 clk_type = SMU_GFXCLK; 3166 break; 3167 case amd_pp_mem_clock: 3168 clk_type = SMU_MCLK; 3169 break; 3170 case amd_pp_dcef_clock: 3171 clk_type = SMU_DCEFCLK; 3172 break; 3173 case amd_pp_disp_clock: 3174 clk_type = SMU_DISPCLK; 3175 break; 3176 default: 3177 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3178 return -EINVAL; 3179 } 3180 3181 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3182 } 3183 3184 return ret; 3185 } 3186 3187 static int smu_display_clock_voltage_request(void *handle, 3188 struct pp_display_clock_request *clock_req) 3189 { 3190 struct smu_context *smu = handle; 3191 int ret = 0; 3192 3193 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3194 return -EOPNOTSUPP; 3195 3196 if (smu->ppt_funcs->display_clock_voltage_request) 3197 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3198 3199 return ret; 3200 } 3201 3202 3203 static int smu_display_disable_memory_clock_switch(void *handle, 3204 bool disable_memory_clock_switch) 3205 { 3206 struct smu_context *smu = handle; 3207 int ret = -EINVAL; 3208 3209 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3210 return -EOPNOTSUPP; 3211 3212 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3213 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3214 3215 return ret; 3216 } 3217 3218 static int smu_set_xgmi_pstate(void *handle, 3219 uint32_t pstate) 3220 { 3221 struct smu_context *smu = handle; 3222 int ret = 0; 3223 3224 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3225 return -EOPNOTSUPP; 3226 3227 if (smu->ppt_funcs->set_xgmi_pstate) 3228 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3229 3230 if (ret) 3231 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3232 3233 return ret; 3234 } 3235 3236 static int smu_get_baco_capability(void *handle) 3237 { 3238 struct smu_context *smu = handle; 3239 3240 if (!smu->pm_enabled) 3241 return false; 3242 3243 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3244 return false; 3245 3246 return smu->ppt_funcs->get_bamaco_support(smu); 3247 } 3248 3249 static int smu_baco_set_state(void *handle, int state) 3250 { 3251 struct smu_context *smu = handle; 3252 int ret = 0; 3253 3254 if (!smu->pm_enabled) 3255 return -EOPNOTSUPP; 3256 3257 if (state == 0) { 3258 if (smu->ppt_funcs->baco_exit) 3259 ret = smu->ppt_funcs->baco_exit(smu); 3260 } else if (state == 1) { 3261 if (smu->ppt_funcs->baco_enter) 3262 ret = smu->ppt_funcs->baco_enter(smu); 3263 } else { 3264 return -EINVAL; 3265 } 3266 3267 if (ret) 3268 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3269 (state)?"enter":"exit"); 3270 3271 return ret; 3272 } 3273 3274 bool smu_mode1_reset_is_support(struct smu_context *smu) 3275 { 3276 bool ret = false; 3277 3278 if (!smu->pm_enabled) 3279 return false; 3280 3281 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3282 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3283 3284 return ret; 3285 } 3286 3287 bool smu_mode2_reset_is_support(struct smu_context *smu) 3288 { 3289 bool ret = false; 3290 3291 if (!smu->pm_enabled) 3292 return false; 3293 3294 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3295 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3296 3297 return ret; 3298 } 3299 3300 int smu_mode1_reset(struct smu_context *smu) 3301 { 3302 int ret = 0; 3303 3304 if (!smu->pm_enabled) 3305 return -EOPNOTSUPP; 3306 3307 if (smu->ppt_funcs->mode1_reset) 3308 ret = smu->ppt_funcs->mode1_reset(smu); 3309 3310 return ret; 3311 } 3312 3313 static int smu_mode2_reset(void *handle) 3314 { 3315 struct smu_context *smu = handle; 3316 int ret = 0; 3317 3318 if (!smu->pm_enabled) 3319 return -EOPNOTSUPP; 3320 3321 if (smu->ppt_funcs->mode2_reset) 3322 ret = smu->ppt_funcs->mode2_reset(smu); 3323 3324 if (ret) 3325 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3326 3327 return ret; 3328 } 3329 3330 static int smu_enable_gfx_features(void *handle) 3331 { 3332 struct smu_context *smu = handle; 3333 int ret = 0; 3334 3335 if (!smu->pm_enabled) 3336 return -EOPNOTSUPP; 3337 3338 if (smu->ppt_funcs->enable_gfx_features) 3339 ret = smu->ppt_funcs->enable_gfx_features(smu); 3340 3341 if (ret) 3342 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3343 3344 return ret; 3345 } 3346 3347 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3348 struct pp_smu_nv_clock_table *max_clocks) 3349 { 3350 struct smu_context *smu = handle; 3351 int ret = 0; 3352 3353 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3354 return -EOPNOTSUPP; 3355 3356 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3357 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3358 3359 return ret; 3360 } 3361 3362 static int smu_get_uclk_dpm_states(void *handle, 3363 unsigned int *clock_values_in_khz, 3364 unsigned int *num_states) 3365 { 3366 struct smu_context *smu = handle; 3367 int ret = 0; 3368 3369 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3370 return -EOPNOTSUPP; 3371 3372 if (smu->ppt_funcs->get_uclk_dpm_states) 3373 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3374 3375 return ret; 3376 } 3377 3378 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3379 { 3380 struct smu_context *smu = handle; 3381 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3382 3383 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3384 return -EOPNOTSUPP; 3385 3386 if (smu->ppt_funcs->get_current_power_state) 3387 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3388 3389 return pm_state; 3390 } 3391 3392 static int smu_get_dpm_clock_table(void *handle, 3393 struct dpm_clocks *clock_table) 3394 { 3395 struct smu_context *smu = handle; 3396 int ret = 0; 3397 3398 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3399 return -EOPNOTSUPP; 3400 3401 if (smu->ppt_funcs->get_dpm_clock_table) 3402 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3403 3404 return ret; 3405 } 3406 3407 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3408 { 3409 struct smu_context *smu = handle; 3410 3411 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3412 return -EOPNOTSUPP; 3413 3414 if (!smu->ppt_funcs->get_gpu_metrics) 3415 return -EOPNOTSUPP; 3416 3417 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3418 } 3419 3420 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3421 size_t size) 3422 { 3423 struct smu_context *smu = handle; 3424 3425 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3426 return -EOPNOTSUPP; 3427 3428 if (!smu->ppt_funcs->get_pm_metrics) 3429 return -EOPNOTSUPP; 3430 3431 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3432 } 3433 3434 static int smu_enable_mgpu_fan_boost(void *handle) 3435 { 3436 struct smu_context *smu = handle; 3437 int ret = 0; 3438 3439 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3440 return -EOPNOTSUPP; 3441 3442 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3443 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3444 3445 return ret; 3446 } 3447 3448 static int smu_gfx_state_change_set(void *handle, 3449 uint32_t state) 3450 { 3451 struct smu_context *smu = handle; 3452 int ret = 0; 3453 3454 if (smu->ppt_funcs->gfx_state_change_set) 3455 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3456 3457 return ret; 3458 } 3459 3460 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3461 { 3462 int ret = 0; 3463 3464 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3465 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3466 3467 return ret; 3468 } 3469 3470 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3471 { 3472 int ret = -EOPNOTSUPP; 3473 3474 if (smu->ppt_funcs && 3475 smu->ppt_funcs->get_ecc_info) 3476 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3477 3478 return ret; 3479 3480 } 3481 3482 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3483 { 3484 struct smu_context *smu = handle; 3485 struct smu_table_context *smu_table = &smu->smu_table; 3486 struct smu_table *memory_pool = &smu_table->memory_pool; 3487 3488 if (!addr || !size) 3489 return -EINVAL; 3490 3491 *addr = NULL; 3492 *size = 0; 3493 if (memory_pool->bo) { 3494 *addr = memory_pool->cpu_addr; 3495 *size = memory_pool->size; 3496 } 3497 3498 return 0; 3499 } 3500 3501 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 3502 enum pp_xgmi_plpd_mode mode) 3503 { 3504 int ret = -EOPNOTSUPP; 3505 3506 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3507 return ret; 3508 3509 /* PLPD policy is not supported if it's NONE */ 3510 if (smu->plpd_mode == XGMI_PLPD_NONE) 3511 return ret; 3512 3513 if (smu->plpd_mode == mode) 3514 return 0; 3515 3516 if (smu->ppt_funcs && smu->ppt_funcs->select_xgmi_plpd_policy) 3517 ret = smu->ppt_funcs->select_xgmi_plpd_policy(smu, mode); 3518 3519 if (!ret) 3520 smu->plpd_mode = mode; 3521 3522 return ret; 3523 } 3524 3525 static const struct amd_pm_funcs swsmu_pm_funcs = { 3526 /* export for sysfs */ 3527 .set_fan_control_mode = smu_set_fan_control_mode, 3528 .get_fan_control_mode = smu_get_fan_control_mode, 3529 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3530 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3531 .force_clock_level = smu_force_ppclk_levels, 3532 .print_clock_levels = smu_print_ppclk_levels, 3533 .emit_clock_levels = smu_emit_ppclk_levels, 3534 .force_performance_level = smu_force_performance_level, 3535 .read_sensor = smu_read_sensor, 3536 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3537 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3538 .get_performance_level = smu_get_performance_level, 3539 .get_current_power_state = smu_get_current_power_state, 3540 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3541 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3542 .get_pp_num_states = smu_get_power_num_states, 3543 .get_pp_table = smu_sys_get_pp_table, 3544 .set_pp_table = smu_sys_set_pp_table, 3545 .switch_power_profile = smu_switch_power_profile, 3546 /* export to amdgpu */ 3547 .dispatch_tasks = smu_handle_dpm_task, 3548 .load_firmware = smu_load_microcode, 3549 .set_powergating_by_smu = smu_dpm_set_power_gate, 3550 .set_power_limit = smu_set_power_limit, 3551 .get_power_limit = smu_get_power_limit, 3552 .get_power_profile_mode = smu_get_power_profile_mode, 3553 .set_power_profile_mode = smu_set_power_profile_mode, 3554 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3555 .set_mp1_state = smu_set_mp1_state, 3556 .gfx_state_change_set = smu_gfx_state_change_set, 3557 /* export to DC */ 3558 .get_sclk = smu_get_sclk, 3559 .get_mclk = smu_get_mclk, 3560 .display_configuration_change = smu_display_configuration_change, 3561 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3562 .display_clock_voltage_request = smu_display_clock_voltage_request, 3563 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3564 .set_active_display_count = smu_set_display_count, 3565 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3566 .get_asic_baco_capability = smu_get_baco_capability, 3567 .set_asic_baco_state = smu_baco_set_state, 3568 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3569 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3570 .asic_reset_mode_2 = smu_mode2_reset, 3571 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3572 .set_df_cstate = smu_set_df_cstate, 3573 .set_xgmi_pstate = smu_set_xgmi_pstate, 3574 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3575 .get_pm_metrics = smu_sys_get_pm_metrics, 3576 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3577 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3578 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3579 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3580 .get_dpm_clock_table = smu_get_dpm_clock_table, 3581 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3582 }; 3583 3584 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3585 uint64_t event_arg) 3586 { 3587 int ret = -EINVAL; 3588 3589 if (smu->ppt_funcs->wait_for_event) 3590 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3591 3592 return ret; 3593 } 3594 3595 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3596 { 3597 3598 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3599 return -EOPNOTSUPP; 3600 3601 /* Confirm the buffer allocated is of correct size */ 3602 if (size != smu->stb_context.stb_buf_size) 3603 return -EINVAL; 3604 3605 /* 3606 * No need to lock smu mutex as we access STB directly through MMIO 3607 * and not going through SMU messaging route (for now at least). 3608 * For registers access rely on implementation internal locking. 3609 */ 3610 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3611 } 3612 3613 #if defined(CONFIG_DEBUG_FS) 3614 3615 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3616 { 3617 struct amdgpu_device *adev = filp->f_inode->i_private; 3618 struct smu_context *smu = adev->powerplay.pp_handle; 3619 unsigned char *buf; 3620 int r; 3621 3622 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3623 if (!buf) 3624 return -ENOMEM; 3625 3626 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3627 if (r) 3628 goto out; 3629 3630 filp->private_data = buf; 3631 3632 return 0; 3633 3634 out: 3635 kvfree(buf); 3636 return r; 3637 } 3638 3639 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3640 loff_t *pos) 3641 { 3642 struct amdgpu_device *adev = filp->f_inode->i_private; 3643 struct smu_context *smu = adev->powerplay.pp_handle; 3644 3645 3646 if (!filp->private_data) 3647 return -EINVAL; 3648 3649 return simple_read_from_buffer(buf, 3650 size, 3651 pos, filp->private_data, 3652 smu->stb_context.stb_buf_size); 3653 } 3654 3655 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3656 { 3657 kvfree(filp->private_data); 3658 filp->private_data = NULL; 3659 3660 return 0; 3661 } 3662 3663 /* 3664 * We have to define not only read method but also 3665 * open and release because .read takes up to PAGE_SIZE 3666 * data each time so and so is invoked multiple times. 3667 * We allocate the STB buffer in .open and release it 3668 * in .release 3669 */ 3670 static const struct file_operations smu_stb_debugfs_fops = { 3671 .owner = THIS_MODULE, 3672 .open = smu_stb_debugfs_open, 3673 .read = smu_stb_debugfs_read, 3674 .release = smu_stb_debugfs_release, 3675 .llseek = default_llseek, 3676 }; 3677 3678 #endif 3679 3680 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3681 { 3682 #if defined(CONFIG_DEBUG_FS) 3683 3684 struct smu_context *smu = adev->powerplay.pp_handle; 3685 3686 if (!smu || (!smu->stb_context.stb_buf_size)) 3687 return; 3688 3689 debugfs_create_file_size("amdgpu_smu_stb_dump", 3690 S_IRUSR, 3691 adev_to_drm(adev)->primary->debugfs_root, 3692 adev, 3693 &smu_stb_debugfs_fops, 3694 smu->stb_context.stb_buf_size); 3695 #endif 3696 } 3697 3698 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3699 { 3700 int ret = 0; 3701 3702 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3703 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3704 3705 return ret; 3706 } 3707 3708 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3709 { 3710 int ret = 0; 3711 3712 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3713 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3714 3715 return ret; 3716 } 3717 3718 int smu_send_rma_reason(struct smu_context *smu) 3719 { 3720 int ret = 0; 3721 3722 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3723 ret = smu->ppt_funcs->send_rma_reason(smu); 3724 3725 return ret; 3726 } 3727