1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 76 static int smu_sys_get_pp_feature_mask(void *handle, 77 char *buf) 78 { 79 struct smu_context *smu = handle; 80 81 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 82 return -EOPNOTSUPP; 83 84 return smu_get_pp_feature_mask(smu, buf); 85 } 86 87 static int smu_sys_set_pp_feature_mask(void *handle, 88 uint64_t new_mask) 89 { 90 struct smu_context *smu = handle; 91 92 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 93 return -EOPNOTSUPP; 94 95 return smu_set_pp_feature_mask(smu, new_mask); 96 } 97 98 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 99 { 100 if (!smu->ppt_funcs->set_gfx_off_residency) 101 return -EINVAL; 102 103 return smu_set_gfx_off_residency(smu, value); 104 } 105 106 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 107 { 108 if (!smu->ppt_funcs->get_gfx_off_residency) 109 return -EINVAL; 110 111 return smu_get_gfx_off_residency(smu, value); 112 } 113 114 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 115 { 116 if (!smu->ppt_funcs->get_gfx_off_entrycount) 117 return -EINVAL; 118 119 return smu_get_gfx_off_entrycount(smu, value); 120 } 121 122 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 123 { 124 if (!smu->ppt_funcs->get_gfx_off_status) 125 return -EINVAL; 126 127 *value = smu_get_gfx_off_status(smu); 128 129 return 0; 130 } 131 132 int smu_set_soft_freq_range(struct smu_context *smu, 133 enum smu_clk_type clk_type, 134 uint32_t min, 135 uint32_t max) 136 { 137 int ret = 0; 138 139 if (smu->ppt_funcs->set_soft_freq_limited_range) 140 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 141 clk_type, 142 min, 143 max, 144 false); 145 146 return ret; 147 } 148 149 int smu_get_dpm_freq_range(struct smu_context *smu, 150 enum smu_clk_type clk_type, 151 uint32_t *min, 152 uint32_t *max) 153 { 154 int ret = -ENOTSUPP; 155 156 if (!min && !max) 157 return -EINVAL; 158 159 if (smu->ppt_funcs->get_dpm_ultimate_freq) 160 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 161 clk_type, 162 min, 163 max); 164 165 return ret; 166 } 167 168 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 169 { 170 int ret = 0; 171 struct amdgpu_device *adev = smu->adev; 172 173 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 174 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 175 if (ret) 176 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 177 } 178 return ret; 179 } 180 181 static u32 smu_get_mclk(void *handle, bool low) 182 { 183 struct smu_context *smu = handle; 184 uint32_t clk_freq; 185 int ret = 0; 186 187 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 188 low ? &clk_freq : NULL, 189 !low ? &clk_freq : NULL); 190 if (ret) 191 return 0; 192 return clk_freq * 100; 193 } 194 195 static u32 smu_get_sclk(void *handle, bool low) 196 { 197 struct smu_context *smu = handle; 198 uint32_t clk_freq; 199 int ret = 0; 200 201 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 202 low ? &clk_freq : NULL, 203 !low ? &clk_freq : NULL); 204 if (ret) 205 return 0; 206 return clk_freq * 100; 207 } 208 209 static int smu_set_gfx_imu_enable(struct smu_context *smu) 210 { 211 struct amdgpu_device *adev = smu->adev; 212 213 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 214 return 0; 215 216 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 217 return 0; 218 219 return smu_set_gfx_power_up_by_imu(smu); 220 } 221 222 static bool is_vcn_enabled(struct amdgpu_device *adev) 223 { 224 int i; 225 226 for (i = 0; i < adev->num_ip_blocks; i++) { 227 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 228 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 229 !adev->ip_blocks[i].status.valid) 230 return false; 231 } 232 233 return true; 234 } 235 236 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 237 bool enable) 238 { 239 struct smu_power_context *smu_power = &smu->smu_power; 240 struct smu_power_gate *power_gate = &smu_power->power_gate; 241 int ret = 0; 242 243 /* 244 * don't poweron vcn/jpeg when they are skipped. 245 */ 246 if (!is_vcn_enabled(smu->adev)) 247 return 0; 248 249 if (!smu->ppt_funcs->dpm_set_vcn_enable) 250 return 0; 251 252 if (atomic_read(&power_gate->vcn_gated) ^ enable) 253 return 0; 254 255 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 256 if (!ret) 257 atomic_set(&power_gate->vcn_gated, !enable); 258 259 return ret; 260 } 261 262 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 263 bool enable) 264 { 265 struct smu_power_context *smu_power = &smu->smu_power; 266 struct smu_power_gate *power_gate = &smu_power->power_gate; 267 int ret = 0; 268 269 if (!is_vcn_enabled(smu->adev)) 270 return 0; 271 272 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 273 return 0; 274 275 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 276 return 0; 277 278 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 279 if (!ret) 280 atomic_set(&power_gate->jpeg_gated, !enable); 281 282 return ret; 283 } 284 285 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 286 bool enable) 287 { 288 struct smu_power_context *smu_power = &smu->smu_power; 289 struct smu_power_gate *power_gate = &smu_power->power_gate; 290 int ret = 0; 291 292 if (!smu->ppt_funcs->dpm_set_vpe_enable) 293 return 0; 294 295 if (atomic_read(&power_gate->vpe_gated) ^ enable) 296 return 0; 297 298 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 299 if (!ret) 300 atomic_set(&power_gate->vpe_gated, !enable); 301 302 return ret; 303 } 304 305 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 306 bool enable) 307 { 308 struct smu_power_context *smu_power = &smu->smu_power; 309 struct smu_power_gate *power_gate = &smu_power->power_gate; 310 int ret = 0; 311 312 if (!smu->adev->enable_umsch_mm) 313 return 0; 314 315 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 316 return 0; 317 318 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 319 return 0; 320 321 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 322 if (!ret) 323 atomic_set(&power_gate->umsch_mm_gated, !enable); 324 325 return ret; 326 } 327 328 static int smu_set_mall_enable(struct smu_context *smu) 329 { 330 int ret = 0; 331 332 if (!smu->ppt_funcs->set_mall_enable) 333 return 0; 334 335 ret = smu->ppt_funcs->set_mall_enable(smu); 336 337 return ret; 338 } 339 340 /** 341 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 342 * 343 * @handle: smu_context pointer 344 * @block_type: the IP block to power gate/ungate 345 * @gate: to power gate if true, ungate otherwise 346 * 347 * This API uses no smu->mutex lock protection due to: 348 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 349 * This is guarded to be race condition free by the caller. 350 * 2. Or get called on user setting request of power_dpm_force_performance_level. 351 * Under this case, the smu->mutex lock protection is already enforced on 352 * the parent API smu_force_performance_level of the call path. 353 */ 354 static int smu_dpm_set_power_gate(void *handle, 355 uint32_t block_type, 356 bool gate) 357 { 358 struct smu_context *smu = handle; 359 int ret = 0; 360 361 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 362 dev_WARN(smu->adev->dev, 363 "SMU uninitialized but power %s requested for %u!\n", 364 gate ? "gate" : "ungate", block_type); 365 return -EOPNOTSUPP; 366 } 367 368 switch (block_type) { 369 /* 370 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 371 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 372 */ 373 case AMD_IP_BLOCK_TYPE_UVD: 374 case AMD_IP_BLOCK_TYPE_VCN: 375 ret = smu_dpm_set_vcn_enable(smu, !gate); 376 if (ret) 377 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 378 gate ? "gate" : "ungate"); 379 break; 380 case AMD_IP_BLOCK_TYPE_GFX: 381 ret = smu_gfx_off_control(smu, gate); 382 if (ret) 383 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 384 gate ? "enable" : "disable"); 385 break; 386 case AMD_IP_BLOCK_TYPE_SDMA: 387 ret = smu_powergate_sdma(smu, gate); 388 if (ret) 389 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 390 gate ? "gate" : "ungate"); 391 break; 392 case AMD_IP_BLOCK_TYPE_JPEG: 393 ret = smu_dpm_set_jpeg_enable(smu, !gate); 394 if (ret) 395 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 396 gate ? "gate" : "ungate"); 397 break; 398 case AMD_IP_BLOCK_TYPE_VPE: 399 ret = smu_dpm_set_vpe_enable(smu, !gate); 400 if (ret) 401 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 402 gate ? "gate" : "ungate"); 403 break; 404 default: 405 dev_err(smu->adev->dev, "Unsupported block type!\n"); 406 return -EINVAL; 407 } 408 409 return ret; 410 } 411 412 /** 413 * smu_set_user_clk_dependencies - set user profile clock dependencies 414 * 415 * @smu: smu_context pointer 416 * @clk: enum smu_clk_type type 417 * 418 * Enable/Disable the clock dependency for the @clk type. 419 */ 420 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 421 { 422 if (smu->adev->in_suspend) 423 return; 424 425 if (clk == SMU_MCLK) { 426 smu->user_dpm_profile.clk_dependency = 0; 427 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 428 } else if (clk == SMU_FCLK) { 429 /* MCLK takes precedence over FCLK */ 430 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 431 return; 432 433 smu->user_dpm_profile.clk_dependency = 0; 434 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 435 } else if (clk == SMU_SOCCLK) { 436 /* MCLK takes precedence over SOCCLK */ 437 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 438 return; 439 440 smu->user_dpm_profile.clk_dependency = 0; 441 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 442 } else 443 /* Add clk dependencies here, if any */ 444 return; 445 } 446 447 /** 448 * smu_restore_dpm_user_profile - reinstate user dpm profile 449 * 450 * @smu: smu_context pointer 451 * 452 * Restore the saved user power configurations include power limit, 453 * clock frequencies, fan control mode and fan speed. 454 */ 455 static void smu_restore_dpm_user_profile(struct smu_context *smu) 456 { 457 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 458 int ret = 0; 459 460 if (!smu->adev->in_suspend) 461 return; 462 463 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 464 return; 465 466 /* Enable restore flag */ 467 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 468 469 /* set the user dpm power limit */ 470 if (smu->user_dpm_profile.power_limit) { 471 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 472 if (ret) 473 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 474 } 475 476 /* set the user dpm clock configurations */ 477 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 478 enum smu_clk_type clk_type; 479 480 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 481 /* 482 * Iterate over smu clk type and force the saved user clk 483 * configs, skip if clock dependency is enabled 484 */ 485 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 486 smu->user_dpm_profile.clk_mask[clk_type]) { 487 ret = smu_force_smuclk_levels(smu, clk_type, 488 smu->user_dpm_profile.clk_mask[clk_type]); 489 if (ret) 490 dev_err(smu->adev->dev, 491 "Failed to set clock type = %d\n", clk_type); 492 } 493 } 494 } 495 496 /* set the user dpm fan configurations */ 497 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 498 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 499 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 500 if (ret != -EOPNOTSUPP) { 501 smu->user_dpm_profile.fan_speed_pwm = 0; 502 smu->user_dpm_profile.fan_speed_rpm = 0; 503 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 504 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 505 } 506 507 if (smu->user_dpm_profile.fan_speed_pwm) { 508 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 509 if (ret != -EOPNOTSUPP) 510 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 511 } 512 513 if (smu->user_dpm_profile.fan_speed_rpm) { 514 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 515 if (ret != -EOPNOTSUPP) 516 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 517 } 518 } 519 520 /* Restore user customized OD settings */ 521 if (smu->user_dpm_profile.user_od) { 522 if (smu->ppt_funcs->restore_user_od_settings) { 523 ret = smu->ppt_funcs->restore_user_od_settings(smu); 524 if (ret) 525 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 526 } 527 } 528 529 /* Disable restore flag */ 530 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 531 } 532 533 static int smu_get_power_num_states(void *handle, 534 struct pp_states_info *state_info) 535 { 536 if (!state_info) 537 return -EINVAL; 538 539 /* not support power state */ 540 memset(state_info, 0, sizeof(struct pp_states_info)); 541 state_info->nums = 1; 542 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 543 544 return 0; 545 } 546 547 bool is_support_sw_smu(struct amdgpu_device *adev) 548 { 549 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 550 if (adev->asic_type == CHIP_VEGA20) 551 return false; 552 553 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && 554 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) 555 return true; 556 557 return false; 558 } 559 560 bool is_support_cclk_dpm(struct amdgpu_device *adev) 561 { 562 struct smu_context *smu = adev->powerplay.pp_handle; 563 564 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 565 return false; 566 567 return true; 568 } 569 570 571 static int smu_sys_get_pp_table(void *handle, 572 char **table) 573 { 574 struct smu_context *smu = handle; 575 struct smu_table_context *smu_table = &smu->smu_table; 576 577 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 578 return -EOPNOTSUPP; 579 580 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 581 return -EINVAL; 582 583 if (smu_table->hardcode_pptable) 584 *table = smu_table->hardcode_pptable; 585 else 586 *table = smu_table->power_play_table; 587 588 return smu_table->power_play_table_size; 589 } 590 591 static int smu_sys_set_pp_table(void *handle, 592 const char *buf, 593 size_t size) 594 { 595 struct smu_context *smu = handle; 596 struct smu_table_context *smu_table = &smu->smu_table; 597 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 598 int ret = 0; 599 600 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 601 return -EOPNOTSUPP; 602 603 if (header->usStructureSize != size) { 604 dev_err(smu->adev->dev, "pp table size not matched !\n"); 605 return -EIO; 606 } 607 608 if (!smu_table->hardcode_pptable) { 609 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 610 if (!smu_table->hardcode_pptable) 611 return -ENOMEM; 612 } 613 614 memcpy(smu_table->hardcode_pptable, buf, size); 615 smu_table->power_play_table = smu_table->hardcode_pptable; 616 smu_table->power_play_table_size = size; 617 618 /* 619 * Special hw_fini action(for Navi1x, the DPMs disablement will be 620 * skipped) may be needed for custom pptable uploading. 621 */ 622 smu->uploading_custom_pp_table = true; 623 624 ret = smu_reset(smu); 625 if (ret) 626 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 627 628 smu->uploading_custom_pp_table = false; 629 630 return ret; 631 } 632 633 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 634 { 635 struct smu_feature *feature = &smu->smu_feature; 636 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 637 int ret = 0; 638 639 /* 640 * With SCPM enabled, the allowed featuremasks setting(via 641 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 642 * That means there is no way to let PMFW knows the settings below. 643 * Thus, we just assume all the features are allowed under 644 * such scenario. 645 */ 646 if (smu->adev->scpm_enabled) { 647 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 648 return 0; 649 } 650 651 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 652 653 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 654 SMU_FEATURE_MAX/32); 655 if (ret) 656 return ret; 657 658 bitmap_or(feature->allowed, feature->allowed, 659 (unsigned long *)allowed_feature_mask, 660 feature->feature_num); 661 662 return ret; 663 } 664 665 static int smu_set_funcs(struct amdgpu_device *adev) 666 { 667 struct smu_context *smu = adev->powerplay.pp_handle; 668 669 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 670 smu->od_enabled = true; 671 672 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 673 case IP_VERSION(11, 0, 0): 674 case IP_VERSION(11, 0, 5): 675 case IP_VERSION(11, 0, 9): 676 navi10_set_ppt_funcs(smu); 677 break; 678 case IP_VERSION(11, 0, 7): 679 case IP_VERSION(11, 0, 11): 680 case IP_VERSION(11, 0, 12): 681 case IP_VERSION(11, 0, 13): 682 sienna_cichlid_set_ppt_funcs(smu); 683 break; 684 case IP_VERSION(12, 0, 0): 685 case IP_VERSION(12, 0, 1): 686 renoir_set_ppt_funcs(smu); 687 break; 688 case IP_VERSION(11, 5, 0): 689 vangogh_set_ppt_funcs(smu); 690 break; 691 case IP_VERSION(13, 0, 1): 692 case IP_VERSION(13, 0, 3): 693 case IP_VERSION(13, 0, 8): 694 yellow_carp_set_ppt_funcs(smu); 695 break; 696 case IP_VERSION(13, 0, 4): 697 case IP_VERSION(13, 0, 11): 698 smu_v13_0_4_set_ppt_funcs(smu); 699 break; 700 case IP_VERSION(13, 0, 5): 701 smu_v13_0_5_set_ppt_funcs(smu); 702 break; 703 case IP_VERSION(11, 0, 8): 704 cyan_skillfish_set_ppt_funcs(smu); 705 break; 706 case IP_VERSION(11, 0, 2): 707 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 708 arcturus_set_ppt_funcs(smu); 709 /* OD is not supported on Arcturus */ 710 smu->od_enabled = false; 711 break; 712 case IP_VERSION(13, 0, 2): 713 aldebaran_set_ppt_funcs(smu); 714 /* Enable pp_od_clk_voltage node */ 715 smu->od_enabled = true; 716 break; 717 case IP_VERSION(13, 0, 0): 718 case IP_VERSION(13, 0, 10): 719 smu_v13_0_0_set_ppt_funcs(smu); 720 break; 721 case IP_VERSION(13, 0, 6): 722 case IP_VERSION(13, 0, 14): 723 smu_v13_0_6_set_ppt_funcs(smu); 724 /* Enable pp_od_clk_voltage node */ 725 smu->od_enabled = true; 726 break; 727 case IP_VERSION(13, 0, 7): 728 smu_v13_0_7_set_ppt_funcs(smu); 729 break; 730 case IP_VERSION(14, 0, 0): 731 case IP_VERSION(14, 0, 1): 732 case IP_VERSION(14, 0, 4): 733 smu_v14_0_0_set_ppt_funcs(smu); 734 break; 735 case IP_VERSION(14, 0, 2): 736 case IP_VERSION(14, 0, 3): 737 smu_v14_0_2_set_ppt_funcs(smu); 738 break; 739 default: 740 return -EINVAL; 741 } 742 743 return 0; 744 } 745 746 static int smu_early_init(struct amdgpu_ip_block *ip_block) 747 { 748 struct amdgpu_device *adev = ip_block->adev; 749 struct smu_context *smu; 750 int r; 751 752 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 753 if (!smu) 754 return -ENOMEM; 755 756 smu->adev = adev; 757 smu->pm_enabled = !!amdgpu_dpm; 758 smu->is_apu = false; 759 smu->smu_baco.state = SMU_BACO_STATE_NONE; 760 smu->smu_baco.platform_support = false; 761 smu->smu_baco.maco_support = false; 762 smu->user_dpm_profile.fan_mode = -1; 763 764 mutex_init(&smu->message_lock); 765 766 adev->powerplay.pp_handle = smu; 767 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 768 769 r = smu_set_funcs(adev); 770 if (r) 771 return r; 772 return smu_init_microcode(smu); 773 } 774 775 static int smu_set_default_dpm_table(struct smu_context *smu) 776 { 777 struct amdgpu_device *adev = smu->adev; 778 struct smu_power_context *smu_power = &smu->smu_power; 779 struct smu_power_gate *power_gate = &smu_power->power_gate; 780 int vcn_gate, jpeg_gate; 781 int ret = 0; 782 783 if (!smu->ppt_funcs->set_default_dpm_table) 784 return 0; 785 786 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 787 vcn_gate = atomic_read(&power_gate->vcn_gated); 788 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 789 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 790 791 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 792 ret = smu_dpm_set_vcn_enable(smu, true); 793 if (ret) 794 return ret; 795 } 796 797 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 798 ret = smu_dpm_set_jpeg_enable(smu, true); 799 if (ret) 800 goto err_out; 801 } 802 803 ret = smu->ppt_funcs->set_default_dpm_table(smu); 804 if (ret) 805 dev_err(smu->adev->dev, 806 "Failed to setup default dpm clock tables!\n"); 807 808 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 809 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 810 err_out: 811 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 812 smu_dpm_set_vcn_enable(smu, !vcn_gate); 813 814 return ret; 815 } 816 817 static int smu_apply_default_config_table_settings(struct smu_context *smu) 818 { 819 struct amdgpu_device *adev = smu->adev; 820 int ret = 0; 821 822 ret = smu_get_default_config_table_settings(smu, 823 &adev->pm.config_table); 824 if (ret) 825 return ret; 826 827 return smu_set_config_table(smu, &adev->pm.config_table); 828 } 829 830 static int smu_late_init(struct amdgpu_ip_block *ip_block) 831 { 832 struct amdgpu_device *adev = ip_block->adev; 833 struct smu_context *smu = adev->powerplay.pp_handle; 834 int ret = 0; 835 836 smu_set_fine_grain_gfx_freq_parameters(smu); 837 838 if (!smu->pm_enabled) 839 return 0; 840 841 ret = smu_post_init(smu); 842 if (ret) { 843 dev_err(adev->dev, "Failed to post smu init!\n"); 844 return ret; 845 } 846 847 /* 848 * Explicitly notify PMFW the power mode the system in. Since 849 * the PMFW may boot the ASIC with a different mode. 850 * For those supporting ACDC switch via gpio, PMFW will 851 * handle the switch automatically. Driver involvement 852 * is unnecessary. 853 */ 854 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 855 smu_set_ac_dc(smu); 856 857 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 858 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 859 return 0; 860 861 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 862 ret = smu_set_default_od_settings(smu); 863 if (ret) { 864 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 865 return ret; 866 } 867 } 868 869 ret = smu_populate_umd_state_clk(smu); 870 if (ret) { 871 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 872 return ret; 873 } 874 875 ret = smu_get_asic_power_limits(smu, 876 &smu->current_power_limit, 877 &smu->default_power_limit, 878 &smu->max_power_limit, 879 &smu->min_power_limit); 880 if (ret) { 881 dev_err(adev->dev, "Failed to get asic power limits!\n"); 882 return ret; 883 } 884 885 if (!amdgpu_sriov_vf(adev)) 886 smu_get_unique_id(smu); 887 888 smu_get_fan_parameters(smu); 889 890 smu_handle_task(smu, 891 smu->smu_dpm.dpm_level, 892 AMD_PP_TASK_COMPLETE_INIT); 893 894 ret = smu_apply_default_config_table_settings(smu); 895 if (ret && (ret != -EOPNOTSUPP)) { 896 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 897 return ret; 898 } 899 900 smu_restore_dpm_user_profile(smu); 901 902 return 0; 903 } 904 905 static int smu_init_fb_allocations(struct smu_context *smu) 906 { 907 struct amdgpu_device *adev = smu->adev; 908 struct smu_table_context *smu_table = &smu->smu_table; 909 struct smu_table *tables = smu_table->tables; 910 struct smu_table *driver_table = &(smu_table->driver_table); 911 uint32_t max_table_size = 0; 912 int ret, i; 913 914 /* VRAM allocation for tool table */ 915 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 916 ret = amdgpu_bo_create_kernel(adev, 917 tables[SMU_TABLE_PMSTATUSLOG].size, 918 tables[SMU_TABLE_PMSTATUSLOG].align, 919 tables[SMU_TABLE_PMSTATUSLOG].domain, 920 &tables[SMU_TABLE_PMSTATUSLOG].bo, 921 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 922 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 923 if (ret) { 924 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 925 return ret; 926 } 927 } 928 929 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 930 /* VRAM allocation for driver table */ 931 for (i = 0; i < SMU_TABLE_COUNT; i++) { 932 if (tables[i].size == 0) 933 continue; 934 935 /* If one of the tables has VRAM domain restriction, keep it in 936 * VRAM 937 */ 938 if ((tables[i].domain & 939 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 940 AMDGPU_GEM_DOMAIN_VRAM) 941 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 942 943 if (i == SMU_TABLE_PMSTATUSLOG) 944 continue; 945 946 if (max_table_size < tables[i].size) 947 max_table_size = tables[i].size; 948 } 949 950 driver_table->size = max_table_size; 951 driver_table->align = PAGE_SIZE; 952 953 ret = amdgpu_bo_create_kernel(adev, 954 driver_table->size, 955 driver_table->align, 956 driver_table->domain, 957 &driver_table->bo, 958 &driver_table->mc_address, 959 &driver_table->cpu_addr); 960 if (ret) { 961 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 962 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 963 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 964 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 965 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 966 } 967 968 return ret; 969 } 970 971 static int smu_fini_fb_allocations(struct smu_context *smu) 972 { 973 struct smu_table_context *smu_table = &smu->smu_table; 974 struct smu_table *tables = smu_table->tables; 975 struct smu_table *driver_table = &(smu_table->driver_table); 976 977 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 978 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 979 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 980 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 981 982 amdgpu_bo_free_kernel(&driver_table->bo, 983 &driver_table->mc_address, 984 &driver_table->cpu_addr); 985 986 return 0; 987 } 988 989 /** 990 * smu_alloc_memory_pool - allocate memory pool in the system memory 991 * 992 * @smu: amdgpu_device pointer 993 * 994 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 995 * and DramLogSetDramAddr can notify it changed. 996 * 997 * Returns 0 on success, error on failure. 998 */ 999 static int smu_alloc_memory_pool(struct smu_context *smu) 1000 { 1001 struct amdgpu_device *adev = smu->adev; 1002 struct smu_table_context *smu_table = &smu->smu_table; 1003 struct smu_table *memory_pool = &smu_table->memory_pool; 1004 uint64_t pool_size = smu->pool_size; 1005 int ret = 0; 1006 1007 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1008 return ret; 1009 1010 memory_pool->size = pool_size; 1011 memory_pool->align = PAGE_SIZE; 1012 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 1013 1014 switch (pool_size) { 1015 case SMU_MEMORY_POOL_SIZE_256_MB: 1016 case SMU_MEMORY_POOL_SIZE_512_MB: 1017 case SMU_MEMORY_POOL_SIZE_1_GB: 1018 case SMU_MEMORY_POOL_SIZE_2_GB: 1019 ret = amdgpu_bo_create_kernel(adev, 1020 memory_pool->size, 1021 memory_pool->align, 1022 memory_pool->domain, 1023 &memory_pool->bo, 1024 &memory_pool->mc_address, 1025 &memory_pool->cpu_addr); 1026 if (ret) 1027 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1028 break; 1029 default: 1030 break; 1031 } 1032 1033 return ret; 1034 } 1035 1036 static int smu_free_memory_pool(struct smu_context *smu) 1037 { 1038 struct smu_table_context *smu_table = &smu->smu_table; 1039 struct smu_table *memory_pool = &smu_table->memory_pool; 1040 1041 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1042 return 0; 1043 1044 amdgpu_bo_free_kernel(&memory_pool->bo, 1045 &memory_pool->mc_address, 1046 &memory_pool->cpu_addr); 1047 1048 memset(memory_pool, 0, sizeof(struct smu_table)); 1049 1050 return 0; 1051 } 1052 1053 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1054 { 1055 struct smu_table_context *smu_table = &smu->smu_table; 1056 struct smu_table *dummy_read_1_table = 1057 &smu_table->dummy_read_1_table; 1058 struct amdgpu_device *adev = smu->adev; 1059 int ret = 0; 1060 1061 if (!dummy_read_1_table->size) 1062 return 0; 1063 1064 ret = amdgpu_bo_create_kernel(adev, 1065 dummy_read_1_table->size, 1066 dummy_read_1_table->align, 1067 dummy_read_1_table->domain, 1068 &dummy_read_1_table->bo, 1069 &dummy_read_1_table->mc_address, 1070 &dummy_read_1_table->cpu_addr); 1071 if (ret) 1072 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1073 1074 return ret; 1075 } 1076 1077 static void smu_free_dummy_read_table(struct smu_context *smu) 1078 { 1079 struct smu_table_context *smu_table = &smu->smu_table; 1080 struct smu_table *dummy_read_1_table = 1081 &smu_table->dummy_read_1_table; 1082 1083 1084 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1085 &dummy_read_1_table->mc_address, 1086 &dummy_read_1_table->cpu_addr); 1087 1088 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1089 } 1090 1091 static int smu_smc_table_sw_init(struct smu_context *smu) 1092 { 1093 int ret; 1094 1095 /** 1096 * Create smu_table structure, and init smc tables such as 1097 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1098 */ 1099 ret = smu_init_smc_tables(smu); 1100 if (ret) { 1101 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1102 return ret; 1103 } 1104 1105 /** 1106 * Create smu_power_context structure, and allocate smu_dpm_context and 1107 * context size to fill the smu_power_context data. 1108 */ 1109 ret = smu_init_power(smu); 1110 if (ret) { 1111 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1112 return ret; 1113 } 1114 1115 /* 1116 * allocate vram bos to store smc table contents. 1117 */ 1118 ret = smu_init_fb_allocations(smu); 1119 if (ret) 1120 return ret; 1121 1122 ret = smu_alloc_memory_pool(smu); 1123 if (ret) 1124 return ret; 1125 1126 ret = smu_alloc_dummy_read_table(smu); 1127 if (ret) 1128 return ret; 1129 1130 ret = smu_i2c_init(smu); 1131 if (ret) 1132 return ret; 1133 1134 return 0; 1135 } 1136 1137 static int smu_smc_table_sw_fini(struct smu_context *smu) 1138 { 1139 int ret; 1140 1141 smu_i2c_fini(smu); 1142 1143 smu_free_dummy_read_table(smu); 1144 1145 ret = smu_free_memory_pool(smu); 1146 if (ret) 1147 return ret; 1148 1149 ret = smu_fini_fb_allocations(smu); 1150 if (ret) 1151 return ret; 1152 1153 ret = smu_fini_power(smu); 1154 if (ret) { 1155 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1156 return ret; 1157 } 1158 1159 ret = smu_fini_smc_tables(smu); 1160 if (ret) { 1161 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1162 return ret; 1163 } 1164 1165 return 0; 1166 } 1167 1168 static void smu_throttling_logging_work_fn(struct work_struct *work) 1169 { 1170 struct smu_context *smu = container_of(work, struct smu_context, 1171 throttling_logging_work); 1172 1173 smu_log_thermal_throttling(smu); 1174 } 1175 1176 static void smu_interrupt_work_fn(struct work_struct *work) 1177 { 1178 struct smu_context *smu = container_of(work, struct smu_context, 1179 interrupt_work); 1180 1181 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1182 smu->ppt_funcs->interrupt_work(smu); 1183 } 1184 1185 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1186 { 1187 struct smu_context *smu = 1188 container_of(work, struct smu_context, swctf_delayed_work.work); 1189 struct smu_temperature_range *range = 1190 &smu->thermal_range; 1191 struct amdgpu_device *adev = smu->adev; 1192 uint32_t hotspot_tmp, size; 1193 1194 /* 1195 * If the hotspot temperature is confirmed as below SW CTF setting point 1196 * after the delay enforced, nothing will be done. 1197 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1198 */ 1199 if (range->software_shutdown_temp && 1200 smu->ppt_funcs->read_sensor && 1201 !smu->ppt_funcs->read_sensor(smu, 1202 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1203 &hotspot_tmp, 1204 &size) && 1205 hotspot_tmp / 1000 < range->software_shutdown_temp) 1206 return; 1207 1208 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1209 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1210 orderly_poweroff(true); 1211 } 1212 1213 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1214 { 1215 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1216 struct smu_dpm_policy_ctxt *policy_ctxt; 1217 struct smu_dpm_policy *policy; 1218 1219 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1220 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1221 if (policy) 1222 policy->current_level = XGMI_PLPD_DEFAULT; 1223 return; 1224 } 1225 1226 /* PMFW put PLPD into default policy after enabling the feature */ 1227 if (smu_feature_is_enabled(smu, 1228 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1229 if (policy) 1230 policy->current_level = XGMI_PLPD_DEFAULT; 1231 } else { 1232 policy_ctxt = dpm_ctxt->dpm_policies; 1233 if (policy_ctxt) 1234 policy_ctxt->policy_mask &= 1235 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1236 } 1237 } 1238 1239 static bool smu_is_workload_profile_available(struct smu_context *smu, 1240 u32 profile) 1241 { 1242 if (profile >= PP_SMC_POWER_PROFILE_COUNT) 1243 return false; 1244 return smu->workload_map && smu->workload_map[profile].valid_mapping; 1245 } 1246 1247 static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1248 { 1249 struct amdgpu_device *adev = ip_block->adev; 1250 struct smu_context *smu = adev->powerplay.pp_handle; 1251 int ret; 1252 1253 smu->pool_size = adev->pm.smu_prv_buffer_size; 1254 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1255 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1256 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1257 1258 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1259 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1260 atomic64_set(&smu->throttle_int_counter, 0); 1261 smu->watermarks_bitmap = 0; 1262 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1263 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1264 1265 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1266 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1267 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1268 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1269 1270 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1271 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1272 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1273 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1274 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1275 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1276 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1277 1278 if (smu->is_apu || 1279 !smu_is_workload_profile_available(smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D)) 1280 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1281 else 1282 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D]; 1283 1284 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1285 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1286 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1287 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1288 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1289 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1290 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1291 smu->display_config = &adev->pm.pm_display_cfg; 1292 1293 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1294 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1295 1296 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1297 smu_swctf_delayed_work_handler); 1298 1299 ret = smu_smc_table_sw_init(smu); 1300 if (ret) { 1301 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1302 return ret; 1303 } 1304 1305 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1306 ret = smu_get_vbios_bootup_values(smu); 1307 if (ret) { 1308 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1309 return ret; 1310 } 1311 1312 ret = smu_init_pptable_microcode(smu); 1313 if (ret) { 1314 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1315 return ret; 1316 } 1317 1318 ret = smu_register_irq_handler(smu); 1319 if (ret) { 1320 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1321 return ret; 1322 } 1323 1324 /* If there is no way to query fan control mode, fan control is not supported */ 1325 if (!smu->ppt_funcs->get_fan_control_mode) 1326 smu->adev->pm.no_fan = true; 1327 1328 return 0; 1329 } 1330 1331 static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1332 { 1333 struct amdgpu_device *adev = ip_block->adev; 1334 struct smu_context *smu = adev->powerplay.pp_handle; 1335 int ret; 1336 1337 ret = smu_smc_table_sw_fini(smu); 1338 if (ret) { 1339 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1340 return ret; 1341 } 1342 1343 smu_fini_microcode(smu); 1344 1345 return 0; 1346 } 1347 1348 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1349 { 1350 struct amdgpu_device *adev = smu->adev; 1351 struct smu_temperature_range *range = 1352 &smu->thermal_range; 1353 int ret = 0; 1354 1355 if (!smu->ppt_funcs->get_thermal_temperature_range) 1356 return 0; 1357 1358 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1359 if (ret) 1360 return ret; 1361 1362 adev->pm.dpm.thermal.min_temp = range->min; 1363 adev->pm.dpm.thermal.max_temp = range->max; 1364 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1365 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1366 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1367 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1368 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1369 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1370 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1371 1372 return ret; 1373 } 1374 1375 /** 1376 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1377 * 1378 * @smu: smu_context pointer 1379 * 1380 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1381 * Returns 0 on success, error on failure. 1382 */ 1383 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1384 { 1385 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1386 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1387 struct amdgpu_device *adev = smu->adev; 1388 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1389 uint64_t start, end; 1390 int ret, i, j; 1391 1392 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1393 if (ret) { 1394 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1395 return ret; 1396 } 1397 1398 /* 1399 * The exclusion ranges array we got might be filled with holes and duplicate 1400 * entries. For example: 1401 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1402 * We need to do some sortups to eliminate those holes and duplicate entries. 1403 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1404 */ 1405 for (i = 0; i < num_of_wbrf_ranges; i++) { 1406 start = wifi_bands[i].start; 1407 end = wifi_bands[i].end; 1408 1409 /* get the last valid entry to fill the intermediate hole */ 1410 if (!start && !end) { 1411 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1412 if (wifi_bands[j].start && wifi_bands[j].end) 1413 break; 1414 1415 /* no valid entry left */ 1416 if (j <= i) 1417 break; 1418 1419 start = wifi_bands[i].start = wifi_bands[j].start; 1420 end = wifi_bands[i].end = wifi_bands[j].end; 1421 wifi_bands[j].start = 0; 1422 wifi_bands[j].end = 0; 1423 num_of_wbrf_ranges = j; 1424 } 1425 1426 /* eliminate duplicate entries */ 1427 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1428 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1429 wifi_bands[j].start = 0; 1430 wifi_bands[j].end = 0; 1431 } 1432 } 1433 } 1434 1435 /* Send the sorted wifi_bands to PMFW */ 1436 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1437 /* Try to set the wifi_bands again */ 1438 if (unlikely(ret == -EBUSY)) { 1439 mdelay(5); 1440 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1441 } 1442 1443 return ret; 1444 } 1445 1446 /** 1447 * smu_wbrf_event_handler - handle notify events 1448 * 1449 * @nb: notifier block 1450 * @action: event type 1451 * @_arg: event data 1452 * 1453 * Calls relevant amdgpu function in response to wbrf event 1454 * notification from kernel. 1455 */ 1456 static int smu_wbrf_event_handler(struct notifier_block *nb, 1457 unsigned long action, void *_arg) 1458 { 1459 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1460 1461 switch (action) { 1462 case WBRF_CHANGED: 1463 schedule_delayed_work(&smu->wbrf_delayed_work, 1464 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1465 break; 1466 default: 1467 return NOTIFY_DONE; 1468 } 1469 1470 return NOTIFY_OK; 1471 } 1472 1473 /** 1474 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1475 * 1476 * @work: struct work_struct pointer 1477 * 1478 * Flood is over and driver will consume the latest exclusion ranges. 1479 */ 1480 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1481 { 1482 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1483 1484 smu_wbrf_handle_exclusion_ranges(smu); 1485 } 1486 1487 /** 1488 * smu_wbrf_support_check - check wbrf support 1489 * 1490 * @smu: smu_context pointer 1491 * 1492 * Verifies the ACPI interface whether wbrf is supported. 1493 */ 1494 static void smu_wbrf_support_check(struct smu_context *smu) 1495 { 1496 struct amdgpu_device *adev = smu->adev; 1497 1498 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1499 acpi_amd_wbrf_supported_consumer(adev->dev); 1500 1501 if (smu->wbrf_supported) 1502 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1503 } 1504 1505 /** 1506 * smu_wbrf_init - init driver wbrf support 1507 * 1508 * @smu: smu_context pointer 1509 * 1510 * Verifies the AMD ACPI interfaces and registers with the wbrf 1511 * notifier chain if wbrf feature is supported. 1512 * Returns 0 on success, error on failure. 1513 */ 1514 static int smu_wbrf_init(struct smu_context *smu) 1515 { 1516 int ret; 1517 1518 if (!smu->wbrf_supported) 1519 return 0; 1520 1521 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1522 1523 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1524 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1525 if (ret) 1526 return ret; 1527 1528 /* 1529 * Some wifiband exclusion ranges may be already there 1530 * before our driver loaded. To make sure our driver 1531 * is awared of those exclusion ranges. 1532 */ 1533 schedule_delayed_work(&smu->wbrf_delayed_work, 1534 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1535 1536 return 0; 1537 } 1538 1539 /** 1540 * smu_wbrf_fini - tear down driver wbrf support 1541 * 1542 * @smu: smu_context pointer 1543 * 1544 * Unregisters with the wbrf notifier chain. 1545 */ 1546 static void smu_wbrf_fini(struct smu_context *smu) 1547 { 1548 if (!smu->wbrf_supported) 1549 return; 1550 1551 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1552 1553 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1554 } 1555 1556 static int smu_smc_hw_setup(struct smu_context *smu) 1557 { 1558 struct smu_feature *feature = &smu->smu_feature; 1559 struct amdgpu_device *adev = smu->adev; 1560 uint8_t pcie_gen = 0, pcie_width = 0; 1561 uint64_t features_supported; 1562 int ret = 0; 1563 1564 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1565 case IP_VERSION(11, 0, 7): 1566 case IP_VERSION(11, 0, 11): 1567 case IP_VERSION(11, 5, 0): 1568 case IP_VERSION(11, 0, 12): 1569 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1570 dev_info(adev->dev, "dpm has been enabled\n"); 1571 ret = smu_system_features_control(smu, true); 1572 if (ret) 1573 dev_err(adev->dev, "Failed system features control!\n"); 1574 return ret; 1575 } 1576 break; 1577 default: 1578 break; 1579 } 1580 1581 ret = smu_init_display_count(smu, 0); 1582 if (ret) { 1583 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1584 return ret; 1585 } 1586 1587 ret = smu_set_driver_table_location(smu); 1588 if (ret) { 1589 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1590 return ret; 1591 } 1592 1593 /* 1594 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1595 */ 1596 ret = smu_set_tool_table_location(smu); 1597 if (ret) { 1598 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1599 return ret; 1600 } 1601 1602 /* 1603 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1604 * pool location. 1605 */ 1606 ret = smu_notify_memory_pool_location(smu); 1607 if (ret) { 1608 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1609 return ret; 1610 } 1611 1612 /* 1613 * It is assumed the pptable used before runpm is same as 1614 * the one used afterwards. Thus, we can reuse the stored 1615 * copy and do not need to resetup the pptable again. 1616 */ 1617 if (!adev->in_runpm) { 1618 ret = smu_setup_pptable(smu); 1619 if (ret) { 1620 dev_err(adev->dev, "Failed to setup pptable!\n"); 1621 return ret; 1622 } 1623 } 1624 1625 /* smu_dump_pptable(smu); */ 1626 1627 /* 1628 * With SCPM enabled, PSP is responsible for the PPTable transferring 1629 * (to SMU). Driver involvement is not needed and permitted. 1630 */ 1631 if (!adev->scpm_enabled) { 1632 /* 1633 * Copy pptable bo in the vram to smc with SMU MSGs such as 1634 * SetDriverDramAddr and TransferTableDram2Smu. 1635 */ 1636 ret = smu_write_pptable(smu); 1637 if (ret) { 1638 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1639 return ret; 1640 } 1641 } 1642 1643 /* issue Run*Btc msg */ 1644 ret = smu_run_btc(smu); 1645 if (ret) 1646 return ret; 1647 1648 /* Enable UclkShadow on wbrf supported */ 1649 if (smu->wbrf_supported) { 1650 ret = smu_enable_uclk_shadow(smu, true); 1651 if (ret) { 1652 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1653 return ret; 1654 } 1655 } 1656 1657 /* 1658 * With SCPM enabled, these actions(and relevant messages) are 1659 * not needed and permitted. 1660 */ 1661 if (!adev->scpm_enabled) { 1662 ret = smu_feature_set_allowed_mask(smu); 1663 if (ret) { 1664 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1665 return ret; 1666 } 1667 } 1668 1669 ret = smu_system_features_control(smu, true); 1670 if (ret) { 1671 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1672 return ret; 1673 } 1674 1675 smu_init_xgmi_plpd_mode(smu); 1676 1677 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1678 if (ret) { 1679 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1680 return ret; 1681 } 1682 bitmap_copy(feature->supported, 1683 (unsigned long *)&features_supported, 1684 feature->feature_num); 1685 1686 if (!smu_is_dpm_running(smu)) 1687 dev_info(adev->dev, "dpm has been disabled\n"); 1688 1689 /* 1690 * Set initialized values (get from vbios) to dpm tables context such as 1691 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1692 * type of clks. 1693 */ 1694 ret = smu_set_default_dpm_table(smu); 1695 if (ret) { 1696 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1697 return ret; 1698 } 1699 1700 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1701 pcie_gen = 3; 1702 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1703 pcie_gen = 2; 1704 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1705 pcie_gen = 1; 1706 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1707 pcie_gen = 0; 1708 1709 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1710 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1711 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1712 */ 1713 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1714 pcie_width = 6; 1715 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1716 pcie_width = 5; 1717 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1718 pcie_width = 4; 1719 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1720 pcie_width = 3; 1721 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1722 pcie_width = 2; 1723 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1724 pcie_width = 1; 1725 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1726 if (ret) { 1727 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1728 return ret; 1729 } 1730 1731 ret = smu_get_thermal_temperature_range(smu); 1732 if (ret) { 1733 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1734 return ret; 1735 } 1736 1737 ret = smu_enable_thermal_alert(smu); 1738 if (ret) { 1739 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1740 return ret; 1741 } 1742 1743 ret = smu_notify_display_change(smu); 1744 if (ret) { 1745 dev_err(adev->dev, "Failed to notify display change!\n"); 1746 return ret; 1747 } 1748 1749 /* 1750 * Set min deep sleep dce fclk with bootup value from vbios via 1751 * SetMinDeepSleepDcefclk MSG. 1752 */ 1753 ret = smu_set_min_dcef_deep_sleep(smu, 1754 smu->smu_table.boot_values.dcefclk / 100); 1755 if (ret) { 1756 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1757 return ret; 1758 } 1759 1760 /* Init wbrf support. Properly setup the notifier */ 1761 ret = smu_wbrf_init(smu); 1762 if (ret) 1763 dev_err(adev->dev, "Error during wbrf init call\n"); 1764 1765 return ret; 1766 } 1767 1768 static int smu_start_smc_engine(struct smu_context *smu) 1769 { 1770 struct amdgpu_device *adev = smu->adev; 1771 int ret = 0; 1772 1773 smu->smc_fw_state = SMU_FW_INIT; 1774 1775 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1776 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1777 if (smu->ppt_funcs->load_microcode) { 1778 ret = smu->ppt_funcs->load_microcode(smu); 1779 if (ret) 1780 return ret; 1781 } 1782 } 1783 } 1784 1785 if (smu->ppt_funcs->check_fw_status) { 1786 ret = smu->ppt_funcs->check_fw_status(smu); 1787 if (ret) { 1788 dev_err(adev->dev, "SMC is not ready\n"); 1789 return ret; 1790 } 1791 } 1792 1793 /* 1794 * Send msg GetDriverIfVersion to check if the return value is equal 1795 * with DRIVER_IF_VERSION of smc header. 1796 */ 1797 ret = smu_check_fw_version(smu); 1798 if (ret) 1799 return ret; 1800 1801 return ret; 1802 } 1803 1804 static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1805 { 1806 int ret; 1807 struct amdgpu_device *adev = ip_block->adev; 1808 struct smu_context *smu = adev->powerplay.pp_handle; 1809 1810 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1811 smu->pm_enabled = false; 1812 return 0; 1813 } 1814 1815 ret = smu_start_smc_engine(smu); 1816 if (ret) { 1817 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1818 return ret; 1819 } 1820 1821 /* 1822 * Check whether wbrf is supported. This needs to be done 1823 * before SMU setup starts since part of SMU configuration 1824 * relies on this. 1825 */ 1826 smu_wbrf_support_check(smu); 1827 1828 if (smu->is_apu) { 1829 ret = smu_set_gfx_imu_enable(smu); 1830 if (ret) 1831 return ret; 1832 smu_dpm_set_vcn_enable(smu, true); 1833 smu_dpm_set_jpeg_enable(smu, true); 1834 smu_dpm_set_vpe_enable(smu, true); 1835 smu_dpm_set_umsch_mm_enable(smu, true); 1836 smu_set_mall_enable(smu); 1837 smu_set_gfx_cgpg(smu, true); 1838 } 1839 1840 if (!smu->pm_enabled) 1841 return 0; 1842 1843 ret = smu_get_driver_allowed_feature_mask(smu); 1844 if (ret) 1845 return ret; 1846 1847 ret = smu_smc_hw_setup(smu); 1848 if (ret) { 1849 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1850 return ret; 1851 } 1852 1853 /* 1854 * Move maximum sustainable clock retrieving here considering 1855 * 1. It is not needed on resume(from S3). 1856 * 2. DAL settings come between .hw_init and .late_init of SMU. 1857 * And DAL needs to know the maximum sustainable clocks. Thus 1858 * it cannot be put in .late_init(). 1859 */ 1860 ret = smu_init_max_sustainable_clocks(smu); 1861 if (ret) { 1862 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1863 return ret; 1864 } 1865 1866 adev->pm.dpm_enabled = true; 1867 1868 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1869 1870 return 0; 1871 } 1872 1873 static int smu_disable_dpms(struct smu_context *smu) 1874 { 1875 struct amdgpu_device *adev = smu->adev; 1876 int ret = 0; 1877 bool use_baco = !smu->is_apu && 1878 ((amdgpu_in_reset(adev) && 1879 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1880 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1881 1882 /* 1883 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1884 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1885 */ 1886 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1887 case IP_VERSION(13, 0, 0): 1888 case IP_VERSION(13, 0, 7): 1889 case IP_VERSION(13, 0, 10): 1890 case IP_VERSION(14, 0, 2): 1891 case IP_VERSION(14, 0, 3): 1892 return 0; 1893 default: 1894 break; 1895 } 1896 1897 /* 1898 * For custom pptable uploading, skip the DPM features 1899 * disable process on Navi1x ASICs. 1900 * - As the gfx related features are under control of 1901 * RLC on those ASICs. RLC reinitialization will be 1902 * needed to reenable them. That will cost much more 1903 * efforts. 1904 * 1905 * - SMU firmware can handle the DPM reenablement 1906 * properly. 1907 */ 1908 if (smu->uploading_custom_pp_table) { 1909 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1910 case IP_VERSION(11, 0, 0): 1911 case IP_VERSION(11, 0, 5): 1912 case IP_VERSION(11, 0, 9): 1913 case IP_VERSION(11, 0, 7): 1914 case IP_VERSION(11, 0, 11): 1915 case IP_VERSION(11, 5, 0): 1916 case IP_VERSION(11, 0, 12): 1917 case IP_VERSION(11, 0, 13): 1918 return 0; 1919 default: 1920 break; 1921 } 1922 } 1923 1924 /* 1925 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1926 * on BACO in. Driver involvement is unnecessary. 1927 */ 1928 if (use_baco) { 1929 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1930 case IP_VERSION(11, 0, 7): 1931 case IP_VERSION(11, 0, 0): 1932 case IP_VERSION(11, 0, 5): 1933 case IP_VERSION(11, 0, 9): 1934 case IP_VERSION(13, 0, 7): 1935 return 0; 1936 default: 1937 break; 1938 } 1939 } 1940 1941 /* 1942 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 1943 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1944 */ 1945 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 1946 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 1947 return 0; 1948 1949 /* 1950 * For gpu reset, runpm and hibernation through BACO, 1951 * BACO feature has to be kept enabled. 1952 */ 1953 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1954 ret = smu_disable_all_features_with_exception(smu, 1955 SMU_FEATURE_BACO_BIT); 1956 if (ret) 1957 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1958 } else { 1959 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1960 if (!adev->scpm_enabled) { 1961 ret = smu_system_features_control(smu, false); 1962 if (ret) 1963 dev_err(adev->dev, "Failed to disable smu features.\n"); 1964 } 1965 } 1966 1967 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1968 * otherwise SMU will hang while interacting with RLC if RLC is halted 1969 * this is a WA for Vangogh asic which fix the SMU hang issue. 1970 */ 1971 ret = smu_notify_rlc_state(smu, false); 1972 if (ret) { 1973 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1974 return ret; 1975 } 1976 1977 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1978 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1979 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1980 adev->gfx.rlc.funcs->stop(adev); 1981 1982 return ret; 1983 } 1984 1985 static int smu_smc_hw_cleanup(struct smu_context *smu) 1986 { 1987 struct amdgpu_device *adev = smu->adev; 1988 int ret = 0; 1989 1990 smu_wbrf_fini(smu); 1991 1992 cancel_work_sync(&smu->throttling_logging_work); 1993 cancel_work_sync(&smu->interrupt_work); 1994 1995 ret = smu_disable_thermal_alert(smu); 1996 if (ret) { 1997 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1998 return ret; 1999 } 2000 2001 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2002 2003 ret = smu_disable_dpms(smu); 2004 if (ret) { 2005 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2006 return ret; 2007 } 2008 2009 return 0; 2010 } 2011 2012 static int smu_reset_mp1_state(struct smu_context *smu) 2013 { 2014 struct amdgpu_device *adev = smu->adev; 2015 int ret = 0; 2016 2017 if ((!adev->in_runpm) && (!adev->in_suspend) && 2018 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 2019 IP_VERSION(13, 0, 10) && 2020 !amdgpu_device_has_display_hardware(adev)) 2021 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2022 2023 return ret; 2024 } 2025 2026 static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2027 { 2028 struct amdgpu_device *adev = ip_block->adev; 2029 struct smu_context *smu = adev->powerplay.pp_handle; 2030 int ret; 2031 2032 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2033 return 0; 2034 2035 smu_dpm_set_vcn_enable(smu, false); 2036 smu_dpm_set_jpeg_enable(smu, false); 2037 smu_dpm_set_vpe_enable(smu, false); 2038 smu_dpm_set_umsch_mm_enable(smu, false); 2039 2040 adev->vcn.cur_state = AMD_PG_STATE_GATE; 2041 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2042 2043 if (!smu->pm_enabled) 2044 return 0; 2045 2046 adev->pm.dpm_enabled = false; 2047 2048 ret = smu_smc_hw_cleanup(smu); 2049 if (ret) 2050 return ret; 2051 2052 ret = smu_reset_mp1_state(smu); 2053 if (ret) 2054 return ret; 2055 2056 return 0; 2057 } 2058 2059 static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2060 { 2061 struct amdgpu_device *adev = ip_block->adev; 2062 struct smu_context *smu = adev->powerplay.pp_handle; 2063 2064 kfree(smu); 2065 } 2066 2067 static int smu_reset(struct smu_context *smu) 2068 { 2069 struct amdgpu_device *adev = smu->adev; 2070 struct amdgpu_ip_block *ip_block; 2071 int ret; 2072 2073 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2074 if (!ip_block) 2075 return -EINVAL; 2076 2077 ret = smu_hw_fini(ip_block); 2078 if (ret) 2079 return ret; 2080 2081 ret = smu_hw_init(ip_block); 2082 if (ret) 2083 return ret; 2084 2085 ret = smu_late_init(ip_block); 2086 if (ret) 2087 return ret; 2088 2089 return 0; 2090 } 2091 2092 static int smu_suspend(struct amdgpu_ip_block *ip_block) 2093 { 2094 struct amdgpu_device *adev = ip_block->adev; 2095 struct smu_context *smu = adev->powerplay.pp_handle; 2096 int ret; 2097 uint64_t count; 2098 2099 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2100 return 0; 2101 2102 if (!smu->pm_enabled) 2103 return 0; 2104 2105 adev->pm.dpm_enabled = false; 2106 2107 ret = smu_smc_hw_cleanup(smu); 2108 if (ret) 2109 return ret; 2110 2111 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2112 2113 smu_set_gfx_cgpg(smu, false); 2114 2115 /* 2116 * pwfw resets entrycount when device is suspended, so we save the 2117 * last value to be used when we resume to keep it consistent 2118 */ 2119 ret = smu_get_entrycount_gfxoff(smu, &count); 2120 if (!ret) 2121 adev->gfx.gfx_off_entrycount = count; 2122 2123 return 0; 2124 } 2125 2126 static int smu_resume(struct amdgpu_ip_block *ip_block) 2127 { 2128 int ret; 2129 struct amdgpu_device *adev = ip_block->adev; 2130 struct smu_context *smu = adev->powerplay.pp_handle; 2131 2132 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2133 return 0; 2134 2135 if (!smu->pm_enabled) 2136 return 0; 2137 2138 dev_info(adev->dev, "SMU is resuming...\n"); 2139 2140 ret = smu_start_smc_engine(smu); 2141 if (ret) { 2142 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2143 return ret; 2144 } 2145 2146 ret = smu_smc_hw_setup(smu); 2147 if (ret) { 2148 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2149 return ret; 2150 } 2151 2152 ret = smu_set_gfx_imu_enable(smu); 2153 if (ret) 2154 return ret; 2155 2156 smu_set_gfx_cgpg(smu, true); 2157 2158 smu->disable_uclk_switch = 0; 2159 2160 adev->pm.dpm_enabled = true; 2161 2162 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2163 2164 return 0; 2165 } 2166 2167 static int smu_display_configuration_change(void *handle, 2168 const struct amd_pp_display_configuration *display_config) 2169 { 2170 struct smu_context *smu = handle; 2171 2172 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2173 return -EOPNOTSUPP; 2174 2175 if (!display_config) 2176 return -EINVAL; 2177 2178 smu_set_min_dcef_deep_sleep(smu, 2179 display_config->min_dcef_deep_sleep_set_clk / 100); 2180 2181 return 0; 2182 } 2183 2184 static int smu_set_clockgating_state(void *handle, 2185 enum amd_clockgating_state state) 2186 { 2187 return 0; 2188 } 2189 2190 static int smu_set_powergating_state(void *handle, 2191 enum amd_powergating_state state) 2192 { 2193 return 0; 2194 } 2195 2196 static int smu_enable_umd_pstate(void *handle, 2197 enum amd_dpm_forced_level *level) 2198 { 2199 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2200 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2201 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2202 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2203 2204 struct smu_context *smu = (struct smu_context*)(handle); 2205 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2206 2207 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2208 return -EINVAL; 2209 2210 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2211 /* enter umd pstate, save current level, disable gfx cg*/ 2212 if (*level & profile_mode_mask) { 2213 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2214 smu_gpo_control(smu, false); 2215 smu_gfx_ulv_control(smu, false); 2216 smu_deep_sleep_control(smu, false); 2217 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2218 } 2219 } else { 2220 /* exit umd pstate, restore level, enable gfx cg*/ 2221 if (!(*level & profile_mode_mask)) { 2222 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2223 *level = smu_dpm_ctx->saved_dpm_level; 2224 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2225 smu_deep_sleep_control(smu, true); 2226 smu_gfx_ulv_control(smu, true); 2227 smu_gpo_control(smu, true); 2228 } 2229 } 2230 2231 return 0; 2232 } 2233 2234 static int smu_bump_power_profile_mode(struct smu_context *smu, 2235 long *param, 2236 uint32_t param_size) 2237 { 2238 int ret = 0; 2239 2240 if (smu->ppt_funcs->set_power_profile_mode) 2241 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2242 2243 return ret; 2244 } 2245 2246 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2247 enum amd_dpm_forced_level level, 2248 bool skip_display_settings, 2249 bool init) 2250 { 2251 int ret = 0; 2252 int index = 0; 2253 long workload[1]; 2254 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2255 2256 if (!skip_display_settings) { 2257 ret = smu_display_config_changed(smu); 2258 if (ret) { 2259 dev_err(smu->adev->dev, "Failed to change display config!"); 2260 return ret; 2261 } 2262 } 2263 2264 ret = smu_apply_clocks_adjust_rules(smu); 2265 if (ret) { 2266 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2267 return ret; 2268 } 2269 2270 if (!skip_display_settings) { 2271 ret = smu_notify_smc_display_config(smu); 2272 if (ret) { 2273 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2274 return ret; 2275 } 2276 } 2277 2278 if (smu_dpm_ctx->dpm_level != level) { 2279 ret = smu_asic_set_performance_level(smu, level); 2280 if (ret) { 2281 dev_err(smu->adev->dev, "Failed to set performance level!"); 2282 return ret; 2283 } 2284 2285 /* update the saved copy */ 2286 smu_dpm_ctx->dpm_level = level; 2287 } 2288 2289 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2290 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2291 index = fls(smu->workload_mask); 2292 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2293 workload[0] = smu->workload_setting[index]; 2294 2295 if (init || smu->power_profile_mode != workload[0]) 2296 smu_bump_power_profile_mode(smu, workload, 0); 2297 } 2298 2299 return ret; 2300 } 2301 2302 static int smu_handle_task(struct smu_context *smu, 2303 enum amd_dpm_forced_level level, 2304 enum amd_pp_task task_id) 2305 { 2306 int ret = 0; 2307 2308 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2309 return -EOPNOTSUPP; 2310 2311 switch (task_id) { 2312 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2313 ret = smu_pre_display_config_changed(smu); 2314 if (ret) 2315 return ret; 2316 ret = smu_adjust_power_state_dynamic(smu, level, false, false); 2317 break; 2318 case AMD_PP_TASK_COMPLETE_INIT: 2319 ret = smu_adjust_power_state_dynamic(smu, level, true, true); 2320 break; 2321 case AMD_PP_TASK_READJUST_POWER_STATE: 2322 ret = smu_adjust_power_state_dynamic(smu, level, true, false); 2323 break; 2324 default: 2325 break; 2326 } 2327 2328 return ret; 2329 } 2330 2331 static int smu_handle_dpm_task(void *handle, 2332 enum amd_pp_task task_id, 2333 enum amd_pm_state_type *user_state) 2334 { 2335 struct smu_context *smu = handle; 2336 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2337 2338 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2339 2340 } 2341 2342 static int smu_switch_power_profile(void *handle, 2343 enum PP_SMC_POWER_PROFILE type, 2344 bool en) 2345 { 2346 struct smu_context *smu = handle; 2347 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2348 long workload[1]; 2349 uint32_t index; 2350 2351 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2352 return -EOPNOTSUPP; 2353 2354 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2355 return -EINVAL; 2356 2357 if (!en) { 2358 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 2359 index = fls(smu->workload_mask); 2360 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2361 workload[0] = smu->workload_setting[index]; 2362 } else { 2363 smu->workload_mask |= (1 << smu->workload_prority[type]); 2364 index = fls(smu->workload_mask); 2365 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2366 workload[0] = smu->workload_setting[index]; 2367 } 2368 2369 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2370 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2371 smu_bump_power_profile_mode(smu, workload, 0); 2372 2373 return 0; 2374 } 2375 2376 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2377 { 2378 struct smu_context *smu = handle; 2379 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2380 2381 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2382 return -EOPNOTSUPP; 2383 2384 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2385 return -EINVAL; 2386 2387 return smu_dpm_ctx->dpm_level; 2388 } 2389 2390 static int smu_force_performance_level(void *handle, 2391 enum amd_dpm_forced_level level) 2392 { 2393 struct smu_context *smu = handle; 2394 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2395 int ret = 0; 2396 2397 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2398 return -EOPNOTSUPP; 2399 2400 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2401 return -EINVAL; 2402 2403 ret = smu_enable_umd_pstate(smu, &level); 2404 if (ret) 2405 return ret; 2406 2407 ret = smu_handle_task(smu, level, 2408 AMD_PP_TASK_READJUST_POWER_STATE); 2409 2410 /* reset user dpm clock state */ 2411 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2412 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2413 smu->user_dpm_profile.clk_dependency = 0; 2414 } 2415 2416 return ret; 2417 } 2418 2419 static int smu_set_display_count(void *handle, uint32_t count) 2420 { 2421 struct smu_context *smu = handle; 2422 2423 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2424 return -EOPNOTSUPP; 2425 2426 return smu_init_display_count(smu, count); 2427 } 2428 2429 static int smu_force_smuclk_levels(struct smu_context *smu, 2430 enum smu_clk_type clk_type, 2431 uint32_t mask) 2432 { 2433 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2434 int ret = 0; 2435 2436 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2437 return -EOPNOTSUPP; 2438 2439 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2440 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2441 return -EINVAL; 2442 } 2443 2444 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2445 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2446 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2447 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2448 smu_set_user_clk_dependencies(smu, clk_type); 2449 } 2450 } 2451 2452 return ret; 2453 } 2454 2455 static int smu_force_ppclk_levels(void *handle, 2456 enum pp_clock_type type, 2457 uint32_t mask) 2458 { 2459 struct smu_context *smu = handle; 2460 enum smu_clk_type clk_type; 2461 2462 switch (type) { 2463 case PP_SCLK: 2464 clk_type = SMU_SCLK; break; 2465 case PP_MCLK: 2466 clk_type = SMU_MCLK; break; 2467 case PP_PCIE: 2468 clk_type = SMU_PCIE; break; 2469 case PP_SOCCLK: 2470 clk_type = SMU_SOCCLK; break; 2471 case PP_FCLK: 2472 clk_type = SMU_FCLK; break; 2473 case PP_DCEFCLK: 2474 clk_type = SMU_DCEFCLK; break; 2475 case PP_VCLK: 2476 clk_type = SMU_VCLK; break; 2477 case PP_VCLK1: 2478 clk_type = SMU_VCLK1; break; 2479 case PP_DCLK: 2480 clk_type = SMU_DCLK; break; 2481 case PP_DCLK1: 2482 clk_type = SMU_DCLK1; break; 2483 case OD_SCLK: 2484 clk_type = SMU_OD_SCLK; break; 2485 case OD_MCLK: 2486 clk_type = SMU_OD_MCLK; break; 2487 case OD_VDDC_CURVE: 2488 clk_type = SMU_OD_VDDC_CURVE; break; 2489 case OD_RANGE: 2490 clk_type = SMU_OD_RANGE; break; 2491 default: 2492 return -EINVAL; 2493 } 2494 2495 return smu_force_smuclk_levels(smu, clk_type, mask); 2496 } 2497 2498 /* 2499 * On system suspending or resetting, the dpm_enabled 2500 * flag will be cleared. So that those SMU services which 2501 * are not supported will be gated. 2502 * However, the mp1 state setting should still be granted 2503 * even if the dpm_enabled cleared. 2504 */ 2505 static int smu_set_mp1_state(void *handle, 2506 enum pp_mp1_state mp1_state) 2507 { 2508 struct smu_context *smu = handle; 2509 int ret = 0; 2510 2511 if (!smu->pm_enabled) 2512 return -EOPNOTSUPP; 2513 2514 if (smu->ppt_funcs && 2515 smu->ppt_funcs->set_mp1_state) 2516 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2517 2518 return ret; 2519 } 2520 2521 static int smu_set_df_cstate(void *handle, 2522 enum pp_df_cstate state) 2523 { 2524 struct smu_context *smu = handle; 2525 int ret = 0; 2526 2527 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2528 return -EOPNOTSUPP; 2529 2530 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2531 return 0; 2532 2533 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2534 if (ret) 2535 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2536 2537 return ret; 2538 } 2539 2540 int smu_write_watermarks_table(struct smu_context *smu) 2541 { 2542 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2543 return -EOPNOTSUPP; 2544 2545 return smu_set_watermarks_table(smu, NULL); 2546 } 2547 2548 static int smu_set_watermarks_for_clock_ranges(void *handle, 2549 struct pp_smu_wm_range_sets *clock_ranges) 2550 { 2551 struct smu_context *smu = handle; 2552 2553 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2554 return -EOPNOTSUPP; 2555 2556 if (smu->disable_watermark) 2557 return 0; 2558 2559 return smu_set_watermarks_table(smu, clock_ranges); 2560 } 2561 2562 int smu_set_ac_dc(struct smu_context *smu) 2563 { 2564 int ret = 0; 2565 2566 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2567 return -EOPNOTSUPP; 2568 2569 /* controlled by firmware */ 2570 if (smu->dc_controlled_by_gpio) 2571 return 0; 2572 2573 ret = smu_set_power_source(smu, 2574 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2575 SMU_POWER_SOURCE_DC); 2576 if (ret) 2577 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2578 smu->adev->pm.ac_power ? "AC" : "DC"); 2579 2580 return ret; 2581 } 2582 2583 const struct amd_ip_funcs smu_ip_funcs = { 2584 .name = "smu", 2585 .early_init = smu_early_init, 2586 .late_init = smu_late_init, 2587 .sw_init = smu_sw_init, 2588 .sw_fini = smu_sw_fini, 2589 .hw_init = smu_hw_init, 2590 .hw_fini = smu_hw_fini, 2591 .late_fini = smu_late_fini, 2592 .suspend = smu_suspend, 2593 .resume = smu_resume, 2594 .is_idle = NULL, 2595 .check_soft_reset = NULL, 2596 .wait_for_idle = NULL, 2597 .soft_reset = NULL, 2598 .set_clockgating_state = smu_set_clockgating_state, 2599 .set_powergating_state = smu_set_powergating_state, 2600 }; 2601 2602 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2603 .type = AMD_IP_BLOCK_TYPE_SMC, 2604 .major = 11, 2605 .minor = 0, 2606 .rev = 0, 2607 .funcs = &smu_ip_funcs, 2608 }; 2609 2610 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2611 .type = AMD_IP_BLOCK_TYPE_SMC, 2612 .major = 12, 2613 .minor = 0, 2614 .rev = 0, 2615 .funcs = &smu_ip_funcs, 2616 }; 2617 2618 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2619 .type = AMD_IP_BLOCK_TYPE_SMC, 2620 .major = 13, 2621 .minor = 0, 2622 .rev = 0, 2623 .funcs = &smu_ip_funcs, 2624 }; 2625 2626 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2627 .type = AMD_IP_BLOCK_TYPE_SMC, 2628 .major = 14, 2629 .minor = 0, 2630 .rev = 0, 2631 .funcs = &smu_ip_funcs, 2632 }; 2633 2634 static int smu_load_microcode(void *handle) 2635 { 2636 struct smu_context *smu = handle; 2637 struct amdgpu_device *adev = smu->adev; 2638 int ret = 0; 2639 2640 if (!smu->pm_enabled) 2641 return -EOPNOTSUPP; 2642 2643 /* This should be used for non PSP loading */ 2644 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2645 return 0; 2646 2647 if (smu->ppt_funcs->load_microcode) { 2648 ret = smu->ppt_funcs->load_microcode(smu); 2649 if (ret) { 2650 dev_err(adev->dev, "Load microcode failed\n"); 2651 return ret; 2652 } 2653 } 2654 2655 if (smu->ppt_funcs->check_fw_status) { 2656 ret = smu->ppt_funcs->check_fw_status(smu); 2657 if (ret) { 2658 dev_err(adev->dev, "SMC is not ready\n"); 2659 return ret; 2660 } 2661 } 2662 2663 return ret; 2664 } 2665 2666 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2667 { 2668 int ret = 0; 2669 2670 if (smu->ppt_funcs->set_gfx_cgpg) 2671 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2672 2673 return ret; 2674 } 2675 2676 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2677 { 2678 struct smu_context *smu = handle; 2679 int ret = 0; 2680 2681 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2682 return -EOPNOTSUPP; 2683 2684 if (!smu->ppt_funcs->set_fan_speed_rpm) 2685 return -EOPNOTSUPP; 2686 2687 if (speed == U32_MAX) 2688 return -EINVAL; 2689 2690 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2691 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2692 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2693 smu->user_dpm_profile.fan_speed_rpm = speed; 2694 2695 /* Override custom PWM setting as they cannot co-exist */ 2696 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2697 smu->user_dpm_profile.fan_speed_pwm = 0; 2698 } 2699 2700 return ret; 2701 } 2702 2703 /** 2704 * smu_get_power_limit - Request one of the SMU Power Limits 2705 * 2706 * @handle: pointer to smu context 2707 * @limit: requested limit is written back to this variable 2708 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2709 * @pp_power_type: &pp_power_type type of power 2710 * Return: 0 on success, <0 on error 2711 * 2712 */ 2713 int smu_get_power_limit(void *handle, 2714 uint32_t *limit, 2715 enum pp_power_limit_level pp_limit_level, 2716 enum pp_power_type pp_power_type) 2717 { 2718 struct smu_context *smu = handle; 2719 struct amdgpu_device *adev = smu->adev; 2720 enum smu_ppt_limit_level limit_level; 2721 uint32_t limit_type; 2722 int ret = 0; 2723 2724 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2725 return -EOPNOTSUPP; 2726 2727 switch (pp_power_type) { 2728 case PP_PWR_TYPE_SUSTAINED: 2729 limit_type = SMU_DEFAULT_PPT_LIMIT; 2730 break; 2731 case PP_PWR_TYPE_FAST: 2732 limit_type = SMU_FAST_PPT_LIMIT; 2733 break; 2734 default: 2735 return -EOPNOTSUPP; 2736 } 2737 2738 switch (pp_limit_level) { 2739 case PP_PWR_LIMIT_CURRENT: 2740 limit_level = SMU_PPT_LIMIT_CURRENT; 2741 break; 2742 case PP_PWR_LIMIT_DEFAULT: 2743 limit_level = SMU_PPT_LIMIT_DEFAULT; 2744 break; 2745 case PP_PWR_LIMIT_MAX: 2746 limit_level = SMU_PPT_LIMIT_MAX; 2747 break; 2748 case PP_PWR_LIMIT_MIN: 2749 limit_level = SMU_PPT_LIMIT_MIN; 2750 break; 2751 default: 2752 return -EOPNOTSUPP; 2753 } 2754 2755 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2756 if (smu->ppt_funcs->get_ppt_limit) 2757 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2758 } else { 2759 switch (limit_level) { 2760 case SMU_PPT_LIMIT_CURRENT: 2761 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2762 case IP_VERSION(13, 0, 2): 2763 case IP_VERSION(13, 0, 6): 2764 case IP_VERSION(13, 0, 14): 2765 case IP_VERSION(11, 0, 7): 2766 case IP_VERSION(11, 0, 11): 2767 case IP_VERSION(11, 0, 12): 2768 case IP_VERSION(11, 0, 13): 2769 ret = smu_get_asic_power_limits(smu, 2770 &smu->current_power_limit, 2771 NULL, NULL, NULL); 2772 break; 2773 default: 2774 break; 2775 } 2776 *limit = smu->current_power_limit; 2777 break; 2778 case SMU_PPT_LIMIT_DEFAULT: 2779 *limit = smu->default_power_limit; 2780 break; 2781 case SMU_PPT_LIMIT_MAX: 2782 *limit = smu->max_power_limit; 2783 break; 2784 case SMU_PPT_LIMIT_MIN: 2785 *limit = smu->min_power_limit; 2786 break; 2787 default: 2788 return -EINVAL; 2789 } 2790 } 2791 2792 return ret; 2793 } 2794 2795 static int smu_set_power_limit(void *handle, uint32_t limit) 2796 { 2797 struct smu_context *smu = handle; 2798 uint32_t limit_type = limit >> 24; 2799 int ret = 0; 2800 2801 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2802 return -EOPNOTSUPP; 2803 2804 limit &= (1<<24)-1; 2805 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2806 if (smu->ppt_funcs->set_power_limit) 2807 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2808 2809 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2810 dev_err(smu->adev->dev, 2811 "New power limit (%d) is out of range [%d,%d]\n", 2812 limit, smu->min_power_limit, smu->max_power_limit); 2813 return -EINVAL; 2814 } 2815 2816 if (!limit) 2817 limit = smu->current_power_limit; 2818 2819 if (smu->ppt_funcs->set_power_limit) { 2820 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2821 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2822 smu->user_dpm_profile.power_limit = limit; 2823 } 2824 2825 return ret; 2826 } 2827 2828 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2829 { 2830 int ret = 0; 2831 2832 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2833 return -EOPNOTSUPP; 2834 2835 if (smu->ppt_funcs->print_clk_levels) 2836 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2837 2838 return ret; 2839 } 2840 2841 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2842 { 2843 enum smu_clk_type clk_type; 2844 2845 switch (type) { 2846 case PP_SCLK: 2847 clk_type = SMU_SCLK; break; 2848 case PP_MCLK: 2849 clk_type = SMU_MCLK; break; 2850 case PP_PCIE: 2851 clk_type = SMU_PCIE; break; 2852 case PP_SOCCLK: 2853 clk_type = SMU_SOCCLK; break; 2854 case PP_FCLK: 2855 clk_type = SMU_FCLK; break; 2856 case PP_DCEFCLK: 2857 clk_type = SMU_DCEFCLK; break; 2858 case PP_VCLK: 2859 clk_type = SMU_VCLK; break; 2860 case PP_VCLK1: 2861 clk_type = SMU_VCLK1; break; 2862 case PP_DCLK: 2863 clk_type = SMU_DCLK; break; 2864 case PP_DCLK1: 2865 clk_type = SMU_DCLK1; break; 2866 case OD_SCLK: 2867 clk_type = SMU_OD_SCLK; break; 2868 case OD_MCLK: 2869 clk_type = SMU_OD_MCLK; break; 2870 case OD_VDDC_CURVE: 2871 clk_type = SMU_OD_VDDC_CURVE; break; 2872 case OD_RANGE: 2873 clk_type = SMU_OD_RANGE; break; 2874 case OD_VDDGFX_OFFSET: 2875 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2876 case OD_CCLK: 2877 clk_type = SMU_OD_CCLK; break; 2878 case OD_FAN_CURVE: 2879 clk_type = SMU_OD_FAN_CURVE; break; 2880 case OD_ACOUSTIC_LIMIT: 2881 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2882 case OD_ACOUSTIC_TARGET: 2883 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2884 case OD_FAN_TARGET_TEMPERATURE: 2885 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2886 case OD_FAN_MINIMUM_PWM: 2887 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2888 default: 2889 clk_type = SMU_CLK_COUNT; break; 2890 } 2891 2892 return clk_type; 2893 } 2894 2895 static int smu_print_ppclk_levels(void *handle, 2896 enum pp_clock_type type, 2897 char *buf) 2898 { 2899 struct smu_context *smu = handle; 2900 enum smu_clk_type clk_type; 2901 2902 clk_type = smu_convert_to_smuclk(type); 2903 if (clk_type == SMU_CLK_COUNT) 2904 return -EINVAL; 2905 2906 return smu_print_smuclk_levels(smu, clk_type, buf); 2907 } 2908 2909 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2910 { 2911 struct smu_context *smu = handle; 2912 enum smu_clk_type clk_type; 2913 2914 clk_type = smu_convert_to_smuclk(type); 2915 if (clk_type == SMU_CLK_COUNT) 2916 return -EINVAL; 2917 2918 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2919 return -EOPNOTSUPP; 2920 2921 if (!smu->ppt_funcs->emit_clk_levels) 2922 return -ENOENT; 2923 2924 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2925 2926 } 2927 2928 static int smu_od_edit_dpm_table(void *handle, 2929 enum PP_OD_DPM_TABLE_COMMAND type, 2930 long *input, uint32_t size) 2931 { 2932 struct smu_context *smu = handle; 2933 int ret = 0; 2934 2935 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2936 return -EOPNOTSUPP; 2937 2938 if (smu->ppt_funcs->od_edit_dpm_table) { 2939 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2940 } 2941 2942 return ret; 2943 } 2944 2945 static int smu_read_sensor(void *handle, 2946 int sensor, 2947 void *data, 2948 int *size_arg) 2949 { 2950 struct smu_context *smu = handle; 2951 struct smu_umd_pstate_table *pstate_table = 2952 &smu->pstate_table; 2953 int ret = 0; 2954 uint32_t *size, size_val; 2955 2956 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2957 return -EOPNOTSUPP; 2958 2959 if (!data || !size_arg) 2960 return -EINVAL; 2961 2962 size_val = *size_arg; 2963 size = &size_val; 2964 2965 if (smu->ppt_funcs->read_sensor) 2966 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2967 goto unlock; 2968 2969 switch (sensor) { 2970 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2971 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2972 *size = 4; 2973 break; 2974 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2975 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2976 *size = 4; 2977 break; 2978 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2979 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2980 *size = 4; 2981 break; 2982 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2983 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2984 *size = 4; 2985 break; 2986 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2987 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2988 *size = 8; 2989 break; 2990 case AMDGPU_PP_SENSOR_UVD_POWER: 2991 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2992 *size = 4; 2993 break; 2994 case AMDGPU_PP_SENSOR_VCE_POWER: 2995 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2996 *size = 4; 2997 break; 2998 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2999 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 3000 *size = 4; 3001 break; 3002 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3003 *(uint32_t *)data = 0; 3004 *size = 4; 3005 break; 3006 default: 3007 *size = 0; 3008 ret = -EOPNOTSUPP; 3009 break; 3010 } 3011 3012 unlock: 3013 // assign uint32_t to int 3014 *size_arg = size_val; 3015 3016 return ret; 3017 } 3018 3019 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3020 { 3021 int ret = -EOPNOTSUPP; 3022 struct smu_context *smu = handle; 3023 3024 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3025 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3026 3027 return ret; 3028 } 3029 3030 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3031 { 3032 int ret = -EOPNOTSUPP; 3033 struct smu_context *smu = handle; 3034 3035 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3036 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3037 3038 return ret; 3039 } 3040 3041 static int smu_get_power_profile_mode(void *handle, char *buf) 3042 { 3043 struct smu_context *smu = handle; 3044 3045 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3046 !smu->ppt_funcs->get_power_profile_mode) 3047 return -EOPNOTSUPP; 3048 if (!buf) 3049 return -EINVAL; 3050 3051 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3052 } 3053 3054 static int smu_set_power_profile_mode(void *handle, 3055 long *param, 3056 uint32_t param_size) 3057 { 3058 struct smu_context *smu = handle; 3059 3060 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3061 !smu->ppt_funcs->set_power_profile_mode) 3062 return -EOPNOTSUPP; 3063 3064 return smu_bump_power_profile_mode(smu, param, param_size); 3065 } 3066 3067 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3068 { 3069 struct smu_context *smu = handle; 3070 3071 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3072 return -EOPNOTSUPP; 3073 3074 if (!smu->ppt_funcs->get_fan_control_mode) 3075 return -EOPNOTSUPP; 3076 3077 if (!fan_mode) 3078 return -EINVAL; 3079 3080 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3081 3082 return 0; 3083 } 3084 3085 static int smu_set_fan_control_mode(void *handle, u32 value) 3086 { 3087 struct smu_context *smu = handle; 3088 int ret = 0; 3089 3090 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3091 return -EOPNOTSUPP; 3092 3093 if (!smu->ppt_funcs->set_fan_control_mode) 3094 return -EOPNOTSUPP; 3095 3096 if (value == U32_MAX) 3097 return -EINVAL; 3098 3099 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3100 if (ret) 3101 goto out; 3102 3103 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3104 smu->user_dpm_profile.fan_mode = value; 3105 3106 /* reset user dpm fan speed */ 3107 if (value != AMD_FAN_CTRL_MANUAL) { 3108 smu->user_dpm_profile.fan_speed_pwm = 0; 3109 smu->user_dpm_profile.fan_speed_rpm = 0; 3110 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3111 } 3112 } 3113 3114 out: 3115 return ret; 3116 } 3117 3118 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3119 { 3120 struct smu_context *smu = handle; 3121 int ret = 0; 3122 3123 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3124 return -EOPNOTSUPP; 3125 3126 if (!smu->ppt_funcs->get_fan_speed_pwm) 3127 return -EOPNOTSUPP; 3128 3129 if (!speed) 3130 return -EINVAL; 3131 3132 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3133 3134 return ret; 3135 } 3136 3137 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3138 { 3139 struct smu_context *smu = handle; 3140 int ret = 0; 3141 3142 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3143 return -EOPNOTSUPP; 3144 3145 if (!smu->ppt_funcs->set_fan_speed_pwm) 3146 return -EOPNOTSUPP; 3147 3148 if (speed == U32_MAX) 3149 return -EINVAL; 3150 3151 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3152 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3153 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3154 smu->user_dpm_profile.fan_speed_pwm = speed; 3155 3156 /* Override custom RPM setting as they cannot co-exist */ 3157 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3158 smu->user_dpm_profile.fan_speed_rpm = 0; 3159 } 3160 3161 return ret; 3162 } 3163 3164 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3165 { 3166 struct smu_context *smu = handle; 3167 int ret = 0; 3168 3169 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3170 return -EOPNOTSUPP; 3171 3172 if (!smu->ppt_funcs->get_fan_speed_rpm) 3173 return -EOPNOTSUPP; 3174 3175 if (!speed) 3176 return -EINVAL; 3177 3178 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3179 3180 return ret; 3181 } 3182 3183 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3184 { 3185 struct smu_context *smu = handle; 3186 3187 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3188 return -EOPNOTSUPP; 3189 3190 return smu_set_min_dcef_deep_sleep(smu, clk); 3191 } 3192 3193 static int smu_get_clock_by_type_with_latency(void *handle, 3194 enum amd_pp_clock_type type, 3195 struct pp_clock_levels_with_latency *clocks) 3196 { 3197 struct smu_context *smu = handle; 3198 enum smu_clk_type clk_type; 3199 int ret = 0; 3200 3201 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3202 return -EOPNOTSUPP; 3203 3204 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3205 switch (type) { 3206 case amd_pp_sys_clock: 3207 clk_type = SMU_GFXCLK; 3208 break; 3209 case amd_pp_mem_clock: 3210 clk_type = SMU_MCLK; 3211 break; 3212 case amd_pp_dcef_clock: 3213 clk_type = SMU_DCEFCLK; 3214 break; 3215 case amd_pp_disp_clock: 3216 clk_type = SMU_DISPCLK; 3217 break; 3218 default: 3219 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3220 return -EINVAL; 3221 } 3222 3223 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3224 } 3225 3226 return ret; 3227 } 3228 3229 static int smu_display_clock_voltage_request(void *handle, 3230 struct pp_display_clock_request *clock_req) 3231 { 3232 struct smu_context *smu = handle; 3233 int ret = 0; 3234 3235 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3236 return -EOPNOTSUPP; 3237 3238 if (smu->ppt_funcs->display_clock_voltage_request) 3239 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3240 3241 return ret; 3242 } 3243 3244 3245 static int smu_display_disable_memory_clock_switch(void *handle, 3246 bool disable_memory_clock_switch) 3247 { 3248 struct smu_context *smu = handle; 3249 int ret = -EINVAL; 3250 3251 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3252 return -EOPNOTSUPP; 3253 3254 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3255 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3256 3257 return ret; 3258 } 3259 3260 static int smu_set_xgmi_pstate(void *handle, 3261 uint32_t pstate) 3262 { 3263 struct smu_context *smu = handle; 3264 int ret = 0; 3265 3266 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3267 return -EOPNOTSUPP; 3268 3269 if (smu->ppt_funcs->set_xgmi_pstate) 3270 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3271 3272 if (ret) 3273 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3274 3275 return ret; 3276 } 3277 3278 static int smu_get_baco_capability(void *handle) 3279 { 3280 struct smu_context *smu = handle; 3281 3282 if (!smu->pm_enabled) 3283 return false; 3284 3285 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3286 return false; 3287 3288 return smu->ppt_funcs->get_bamaco_support(smu); 3289 } 3290 3291 static int smu_baco_set_state(void *handle, int state) 3292 { 3293 struct smu_context *smu = handle; 3294 int ret = 0; 3295 3296 if (!smu->pm_enabled) 3297 return -EOPNOTSUPP; 3298 3299 if (state == 0) { 3300 if (smu->ppt_funcs->baco_exit) 3301 ret = smu->ppt_funcs->baco_exit(smu); 3302 } else if (state == 1) { 3303 if (smu->ppt_funcs->baco_enter) 3304 ret = smu->ppt_funcs->baco_enter(smu); 3305 } else { 3306 return -EINVAL; 3307 } 3308 3309 if (ret) 3310 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3311 (state)?"enter":"exit"); 3312 3313 return ret; 3314 } 3315 3316 bool smu_mode1_reset_is_support(struct smu_context *smu) 3317 { 3318 bool ret = false; 3319 3320 if (!smu->pm_enabled) 3321 return false; 3322 3323 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3324 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3325 3326 return ret; 3327 } 3328 3329 bool smu_mode2_reset_is_support(struct smu_context *smu) 3330 { 3331 bool ret = false; 3332 3333 if (!smu->pm_enabled) 3334 return false; 3335 3336 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3337 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3338 3339 return ret; 3340 } 3341 3342 int smu_mode1_reset(struct smu_context *smu) 3343 { 3344 int ret = 0; 3345 3346 if (!smu->pm_enabled) 3347 return -EOPNOTSUPP; 3348 3349 if (smu->ppt_funcs->mode1_reset) 3350 ret = smu->ppt_funcs->mode1_reset(smu); 3351 3352 return ret; 3353 } 3354 3355 static int smu_mode2_reset(void *handle) 3356 { 3357 struct smu_context *smu = handle; 3358 int ret = 0; 3359 3360 if (!smu->pm_enabled) 3361 return -EOPNOTSUPP; 3362 3363 if (smu->ppt_funcs->mode2_reset) 3364 ret = smu->ppt_funcs->mode2_reset(smu); 3365 3366 if (ret) 3367 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3368 3369 return ret; 3370 } 3371 3372 static int smu_enable_gfx_features(void *handle) 3373 { 3374 struct smu_context *smu = handle; 3375 int ret = 0; 3376 3377 if (!smu->pm_enabled) 3378 return -EOPNOTSUPP; 3379 3380 if (smu->ppt_funcs->enable_gfx_features) 3381 ret = smu->ppt_funcs->enable_gfx_features(smu); 3382 3383 if (ret) 3384 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3385 3386 return ret; 3387 } 3388 3389 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3390 struct pp_smu_nv_clock_table *max_clocks) 3391 { 3392 struct smu_context *smu = handle; 3393 int ret = 0; 3394 3395 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3396 return -EOPNOTSUPP; 3397 3398 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3399 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3400 3401 return ret; 3402 } 3403 3404 static int smu_get_uclk_dpm_states(void *handle, 3405 unsigned int *clock_values_in_khz, 3406 unsigned int *num_states) 3407 { 3408 struct smu_context *smu = handle; 3409 int ret = 0; 3410 3411 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3412 return -EOPNOTSUPP; 3413 3414 if (smu->ppt_funcs->get_uclk_dpm_states) 3415 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3416 3417 return ret; 3418 } 3419 3420 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3421 { 3422 struct smu_context *smu = handle; 3423 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3424 3425 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3426 return -EOPNOTSUPP; 3427 3428 if (smu->ppt_funcs->get_current_power_state) 3429 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3430 3431 return pm_state; 3432 } 3433 3434 static int smu_get_dpm_clock_table(void *handle, 3435 struct dpm_clocks *clock_table) 3436 { 3437 struct smu_context *smu = handle; 3438 int ret = 0; 3439 3440 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3441 return -EOPNOTSUPP; 3442 3443 if (smu->ppt_funcs->get_dpm_clock_table) 3444 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3445 3446 return ret; 3447 } 3448 3449 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3450 { 3451 struct smu_context *smu = handle; 3452 3453 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3454 return -EOPNOTSUPP; 3455 3456 if (!smu->ppt_funcs->get_gpu_metrics) 3457 return -EOPNOTSUPP; 3458 3459 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3460 } 3461 3462 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3463 size_t size) 3464 { 3465 struct smu_context *smu = handle; 3466 3467 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3468 return -EOPNOTSUPP; 3469 3470 if (!smu->ppt_funcs->get_pm_metrics) 3471 return -EOPNOTSUPP; 3472 3473 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3474 } 3475 3476 static int smu_enable_mgpu_fan_boost(void *handle) 3477 { 3478 struct smu_context *smu = handle; 3479 int ret = 0; 3480 3481 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3482 return -EOPNOTSUPP; 3483 3484 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3485 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3486 3487 return ret; 3488 } 3489 3490 static int smu_gfx_state_change_set(void *handle, 3491 uint32_t state) 3492 { 3493 struct smu_context *smu = handle; 3494 int ret = 0; 3495 3496 if (smu->ppt_funcs->gfx_state_change_set) 3497 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3498 3499 return ret; 3500 } 3501 3502 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3503 { 3504 int ret = 0; 3505 3506 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3507 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3508 3509 return ret; 3510 } 3511 3512 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3513 { 3514 int ret = -EOPNOTSUPP; 3515 3516 if (smu->ppt_funcs && 3517 smu->ppt_funcs->get_ecc_info) 3518 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3519 3520 return ret; 3521 3522 } 3523 3524 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3525 { 3526 struct smu_context *smu = handle; 3527 struct smu_table_context *smu_table = &smu->smu_table; 3528 struct smu_table *memory_pool = &smu_table->memory_pool; 3529 3530 if (!addr || !size) 3531 return -EINVAL; 3532 3533 *addr = NULL; 3534 *size = 0; 3535 if (memory_pool->bo) { 3536 *addr = memory_pool->cpu_addr; 3537 *size = memory_pool->size; 3538 } 3539 3540 return 0; 3541 } 3542 3543 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3544 size_t *size) 3545 { 3546 size_t offset = *size; 3547 int level; 3548 3549 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3550 if (level == policy->current_level) 3551 offset += sysfs_emit_at(sysbuf, offset, 3552 "%d : %s*\n", level, 3553 policy->desc->get_desc(policy, level)); 3554 else 3555 offset += sysfs_emit_at(sysbuf, offset, 3556 "%d : %s\n", level, 3557 policy->desc->get_desc(policy, level)); 3558 } 3559 3560 *size = offset; 3561 } 3562 3563 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3564 enum pp_pm_policy p_type, char *sysbuf) 3565 { 3566 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3567 struct smu_dpm_policy_ctxt *policy_ctxt; 3568 struct smu_dpm_policy *dpm_policy; 3569 size_t offset = 0; 3570 3571 policy_ctxt = dpm_ctxt->dpm_policies; 3572 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3573 !policy_ctxt->policy_mask) 3574 return -EOPNOTSUPP; 3575 3576 if (p_type == PP_PM_POLICY_NONE) 3577 return -EINVAL; 3578 3579 dpm_policy = smu_get_pm_policy(smu, p_type); 3580 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3581 return -ENOENT; 3582 3583 if (!sysbuf) 3584 return -EINVAL; 3585 3586 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3587 3588 return offset; 3589 } 3590 3591 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3592 enum pp_pm_policy p_type) 3593 { 3594 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3595 struct smu_dpm_policy_ctxt *policy_ctxt; 3596 int i; 3597 3598 policy_ctxt = dpm_ctxt->dpm_policies; 3599 if (!policy_ctxt) 3600 return NULL; 3601 3602 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3603 if (policy_ctxt->policies[i].policy_type == p_type) 3604 return &policy_ctxt->policies[i]; 3605 } 3606 3607 return NULL; 3608 } 3609 3610 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3611 int level) 3612 { 3613 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3614 struct smu_dpm_policy *dpm_policy = NULL; 3615 struct smu_dpm_policy_ctxt *policy_ctxt; 3616 int ret = -EOPNOTSUPP; 3617 3618 policy_ctxt = dpm_ctxt->dpm_policies; 3619 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3620 !policy_ctxt->policy_mask) 3621 return ret; 3622 3623 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3624 return -EINVAL; 3625 3626 dpm_policy = smu_get_pm_policy(smu, p_type); 3627 3628 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3629 return ret; 3630 3631 if (dpm_policy->current_level == level) 3632 return 0; 3633 3634 ret = dpm_policy->set_policy(smu, level); 3635 3636 if (!ret) 3637 dpm_policy->current_level = level; 3638 3639 return ret; 3640 } 3641 3642 static const struct amd_pm_funcs swsmu_pm_funcs = { 3643 /* export for sysfs */ 3644 .set_fan_control_mode = smu_set_fan_control_mode, 3645 .get_fan_control_mode = smu_get_fan_control_mode, 3646 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3647 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3648 .force_clock_level = smu_force_ppclk_levels, 3649 .print_clock_levels = smu_print_ppclk_levels, 3650 .emit_clock_levels = smu_emit_ppclk_levels, 3651 .force_performance_level = smu_force_performance_level, 3652 .read_sensor = smu_read_sensor, 3653 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3654 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3655 .get_performance_level = smu_get_performance_level, 3656 .get_current_power_state = smu_get_current_power_state, 3657 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3658 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3659 .get_pp_num_states = smu_get_power_num_states, 3660 .get_pp_table = smu_sys_get_pp_table, 3661 .set_pp_table = smu_sys_set_pp_table, 3662 .switch_power_profile = smu_switch_power_profile, 3663 /* export to amdgpu */ 3664 .dispatch_tasks = smu_handle_dpm_task, 3665 .load_firmware = smu_load_microcode, 3666 .set_powergating_by_smu = smu_dpm_set_power_gate, 3667 .set_power_limit = smu_set_power_limit, 3668 .get_power_limit = smu_get_power_limit, 3669 .get_power_profile_mode = smu_get_power_profile_mode, 3670 .set_power_profile_mode = smu_set_power_profile_mode, 3671 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3672 .set_mp1_state = smu_set_mp1_state, 3673 .gfx_state_change_set = smu_gfx_state_change_set, 3674 /* export to DC */ 3675 .get_sclk = smu_get_sclk, 3676 .get_mclk = smu_get_mclk, 3677 .display_configuration_change = smu_display_configuration_change, 3678 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3679 .display_clock_voltage_request = smu_display_clock_voltage_request, 3680 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3681 .set_active_display_count = smu_set_display_count, 3682 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3683 .get_asic_baco_capability = smu_get_baco_capability, 3684 .set_asic_baco_state = smu_baco_set_state, 3685 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3686 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3687 .asic_reset_mode_2 = smu_mode2_reset, 3688 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3689 .set_df_cstate = smu_set_df_cstate, 3690 .set_xgmi_pstate = smu_set_xgmi_pstate, 3691 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3692 .get_pm_metrics = smu_sys_get_pm_metrics, 3693 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3694 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3695 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3696 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3697 .get_dpm_clock_table = smu_get_dpm_clock_table, 3698 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3699 }; 3700 3701 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3702 uint64_t event_arg) 3703 { 3704 int ret = -EINVAL; 3705 3706 if (smu->ppt_funcs->wait_for_event) 3707 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3708 3709 return ret; 3710 } 3711 3712 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3713 { 3714 3715 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3716 return -EOPNOTSUPP; 3717 3718 /* Confirm the buffer allocated is of correct size */ 3719 if (size != smu->stb_context.stb_buf_size) 3720 return -EINVAL; 3721 3722 /* 3723 * No need to lock smu mutex as we access STB directly through MMIO 3724 * and not going through SMU messaging route (for now at least). 3725 * For registers access rely on implementation internal locking. 3726 */ 3727 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3728 } 3729 3730 #if defined(CONFIG_DEBUG_FS) 3731 3732 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3733 { 3734 struct amdgpu_device *adev = filp->f_inode->i_private; 3735 struct smu_context *smu = adev->powerplay.pp_handle; 3736 unsigned char *buf; 3737 int r; 3738 3739 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3740 if (!buf) 3741 return -ENOMEM; 3742 3743 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3744 if (r) 3745 goto out; 3746 3747 filp->private_data = buf; 3748 3749 return 0; 3750 3751 out: 3752 kvfree(buf); 3753 return r; 3754 } 3755 3756 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3757 loff_t *pos) 3758 { 3759 struct amdgpu_device *adev = filp->f_inode->i_private; 3760 struct smu_context *smu = adev->powerplay.pp_handle; 3761 3762 3763 if (!filp->private_data) 3764 return -EINVAL; 3765 3766 return simple_read_from_buffer(buf, 3767 size, 3768 pos, filp->private_data, 3769 smu->stb_context.stb_buf_size); 3770 } 3771 3772 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3773 { 3774 kvfree(filp->private_data); 3775 filp->private_data = NULL; 3776 3777 return 0; 3778 } 3779 3780 /* 3781 * We have to define not only read method but also 3782 * open and release because .read takes up to PAGE_SIZE 3783 * data each time so and so is invoked multiple times. 3784 * We allocate the STB buffer in .open and release it 3785 * in .release 3786 */ 3787 static const struct file_operations smu_stb_debugfs_fops = { 3788 .owner = THIS_MODULE, 3789 .open = smu_stb_debugfs_open, 3790 .read = smu_stb_debugfs_read, 3791 .release = smu_stb_debugfs_release, 3792 .llseek = default_llseek, 3793 }; 3794 3795 #endif 3796 3797 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3798 { 3799 #if defined(CONFIG_DEBUG_FS) 3800 3801 struct smu_context *smu = adev->powerplay.pp_handle; 3802 3803 if (!smu || (!smu->stb_context.stb_buf_size)) 3804 return; 3805 3806 debugfs_create_file_size("amdgpu_smu_stb_dump", 3807 S_IRUSR, 3808 adev_to_drm(adev)->primary->debugfs_root, 3809 adev, 3810 &smu_stb_debugfs_fops, 3811 smu->stb_context.stb_buf_size); 3812 #endif 3813 } 3814 3815 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3816 { 3817 int ret = 0; 3818 3819 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3820 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3821 3822 return ret; 3823 } 3824 3825 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3826 { 3827 int ret = 0; 3828 3829 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3830 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3831 3832 return ret; 3833 } 3834 3835 int smu_send_rma_reason(struct smu_context *smu) 3836 { 3837 int ret = 0; 3838 3839 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3840 ret = smu->ppt_funcs->send_rma_reason(smu); 3841 3842 return ret; 3843 } 3844