1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "amd_pcie.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 static const struct amd_pm_funcs swsmu_pm_funcs; 62 static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65 static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68 static int smu_reset(struct smu_context *smu); 69 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70 static int smu_set_fan_control_mode(void *handle, u32 value); 71 static int smu_set_power_limit(void *handle, uint32_t limit); 72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75 76 static int smu_sys_get_pp_feature_mask(void *handle, 77 char *buf) 78 { 79 struct smu_context *smu = handle; 80 81 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 82 return -EOPNOTSUPP; 83 84 return smu_get_pp_feature_mask(smu, buf); 85 } 86 87 static int smu_sys_set_pp_feature_mask(void *handle, 88 uint64_t new_mask) 89 { 90 struct smu_context *smu = handle; 91 92 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 93 return -EOPNOTSUPP; 94 95 return smu_set_pp_feature_mask(smu, new_mask); 96 } 97 98 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 99 { 100 if (!smu->ppt_funcs->set_gfx_off_residency) 101 return -EINVAL; 102 103 return smu_set_gfx_off_residency(smu, value); 104 } 105 106 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 107 { 108 if (!smu->ppt_funcs->get_gfx_off_residency) 109 return -EINVAL; 110 111 return smu_get_gfx_off_residency(smu, value); 112 } 113 114 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 115 { 116 if (!smu->ppt_funcs->get_gfx_off_entrycount) 117 return -EINVAL; 118 119 return smu_get_gfx_off_entrycount(smu, value); 120 } 121 122 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 123 { 124 if (!smu->ppt_funcs->get_gfx_off_status) 125 return -EINVAL; 126 127 *value = smu_get_gfx_off_status(smu); 128 129 return 0; 130 } 131 132 int smu_set_soft_freq_range(struct smu_context *smu, 133 enum smu_clk_type clk_type, 134 uint32_t min, 135 uint32_t max) 136 { 137 int ret = 0; 138 139 if (smu->ppt_funcs->set_soft_freq_limited_range) 140 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 141 clk_type, 142 min, 143 max); 144 145 return ret; 146 } 147 148 int smu_get_dpm_freq_range(struct smu_context *smu, 149 enum smu_clk_type clk_type, 150 uint32_t *min, 151 uint32_t *max) 152 { 153 int ret = -ENOTSUPP; 154 155 if (!min && !max) 156 return -EINVAL; 157 158 if (smu->ppt_funcs->get_dpm_ultimate_freq) 159 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 160 clk_type, 161 min, 162 max); 163 164 return ret; 165 } 166 167 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 168 { 169 int ret = 0; 170 struct amdgpu_device *adev = smu->adev; 171 172 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 173 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 174 if (ret) 175 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 176 } 177 return ret; 178 } 179 180 static u32 smu_get_mclk(void *handle, bool low) 181 { 182 struct smu_context *smu = handle; 183 uint32_t clk_freq; 184 int ret = 0; 185 186 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 187 low ? &clk_freq : NULL, 188 !low ? &clk_freq : NULL); 189 if (ret) 190 return 0; 191 return clk_freq * 100; 192 } 193 194 static u32 smu_get_sclk(void *handle, bool low) 195 { 196 struct smu_context *smu = handle; 197 uint32_t clk_freq; 198 int ret = 0; 199 200 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 201 low ? &clk_freq : NULL, 202 !low ? &clk_freq : NULL); 203 if (ret) 204 return 0; 205 return clk_freq * 100; 206 } 207 208 static int smu_set_gfx_imu_enable(struct smu_context *smu) 209 { 210 struct amdgpu_device *adev = smu->adev; 211 212 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 213 return 0; 214 215 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 216 return 0; 217 218 return smu_set_gfx_power_up_by_imu(smu); 219 } 220 221 static bool is_vcn_enabled(struct amdgpu_device *adev) 222 { 223 int i; 224 225 for (i = 0; i < adev->num_ip_blocks; i++) { 226 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 227 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 228 !adev->ip_blocks[i].status.valid) 229 return false; 230 } 231 232 return true; 233 } 234 235 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 236 bool enable) 237 { 238 struct smu_power_context *smu_power = &smu->smu_power; 239 struct smu_power_gate *power_gate = &smu_power->power_gate; 240 int ret = 0; 241 242 /* 243 * don't poweron vcn/jpeg when they are skipped. 244 */ 245 if (!is_vcn_enabled(smu->adev)) 246 return 0; 247 248 if (!smu->ppt_funcs->dpm_set_vcn_enable) 249 return 0; 250 251 if (atomic_read(&power_gate->vcn_gated) ^ enable) 252 return 0; 253 254 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 255 if (!ret) 256 atomic_set(&power_gate->vcn_gated, !enable); 257 258 return ret; 259 } 260 261 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 262 bool enable) 263 { 264 struct smu_power_context *smu_power = &smu->smu_power; 265 struct smu_power_gate *power_gate = &smu_power->power_gate; 266 int ret = 0; 267 268 if (!is_vcn_enabled(smu->adev)) 269 return 0; 270 271 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 272 return 0; 273 274 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 275 return 0; 276 277 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 278 if (!ret) 279 atomic_set(&power_gate->jpeg_gated, !enable); 280 281 return ret; 282 } 283 284 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 285 bool enable) 286 { 287 struct smu_power_context *smu_power = &smu->smu_power; 288 struct smu_power_gate *power_gate = &smu_power->power_gate; 289 int ret = 0; 290 291 if (!smu->ppt_funcs->dpm_set_vpe_enable) 292 return 0; 293 294 if (atomic_read(&power_gate->vpe_gated) ^ enable) 295 return 0; 296 297 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 298 if (!ret) 299 atomic_set(&power_gate->vpe_gated, !enable); 300 301 return ret; 302 } 303 304 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 305 bool enable) 306 { 307 struct smu_power_context *smu_power = &smu->smu_power; 308 struct smu_power_gate *power_gate = &smu_power->power_gate; 309 int ret = 0; 310 311 if (!smu->adev->enable_umsch_mm) 312 return 0; 313 314 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 315 return 0; 316 317 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 318 return 0; 319 320 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 321 if (!ret) 322 atomic_set(&power_gate->umsch_mm_gated, !enable); 323 324 return ret; 325 } 326 327 static int smu_set_mall_enable(struct smu_context *smu) 328 { 329 int ret = 0; 330 331 if (!smu->ppt_funcs->set_mall_enable) 332 return 0; 333 334 ret = smu->ppt_funcs->set_mall_enable(smu); 335 336 return ret; 337 } 338 339 /** 340 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 341 * 342 * @handle: smu_context pointer 343 * @block_type: the IP block to power gate/ungate 344 * @gate: to power gate if true, ungate otherwise 345 * 346 * This API uses no smu->mutex lock protection due to: 347 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 348 * This is guarded to be race condition free by the caller. 349 * 2. Or get called on user setting request of power_dpm_force_performance_level. 350 * Under this case, the smu->mutex lock protection is already enforced on 351 * the parent API smu_force_performance_level of the call path. 352 */ 353 static int smu_dpm_set_power_gate(void *handle, 354 uint32_t block_type, 355 bool gate) 356 { 357 struct smu_context *smu = handle; 358 int ret = 0; 359 360 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 361 dev_WARN(smu->adev->dev, 362 "SMU uninitialized but power %s requested for %u!\n", 363 gate ? "gate" : "ungate", block_type); 364 return -EOPNOTSUPP; 365 } 366 367 switch (block_type) { 368 /* 369 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 370 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 371 */ 372 case AMD_IP_BLOCK_TYPE_UVD: 373 case AMD_IP_BLOCK_TYPE_VCN: 374 ret = smu_dpm_set_vcn_enable(smu, !gate); 375 if (ret) 376 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 377 gate ? "gate" : "ungate"); 378 break; 379 case AMD_IP_BLOCK_TYPE_GFX: 380 ret = smu_gfx_off_control(smu, gate); 381 if (ret) 382 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 383 gate ? "enable" : "disable"); 384 break; 385 case AMD_IP_BLOCK_TYPE_SDMA: 386 ret = smu_powergate_sdma(smu, gate); 387 if (ret) 388 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 389 gate ? "gate" : "ungate"); 390 break; 391 case AMD_IP_BLOCK_TYPE_JPEG: 392 ret = smu_dpm_set_jpeg_enable(smu, !gate); 393 if (ret) 394 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 395 gate ? "gate" : "ungate"); 396 break; 397 case AMD_IP_BLOCK_TYPE_VPE: 398 ret = smu_dpm_set_vpe_enable(smu, !gate); 399 if (ret) 400 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 401 gate ? "gate" : "ungate"); 402 break; 403 default: 404 dev_err(smu->adev->dev, "Unsupported block type!\n"); 405 return -EINVAL; 406 } 407 408 return ret; 409 } 410 411 /** 412 * smu_set_user_clk_dependencies - set user profile clock dependencies 413 * 414 * @smu: smu_context pointer 415 * @clk: enum smu_clk_type type 416 * 417 * Enable/Disable the clock dependency for the @clk type. 418 */ 419 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 420 { 421 if (smu->adev->in_suspend) 422 return; 423 424 if (clk == SMU_MCLK) { 425 smu->user_dpm_profile.clk_dependency = 0; 426 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 427 } else if (clk == SMU_FCLK) { 428 /* MCLK takes precedence over FCLK */ 429 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 430 return; 431 432 smu->user_dpm_profile.clk_dependency = 0; 433 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 434 } else if (clk == SMU_SOCCLK) { 435 /* MCLK takes precedence over SOCCLK */ 436 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 437 return; 438 439 smu->user_dpm_profile.clk_dependency = 0; 440 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 441 } else 442 /* Add clk dependencies here, if any */ 443 return; 444 } 445 446 /** 447 * smu_restore_dpm_user_profile - reinstate user dpm profile 448 * 449 * @smu: smu_context pointer 450 * 451 * Restore the saved user power configurations include power limit, 452 * clock frequencies, fan control mode and fan speed. 453 */ 454 static void smu_restore_dpm_user_profile(struct smu_context *smu) 455 { 456 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 457 int ret = 0; 458 459 if (!smu->adev->in_suspend) 460 return; 461 462 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 463 return; 464 465 /* Enable restore flag */ 466 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 467 468 /* set the user dpm power limit */ 469 if (smu->user_dpm_profile.power_limit) { 470 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 471 if (ret) 472 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 473 } 474 475 /* set the user dpm clock configurations */ 476 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 477 enum smu_clk_type clk_type; 478 479 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 480 /* 481 * Iterate over smu clk type and force the saved user clk 482 * configs, skip if clock dependency is enabled 483 */ 484 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 485 smu->user_dpm_profile.clk_mask[clk_type]) { 486 ret = smu_force_smuclk_levels(smu, clk_type, 487 smu->user_dpm_profile.clk_mask[clk_type]); 488 if (ret) 489 dev_err(smu->adev->dev, 490 "Failed to set clock type = %d\n", clk_type); 491 } 492 } 493 } 494 495 /* set the user dpm fan configurations */ 496 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 497 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 498 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 499 if (ret != -EOPNOTSUPP) { 500 smu->user_dpm_profile.fan_speed_pwm = 0; 501 smu->user_dpm_profile.fan_speed_rpm = 0; 502 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 503 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 504 } 505 506 if (smu->user_dpm_profile.fan_speed_pwm) { 507 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 508 if (ret != -EOPNOTSUPP) 509 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 510 } 511 512 if (smu->user_dpm_profile.fan_speed_rpm) { 513 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 514 if (ret != -EOPNOTSUPP) 515 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 516 } 517 } 518 519 /* Restore user customized OD settings */ 520 if (smu->user_dpm_profile.user_od) { 521 if (smu->ppt_funcs->restore_user_od_settings) { 522 ret = smu->ppt_funcs->restore_user_od_settings(smu); 523 if (ret) 524 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 525 } 526 } 527 528 /* Disable restore flag */ 529 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 530 } 531 532 static int smu_get_power_num_states(void *handle, 533 struct pp_states_info *state_info) 534 { 535 if (!state_info) 536 return -EINVAL; 537 538 /* not support power state */ 539 memset(state_info, 0, sizeof(struct pp_states_info)); 540 state_info->nums = 1; 541 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 542 543 return 0; 544 } 545 546 bool is_support_sw_smu(struct amdgpu_device *adev) 547 { 548 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 549 if (adev->asic_type == CHIP_VEGA20) 550 return false; 551 552 if (amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) 553 return true; 554 555 return false; 556 } 557 558 bool is_support_cclk_dpm(struct amdgpu_device *adev) 559 { 560 struct smu_context *smu = adev->powerplay.pp_handle; 561 562 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 563 return false; 564 565 return true; 566 } 567 568 569 static int smu_sys_get_pp_table(void *handle, 570 char **table) 571 { 572 struct smu_context *smu = handle; 573 struct smu_table_context *smu_table = &smu->smu_table; 574 575 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 576 return -EOPNOTSUPP; 577 578 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 579 return -EINVAL; 580 581 if (smu_table->hardcode_pptable) 582 *table = smu_table->hardcode_pptable; 583 else 584 *table = smu_table->power_play_table; 585 586 return smu_table->power_play_table_size; 587 } 588 589 static int smu_sys_set_pp_table(void *handle, 590 const char *buf, 591 size_t size) 592 { 593 struct smu_context *smu = handle; 594 struct smu_table_context *smu_table = &smu->smu_table; 595 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 596 int ret = 0; 597 598 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 599 return -EOPNOTSUPP; 600 601 if (header->usStructureSize != size) { 602 dev_err(smu->adev->dev, "pp table size not matched !\n"); 603 return -EIO; 604 } 605 606 if (!smu_table->hardcode_pptable) { 607 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 608 if (!smu_table->hardcode_pptable) 609 return -ENOMEM; 610 } 611 612 memcpy(smu_table->hardcode_pptable, buf, size); 613 smu_table->power_play_table = smu_table->hardcode_pptable; 614 smu_table->power_play_table_size = size; 615 616 /* 617 * Special hw_fini action(for Navi1x, the DPMs disablement will be 618 * skipped) may be needed for custom pptable uploading. 619 */ 620 smu->uploading_custom_pp_table = true; 621 622 ret = smu_reset(smu); 623 if (ret) 624 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 625 626 smu->uploading_custom_pp_table = false; 627 628 return ret; 629 } 630 631 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 632 { 633 struct smu_feature *feature = &smu->smu_feature; 634 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 635 int ret = 0; 636 637 /* 638 * With SCPM enabled, the allowed featuremasks setting(via 639 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 640 * That means there is no way to let PMFW knows the settings below. 641 * Thus, we just assume all the features are allowed under 642 * such scenario. 643 */ 644 if (smu->adev->scpm_enabled) { 645 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 646 return 0; 647 } 648 649 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 650 651 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 652 SMU_FEATURE_MAX/32); 653 if (ret) 654 return ret; 655 656 bitmap_or(feature->allowed, feature->allowed, 657 (unsigned long *)allowed_feature_mask, 658 feature->feature_num); 659 660 return ret; 661 } 662 663 static int smu_set_funcs(struct amdgpu_device *adev) 664 { 665 struct smu_context *smu = adev->powerplay.pp_handle; 666 667 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 668 smu->od_enabled = true; 669 670 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 671 case IP_VERSION(11, 0, 0): 672 case IP_VERSION(11, 0, 5): 673 case IP_VERSION(11, 0, 9): 674 navi10_set_ppt_funcs(smu); 675 break; 676 case IP_VERSION(11, 0, 7): 677 case IP_VERSION(11, 0, 11): 678 case IP_VERSION(11, 0, 12): 679 case IP_VERSION(11, 0, 13): 680 sienna_cichlid_set_ppt_funcs(smu); 681 break; 682 case IP_VERSION(12, 0, 0): 683 case IP_VERSION(12, 0, 1): 684 renoir_set_ppt_funcs(smu); 685 break; 686 case IP_VERSION(11, 5, 0): 687 vangogh_set_ppt_funcs(smu); 688 break; 689 case IP_VERSION(13, 0, 1): 690 case IP_VERSION(13, 0, 3): 691 case IP_VERSION(13, 0, 8): 692 yellow_carp_set_ppt_funcs(smu); 693 break; 694 case IP_VERSION(13, 0, 4): 695 case IP_VERSION(13, 0, 11): 696 smu_v13_0_4_set_ppt_funcs(smu); 697 break; 698 case IP_VERSION(13, 0, 5): 699 smu_v13_0_5_set_ppt_funcs(smu); 700 break; 701 case IP_VERSION(11, 0, 8): 702 cyan_skillfish_set_ppt_funcs(smu); 703 break; 704 case IP_VERSION(11, 0, 2): 705 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 706 arcturus_set_ppt_funcs(smu); 707 /* OD is not supported on Arcturus */ 708 smu->od_enabled = false; 709 break; 710 case IP_VERSION(13, 0, 2): 711 aldebaran_set_ppt_funcs(smu); 712 /* Enable pp_od_clk_voltage node */ 713 smu->od_enabled = true; 714 break; 715 case IP_VERSION(13, 0, 0): 716 case IP_VERSION(13, 0, 10): 717 smu_v13_0_0_set_ppt_funcs(smu); 718 break; 719 case IP_VERSION(13, 0, 6): 720 smu_v13_0_6_set_ppt_funcs(smu); 721 /* Enable pp_od_clk_voltage node */ 722 smu->od_enabled = true; 723 break; 724 case IP_VERSION(13, 0, 7): 725 smu_v13_0_7_set_ppt_funcs(smu); 726 break; 727 case IP_VERSION(14, 0, 0): 728 case IP_VERSION(14, 0, 1): 729 smu_v14_0_0_set_ppt_funcs(smu); 730 break; 731 case IP_VERSION(14, 0, 2): 732 case IP_VERSION(14, 0, 3): 733 smu_v14_0_2_set_ppt_funcs(smu); 734 break; 735 default: 736 return -EINVAL; 737 } 738 739 return 0; 740 } 741 742 static int smu_early_init(void *handle) 743 { 744 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 745 struct smu_context *smu; 746 int r; 747 748 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 749 if (!smu) 750 return -ENOMEM; 751 752 smu->adev = adev; 753 smu->pm_enabled = !!amdgpu_dpm; 754 smu->is_apu = false; 755 smu->smu_baco.state = SMU_BACO_STATE_NONE; 756 smu->smu_baco.platform_support = false; 757 smu->smu_baco.maco_support = false; 758 smu->user_dpm_profile.fan_mode = -1; 759 760 mutex_init(&smu->message_lock); 761 762 adev->powerplay.pp_handle = smu; 763 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 764 765 r = smu_set_funcs(adev); 766 if (r) 767 return r; 768 return smu_init_microcode(smu); 769 } 770 771 static int smu_set_default_dpm_table(struct smu_context *smu) 772 { 773 struct amdgpu_device *adev = smu->adev; 774 struct smu_power_context *smu_power = &smu->smu_power; 775 struct smu_power_gate *power_gate = &smu_power->power_gate; 776 int vcn_gate, jpeg_gate; 777 int ret = 0; 778 779 if (!smu->ppt_funcs->set_default_dpm_table) 780 return 0; 781 782 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 783 vcn_gate = atomic_read(&power_gate->vcn_gated); 784 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 785 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 786 787 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 788 ret = smu_dpm_set_vcn_enable(smu, true); 789 if (ret) 790 return ret; 791 } 792 793 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 794 ret = smu_dpm_set_jpeg_enable(smu, true); 795 if (ret) 796 goto err_out; 797 } 798 799 ret = smu->ppt_funcs->set_default_dpm_table(smu); 800 if (ret) 801 dev_err(smu->adev->dev, 802 "Failed to setup default dpm clock tables!\n"); 803 804 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 805 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 806 err_out: 807 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 808 smu_dpm_set_vcn_enable(smu, !vcn_gate); 809 810 return ret; 811 } 812 813 static int smu_apply_default_config_table_settings(struct smu_context *smu) 814 { 815 struct amdgpu_device *adev = smu->adev; 816 int ret = 0; 817 818 ret = smu_get_default_config_table_settings(smu, 819 &adev->pm.config_table); 820 if (ret) 821 return ret; 822 823 return smu_set_config_table(smu, &adev->pm.config_table); 824 } 825 826 static int smu_late_init(void *handle) 827 { 828 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 829 struct smu_context *smu = adev->powerplay.pp_handle; 830 int ret = 0; 831 832 smu_set_fine_grain_gfx_freq_parameters(smu); 833 834 if (!smu->pm_enabled) 835 return 0; 836 837 ret = smu_post_init(smu); 838 if (ret) { 839 dev_err(adev->dev, "Failed to post smu init!\n"); 840 return ret; 841 } 842 843 /* 844 * Explicitly notify PMFW the power mode the system in. Since 845 * the PMFW may boot the ASIC with a different mode. 846 * For those supporting ACDC switch via gpio, PMFW will 847 * handle the switch automatically. Driver involvement 848 * is unnecessary. 849 */ 850 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 851 smu_set_ac_dc(smu); 852 853 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 854 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 855 return 0; 856 857 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 858 ret = smu_set_default_od_settings(smu); 859 if (ret) { 860 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 861 return ret; 862 } 863 } 864 865 ret = smu_populate_umd_state_clk(smu); 866 if (ret) { 867 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 868 return ret; 869 } 870 871 ret = smu_get_asic_power_limits(smu, 872 &smu->current_power_limit, 873 &smu->default_power_limit, 874 &smu->max_power_limit, 875 &smu->min_power_limit); 876 if (ret) { 877 dev_err(adev->dev, "Failed to get asic power limits!\n"); 878 return ret; 879 } 880 881 if (!amdgpu_sriov_vf(adev)) 882 smu_get_unique_id(smu); 883 884 smu_get_fan_parameters(smu); 885 886 smu_handle_task(smu, 887 smu->smu_dpm.dpm_level, 888 AMD_PP_TASK_COMPLETE_INIT); 889 890 ret = smu_apply_default_config_table_settings(smu); 891 if (ret && (ret != -EOPNOTSUPP)) { 892 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 893 return ret; 894 } 895 896 smu_restore_dpm_user_profile(smu); 897 898 return 0; 899 } 900 901 static int smu_init_fb_allocations(struct smu_context *smu) 902 { 903 struct amdgpu_device *adev = smu->adev; 904 struct smu_table_context *smu_table = &smu->smu_table; 905 struct smu_table *tables = smu_table->tables; 906 struct smu_table *driver_table = &(smu_table->driver_table); 907 uint32_t max_table_size = 0; 908 int ret, i; 909 910 /* VRAM allocation for tool table */ 911 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 912 ret = amdgpu_bo_create_kernel(adev, 913 tables[SMU_TABLE_PMSTATUSLOG].size, 914 tables[SMU_TABLE_PMSTATUSLOG].align, 915 tables[SMU_TABLE_PMSTATUSLOG].domain, 916 &tables[SMU_TABLE_PMSTATUSLOG].bo, 917 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 918 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 919 if (ret) { 920 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 921 return ret; 922 } 923 } 924 925 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 926 /* VRAM allocation for driver table */ 927 for (i = 0; i < SMU_TABLE_COUNT; i++) { 928 if (tables[i].size == 0) 929 continue; 930 931 /* If one of the tables has VRAM domain restriction, keep it in 932 * VRAM 933 */ 934 if ((tables[i].domain & 935 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 936 AMDGPU_GEM_DOMAIN_VRAM) 937 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 938 939 if (i == SMU_TABLE_PMSTATUSLOG) 940 continue; 941 942 if (max_table_size < tables[i].size) 943 max_table_size = tables[i].size; 944 } 945 946 driver_table->size = max_table_size; 947 driver_table->align = PAGE_SIZE; 948 949 ret = amdgpu_bo_create_kernel(adev, 950 driver_table->size, 951 driver_table->align, 952 driver_table->domain, 953 &driver_table->bo, 954 &driver_table->mc_address, 955 &driver_table->cpu_addr); 956 if (ret) { 957 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 958 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 959 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 960 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 961 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 962 } 963 964 return ret; 965 } 966 967 static int smu_fini_fb_allocations(struct smu_context *smu) 968 { 969 struct smu_table_context *smu_table = &smu->smu_table; 970 struct smu_table *tables = smu_table->tables; 971 struct smu_table *driver_table = &(smu_table->driver_table); 972 973 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 974 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 975 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 976 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 977 978 amdgpu_bo_free_kernel(&driver_table->bo, 979 &driver_table->mc_address, 980 &driver_table->cpu_addr); 981 982 return 0; 983 } 984 985 /** 986 * smu_alloc_memory_pool - allocate memory pool in the system memory 987 * 988 * @smu: amdgpu_device pointer 989 * 990 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 991 * and DramLogSetDramAddr can notify it changed. 992 * 993 * Returns 0 on success, error on failure. 994 */ 995 static int smu_alloc_memory_pool(struct smu_context *smu) 996 { 997 struct amdgpu_device *adev = smu->adev; 998 struct smu_table_context *smu_table = &smu->smu_table; 999 struct smu_table *memory_pool = &smu_table->memory_pool; 1000 uint64_t pool_size = smu->pool_size; 1001 int ret = 0; 1002 1003 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1004 return ret; 1005 1006 memory_pool->size = pool_size; 1007 memory_pool->align = PAGE_SIZE; 1008 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 1009 1010 switch (pool_size) { 1011 case SMU_MEMORY_POOL_SIZE_256_MB: 1012 case SMU_MEMORY_POOL_SIZE_512_MB: 1013 case SMU_MEMORY_POOL_SIZE_1_GB: 1014 case SMU_MEMORY_POOL_SIZE_2_GB: 1015 ret = amdgpu_bo_create_kernel(adev, 1016 memory_pool->size, 1017 memory_pool->align, 1018 memory_pool->domain, 1019 &memory_pool->bo, 1020 &memory_pool->mc_address, 1021 &memory_pool->cpu_addr); 1022 if (ret) 1023 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1024 break; 1025 default: 1026 break; 1027 } 1028 1029 return ret; 1030 } 1031 1032 static int smu_free_memory_pool(struct smu_context *smu) 1033 { 1034 struct smu_table_context *smu_table = &smu->smu_table; 1035 struct smu_table *memory_pool = &smu_table->memory_pool; 1036 1037 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1038 return 0; 1039 1040 amdgpu_bo_free_kernel(&memory_pool->bo, 1041 &memory_pool->mc_address, 1042 &memory_pool->cpu_addr); 1043 1044 memset(memory_pool, 0, sizeof(struct smu_table)); 1045 1046 return 0; 1047 } 1048 1049 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1050 { 1051 struct smu_table_context *smu_table = &smu->smu_table; 1052 struct smu_table *dummy_read_1_table = 1053 &smu_table->dummy_read_1_table; 1054 struct amdgpu_device *adev = smu->adev; 1055 int ret = 0; 1056 1057 if (!dummy_read_1_table->size) 1058 return 0; 1059 1060 ret = amdgpu_bo_create_kernel(adev, 1061 dummy_read_1_table->size, 1062 dummy_read_1_table->align, 1063 dummy_read_1_table->domain, 1064 &dummy_read_1_table->bo, 1065 &dummy_read_1_table->mc_address, 1066 &dummy_read_1_table->cpu_addr); 1067 if (ret) 1068 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1069 1070 return ret; 1071 } 1072 1073 static void smu_free_dummy_read_table(struct smu_context *smu) 1074 { 1075 struct smu_table_context *smu_table = &smu->smu_table; 1076 struct smu_table *dummy_read_1_table = 1077 &smu_table->dummy_read_1_table; 1078 1079 1080 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1081 &dummy_read_1_table->mc_address, 1082 &dummy_read_1_table->cpu_addr); 1083 1084 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1085 } 1086 1087 static int smu_smc_table_sw_init(struct smu_context *smu) 1088 { 1089 int ret; 1090 1091 /** 1092 * Create smu_table structure, and init smc tables such as 1093 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1094 */ 1095 ret = smu_init_smc_tables(smu); 1096 if (ret) { 1097 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1098 return ret; 1099 } 1100 1101 /** 1102 * Create smu_power_context structure, and allocate smu_dpm_context and 1103 * context size to fill the smu_power_context data. 1104 */ 1105 ret = smu_init_power(smu); 1106 if (ret) { 1107 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1108 return ret; 1109 } 1110 1111 /* 1112 * allocate vram bos to store smc table contents. 1113 */ 1114 ret = smu_init_fb_allocations(smu); 1115 if (ret) 1116 return ret; 1117 1118 ret = smu_alloc_memory_pool(smu); 1119 if (ret) 1120 return ret; 1121 1122 ret = smu_alloc_dummy_read_table(smu); 1123 if (ret) 1124 return ret; 1125 1126 ret = smu_i2c_init(smu); 1127 if (ret) 1128 return ret; 1129 1130 return 0; 1131 } 1132 1133 static int smu_smc_table_sw_fini(struct smu_context *smu) 1134 { 1135 int ret; 1136 1137 smu_i2c_fini(smu); 1138 1139 smu_free_dummy_read_table(smu); 1140 1141 ret = smu_free_memory_pool(smu); 1142 if (ret) 1143 return ret; 1144 1145 ret = smu_fini_fb_allocations(smu); 1146 if (ret) 1147 return ret; 1148 1149 ret = smu_fini_power(smu); 1150 if (ret) { 1151 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1152 return ret; 1153 } 1154 1155 ret = smu_fini_smc_tables(smu); 1156 if (ret) { 1157 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1158 return ret; 1159 } 1160 1161 return 0; 1162 } 1163 1164 static void smu_throttling_logging_work_fn(struct work_struct *work) 1165 { 1166 struct smu_context *smu = container_of(work, struct smu_context, 1167 throttling_logging_work); 1168 1169 smu_log_thermal_throttling(smu); 1170 } 1171 1172 static void smu_interrupt_work_fn(struct work_struct *work) 1173 { 1174 struct smu_context *smu = container_of(work, struct smu_context, 1175 interrupt_work); 1176 1177 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1178 smu->ppt_funcs->interrupt_work(smu); 1179 } 1180 1181 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1182 { 1183 struct smu_context *smu = 1184 container_of(work, struct smu_context, swctf_delayed_work.work); 1185 struct smu_temperature_range *range = 1186 &smu->thermal_range; 1187 struct amdgpu_device *adev = smu->adev; 1188 uint32_t hotspot_tmp, size; 1189 1190 /* 1191 * If the hotspot temperature is confirmed as below SW CTF setting point 1192 * after the delay enforced, nothing will be done. 1193 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1194 */ 1195 if (range->software_shutdown_temp && 1196 smu->ppt_funcs->read_sensor && 1197 !smu->ppt_funcs->read_sensor(smu, 1198 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1199 &hotspot_tmp, 1200 &size) && 1201 hotspot_tmp / 1000 < range->software_shutdown_temp) 1202 return; 1203 1204 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1205 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1206 orderly_poweroff(true); 1207 } 1208 1209 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1210 { 1211 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1212 smu->plpd_mode = XGMI_PLPD_DEFAULT; 1213 return; 1214 } 1215 1216 /* PMFW put PLPD into default policy after enabling the feature */ 1217 if (smu_feature_is_enabled(smu, 1218 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) 1219 smu->plpd_mode = XGMI_PLPD_DEFAULT; 1220 else 1221 smu->plpd_mode = XGMI_PLPD_NONE; 1222 } 1223 1224 static int smu_sw_init(void *handle) 1225 { 1226 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1227 struct smu_context *smu = adev->powerplay.pp_handle; 1228 int ret; 1229 1230 smu->pool_size = adev->pm.smu_prv_buffer_size; 1231 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1232 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1233 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1234 1235 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1236 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1237 atomic64_set(&smu->throttle_int_counter, 0); 1238 smu->watermarks_bitmap = 0; 1239 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1240 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1241 1242 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1243 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1244 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1245 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1246 1247 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1248 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1249 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1250 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1251 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1252 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1253 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1254 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1255 1256 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1257 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1258 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1259 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1260 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1261 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1262 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1263 smu->display_config = &adev->pm.pm_display_cfg; 1264 1265 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1266 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1267 1268 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1269 smu_swctf_delayed_work_handler); 1270 1271 ret = smu_smc_table_sw_init(smu); 1272 if (ret) { 1273 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1274 return ret; 1275 } 1276 1277 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1278 ret = smu_get_vbios_bootup_values(smu); 1279 if (ret) { 1280 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1281 return ret; 1282 } 1283 1284 ret = smu_init_pptable_microcode(smu); 1285 if (ret) { 1286 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1287 return ret; 1288 } 1289 1290 ret = smu_register_irq_handler(smu); 1291 if (ret) { 1292 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1293 return ret; 1294 } 1295 1296 /* If there is no way to query fan control mode, fan control is not supported */ 1297 if (!smu->ppt_funcs->get_fan_control_mode) 1298 smu->adev->pm.no_fan = true; 1299 1300 return 0; 1301 } 1302 1303 static int smu_sw_fini(void *handle) 1304 { 1305 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1306 struct smu_context *smu = adev->powerplay.pp_handle; 1307 int ret; 1308 1309 ret = smu_smc_table_sw_fini(smu); 1310 if (ret) { 1311 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1312 return ret; 1313 } 1314 1315 smu_fini_microcode(smu); 1316 1317 return 0; 1318 } 1319 1320 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1321 { 1322 struct amdgpu_device *adev = smu->adev; 1323 struct smu_temperature_range *range = 1324 &smu->thermal_range; 1325 int ret = 0; 1326 1327 if (!smu->ppt_funcs->get_thermal_temperature_range) 1328 return 0; 1329 1330 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1331 if (ret) 1332 return ret; 1333 1334 adev->pm.dpm.thermal.min_temp = range->min; 1335 adev->pm.dpm.thermal.max_temp = range->max; 1336 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1337 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1338 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1339 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1340 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1341 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1342 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1343 1344 return ret; 1345 } 1346 1347 /** 1348 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1349 * 1350 * @smu: smu_context pointer 1351 * 1352 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1353 * Returns 0 on success, error on failure. 1354 */ 1355 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1356 { 1357 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1358 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1359 struct amdgpu_device *adev = smu->adev; 1360 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1361 uint64_t start, end; 1362 int ret, i, j; 1363 1364 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1365 if (ret) { 1366 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1367 return ret; 1368 } 1369 1370 /* 1371 * The exclusion ranges array we got might be filled with holes and duplicate 1372 * entries. For example: 1373 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1374 * We need to do some sortups to eliminate those holes and duplicate entries. 1375 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1376 */ 1377 for (i = 0; i < num_of_wbrf_ranges; i++) { 1378 start = wifi_bands[i].start; 1379 end = wifi_bands[i].end; 1380 1381 /* get the last valid entry to fill the intermediate hole */ 1382 if (!start && !end) { 1383 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1384 if (wifi_bands[j].start && wifi_bands[j].end) 1385 break; 1386 1387 /* no valid entry left */ 1388 if (j <= i) 1389 break; 1390 1391 start = wifi_bands[i].start = wifi_bands[j].start; 1392 end = wifi_bands[i].end = wifi_bands[j].end; 1393 wifi_bands[j].start = 0; 1394 wifi_bands[j].end = 0; 1395 num_of_wbrf_ranges = j; 1396 } 1397 1398 /* eliminate duplicate entries */ 1399 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1400 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1401 wifi_bands[j].start = 0; 1402 wifi_bands[j].end = 0; 1403 } 1404 } 1405 } 1406 1407 /* Send the sorted wifi_bands to PMFW */ 1408 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1409 /* Try to set the wifi_bands again */ 1410 if (unlikely(ret == -EBUSY)) { 1411 mdelay(5); 1412 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1413 } 1414 1415 return ret; 1416 } 1417 1418 /** 1419 * smu_wbrf_event_handler - handle notify events 1420 * 1421 * @nb: notifier block 1422 * @action: event type 1423 * @_arg: event data 1424 * 1425 * Calls relevant amdgpu function in response to wbrf event 1426 * notification from kernel. 1427 */ 1428 static int smu_wbrf_event_handler(struct notifier_block *nb, 1429 unsigned long action, void *_arg) 1430 { 1431 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1432 1433 switch (action) { 1434 case WBRF_CHANGED: 1435 schedule_delayed_work(&smu->wbrf_delayed_work, 1436 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1437 break; 1438 default: 1439 return NOTIFY_DONE; 1440 } 1441 1442 return NOTIFY_OK; 1443 } 1444 1445 /** 1446 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1447 * 1448 * @work: struct work_struct pointer 1449 * 1450 * Flood is over and driver will consume the latest exclusion ranges. 1451 */ 1452 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1453 { 1454 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1455 1456 smu_wbrf_handle_exclusion_ranges(smu); 1457 } 1458 1459 /** 1460 * smu_wbrf_support_check - check wbrf support 1461 * 1462 * @smu: smu_context pointer 1463 * 1464 * Verifies the ACPI interface whether wbrf is supported. 1465 */ 1466 static void smu_wbrf_support_check(struct smu_context *smu) 1467 { 1468 struct amdgpu_device *adev = smu->adev; 1469 1470 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1471 acpi_amd_wbrf_supported_consumer(adev->dev); 1472 1473 if (smu->wbrf_supported) 1474 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1475 } 1476 1477 /** 1478 * smu_wbrf_init - init driver wbrf support 1479 * 1480 * @smu: smu_context pointer 1481 * 1482 * Verifies the AMD ACPI interfaces and registers with the wbrf 1483 * notifier chain if wbrf feature is supported. 1484 * Returns 0 on success, error on failure. 1485 */ 1486 static int smu_wbrf_init(struct smu_context *smu) 1487 { 1488 int ret; 1489 1490 if (!smu->wbrf_supported) 1491 return 0; 1492 1493 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1494 1495 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1496 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1497 if (ret) 1498 return ret; 1499 1500 /* 1501 * Some wifiband exclusion ranges may be already there 1502 * before our driver loaded. To make sure our driver 1503 * is awared of those exclusion ranges. 1504 */ 1505 schedule_delayed_work(&smu->wbrf_delayed_work, 1506 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1507 1508 return 0; 1509 } 1510 1511 /** 1512 * smu_wbrf_fini - tear down driver wbrf support 1513 * 1514 * @smu: smu_context pointer 1515 * 1516 * Unregisters with the wbrf notifier chain. 1517 */ 1518 static void smu_wbrf_fini(struct smu_context *smu) 1519 { 1520 if (!smu->wbrf_supported) 1521 return; 1522 1523 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1524 1525 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1526 } 1527 1528 static int smu_smc_hw_setup(struct smu_context *smu) 1529 { 1530 struct smu_feature *feature = &smu->smu_feature; 1531 struct amdgpu_device *adev = smu->adev; 1532 uint8_t pcie_gen = 0, pcie_width = 0; 1533 uint64_t features_supported; 1534 int ret = 0; 1535 1536 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1537 case IP_VERSION(11, 0, 7): 1538 case IP_VERSION(11, 0, 11): 1539 case IP_VERSION(11, 5, 0): 1540 case IP_VERSION(11, 0, 12): 1541 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1542 dev_info(adev->dev, "dpm has been enabled\n"); 1543 ret = smu_system_features_control(smu, true); 1544 if (ret) 1545 dev_err(adev->dev, "Failed system features control!\n"); 1546 return ret; 1547 } 1548 break; 1549 default: 1550 break; 1551 } 1552 1553 ret = smu_init_display_count(smu, 0); 1554 if (ret) { 1555 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1556 return ret; 1557 } 1558 1559 ret = smu_set_driver_table_location(smu); 1560 if (ret) { 1561 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1562 return ret; 1563 } 1564 1565 /* 1566 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1567 */ 1568 ret = smu_set_tool_table_location(smu); 1569 if (ret) { 1570 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1571 return ret; 1572 } 1573 1574 /* 1575 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1576 * pool location. 1577 */ 1578 ret = smu_notify_memory_pool_location(smu); 1579 if (ret) { 1580 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1581 return ret; 1582 } 1583 1584 /* 1585 * It is assumed the pptable used before runpm is same as 1586 * the one used afterwards. Thus, we can reuse the stored 1587 * copy and do not need to resetup the pptable again. 1588 */ 1589 if (!adev->in_runpm) { 1590 ret = smu_setup_pptable(smu); 1591 if (ret) { 1592 dev_err(adev->dev, "Failed to setup pptable!\n"); 1593 return ret; 1594 } 1595 } 1596 1597 /* smu_dump_pptable(smu); */ 1598 1599 /* 1600 * With SCPM enabled, PSP is responsible for the PPTable transferring 1601 * (to SMU). Driver involvement is not needed and permitted. 1602 */ 1603 if (!adev->scpm_enabled) { 1604 /* 1605 * Copy pptable bo in the vram to smc with SMU MSGs such as 1606 * SetDriverDramAddr and TransferTableDram2Smu. 1607 */ 1608 ret = smu_write_pptable(smu); 1609 if (ret) { 1610 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1611 return ret; 1612 } 1613 } 1614 1615 /* issue Run*Btc msg */ 1616 ret = smu_run_btc(smu); 1617 if (ret) 1618 return ret; 1619 1620 /* Enable UclkShadow on wbrf supported */ 1621 if (smu->wbrf_supported) { 1622 ret = smu_enable_uclk_shadow(smu, true); 1623 if (ret) { 1624 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1625 return ret; 1626 } 1627 } 1628 1629 /* 1630 * With SCPM enabled, these actions(and relevant messages) are 1631 * not needed and permitted. 1632 */ 1633 if (!adev->scpm_enabled) { 1634 ret = smu_feature_set_allowed_mask(smu); 1635 if (ret) { 1636 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1637 return ret; 1638 } 1639 } 1640 1641 ret = smu_system_features_control(smu, true); 1642 if (ret) { 1643 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1644 return ret; 1645 } 1646 1647 smu_init_xgmi_plpd_mode(smu); 1648 1649 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1650 if (ret) { 1651 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1652 return ret; 1653 } 1654 bitmap_copy(feature->supported, 1655 (unsigned long *)&features_supported, 1656 feature->feature_num); 1657 1658 if (!smu_is_dpm_running(smu)) 1659 dev_info(adev->dev, "dpm has been disabled\n"); 1660 1661 /* 1662 * Set initialized values (get from vbios) to dpm tables context such as 1663 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1664 * type of clks. 1665 */ 1666 ret = smu_set_default_dpm_table(smu); 1667 if (ret) { 1668 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1669 return ret; 1670 } 1671 1672 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1673 pcie_gen = 3; 1674 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1675 pcie_gen = 2; 1676 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1677 pcie_gen = 1; 1678 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1679 pcie_gen = 0; 1680 1681 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1682 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1683 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1684 */ 1685 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1686 pcie_width = 6; 1687 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1688 pcie_width = 5; 1689 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1690 pcie_width = 4; 1691 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1692 pcie_width = 3; 1693 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1694 pcie_width = 2; 1695 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1696 pcie_width = 1; 1697 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1698 if (ret) { 1699 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1700 return ret; 1701 } 1702 1703 ret = smu_get_thermal_temperature_range(smu); 1704 if (ret) { 1705 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1706 return ret; 1707 } 1708 1709 ret = smu_enable_thermal_alert(smu); 1710 if (ret) { 1711 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1712 return ret; 1713 } 1714 1715 ret = smu_notify_display_change(smu); 1716 if (ret) { 1717 dev_err(adev->dev, "Failed to notify display change!\n"); 1718 return ret; 1719 } 1720 1721 /* 1722 * Set min deep sleep dce fclk with bootup value from vbios via 1723 * SetMinDeepSleepDcefclk MSG. 1724 */ 1725 ret = smu_set_min_dcef_deep_sleep(smu, 1726 smu->smu_table.boot_values.dcefclk / 100); 1727 if (ret) { 1728 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1729 return ret; 1730 } 1731 1732 /* Init wbrf support. Properly setup the notifier */ 1733 ret = smu_wbrf_init(smu); 1734 if (ret) 1735 dev_err(adev->dev, "Error during wbrf init call\n"); 1736 1737 return ret; 1738 } 1739 1740 static int smu_start_smc_engine(struct smu_context *smu) 1741 { 1742 struct amdgpu_device *adev = smu->adev; 1743 int ret = 0; 1744 1745 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1746 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1747 if (smu->ppt_funcs->load_microcode) { 1748 ret = smu->ppt_funcs->load_microcode(smu); 1749 if (ret) 1750 return ret; 1751 } 1752 } 1753 } 1754 1755 if (smu->ppt_funcs->check_fw_status) { 1756 ret = smu->ppt_funcs->check_fw_status(smu); 1757 if (ret) { 1758 dev_err(adev->dev, "SMC is not ready\n"); 1759 return ret; 1760 } 1761 } 1762 1763 /* 1764 * Send msg GetDriverIfVersion to check if the return value is equal 1765 * with DRIVER_IF_VERSION of smc header. 1766 */ 1767 ret = smu_check_fw_version(smu); 1768 if (ret) 1769 return ret; 1770 1771 return ret; 1772 } 1773 1774 static int smu_hw_init(void *handle) 1775 { 1776 int ret; 1777 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1778 struct smu_context *smu = adev->powerplay.pp_handle; 1779 1780 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1781 smu->pm_enabled = false; 1782 return 0; 1783 } 1784 1785 ret = smu_start_smc_engine(smu); 1786 if (ret) { 1787 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1788 return ret; 1789 } 1790 1791 /* 1792 * Check whether wbrf is supported. This needs to be done 1793 * before SMU setup starts since part of SMU configuration 1794 * relies on this. 1795 */ 1796 smu_wbrf_support_check(smu); 1797 1798 if (smu->is_apu) { 1799 ret = smu_set_gfx_imu_enable(smu); 1800 if (ret) 1801 return ret; 1802 smu_dpm_set_vcn_enable(smu, true); 1803 smu_dpm_set_jpeg_enable(smu, true); 1804 smu_dpm_set_vpe_enable(smu, true); 1805 smu_dpm_set_umsch_mm_enable(smu, true); 1806 smu_set_mall_enable(smu); 1807 smu_set_gfx_cgpg(smu, true); 1808 } 1809 1810 if (!smu->pm_enabled) 1811 return 0; 1812 1813 ret = smu_get_driver_allowed_feature_mask(smu); 1814 if (ret) 1815 return ret; 1816 1817 ret = smu_smc_hw_setup(smu); 1818 if (ret) { 1819 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1820 return ret; 1821 } 1822 1823 /* 1824 * Move maximum sustainable clock retrieving here considering 1825 * 1. It is not needed on resume(from S3). 1826 * 2. DAL settings come between .hw_init and .late_init of SMU. 1827 * And DAL needs to know the maximum sustainable clocks. Thus 1828 * it cannot be put in .late_init(). 1829 */ 1830 ret = smu_init_max_sustainable_clocks(smu); 1831 if (ret) { 1832 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1833 return ret; 1834 } 1835 1836 adev->pm.dpm_enabled = true; 1837 1838 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1839 1840 return 0; 1841 } 1842 1843 static int smu_disable_dpms(struct smu_context *smu) 1844 { 1845 struct amdgpu_device *adev = smu->adev; 1846 int ret = 0; 1847 bool use_baco = !smu->is_apu && 1848 ((amdgpu_in_reset(adev) && 1849 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1850 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1851 1852 /* 1853 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1854 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1855 */ 1856 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1857 case IP_VERSION(13, 0, 0): 1858 case IP_VERSION(13, 0, 7): 1859 case IP_VERSION(13, 0, 10): 1860 return 0; 1861 default: 1862 break; 1863 } 1864 1865 /* 1866 * For custom pptable uploading, skip the DPM features 1867 * disable process on Navi1x ASICs. 1868 * - As the gfx related features are under control of 1869 * RLC on those ASICs. RLC reinitialization will be 1870 * needed to reenable them. That will cost much more 1871 * efforts. 1872 * 1873 * - SMU firmware can handle the DPM reenablement 1874 * properly. 1875 */ 1876 if (smu->uploading_custom_pp_table) { 1877 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1878 case IP_VERSION(11, 0, 0): 1879 case IP_VERSION(11, 0, 5): 1880 case IP_VERSION(11, 0, 9): 1881 case IP_VERSION(11, 0, 7): 1882 case IP_VERSION(11, 0, 11): 1883 case IP_VERSION(11, 5, 0): 1884 case IP_VERSION(11, 0, 12): 1885 case IP_VERSION(11, 0, 13): 1886 return 0; 1887 default: 1888 break; 1889 } 1890 } 1891 1892 /* 1893 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1894 * on BACO in. Driver involvement is unnecessary. 1895 */ 1896 if (use_baco) { 1897 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1898 case IP_VERSION(11, 0, 7): 1899 case IP_VERSION(11, 0, 0): 1900 case IP_VERSION(11, 0, 5): 1901 case IP_VERSION(11, 0, 9): 1902 case IP_VERSION(13, 0, 7): 1903 return 0; 1904 default: 1905 break; 1906 } 1907 } 1908 1909 /* 1910 * For SMU 13.0.4/11 and 14.0.0, PMFW will handle the features disablement properly 1911 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1912 */ 1913 if (amdgpu_in_reset(adev) || adev->in_s0ix) { 1914 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1915 case IP_VERSION(13, 0, 4): 1916 case IP_VERSION(13, 0, 11): 1917 case IP_VERSION(14, 0, 0): 1918 case IP_VERSION(14, 0, 1): 1919 return 0; 1920 default: 1921 break; 1922 } 1923 } 1924 1925 /* 1926 * For gpu reset, runpm and hibernation through BACO, 1927 * BACO feature has to be kept enabled. 1928 */ 1929 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1930 ret = smu_disable_all_features_with_exception(smu, 1931 SMU_FEATURE_BACO_BIT); 1932 if (ret) 1933 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1934 } else { 1935 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1936 if (!adev->scpm_enabled) { 1937 ret = smu_system_features_control(smu, false); 1938 if (ret) 1939 dev_err(adev->dev, "Failed to disable smu features.\n"); 1940 } 1941 } 1942 1943 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 1944 * otherwise SMU will hang while interacting with RLC if RLC is halted 1945 * this is a WA for Vangogh asic which fix the SMU hang issue. 1946 */ 1947 ret = smu_notify_rlc_state(smu, false); 1948 if (ret) { 1949 dev_err(adev->dev, "Fail to notify rlc status!\n"); 1950 return ret; 1951 } 1952 1953 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1954 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1955 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1956 adev->gfx.rlc.funcs->stop(adev); 1957 1958 return ret; 1959 } 1960 1961 static int smu_smc_hw_cleanup(struct smu_context *smu) 1962 { 1963 struct amdgpu_device *adev = smu->adev; 1964 int ret = 0; 1965 1966 smu_wbrf_fini(smu); 1967 1968 cancel_work_sync(&smu->throttling_logging_work); 1969 cancel_work_sync(&smu->interrupt_work); 1970 1971 ret = smu_disable_thermal_alert(smu); 1972 if (ret) { 1973 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1974 return ret; 1975 } 1976 1977 cancel_delayed_work_sync(&smu->swctf_delayed_work); 1978 1979 ret = smu_disable_dpms(smu); 1980 if (ret) { 1981 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1982 return ret; 1983 } 1984 1985 return 0; 1986 } 1987 1988 static int smu_reset_mp1_state(struct smu_context *smu) 1989 { 1990 struct amdgpu_device *adev = smu->adev; 1991 int ret = 0; 1992 1993 if ((!adev->in_runpm) && (!adev->in_suspend) && 1994 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 1995 IP_VERSION(13, 0, 10) && 1996 !amdgpu_device_has_display_hardware(adev)) 1997 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 1998 1999 return ret; 2000 } 2001 2002 static int smu_hw_fini(void *handle) 2003 { 2004 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2005 struct smu_context *smu = adev->powerplay.pp_handle; 2006 int ret; 2007 2008 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2009 return 0; 2010 2011 smu_dpm_set_vcn_enable(smu, false); 2012 smu_dpm_set_jpeg_enable(smu, false); 2013 smu_dpm_set_vpe_enable(smu, false); 2014 smu_dpm_set_umsch_mm_enable(smu, false); 2015 2016 adev->vcn.cur_state = AMD_PG_STATE_GATE; 2017 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2018 2019 if (!smu->pm_enabled) 2020 return 0; 2021 2022 adev->pm.dpm_enabled = false; 2023 2024 ret = smu_smc_hw_cleanup(smu); 2025 if (ret) 2026 return ret; 2027 2028 ret = smu_reset_mp1_state(smu); 2029 if (ret) 2030 return ret; 2031 2032 return 0; 2033 } 2034 2035 static void smu_late_fini(void *handle) 2036 { 2037 struct amdgpu_device *adev = handle; 2038 struct smu_context *smu = adev->powerplay.pp_handle; 2039 2040 kfree(smu); 2041 } 2042 2043 static int smu_reset(struct smu_context *smu) 2044 { 2045 struct amdgpu_device *adev = smu->adev; 2046 int ret; 2047 2048 ret = smu_hw_fini(adev); 2049 if (ret) 2050 return ret; 2051 2052 ret = smu_hw_init(adev); 2053 if (ret) 2054 return ret; 2055 2056 ret = smu_late_init(adev); 2057 if (ret) 2058 return ret; 2059 2060 return 0; 2061 } 2062 2063 static int smu_suspend(void *handle) 2064 { 2065 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2066 struct smu_context *smu = adev->powerplay.pp_handle; 2067 int ret; 2068 uint64_t count; 2069 2070 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 2071 return 0; 2072 2073 if (!smu->pm_enabled) 2074 return 0; 2075 2076 adev->pm.dpm_enabled = false; 2077 2078 ret = smu_smc_hw_cleanup(smu); 2079 if (ret) 2080 return ret; 2081 2082 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2083 2084 smu_set_gfx_cgpg(smu, false); 2085 2086 /* 2087 * pwfw resets entrycount when device is suspended, so we save the 2088 * last value to be used when we resume to keep it consistent 2089 */ 2090 ret = smu_get_entrycount_gfxoff(smu, &count); 2091 if (!ret) 2092 adev->gfx.gfx_off_entrycount = count; 2093 2094 return 0; 2095 } 2096 2097 static int smu_resume(void *handle) 2098 { 2099 int ret; 2100 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2101 struct smu_context *smu = adev->powerplay.pp_handle; 2102 2103 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 2104 return 0; 2105 2106 if (!smu->pm_enabled) 2107 return 0; 2108 2109 dev_info(adev->dev, "SMU is resuming...\n"); 2110 2111 ret = smu_start_smc_engine(smu); 2112 if (ret) { 2113 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2114 return ret; 2115 } 2116 2117 ret = smu_smc_hw_setup(smu); 2118 if (ret) { 2119 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2120 return ret; 2121 } 2122 2123 ret = smu_set_gfx_imu_enable(smu); 2124 if (ret) 2125 return ret; 2126 2127 smu_set_gfx_cgpg(smu, true); 2128 2129 smu->disable_uclk_switch = 0; 2130 2131 adev->pm.dpm_enabled = true; 2132 2133 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2134 2135 return 0; 2136 } 2137 2138 static int smu_display_configuration_change(void *handle, 2139 const struct amd_pp_display_configuration *display_config) 2140 { 2141 struct smu_context *smu = handle; 2142 2143 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2144 return -EOPNOTSUPP; 2145 2146 if (!display_config) 2147 return -EINVAL; 2148 2149 smu_set_min_dcef_deep_sleep(smu, 2150 display_config->min_dcef_deep_sleep_set_clk / 100); 2151 2152 return 0; 2153 } 2154 2155 static int smu_set_clockgating_state(void *handle, 2156 enum amd_clockgating_state state) 2157 { 2158 return 0; 2159 } 2160 2161 static int smu_set_powergating_state(void *handle, 2162 enum amd_powergating_state state) 2163 { 2164 return 0; 2165 } 2166 2167 static int smu_enable_umd_pstate(void *handle, 2168 enum amd_dpm_forced_level *level) 2169 { 2170 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2171 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2172 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2173 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2174 2175 struct smu_context *smu = (struct smu_context*)(handle); 2176 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2177 2178 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2179 return -EINVAL; 2180 2181 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2182 /* enter umd pstate, save current level, disable gfx cg*/ 2183 if (*level & profile_mode_mask) { 2184 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2185 smu_gpo_control(smu, false); 2186 smu_gfx_ulv_control(smu, false); 2187 smu_deep_sleep_control(smu, false); 2188 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2189 } 2190 } else { 2191 /* exit umd pstate, restore level, enable gfx cg*/ 2192 if (!(*level & profile_mode_mask)) { 2193 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2194 *level = smu_dpm_ctx->saved_dpm_level; 2195 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2196 smu_deep_sleep_control(smu, true); 2197 smu_gfx_ulv_control(smu, true); 2198 smu_gpo_control(smu, true); 2199 } 2200 } 2201 2202 return 0; 2203 } 2204 2205 static int smu_bump_power_profile_mode(struct smu_context *smu, 2206 long *param, 2207 uint32_t param_size) 2208 { 2209 int ret = 0; 2210 2211 if (smu->ppt_funcs->set_power_profile_mode) 2212 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2213 2214 return ret; 2215 } 2216 2217 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2218 enum amd_dpm_forced_level level, 2219 bool skip_display_settings) 2220 { 2221 int ret = 0; 2222 int index = 0; 2223 long workload; 2224 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2225 2226 if (!skip_display_settings) { 2227 ret = smu_display_config_changed(smu); 2228 if (ret) { 2229 dev_err(smu->adev->dev, "Failed to change display config!"); 2230 return ret; 2231 } 2232 } 2233 2234 ret = smu_apply_clocks_adjust_rules(smu); 2235 if (ret) { 2236 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2237 return ret; 2238 } 2239 2240 if (!skip_display_settings) { 2241 ret = smu_notify_smc_display_config(smu); 2242 if (ret) { 2243 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2244 return ret; 2245 } 2246 } 2247 2248 if (smu_dpm_ctx->dpm_level != level) { 2249 ret = smu_asic_set_performance_level(smu, level); 2250 if (ret) { 2251 dev_err(smu->adev->dev, "Failed to set performance level!"); 2252 return ret; 2253 } 2254 2255 /* update the saved copy */ 2256 smu_dpm_ctx->dpm_level = level; 2257 } 2258 2259 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2260 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2261 index = fls(smu->workload_mask); 2262 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2263 workload = smu->workload_setting[index]; 2264 2265 if (smu->power_profile_mode != workload) 2266 smu_bump_power_profile_mode(smu, &workload, 0); 2267 } 2268 2269 return ret; 2270 } 2271 2272 static int smu_handle_task(struct smu_context *smu, 2273 enum amd_dpm_forced_level level, 2274 enum amd_pp_task task_id) 2275 { 2276 int ret = 0; 2277 2278 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2279 return -EOPNOTSUPP; 2280 2281 switch (task_id) { 2282 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2283 ret = smu_pre_display_config_changed(smu); 2284 if (ret) 2285 return ret; 2286 ret = smu_adjust_power_state_dynamic(smu, level, false); 2287 break; 2288 case AMD_PP_TASK_COMPLETE_INIT: 2289 case AMD_PP_TASK_READJUST_POWER_STATE: 2290 ret = smu_adjust_power_state_dynamic(smu, level, true); 2291 break; 2292 default: 2293 break; 2294 } 2295 2296 return ret; 2297 } 2298 2299 static int smu_handle_dpm_task(void *handle, 2300 enum amd_pp_task task_id, 2301 enum amd_pm_state_type *user_state) 2302 { 2303 struct smu_context *smu = handle; 2304 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2305 2306 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2307 2308 } 2309 2310 static int smu_switch_power_profile(void *handle, 2311 enum PP_SMC_POWER_PROFILE type, 2312 bool en) 2313 { 2314 struct smu_context *smu = handle; 2315 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2316 long workload; 2317 uint32_t index; 2318 2319 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2320 return -EOPNOTSUPP; 2321 2322 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2323 return -EINVAL; 2324 2325 if (!en) { 2326 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 2327 index = fls(smu->workload_mask); 2328 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2329 workload = smu->workload_setting[index]; 2330 } else { 2331 smu->workload_mask |= (1 << smu->workload_prority[type]); 2332 index = fls(smu->workload_mask); 2333 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2334 workload = smu->workload_setting[index]; 2335 } 2336 2337 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2338 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2339 smu_bump_power_profile_mode(smu, &workload, 0); 2340 2341 return 0; 2342 } 2343 2344 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2345 { 2346 struct smu_context *smu = handle; 2347 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2348 2349 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2350 return -EOPNOTSUPP; 2351 2352 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2353 return -EINVAL; 2354 2355 return smu_dpm_ctx->dpm_level; 2356 } 2357 2358 static int smu_force_performance_level(void *handle, 2359 enum amd_dpm_forced_level level) 2360 { 2361 struct smu_context *smu = handle; 2362 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2363 int ret = 0; 2364 2365 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2366 return -EOPNOTSUPP; 2367 2368 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2369 return -EINVAL; 2370 2371 ret = smu_enable_umd_pstate(smu, &level); 2372 if (ret) 2373 return ret; 2374 2375 ret = smu_handle_task(smu, level, 2376 AMD_PP_TASK_READJUST_POWER_STATE); 2377 2378 /* reset user dpm clock state */ 2379 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2380 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2381 smu->user_dpm_profile.clk_dependency = 0; 2382 } 2383 2384 return ret; 2385 } 2386 2387 static int smu_set_display_count(void *handle, uint32_t count) 2388 { 2389 struct smu_context *smu = handle; 2390 2391 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2392 return -EOPNOTSUPP; 2393 2394 return smu_init_display_count(smu, count); 2395 } 2396 2397 static int smu_force_smuclk_levels(struct smu_context *smu, 2398 enum smu_clk_type clk_type, 2399 uint32_t mask) 2400 { 2401 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2402 int ret = 0; 2403 2404 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2405 return -EOPNOTSUPP; 2406 2407 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2408 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2409 return -EINVAL; 2410 } 2411 2412 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2413 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2414 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2415 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2416 smu_set_user_clk_dependencies(smu, clk_type); 2417 } 2418 } 2419 2420 return ret; 2421 } 2422 2423 static int smu_force_ppclk_levels(void *handle, 2424 enum pp_clock_type type, 2425 uint32_t mask) 2426 { 2427 struct smu_context *smu = handle; 2428 enum smu_clk_type clk_type; 2429 2430 switch (type) { 2431 case PP_SCLK: 2432 clk_type = SMU_SCLK; break; 2433 case PP_MCLK: 2434 clk_type = SMU_MCLK; break; 2435 case PP_PCIE: 2436 clk_type = SMU_PCIE; break; 2437 case PP_SOCCLK: 2438 clk_type = SMU_SOCCLK; break; 2439 case PP_FCLK: 2440 clk_type = SMU_FCLK; break; 2441 case PP_DCEFCLK: 2442 clk_type = SMU_DCEFCLK; break; 2443 case PP_VCLK: 2444 clk_type = SMU_VCLK; break; 2445 case PP_VCLK1: 2446 clk_type = SMU_VCLK1; break; 2447 case PP_DCLK: 2448 clk_type = SMU_DCLK; break; 2449 case PP_DCLK1: 2450 clk_type = SMU_DCLK1; break; 2451 case OD_SCLK: 2452 clk_type = SMU_OD_SCLK; break; 2453 case OD_MCLK: 2454 clk_type = SMU_OD_MCLK; break; 2455 case OD_VDDC_CURVE: 2456 clk_type = SMU_OD_VDDC_CURVE; break; 2457 case OD_RANGE: 2458 clk_type = SMU_OD_RANGE; break; 2459 default: 2460 return -EINVAL; 2461 } 2462 2463 return smu_force_smuclk_levels(smu, clk_type, mask); 2464 } 2465 2466 /* 2467 * On system suspending or resetting, the dpm_enabled 2468 * flag will be cleared. So that those SMU services which 2469 * are not supported will be gated. 2470 * However, the mp1 state setting should still be granted 2471 * even if the dpm_enabled cleared. 2472 */ 2473 static int smu_set_mp1_state(void *handle, 2474 enum pp_mp1_state mp1_state) 2475 { 2476 struct smu_context *smu = handle; 2477 int ret = 0; 2478 2479 if (!smu->pm_enabled) 2480 return -EOPNOTSUPP; 2481 2482 if (smu->ppt_funcs && 2483 smu->ppt_funcs->set_mp1_state) 2484 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2485 2486 return ret; 2487 } 2488 2489 static int smu_set_df_cstate(void *handle, 2490 enum pp_df_cstate state) 2491 { 2492 struct smu_context *smu = handle; 2493 int ret = 0; 2494 2495 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2496 return -EOPNOTSUPP; 2497 2498 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2499 return 0; 2500 2501 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2502 if (ret) 2503 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2504 2505 return ret; 2506 } 2507 2508 int smu_write_watermarks_table(struct smu_context *smu) 2509 { 2510 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2511 return -EOPNOTSUPP; 2512 2513 return smu_set_watermarks_table(smu, NULL); 2514 } 2515 2516 static int smu_set_watermarks_for_clock_ranges(void *handle, 2517 struct pp_smu_wm_range_sets *clock_ranges) 2518 { 2519 struct smu_context *smu = handle; 2520 2521 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2522 return -EOPNOTSUPP; 2523 2524 if (smu->disable_watermark) 2525 return 0; 2526 2527 return smu_set_watermarks_table(smu, clock_ranges); 2528 } 2529 2530 int smu_set_ac_dc(struct smu_context *smu) 2531 { 2532 int ret = 0; 2533 2534 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2535 return -EOPNOTSUPP; 2536 2537 /* controlled by firmware */ 2538 if (smu->dc_controlled_by_gpio) 2539 return 0; 2540 2541 ret = smu_set_power_source(smu, 2542 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2543 SMU_POWER_SOURCE_DC); 2544 if (ret) 2545 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2546 smu->adev->pm.ac_power ? "AC" : "DC"); 2547 2548 return ret; 2549 } 2550 2551 const struct amd_ip_funcs smu_ip_funcs = { 2552 .name = "smu", 2553 .early_init = smu_early_init, 2554 .late_init = smu_late_init, 2555 .sw_init = smu_sw_init, 2556 .sw_fini = smu_sw_fini, 2557 .hw_init = smu_hw_init, 2558 .hw_fini = smu_hw_fini, 2559 .late_fini = smu_late_fini, 2560 .suspend = smu_suspend, 2561 .resume = smu_resume, 2562 .is_idle = NULL, 2563 .check_soft_reset = NULL, 2564 .wait_for_idle = NULL, 2565 .soft_reset = NULL, 2566 .set_clockgating_state = smu_set_clockgating_state, 2567 .set_powergating_state = smu_set_powergating_state, 2568 }; 2569 2570 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2571 .type = AMD_IP_BLOCK_TYPE_SMC, 2572 .major = 11, 2573 .minor = 0, 2574 .rev = 0, 2575 .funcs = &smu_ip_funcs, 2576 }; 2577 2578 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2579 .type = AMD_IP_BLOCK_TYPE_SMC, 2580 .major = 12, 2581 .minor = 0, 2582 .rev = 0, 2583 .funcs = &smu_ip_funcs, 2584 }; 2585 2586 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2587 .type = AMD_IP_BLOCK_TYPE_SMC, 2588 .major = 13, 2589 .minor = 0, 2590 .rev = 0, 2591 .funcs = &smu_ip_funcs, 2592 }; 2593 2594 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2595 .type = AMD_IP_BLOCK_TYPE_SMC, 2596 .major = 14, 2597 .minor = 0, 2598 .rev = 0, 2599 .funcs = &smu_ip_funcs, 2600 }; 2601 2602 static int smu_load_microcode(void *handle) 2603 { 2604 struct smu_context *smu = handle; 2605 struct amdgpu_device *adev = smu->adev; 2606 int ret = 0; 2607 2608 if (!smu->pm_enabled) 2609 return -EOPNOTSUPP; 2610 2611 /* This should be used for non PSP loading */ 2612 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2613 return 0; 2614 2615 if (smu->ppt_funcs->load_microcode) { 2616 ret = smu->ppt_funcs->load_microcode(smu); 2617 if (ret) { 2618 dev_err(adev->dev, "Load microcode failed\n"); 2619 return ret; 2620 } 2621 } 2622 2623 if (smu->ppt_funcs->check_fw_status) { 2624 ret = smu->ppt_funcs->check_fw_status(smu); 2625 if (ret) { 2626 dev_err(adev->dev, "SMC is not ready\n"); 2627 return ret; 2628 } 2629 } 2630 2631 return ret; 2632 } 2633 2634 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2635 { 2636 int ret = 0; 2637 2638 if (smu->ppt_funcs->set_gfx_cgpg) 2639 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2640 2641 return ret; 2642 } 2643 2644 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2645 { 2646 struct smu_context *smu = handle; 2647 int ret = 0; 2648 2649 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2650 return -EOPNOTSUPP; 2651 2652 if (!smu->ppt_funcs->set_fan_speed_rpm) 2653 return -EOPNOTSUPP; 2654 2655 if (speed == U32_MAX) 2656 return -EINVAL; 2657 2658 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2659 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2660 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2661 smu->user_dpm_profile.fan_speed_rpm = speed; 2662 2663 /* Override custom PWM setting as they cannot co-exist */ 2664 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2665 smu->user_dpm_profile.fan_speed_pwm = 0; 2666 } 2667 2668 return ret; 2669 } 2670 2671 /** 2672 * smu_get_power_limit - Request one of the SMU Power Limits 2673 * 2674 * @handle: pointer to smu context 2675 * @limit: requested limit is written back to this variable 2676 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2677 * @pp_power_type: &pp_power_type type of power 2678 * Return: 0 on success, <0 on error 2679 * 2680 */ 2681 int smu_get_power_limit(void *handle, 2682 uint32_t *limit, 2683 enum pp_power_limit_level pp_limit_level, 2684 enum pp_power_type pp_power_type) 2685 { 2686 struct smu_context *smu = handle; 2687 struct amdgpu_device *adev = smu->adev; 2688 enum smu_ppt_limit_level limit_level; 2689 uint32_t limit_type; 2690 int ret = 0; 2691 2692 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2693 return -EOPNOTSUPP; 2694 2695 switch (pp_power_type) { 2696 case PP_PWR_TYPE_SUSTAINED: 2697 limit_type = SMU_DEFAULT_PPT_LIMIT; 2698 break; 2699 case PP_PWR_TYPE_FAST: 2700 limit_type = SMU_FAST_PPT_LIMIT; 2701 break; 2702 default: 2703 return -EOPNOTSUPP; 2704 } 2705 2706 switch (pp_limit_level) { 2707 case PP_PWR_LIMIT_CURRENT: 2708 limit_level = SMU_PPT_LIMIT_CURRENT; 2709 break; 2710 case PP_PWR_LIMIT_DEFAULT: 2711 limit_level = SMU_PPT_LIMIT_DEFAULT; 2712 break; 2713 case PP_PWR_LIMIT_MAX: 2714 limit_level = SMU_PPT_LIMIT_MAX; 2715 break; 2716 case PP_PWR_LIMIT_MIN: 2717 limit_level = SMU_PPT_LIMIT_MIN; 2718 break; 2719 default: 2720 return -EOPNOTSUPP; 2721 } 2722 2723 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2724 if (smu->ppt_funcs->get_ppt_limit) 2725 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2726 } else { 2727 switch (limit_level) { 2728 case SMU_PPT_LIMIT_CURRENT: 2729 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2730 case IP_VERSION(13, 0, 2): 2731 case IP_VERSION(13, 0, 6): 2732 case IP_VERSION(11, 0, 7): 2733 case IP_VERSION(11, 0, 11): 2734 case IP_VERSION(11, 0, 12): 2735 case IP_VERSION(11, 0, 13): 2736 ret = smu_get_asic_power_limits(smu, 2737 &smu->current_power_limit, 2738 NULL, NULL, NULL); 2739 break; 2740 default: 2741 break; 2742 } 2743 *limit = smu->current_power_limit; 2744 break; 2745 case SMU_PPT_LIMIT_DEFAULT: 2746 *limit = smu->default_power_limit; 2747 break; 2748 case SMU_PPT_LIMIT_MAX: 2749 *limit = smu->max_power_limit; 2750 break; 2751 case SMU_PPT_LIMIT_MIN: 2752 *limit = smu->min_power_limit; 2753 break; 2754 default: 2755 return -EINVAL; 2756 } 2757 } 2758 2759 return ret; 2760 } 2761 2762 static int smu_set_power_limit(void *handle, uint32_t limit) 2763 { 2764 struct smu_context *smu = handle; 2765 uint32_t limit_type = limit >> 24; 2766 int ret = 0; 2767 2768 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2769 return -EOPNOTSUPP; 2770 2771 limit &= (1<<24)-1; 2772 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2773 if (smu->ppt_funcs->set_power_limit) 2774 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2775 2776 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2777 dev_err(smu->adev->dev, 2778 "New power limit (%d) is out of range [%d,%d]\n", 2779 limit, smu->min_power_limit, smu->max_power_limit); 2780 return -EINVAL; 2781 } 2782 2783 if (!limit) 2784 limit = smu->current_power_limit; 2785 2786 if (smu->ppt_funcs->set_power_limit) { 2787 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2788 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2789 smu->user_dpm_profile.power_limit = limit; 2790 } 2791 2792 return ret; 2793 } 2794 2795 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2796 { 2797 int ret = 0; 2798 2799 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2800 return -EOPNOTSUPP; 2801 2802 if (smu->ppt_funcs->print_clk_levels) 2803 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2804 2805 return ret; 2806 } 2807 2808 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2809 { 2810 enum smu_clk_type clk_type; 2811 2812 switch (type) { 2813 case PP_SCLK: 2814 clk_type = SMU_SCLK; break; 2815 case PP_MCLK: 2816 clk_type = SMU_MCLK; break; 2817 case PP_PCIE: 2818 clk_type = SMU_PCIE; break; 2819 case PP_SOCCLK: 2820 clk_type = SMU_SOCCLK; break; 2821 case PP_FCLK: 2822 clk_type = SMU_FCLK; break; 2823 case PP_DCEFCLK: 2824 clk_type = SMU_DCEFCLK; break; 2825 case PP_VCLK: 2826 clk_type = SMU_VCLK; break; 2827 case PP_VCLK1: 2828 clk_type = SMU_VCLK1; break; 2829 case PP_DCLK: 2830 clk_type = SMU_DCLK; break; 2831 case PP_DCLK1: 2832 clk_type = SMU_DCLK1; break; 2833 case OD_SCLK: 2834 clk_type = SMU_OD_SCLK; break; 2835 case OD_MCLK: 2836 clk_type = SMU_OD_MCLK; break; 2837 case OD_VDDC_CURVE: 2838 clk_type = SMU_OD_VDDC_CURVE; break; 2839 case OD_RANGE: 2840 clk_type = SMU_OD_RANGE; break; 2841 case OD_VDDGFX_OFFSET: 2842 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2843 case OD_CCLK: 2844 clk_type = SMU_OD_CCLK; break; 2845 case OD_FAN_CURVE: 2846 clk_type = SMU_OD_FAN_CURVE; break; 2847 case OD_ACOUSTIC_LIMIT: 2848 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 2849 case OD_ACOUSTIC_TARGET: 2850 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 2851 case OD_FAN_TARGET_TEMPERATURE: 2852 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2853 case OD_FAN_MINIMUM_PWM: 2854 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2855 default: 2856 clk_type = SMU_CLK_COUNT; break; 2857 } 2858 2859 return clk_type; 2860 } 2861 2862 static int smu_print_ppclk_levels(void *handle, 2863 enum pp_clock_type type, 2864 char *buf) 2865 { 2866 struct smu_context *smu = handle; 2867 enum smu_clk_type clk_type; 2868 2869 clk_type = smu_convert_to_smuclk(type); 2870 if (clk_type == SMU_CLK_COUNT) 2871 return -EINVAL; 2872 2873 return smu_print_smuclk_levels(smu, clk_type, buf); 2874 } 2875 2876 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2877 { 2878 struct smu_context *smu = handle; 2879 enum smu_clk_type clk_type; 2880 2881 clk_type = smu_convert_to_smuclk(type); 2882 if (clk_type == SMU_CLK_COUNT) 2883 return -EINVAL; 2884 2885 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2886 return -EOPNOTSUPP; 2887 2888 if (!smu->ppt_funcs->emit_clk_levels) 2889 return -ENOENT; 2890 2891 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2892 2893 } 2894 2895 static int smu_od_edit_dpm_table(void *handle, 2896 enum PP_OD_DPM_TABLE_COMMAND type, 2897 long *input, uint32_t size) 2898 { 2899 struct smu_context *smu = handle; 2900 int ret = 0; 2901 2902 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2903 return -EOPNOTSUPP; 2904 2905 if (smu->ppt_funcs->od_edit_dpm_table) { 2906 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2907 } 2908 2909 return ret; 2910 } 2911 2912 static int smu_read_sensor(void *handle, 2913 int sensor, 2914 void *data, 2915 int *size_arg) 2916 { 2917 struct smu_context *smu = handle; 2918 struct smu_umd_pstate_table *pstate_table = 2919 &smu->pstate_table; 2920 int ret = 0; 2921 uint32_t *size, size_val; 2922 2923 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2924 return -EOPNOTSUPP; 2925 2926 if (!data || !size_arg) 2927 return -EINVAL; 2928 2929 size_val = *size_arg; 2930 size = &size_val; 2931 2932 if (smu->ppt_funcs->read_sensor) 2933 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2934 goto unlock; 2935 2936 switch (sensor) { 2937 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2938 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2939 *size = 4; 2940 break; 2941 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2942 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2943 *size = 4; 2944 break; 2945 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2946 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2947 *size = 4; 2948 break; 2949 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2950 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2951 *size = 4; 2952 break; 2953 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2954 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2955 *size = 8; 2956 break; 2957 case AMDGPU_PP_SENSOR_UVD_POWER: 2958 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2959 *size = 4; 2960 break; 2961 case AMDGPU_PP_SENSOR_VCE_POWER: 2962 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2963 *size = 4; 2964 break; 2965 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2966 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 2967 *size = 4; 2968 break; 2969 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2970 *(uint32_t *)data = 0; 2971 *size = 4; 2972 break; 2973 default: 2974 *size = 0; 2975 ret = -EOPNOTSUPP; 2976 break; 2977 } 2978 2979 unlock: 2980 // assign uint32_t to int 2981 *size_arg = size_val; 2982 2983 return ret; 2984 } 2985 2986 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 2987 { 2988 int ret = -EOPNOTSUPP; 2989 struct smu_context *smu = handle; 2990 2991 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 2992 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 2993 2994 return ret; 2995 } 2996 2997 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 2998 { 2999 int ret = -EOPNOTSUPP; 3000 struct smu_context *smu = handle; 3001 3002 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3003 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3004 3005 return ret; 3006 } 3007 3008 static int smu_get_power_profile_mode(void *handle, char *buf) 3009 { 3010 struct smu_context *smu = handle; 3011 3012 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3013 !smu->ppt_funcs->get_power_profile_mode) 3014 return -EOPNOTSUPP; 3015 if (!buf) 3016 return -EINVAL; 3017 3018 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3019 } 3020 3021 static int smu_set_power_profile_mode(void *handle, 3022 long *param, 3023 uint32_t param_size) 3024 { 3025 struct smu_context *smu = handle; 3026 3027 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3028 !smu->ppt_funcs->set_power_profile_mode) 3029 return -EOPNOTSUPP; 3030 3031 return smu_bump_power_profile_mode(smu, param, param_size); 3032 } 3033 3034 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3035 { 3036 struct smu_context *smu = handle; 3037 3038 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3039 return -EOPNOTSUPP; 3040 3041 if (!smu->ppt_funcs->get_fan_control_mode) 3042 return -EOPNOTSUPP; 3043 3044 if (!fan_mode) 3045 return -EINVAL; 3046 3047 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3048 3049 return 0; 3050 } 3051 3052 static int smu_set_fan_control_mode(void *handle, u32 value) 3053 { 3054 struct smu_context *smu = handle; 3055 int ret = 0; 3056 3057 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3058 return -EOPNOTSUPP; 3059 3060 if (!smu->ppt_funcs->set_fan_control_mode) 3061 return -EOPNOTSUPP; 3062 3063 if (value == U32_MAX) 3064 return -EINVAL; 3065 3066 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3067 if (ret) 3068 goto out; 3069 3070 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3071 smu->user_dpm_profile.fan_mode = value; 3072 3073 /* reset user dpm fan speed */ 3074 if (value != AMD_FAN_CTRL_MANUAL) { 3075 smu->user_dpm_profile.fan_speed_pwm = 0; 3076 smu->user_dpm_profile.fan_speed_rpm = 0; 3077 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3078 } 3079 } 3080 3081 out: 3082 return ret; 3083 } 3084 3085 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3086 { 3087 struct smu_context *smu = handle; 3088 int ret = 0; 3089 3090 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3091 return -EOPNOTSUPP; 3092 3093 if (!smu->ppt_funcs->get_fan_speed_pwm) 3094 return -EOPNOTSUPP; 3095 3096 if (!speed) 3097 return -EINVAL; 3098 3099 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3100 3101 return ret; 3102 } 3103 3104 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3105 { 3106 struct smu_context *smu = handle; 3107 int ret = 0; 3108 3109 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3110 return -EOPNOTSUPP; 3111 3112 if (!smu->ppt_funcs->set_fan_speed_pwm) 3113 return -EOPNOTSUPP; 3114 3115 if (speed == U32_MAX) 3116 return -EINVAL; 3117 3118 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3119 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3120 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3121 smu->user_dpm_profile.fan_speed_pwm = speed; 3122 3123 /* Override custom RPM setting as they cannot co-exist */ 3124 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3125 smu->user_dpm_profile.fan_speed_rpm = 0; 3126 } 3127 3128 return ret; 3129 } 3130 3131 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3132 { 3133 struct smu_context *smu = handle; 3134 int ret = 0; 3135 3136 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3137 return -EOPNOTSUPP; 3138 3139 if (!smu->ppt_funcs->get_fan_speed_rpm) 3140 return -EOPNOTSUPP; 3141 3142 if (!speed) 3143 return -EINVAL; 3144 3145 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3146 3147 return ret; 3148 } 3149 3150 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3151 { 3152 struct smu_context *smu = handle; 3153 3154 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3155 return -EOPNOTSUPP; 3156 3157 return smu_set_min_dcef_deep_sleep(smu, clk); 3158 } 3159 3160 static int smu_get_clock_by_type_with_latency(void *handle, 3161 enum amd_pp_clock_type type, 3162 struct pp_clock_levels_with_latency *clocks) 3163 { 3164 struct smu_context *smu = handle; 3165 enum smu_clk_type clk_type; 3166 int ret = 0; 3167 3168 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3169 return -EOPNOTSUPP; 3170 3171 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3172 switch (type) { 3173 case amd_pp_sys_clock: 3174 clk_type = SMU_GFXCLK; 3175 break; 3176 case amd_pp_mem_clock: 3177 clk_type = SMU_MCLK; 3178 break; 3179 case amd_pp_dcef_clock: 3180 clk_type = SMU_DCEFCLK; 3181 break; 3182 case amd_pp_disp_clock: 3183 clk_type = SMU_DISPCLK; 3184 break; 3185 default: 3186 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3187 return -EINVAL; 3188 } 3189 3190 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3191 } 3192 3193 return ret; 3194 } 3195 3196 static int smu_display_clock_voltage_request(void *handle, 3197 struct pp_display_clock_request *clock_req) 3198 { 3199 struct smu_context *smu = handle; 3200 int ret = 0; 3201 3202 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3203 return -EOPNOTSUPP; 3204 3205 if (smu->ppt_funcs->display_clock_voltage_request) 3206 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3207 3208 return ret; 3209 } 3210 3211 3212 static int smu_display_disable_memory_clock_switch(void *handle, 3213 bool disable_memory_clock_switch) 3214 { 3215 struct smu_context *smu = handle; 3216 int ret = -EINVAL; 3217 3218 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3219 return -EOPNOTSUPP; 3220 3221 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3222 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3223 3224 return ret; 3225 } 3226 3227 static int smu_set_xgmi_pstate(void *handle, 3228 uint32_t pstate) 3229 { 3230 struct smu_context *smu = handle; 3231 int ret = 0; 3232 3233 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3234 return -EOPNOTSUPP; 3235 3236 if (smu->ppt_funcs->set_xgmi_pstate) 3237 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3238 3239 if (ret) 3240 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3241 3242 return ret; 3243 } 3244 3245 static int smu_get_baco_capability(void *handle) 3246 { 3247 struct smu_context *smu = handle; 3248 3249 if (!smu->pm_enabled) 3250 return false; 3251 3252 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3253 return false; 3254 3255 return smu->ppt_funcs->get_bamaco_support(smu); 3256 } 3257 3258 static int smu_baco_set_state(void *handle, int state) 3259 { 3260 struct smu_context *smu = handle; 3261 int ret = 0; 3262 3263 if (!smu->pm_enabled) 3264 return -EOPNOTSUPP; 3265 3266 if (state == 0) { 3267 if (smu->ppt_funcs->baco_exit) 3268 ret = smu->ppt_funcs->baco_exit(smu); 3269 } else if (state == 1) { 3270 if (smu->ppt_funcs->baco_enter) 3271 ret = smu->ppt_funcs->baco_enter(smu); 3272 } else { 3273 return -EINVAL; 3274 } 3275 3276 if (ret) 3277 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3278 (state)?"enter":"exit"); 3279 3280 return ret; 3281 } 3282 3283 bool smu_mode1_reset_is_support(struct smu_context *smu) 3284 { 3285 bool ret = false; 3286 3287 if (!smu->pm_enabled) 3288 return false; 3289 3290 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3291 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3292 3293 return ret; 3294 } 3295 3296 bool smu_mode2_reset_is_support(struct smu_context *smu) 3297 { 3298 bool ret = false; 3299 3300 if (!smu->pm_enabled) 3301 return false; 3302 3303 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 3304 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 3305 3306 return ret; 3307 } 3308 3309 int smu_mode1_reset(struct smu_context *smu) 3310 { 3311 int ret = 0; 3312 3313 if (!smu->pm_enabled) 3314 return -EOPNOTSUPP; 3315 3316 if (smu->ppt_funcs->mode1_reset) 3317 ret = smu->ppt_funcs->mode1_reset(smu); 3318 3319 return ret; 3320 } 3321 3322 static int smu_mode2_reset(void *handle) 3323 { 3324 struct smu_context *smu = handle; 3325 int ret = 0; 3326 3327 if (!smu->pm_enabled) 3328 return -EOPNOTSUPP; 3329 3330 if (smu->ppt_funcs->mode2_reset) 3331 ret = smu->ppt_funcs->mode2_reset(smu); 3332 3333 if (ret) 3334 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3335 3336 return ret; 3337 } 3338 3339 static int smu_enable_gfx_features(void *handle) 3340 { 3341 struct smu_context *smu = handle; 3342 int ret = 0; 3343 3344 if (!smu->pm_enabled) 3345 return -EOPNOTSUPP; 3346 3347 if (smu->ppt_funcs->enable_gfx_features) 3348 ret = smu->ppt_funcs->enable_gfx_features(smu); 3349 3350 if (ret) 3351 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3352 3353 return ret; 3354 } 3355 3356 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3357 struct pp_smu_nv_clock_table *max_clocks) 3358 { 3359 struct smu_context *smu = handle; 3360 int ret = 0; 3361 3362 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3363 return -EOPNOTSUPP; 3364 3365 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3366 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3367 3368 return ret; 3369 } 3370 3371 static int smu_get_uclk_dpm_states(void *handle, 3372 unsigned int *clock_values_in_khz, 3373 unsigned int *num_states) 3374 { 3375 struct smu_context *smu = handle; 3376 int ret = 0; 3377 3378 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3379 return -EOPNOTSUPP; 3380 3381 if (smu->ppt_funcs->get_uclk_dpm_states) 3382 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3383 3384 return ret; 3385 } 3386 3387 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3388 { 3389 struct smu_context *smu = handle; 3390 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3391 3392 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3393 return -EOPNOTSUPP; 3394 3395 if (smu->ppt_funcs->get_current_power_state) 3396 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3397 3398 return pm_state; 3399 } 3400 3401 static int smu_get_dpm_clock_table(void *handle, 3402 struct dpm_clocks *clock_table) 3403 { 3404 struct smu_context *smu = handle; 3405 int ret = 0; 3406 3407 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3408 return -EOPNOTSUPP; 3409 3410 if (smu->ppt_funcs->get_dpm_clock_table) 3411 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3412 3413 return ret; 3414 } 3415 3416 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3417 { 3418 struct smu_context *smu = handle; 3419 3420 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3421 return -EOPNOTSUPP; 3422 3423 if (!smu->ppt_funcs->get_gpu_metrics) 3424 return -EOPNOTSUPP; 3425 3426 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3427 } 3428 3429 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3430 size_t size) 3431 { 3432 struct smu_context *smu = handle; 3433 3434 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3435 return -EOPNOTSUPP; 3436 3437 if (!smu->ppt_funcs->get_pm_metrics) 3438 return -EOPNOTSUPP; 3439 3440 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3441 } 3442 3443 static int smu_enable_mgpu_fan_boost(void *handle) 3444 { 3445 struct smu_context *smu = handle; 3446 int ret = 0; 3447 3448 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3449 return -EOPNOTSUPP; 3450 3451 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3452 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3453 3454 return ret; 3455 } 3456 3457 static int smu_gfx_state_change_set(void *handle, 3458 uint32_t state) 3459 { 3460 struct smu_context *smu = handle; 3461 int ret = 0; 3462 3463 if (smu->ppt_funcs->gfx_state_change_set) 3464 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3465 3466 return ret; 3467 } 3468 3469 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3470 { 3471 int ret = 0; 3472 3473 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3474 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3475 3476 return ret; 3477 } 3478 3479 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3480 { 3481 int ret = -EOPNOTSUPP; 3482 3483 if (smu->ppt_funcs && 3484 smu->ppt_funcs->get_ecc_info) 3485 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3486 3487 return ret; 3488 3489 } 3490 3491 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3492 { 3493 struct smu_context *smu = handle; 3494 struct smu_table_context *smu_table = &smu->smu_table; 3495 struct smu_table *memory_pool = &smu_table->memory_pool; 3496 3497 if (!addr || !size) 3498 return -EINVAL; 3499 3500 *addr = NULL; 3501 *size = 0; 3502 if (memory_pool->bo) { 3503 *addr = memory_pool->cpu_addr; 3504 *size = memory_pool->size; 3505 } 3506 3507 return 0; 3508 } 3509 3510 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 3511 enum pp_xgmi_plpd_mode mode) 3512 { 3513 int ret = -EOPNOTSUPP; 3514 3515 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3516 return ret; 3517 3518 /* PLPD policy is not supported if it's NONE */ 3519 if (smu->plpd_mode == XGMI_PLPD_NONE) 3520 return ret; 3521 3522 if (smu->plpd_mode == mode) 3523 return 0; 3524 3525 if (smu->ppt_funcs && smu->ppt_funcs->select_xgmi_plpd_policy) 3526 ret = smu->ppt_funcs->select_xgmi_plpd_policy(smu, mode); 3527 3528 if (!ret) 3529 smu->plpd_mode = mode; 3530 3531 return ret; 3532 } 3533 3534 static const struct amd_pm_funcs swsmu_pm_funcs = { 3535 /* export for sysfs */ 3536 .set_fan_control_mode = smu_set_fan_control_mode, 3537 .get_fan_control_mode = smu_get_fan_control_mode, 3538 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3539 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3540 .force_clock_level = smu_force_ppclk_levels, 3541 .print_clock_levels = smu_print_ppclk_levels, 3542 .emit_clock_levels = smu_emit_ppclk_levels, 3543 .force_performance_level = smu_force_performance_level, 3544 .read_sensor = smu_read_sensor, 3545 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3546 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3547 .get_performance_level = smu_get_performance_level, 3548 .get_current_power_state = smu_get_current_power_state, 3549 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3550 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3551 .get_pp_num_states = smu_get_power_num_states, 3552 .get_pp_table = smu_sys_get_pp_table, 3553 .set_pp_table = smu_sys_set_pp_table, 3554 .switch_power_profile = smu_switch_power_profile, 3555 /* export to amdgpu */ 3556 .dispatch_tasks = smu_handle_dpm_task, 3557 .load_firmware = smu_load_microcode, 3558 .set_powergating_by_smu = smu_dpm_set_power_gate, 3559 .set_power_limit = smu_set_power_limit, 3560 .get_power_limit = smu_get_power_limit, 3561 .get_power_profile_mode = smu_get_power_profile_mode, 3562 .set_power_profile_mode = smu_set_power_profile_mode, 3563 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3564 .set_mp1_state = smu_set_mp1_state, 3565 .gfx_state_change_set = smu_gfx_state_change_set, 3566 /* export to DC */ 3567 .get_sclk = smu_get_sclk, 3568 .get_mclk = smu_get_mclk, 3569 .display_configuration_change = smu_display_configuration_change, 3570 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3571 .display_clock_voltage_request = smu_display_clock_voltage_request, 3572 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3573 .set_active_display_count = smu_set_display_count, 3574 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3575 .get_asic_baco_capability = smu_get_baco_capability, 3576 .set_asic_baco_state = smu_baco_set_state, 3577 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3578 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3579 .asic_reset_mode_2 = smu_mode2_reset, 3580 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3581 .set_df_cstate = smu_set_df_cstate, 3582 .set_xgmi_pstate = smu_set_xgmi_pstate, 3583 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3584 .get_pm_metrics = smu_sys_get_pm_metrics, 3585 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3586 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3587 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3588 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3589 .get_dpm_clock_table = smu_get_dpm_clock_table, 3590 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3591 }; 3592 3593 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3594 uint64_t event_arg) 3595 { 3596 int ret = -EINVAL; 3597 3598 if (smu->ppt_funcs->wait_for_event) 3599 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3600 3601 return ret; 3602 } 3603 3604 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3605 { 3606 3607 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3608 return -EOPNOTSUPP; 3609 3610 /* Confirm the buffer allocated is of correct size */ 3611 if (size != smu->stb_context.stb_buf_size) 3612 return -EINVAL; 3613 3614 /* 3615 * No need to lock smu mutex as we access STB directly through MMIO 3616 * and not going through SMU messaging route (for now at least). 3617 * For registers access rely on implementation internal locking. 3618 */ 3619 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3620 } 3621 3622 #if defined(CONFIG_DEBUG_FS) 3623 3624 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3625 { 3626 struct amdgpu_device *adev = filp->f_inode->i_private; 3627 struct smu_context *smu = adev->powerplay.pp_handle; 3628 unsigned char *buf; 3629 int r; 3630 3631 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3632 if (!buf) 3633 return -ENOMEM; 3634 3635 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3636 if (r) 3637 goto out; 3638 3639 filp->private_data = buf; 3640 3641 return 0; 3642 3643 out: 3644 kvfree(buf); 3645 return r; 3646 } 3647 3648 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3649 loff_t *pos) 3650 { 3651 struct amdgpu_device *adev = filp->f_inode->i_private; 3652 struct smu_context *smu = adev->powerplay.pp_handle; 3653 3654 3655 if (!filp->private_data) 3656 return -EINVAL; 3657 3658 return simple_read_from_buffer(buf, 3659 size, 3660 pos, filp->private_data, 3661 smu->stb_context.stb_buf_size); 3662 } 3663 3664 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3665 { 3666 kvfree(filp->private_data); 3667 filp->private_data = NULL; 3668 3669 return 0; 3670 } 3671 3672 /* 3673 * We have to define not only read method but also 3674 * open and release because .read takes up to PAGE_SIZE 3675 * data each time so and so is invoked multiple times. 3676 * We allocate the STB buffer in .open and release it 3677 * in .release 3678 */ 3679 static const struct file_operations smu_stb_debugfs_fops = { 3680 .owner = THIS_MODULE, 3681 .open = smu_stb_debugfs_open, 3682 .read = smu_stb_debugfs_read, 3683 .release = smu_stb_debugfs_release, 3684 .llseek = default_llseek, 3685 }; 3686 3687 #endif 3688 3689 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3690 { 3691 #if defined(CONFIG_DEBUG_FS) 3692 3693 struct smu_context *smu = adev->powerplay.pp_handle; 3694 3695 if (!smu || (!smu->stb_context.stb_buf_size)) 3696 return; 3697 3698 debugfs_create_file_size("amdgpu_smu_stb_dump", 3699 S_IRUSR, 3700 adev_to_drm(adev)->primary->debugfs_root, 3701 adev, 3702 &smu_stb_debugfs_fops, 3703 smu->stb_context.stb_buf_size); 3704 #endif 3705 } 3706 3707 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3708 { 3709 int ret = 0; 3710 3711 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3712 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3713 3714 return ret; 3715 } 3716 3717 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3718 { 3719 int ret = 0; 3720 3721 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3722 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3723 3724 return ret; 3725 } 3726 3727 int smu_send_rma_reason(struct smu_context *smu) 3728 { 3729 int ret = 0; 3730 3731 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 3732 ret = smu->ppt_funcs->send_rma_reason(smu); 3733 3734 return ret; 3735 } 3736